ARM,AArch64: Use generic tables instead of SearchableTable

[nhaehnle]

Summary

Change-Id: If7cec95d7d7e6335bbf81f5c589a8e14de9375f9

[javed.absar]

Its not clear to me why 'GenericTable' is more efficient/better than SearchableTable. Maybe you could give some background in the commit message about this. I implemented the ARMSystemRegister bit sometime ago and found SearchableTable quite useful and concise but perhaps GenericTable/Enum is even better.

[nhaehnle]

Sorry for the lack of context.

With the parent revision, SearchableTable is implemented entirely in terms of the new primitives. So the idea is to remove SearchableTable to have only One Way of doing things rather than a proliferation of different approaches to expressing the same thing.

If people feel strongly that using GenericTable + SearchIndex is too verbose relative to SearchableTable, we can leave SearchableTable in. I just thought it'd be cleaner to get rid of it, given that it has become redundant.

[javed.absar]

Probably good to mention that this patch relies on https://reviews.llvm.org/D48013

[nhaehnle]

In D48015#1128840, @javed.absar wrote:

Probably good to mention that this patch relies on https://reviews.llvm.org/D48013

Well, yes. I linked the revisions, but Phabricator's support for patch series doesn't seem to be widely used. It's what you see when you click on "Stack" in the overview.

[nhaehnle]

Rebased.

lib/Target/AArch64/AArch64SystemOperands.td

 //===----------------------------------------------------------------------===//
 
 include "llvm/TableGen/SearchableTable.td"
 
 //===----------------------------------------------------------------------===//
 // AT (address translate) instruction options.
 //===----------------------------------------------------------------------===//
 
-class AT<string name, bits<3> op1, bits<4> crn, bits<4> crm,
-         bits<3> op2> : SearchableTable {
-  let SearchableFields = ["Name", "Encoding"];
-  let EnumValueField = "Encoding";
-
+class AT<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2> {
   string Name = name;
   bits<14> Encoding;
   let Encoding{13-11} = op1;
   let Encoding{10-7} = crn;
   let Encoding{6-3} = crm;
   let Encoding{2-0} = op2;
   code Requires = [{ {} }];
 }
 
+def ATsList : GenericTable {
+  let FilterClass = "AT";
+  let Fields = ["Name", "Encoding", "Requires"];
+
+  let PrimaryKey = ["Encoding"];
+  let PrimaryKeyName = "lookupATByEncoding";
+}
+
+def lookupATByName : SearchIndex {
+  let Table = ATsList;
+  let Key = ["Name"];
+}
+
 def : AT<"S1E1R",  0b000, 0b0111, 0b1000, 0b000>;
 def : AT<"S1E2R",  0b100, 0b0111, 0b1000, 0b000>;
 def : AT<"S1E3R",  0b110, 0b0111, 0b1000, 0b000>;
 def : AT<"S1E1W",  0b000, 0b0111, 0b1000, 0b001>;
 def : AT<"S1E2W",  0b100, 0b0111, 0b1000, 0b001>;
 def : AT<"S1E3W",  0b110, 0b0111, 0b1000, 0b001>;
 def : AT<"S1E0R",  0b000, 0b0111, 0b1000, 0b010>;
 def : AT<"S1E0W",  0b000, 0b0111, 0b1000, 0b011>;
 def : AT<"S12E1R", 0b100, 0b0111, 0b1000, 0b100>;
 def : AT<"S12E1W", 0b100, 0b0111, 0b1000, 0b101>;
 def : AT<"S12E0R", 0b100, 0b0111, 0b1000, 0b110>;
 def : AT<"S12E0W", 0b100, 0b0111, 0b1000, 0b111>;
 
 let Requires = [{ {AArch64::HasV8_2aOps} }] in {
 def : AT<"S1E1RP", 0b000, 0b0111, 0b1001, 0b000>;
 def : AT<"S1E1WP", 0b000, 0b0111, 0b1001, 0b001>;
 }
 
 //===----------------------------------------------------------------------===//
 // DMB/DSB (data barrier) instruction options.
 //===----------------------------------------------------------------------===//
 
-class DB<string name, bits<4> encoding> : SearchableTable {
-  let SearchableFields = ["Name", "Encoding"];
-  let EnumValueField = "Encoding";
-
+class DB<string name, bits<4> encoding> {
   string Name = name;
   bits<4> Encoding = encoding;
 }
 
+def DBValues : GenericEnum {
+  let FilterClass = "DB";
+  let NameField = "Name";
+  let ValueField = "Encoding";
+}
+
+def DBsList : GenericTable {
+  let FilterClass = "DB";
+  let Fields = ["Name", "Encoding"];
+
+  let PrimaryKey = ["Encoding"];
+  let PrimaryKeyName = "lookupDBByEncoding";
+}
+
+def lookupDBByName : SearchIndex {
+  let Table = DBsList;
+  let Key = ["Name"];
+}
+
 def : DB<"oshld", 0x1>;
 def : DB<"oshst", 0x2>;
 def : DB<"osh",   0x3>;
 def : DB<"nshld", 0x5>;
 def : DB<"nshst", 0x6>;
 def : DB<"nsh",   0x7>;
 def : DB<"ishld", 0x9>;
 def : DB<"ishst", 0xa>;
 def : DB<"ish",   0xb>;
 def : DB<"ld",    0xd>;
 def : DB<"st",    0xe>;
 def : DB<"sy",    0xf>;
 
 //===----------------------------------------------------------------------===//
 // DC (data cache maintenance) instruction options.
 //===----------------------------------------------------------------------===//
 
-class DC<string name, bits<3> op1, bits<4> crn, bits<4> crm,
-         bits<3> op2> : SearchableTable {
-  let SearchableFields = ["Name", "Encoding"];
-  let EnumValueField = "Encoding";
-
+class DC<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2> {
   string Name = name;
   bits<14> Encoding;
   let Encoding{13-11} = op1;
   let Encoding{10-7} = crn;
   let Encoding{6-3} = crm;
   let Encoding{2-0} = op2;
   code Requires = [{ {} }];
 }
 
+def DCsList : GenericTable {
+  let FilterClass = "DC";
+  let Fields = ["Name", "Encoding", "Requires"];
+
+  let PrimaryKey = ["Encoding"];
+  let PrimaryKeyName = "lookupDCByEncoding";
+}
+
+def lookupDCByName : SearchIndex {
+  let Table = DCsList;
+  let Key = ["Name"];
+}
+
 def : DC<"ZVA",   0b011, 0b0111, 0b0100, 0b001>;
 def : DC<"IVAC",  0b000, 0b0111, 0b0110, 0b001>;
 def : DC<"ISW",   0b000, 0b0111, 0b0110, 0b010>;
 def : DC<"CVAC",  0b011, 0b0111, 0b1010, 0b001>;
 def : DC<"CSW",   0b000, 0b0111, 0b1010, 0b010>;
 def : DC<"CVAU",  0b011, 0b0111, 0b1011, 0b001>;
 def : DC<"CIVAC", 0b011, 0b0111, 0b1110, 0b001>;
 def : DC<"CISW",  0b000, 0b0111, 0b1110, 0b010>;
 
 let Requires = [{ {AArch64::HasV8_2aOps} }] in
 def : DC<"CVAP",  0b011, 0b0111, 0b1100, 0b001>;
 
 //===----------------------------------------------------------------------===//
 // IC (instruction cache maintenance) instruction options.
 //===----------------------------------------------------------------------===//
 
 class IC<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2,
-         bit needsreg> : SearchableTable {
-  let SearchableFields = ["Name", "Encoding"];
-  let EnumValueField = "Encoding";
-
+         bit needsreg> {
   string Name = name;
   bits<14> Encoding;
   let Encoding{13-11} = op1;
   let Encoding{10-7} = crn;
   let Encoding{6-3} = crm;
   let Encoding{2-0} = op2;
   bit NeedsReg = needsreg;
 }
 
+def ICsList : GenericTable {
+  let FilterClass = "IC";
+  let Fields = ["Name", "Encoding", "NeedsReg"];
+
+  let PrimaryKey = ["Encoding"];
+  let PrimaryKeyName = "lookupICByEncoding";
+}
+
+def lookupICByName : SearchIndex {
+  let Table = ICsList;
+  let Key = ["Name"];
+}
+
 def : IC<"IALLUIS", 0b000, 0b0111, 0b0001, 0b000, 0>;
 def : IC<"IALLU",   0b000, 0b0111, 0b0101, 0b000, 0>;
 def : IC<"IVAU",    0b011, 0b0111, 0b0101, 0b001, 1>;
 
 //===----------------------------------------------------------------------===//
 // ISB (instruction-fetch barrier) instruction options.
 //===----------------------------------------------------------------------===//
 
-class ISB<string name, bits<4> encoding> : SearchableTable{
-  let SearchableFields = ["Name", "Encoding"];
-  let EnumValueField = "Encoding";
-
+class ISB<string name, bits<4> encoding> {
   string Name = name;
   bits<4> Encoding;
   let Encoding = encoding;
 }
 
+def ISBsList : GenericTable {
+  let FilterClass = "ISB";
+  let Fields = ["Name", "Encoding"];
+
+  let PrimaryKey = ["Encoding"];
+  let PrimaryKeyName = "lookupISBByEncoding";
+}
+
+def lookupISBByName : SearchIndex {
+  let Table = ISBsList;
+  let Key = ["Name"];
+}
+
 def : ISB<"sy", 0xf>;
 
 //===----------------------------------------------------------------------===//
 // PRFM (prefetch) instruction options.
 //===----------------------------------------------------------------------===//
 
-class PRFM<string name, bits<5> encoding> : SearchableTable {
-  let SearchableFields = ["Name", "Encoding"];
-  let EnumValueField = "Encoding";
-
+class PRFM<string name, bits<5> encoding> {
   string Name = name;
   bits<5> Encoding;
   let Encoding = encoding;
 }
 
+def PRFMsList : GenericTable {
+  let FilterClass = "PRFM";
+  let Fields = ["Name", "Encoding"];
+
+  let PrimaryKey = ["Encoding"];
+  let PrimaryKeyName = "lookupPRFMByEncoding";
+}
+
+def lookupPRFMByName : SearchIndex {
+  let Table = PRFMsList;
+  let Key = ["Name"];
+}
+
 def : PRFM<"pldl1keep", 0x00>;
 def : PRFM<"pldl1strm", 0x01>;
 def : PRFM<"pldl2keep", 0x02>;
 def : PRFM<"pldl2strm", 0x03>;
 def : PRFM<"pldl3keep", 0x04>;
 def : PRFM<"pldl3strm", 0x05>;
 def : PRFM<"plil1keep", 0x08>;
 def : PRFM<"plil1strm", 0x09>;
 def : PRFM<"plil2keep", 0x0a>;
 def : PRFM<"plil2strm", 0x0b>;
 def : PRFM<"plil3keep", 0x0c>;
 def : PRFM<"plil3strm", 0x0d>;
 def : PRFM<"pstl1keep", 0x10>;
 def : PRFM<"pstl1strm", 0x11>;
 def : PRFM<"pstl2keep", 0x12>;
 def : PRFM<"pstl2strm", 0x13>;
 def : PRFM<"pstl3keep", 0x14>;
 def : PRFM<"pstl3strm", 0x15>;
 
 //===----------------------------------------------------------------------===//
 // SVE Prefetch instruction options.
 //===----------------------------------------------------------------------===//
 
-class SVEPRFM<string name, bits<4> encoding> : SearchableTable {
-  let SearchableFields = ["Name", "Encoding"];
-  let EnumValueField = "Encoding";
-
+class SVEPRFM<string name, bits<4> encoding> {
   string Name = name;
   bits<4> Encoding;
   let Encoding = encoding;
   code Requires = [{ {} }];
 }
 
+def SVEPRFMsList : GenericTable {
+  let FilterClass = "SVEPRFM";
+  let Fields = ["Name", "Encoding", "Requires"];
+
+  let PrimaryKey = ["Encoding"];
+  let PrimaryKeyName = "lookupSVEPRFMByEncoding";
+}
+
+def lookupSVEPRFMByName : SearchIndex {
+  let Table = SVEPRFMsList;
+  let Key = ["Name"];
+}
+
 let Requires = [{ {AArch64::FeatureSVE} }] in {
 def : SVEPRFM<"pldl1keep", 0x00>;
 def : SVEPRFM<"pldl1strm", 0x01>;
 def : SVEPRFM<"pldl2keep", 0x02>;
 def : SVEPRFM<"pldl2strm", 0x03>;
 def : SVEPRFM<"pldl3keep", 0x04>;
 def : SVEPRFM<"pldl3strm", 0x05>;
 def : SVEPRFM<"pstl1keep", 0x08>;
 def : SVEPRFM<"pstl1strm", 0x09>;
 def : SVEPRFM<"pstl2keep", 0x0a>;
 def : SVEPRFM<"pstl2strm", 0x0b>;
 def : SVEPRFM<"pstl3keep", 0x0c>;
 def : SVEPRFM<"pstl3strm", 0x0d>;
 }
 
 //===----------------------------------------------------------------------===//
 // SVE Predicate patterns
 //===----------------------------------------------------------------------===//
 
-class SVEPREDPAT<string name, bits<5> encoding> : SearchableTable {
-  let SearchableFields = ["Name", "Encoding"];
-  let EnumValueField = "Encoding";
-
+class SVEPREDPAT<string name, bits<5> encoding> {
   string Name = name;
   bits<5> Encoding;
   let Encoding = encoding;
 }
 
+def SVEPREDPATsList : GenericTable {
+  let FilterClass = "SVEPREDPAT";
+  let Fields = ["Name", "Encoding"];
+
+  let PrimaryKey = ["Encoding"];
+  let PrimaryKeyName = "lookupSVEPREDPATByEncoding";
+}
+
+def lookupSVEPREDPATByName : SearchIndex {
+  let Table = SVEPREDPATsList;
+  let Key = ["Name"];
+}
+
 def : SVEPREDPAT<"pow2",  0x00>;
 def : SVEPREDPAT<"vl1",   0x01>;
 def : SVEPREDPAT<"vl2",   0x02>;
 def : SVEPREDPAT<"vl3",   0x03>;
 def : SVEPREDPAT<"vl4",   0x04>;
 def : SVEPREDPAT<"vl5",   0x05>;
 def : SVEPREDPAT<"vl6",   0x06>;
 def : SVEPREDPAT<"vl7",   0x07>;

 
 //===----------------------------------------------------------------------===//
 // Exact FP Immediates.
 //
 // These definitions are used to create a lookup table with FP Immediates that
 // is used for a few instructions that only accept a limited set of exact FP
 // immediates values.
 //===----------------------------------------------------------------------===//
-class ExactFPImm<string name, string repr, bits<4> enum > : SearchableTable {
-  let SearchableFields = ["Enum", "Repr"];
-  let EnumValueField = "Enum";
-
+class ExactFPImm<string name, string repr, bits<4> enum > {
   string Name = name;
   bits<4> Enum = enum;
   string Repr = repr;
 }
 
+def ExactFPImmValues : GenericEnum {
+  let FilterClass = "ExactFPImm";
+  let NameField = "Name";
+  let ValueField = "Enum";
+}
+
+def ExactFPImmsList : GenericTable {
+  let FilterClass = "ExactFPImm";
+  let Fields = ["Name", "Enum", "Repr"];
+
+  let PrimaryKey = ["Enum"];
+  let PrimaryKeyName = "lookupExactFPImmByEnum";
+}
+
+def lookupExactFPImmByRepr : SearchIndex {
+  let Table = ExactFPImmsList;
+  let Key = ["Repr"];
+}
+
 def : ExactFPImm<"zero", "0.0", 0x0>;
 def : ExactFPImm<"half", "0.5", 0x1>;
 def : ExactFPImm<"one",  "1.0", 0x2>;
 def : ExactFPImm<"two",  "2.0", 0x3>;
 
 //===----------------------------------------------------------------------===//
 // PState instruction options.
 //===----------------------------------------------------------------------===//
 
-class PState<string name, bits<5> encoding> : SearchableTable {
-  let SearchableFields = ["Name", "Encoding"];
-  let EnumValueField = "Encoding";
-
+class PState<string name, bits<5> encoding> {
   string Name = name;
   bits<5> Encoding;
   let Encoding = encoding;
   code Requires = [{ {} }];
 }
 
+def PStateValues : GenericEnum {
+  let FilterClass = "PState";
+  let NameField = "Name";
+  let ValueField = "Encoding";
+}
+
+def PStatesList : GenericTable {
+  let FilterClass = "PState";
+  let Fields = ["Name", "Encoding", "Requires"];
+
+  let PrimaryKey = ["Encoding"];
+  let PrimaryKeyName = "lookupPStateByEncoding";
+}
+
+def lookupPStateByName : SearchIndex {
+  let Table = PStatesList;
+  let Key = ["Name"];
+}
+
 def : PState<"SPSel",   0b00101>;
 def : PState<"DAIFSet", 0b11110>;
 def : PState<"DAIFClr", 0b11111>;
 // v8.1a "Privileged Access Never" extension-specific PStates
 let Requires = [{ {AArch64::HasV8_1aOps} }] in
 def : PState<"PAN",     0b00100>;
 // v8.2a "User Access Override" extension-specific PStates
 let Requires = [{ {AArch64::HasV8_2aOps} }] in
 def : PState<"UAO",     0b00011>;
 
 
 //===----------------------------------------------------------------------===//
 // PSB instruction options.
 //===----------------------------------------------------------------------===//
 
-class PSB<string name, bits<5> encoding> : SearchableTable {
-  let SearchableFields = ["Name", "Encoding"];
-  let EnumValueField = "Encoding";
-
+class PSB<string name, bits<5> encoding> {
   string Name = name;
   bits<5> Encoding;
   let Encoding = encoding;
 }
 
+def PSBsList : GenericTable {
+  let FilterClass = "PSB";
+  let Fields = ["Name", "Encoding"];
+
+  let PrimaryKey = ["Encoding"];
+  let PrimaryKeyName = "lookupPSBByEncoding";
+}
+
+def lookupPSBByName : SearchIndex {
+  let Table = PSBsList;
+  let Key = ["Name"];
+}
+
 def : PSB<"csync", 0x11>;
 
 //===----------------------------------------------------------------------===//
 // TLBI (translation lookaside buffer invalidate) instruction options.
 //===----------------------------------------------------------------------===//
 
 class TLBI<string name, bits<3> op1, bits<4> crn, bits<4> crm,
-             bits<3> op2, bit needsreg = 1> : SearchableTable {
-  let SearchableFields = ["Name", "Encoding"];
-  let EnumValueField = "Encoding";
-
+             bits<3> op2, bit needsreg = 1> {
   string Name = name;
   bits<14> Encoding;
   let Encoding{13-11} = op1;
   let Encoding{10-7} = crn;
   let Encoding{6-3} = crm;
   let Encoding{2-0} = op2;
   bit NeedsReg = needsreg;
 }
 
+def TLBIsList : GenericTable {
+  let FilterClass = "TLBI";
+  let Fields = ["Name", "Encoding", "NeedsReg"];
+
+  let PrimaryKey = ["Encoding"];
+  let PrimaryKeyName = "lookupTLBIByEncoding";
+}
+
+def lookupTLBIByName : SearchIndex {
+  let Table = TLBIsList;
+  let Key = ["Name"];
+}
+
 def : TLBI<"IPAS2E1IS",    0b100, 0b1000, 0b0000, 0b001>;
 def : TLBI<"IPAS2LE1IS",   0b100, 0b1000, 0b0000, 0b101>;
 def : TLBI<"VMALLE1IS",    0b000, 0b1000, 0b0011, 0b000, 0>;
 def : TLBI<"ALLE2IS",      0b100, 0b1000, 0b0011, 0b000, 0>;
 def : TLBI<"ALLE3IS",      0b110, 0b1000, 0b0011, 0b000, 0>;
 def : TLBI<"VAE1IS",       0b000, 0b1000, 0b0011, 0b001>;
 def : TLBI<"VAE2IS",       0b100, 0b1000, 0b0011, 0b001>;
 def : TLBI<"VAE3IS",       0b110, 0b1000, 0b0011, 0b001>;

 def : TLBI<"VAALE1",       0b000, 0b1000, 0b0111, 0b111>;
 
 
 //===----------------------------------------------------------------------===//
 // MRS/MSR (system register read/write) instruction options.
 //===----------------------------------------------------------------------===//
 
 class SysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
-             bits<3> op2> : SearchableTable {
-  let SearchableFields = ["Name", "Encoding"];
-  let EnumValueField = "Encoding";
-
+             bits<3> op2> {
   string Name = name;
   bits<16> Encoding;
   let Encoding{15-14} = op0;
   let Encoding{13-11} = op1;
   let Encoding{10-7} = crn;
   let Encoding{6-3} = crm;
   let Encoding{2-0} = op2;
   bit Readable = ?;
   bit Writeable = ?;
   code Requires = [{ {} }];
 }
 
+def SysRegValues : GenericEnum {
+  let FilterClass = "SysReg";
+  let NameField = "Name";
+  let ValueField = "Encoding";
+}
+
+def SysRegsList : GenericTable {
+  let FilterClass = "SysReg";
+  let Fields = ["Name", "Encoding", "Readable", "Writeable", "Requires"];
+
+  let PrimaryKey = ["Encoding"];
+  let PrimaryKeyName = "lookupSysRegByEncoding";
+}
+
+def lookupSysRegByName : SearchIndex {
+  let Table = SysRegsList;
+  let Key = ["Name"];
+}
+
 class RWSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
                bits<3> op2>
     : SysReg<name, op0, op1, crn, crm, op2> {
   let Readable = 1;
   let Writeable = 1;
 }
 
 class ROSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,

lib/Target/AArch64/Utils/AArch64BaseInfo.h

struct SysAliasReg : SysAlias {
   bool NeedsReg;
   SysAliasReg(const char *N, uint16_t E, bool R) : SysAlias(N, E), NeedsReg(R) {};
 };
 
 namespace AArch64AT{
   struct AT : SysAlias {
     using SysAlias::SysAlias;
   };
-  #define GET_AT_DECL
+  #define GET_ATsList_DECL
   #include "AArch64GenSystemOperands.inc"
 }
 
 namespace AArch64DB {
   struct DB : SysAlias {
     using SysAlias::SysAlias;
   };
-  #define GET_DB_DECL
+  #define GET_DBValues_DECL
+  #define GET_DBsList_DECL
   #include "AArch64GenSystemOperands.inc"
 }
 
 namespace  AArch64DC {
   struct DC : SysAlias {
     using SysAlias::SysAlias;
   };
-  #define GET_DC_DECL
+  #define GET_DCsList_DECL
   #include "AArch64GenSystemOperands.inc"
 }
 
 namespace  AArch64IC {
   struct IC : SysAliasReg {
     using SysAliasReg::SysAliasReg;
   };
-  #define GET_IC_DECL
+  #define GET_ICsList_DECL
   #include "AArch64GenSystemOperands.inc"
 }
 
 namespace  AArch64ISB {
   struct ISB : SysAlias {
     using SysAlias::SysAlias;
   };
-  #define GET_ISB_DECL
+  #define GET_ISBsList_DECL
   #include "AArch64GenSystemOperands.inc"
 }
 
 namespace AArch64PRFM {
   struct PRFM : SysAlias {
     using SysAlias::SysAlias;
   };
-  #define GET_PRFM_DECL
+  #define GET_PRFMsList_DECL
   #include "AArch64GenSystemOperands.inc"
 }
 
 namespace AArch64SVEPRFM {
   struct SVEPRFM : SysAlias {
     using SysAlias::SysAlias;
   };
-#define GET_SVEPRFM_DECL
+#define GET_SVEPRFMsList_DECL
 #include "AArch64GenSystemOperands.inc"
 }
 
 namespace AArch64SVEPredPattern {
   struct SVEPREDPAT {
     const char *Name;
     uint16_t Encoding;
   };
-#define GET_SVEPREDPAT_DECL
+#define GET_SVEPREDPATsList_DECL
 #include "AArch64GenSystemOperands.inc"
 }
 
 namespace AArch64ExactFPImm {
   struct ExactFPImm {
     const char *Name;
     int Enum;
     const char *Repr;
   };
-#define GET_EXACTFPIMM_DECL
+#define GET_ExactFPImmValues_DECL
+#define GET_ExactFPImmsList_DECL
 #include "AArch64GenSystemOperands.inc"
 }
 
 namespace AArch64PState {
   struct PState : SysAlias{
     using SysAlias::SysAlias;
   };
-  #define GET_PSTATE_DECL
+  #define GET_PStateValues_DECL
+  #define GET_PStatesList_DECL
   #include "AArch64GenSystemOperands.inc"
 }
 
 namespace AArch64PSBHint {
   struct PSB : SysAlias {
     using SysAlias::SysAlias;
   };
-  #define GET_PSB_DECL
+  #define GET_PSBsList_DECL
   #include "AArch64GenSystemOperands.inc"
 }
 
 namespace AArch64SE {
     enum ShiftExtSpecifiers {
         Invalid = -1,
         LSL,
         MSL,
struct SysReg {
     bool Writeable;
     FeatureBitset FeaturesRequired;
 
     bool haveFeatures(FeatureBitset ActiveFeatures) const {
       return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
     }
   };
 
-  #define GET_SYSREG_DECL
+  #define GET_SysRegValues_DECL
+  #define GET_SysRegsList_DECL
   #include "AArch64GenSystemOperands.inc"
 
   const SysReg *lookupSysRegByName(StringRef);
   const SysReg *lookupSysRegByEncoding(uint16_t);
 
   uint32_t parseGenericRegister(StringRef Name);
   std::string genericRegisterString(uint32_t Bits);
 }
 
 namespace AArch64TLBI {
   struct TLBI : SysAliasReg {
     using SysAliasReg::SysAliasReg;
   };
-  #define GET_TLBI_DECL
+  #define GET_TLBIsList_DECL
   #include "AArch64GenSystemOperands.inc"
 }
 
 namespace AArch64II {
   /// Target Operand Flag enum.
   enum TOF {
     //===------------------------------------------------------------------===//
     // AArch64 Specific MachineOperand flags.

lib/Target/AArch64/Utils/AArch64BaseInfo.cpp

 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/Support/Regex.h"
 
 using namespace llvm;
 
 namespace llvm {
   namespace AArch64AT {
-#define GET_AT_IMPL
+#define GET_ATsList_IMPL
 #include "AArch64GenSystemOperands.inc"
   }
 }
 
 
 namespace llvm {
   namespace AArch64DB {
-#define GET_DB_IMPL
+#define GET_DBsList_IMPL
 #include "AArch64GenSystemOperands.inc"
   }
 }
 
 namespace llvm {
   namespace AArch64DC {
-#define GET_DC_IMPL
+#define GET_DCsList_IMPL
 #include "AArch64GenSystemOperands.inc"
   }
 }
 
 namespace llvm {
   namespace AArch64IC {
-#define GET_IC_IMPL
+#define GET_ICsList_IMPL
 #include "AArch64GenSystemOperands.inc"
   }
 }
 
 namespace llvm {
   namespace AArch64ISB {
-#define GET_ISB_IMPL
+#define GET_ISBsList_IMPL
 #include "AArch64GenSystemOperands.inc"
   }
 }
 namespace llvm {
   namespace AArch64PRFM {
-#define GET_PRFM_IMPL
+#define GET_PRFMsList_IMPL
 #include "AArch64GenSystemOperands.inc"
   }
 }
 
 namespace llvm {
   namespace AArch64SVEPRFM {
-#define GET_SVEPRFM_IMPL
+#define GET_SVEPRFMsList_IMPL
 #include "AArch64GenSystemOperands.inc"
   }
 }
 
 namespace llvm {
   namespace AArch64SVEPredPattern {
-#define GET_SVEPREDPAT_IMPL
+#define GET_SVEPREDPATsList_IMPL
 #include "AArch64GenSystemOperands.inc"
   }
 }
 
 namespace llvm {
   namespace AArch64ExactFPImm {
-#define GET_EXACTFPIMM_IMPL
+#define GET_ExactFPImmsList_IMPL
 #include "AArch64GenSystemOperands.inc"
   }
 }
 
 namespace llvm {
   namespace AArch64PState {
-#define GET_PSTATE_IMPL
+#define GET_PStatesList_IMPL
 #include "AArch64GenSystemOperands.inc"
   }
 }
 
 namespace llvm {
   namespace AArch64PSBHint {
-#define GET_PSB_IMPL
+#define GET_PSBsList_IMPL
 #include "AArch64GenSystemOperands.inc"
   }
 }
 
 namespace llvm {
   namespace AArch64SysReg {
-#define GET_SYSREG_IMPL
+#define GET_SysRegsList_IMPL
 #include "AArch64GenSystemOperands.inc"
   }
 }
 
 uint32_t AArch64SysReg::parseGenericRegister(StringRef Name) {
   // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
   Regex GenericRegPattern("^S([0-3])_([0-7])_C([0-9]|1[0-5])_C([0-9]|1[0-5])_([0-7])$");
 
std::string AArch64SysReg::genericRegisterString(uint32_t Bits) {
   uint32_t Op2 = Bits & 0x7;
 
   return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" +
          utostr(CRm) + "_" + utostr(Op2);
 }
 
 namespace llvm {
   namespace AArch64TLBI {
-#define GET_TLBI_IMPL
+#define GET_TLBIsList_IMPL
 #include "AArch64GenSystemOperands.inc"
   }
 }

lib/Target/ARM/ARMSystemRegister.td

 
 // M-Class System Registers.
 // 'Mask' bits create unique keys for searches.
 //
 class MClassSysReg<bits<1> UniqMask1,
                    bits<1> UniqMask2,
                    bits<1> UniqMask3,
                    bits<12> Enc12,
-                   string name> : SearchableTable {
-  let SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
+                   string name> {
   string Name;
   bits<13> M1Encoding12;
   bits<10> M2M3Encoding8;
   bits<12> Encoding;
 
   let Name = name;
-  let EnumValueField = "M1Encoding12";
-  let EnumValueField = "M2M3Encoding8";
-  let EnumValueField = "Encoding";
 
   let M1Encoding12{12}    = UniqMask1;
   let M1Encoding12{11-00} = Enc12;
   let Encoding            = Enc12;
 
   let M2M3Encoding8{9}    = UniqMask2;
   let M2M3Encoding8{8}    = UniqMask3;
   let M2M3Encoding8{7-0}  = Enc12{7-0};
   code Requires           = [{ {} }];
 }
 
+def MClassSysRegValues : GenericEnum {
+  let FilterClass = "MClassSysReg";
+  let NameField = "Name";
+  let ValueField = "Encoding";
+}
+
+def MClassSysRegsList : GenericTable {
+  let FilterClass = "MClassSysReg";
+  let Fields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding", "Requires"];
+
+  let PrimaryKey = ["M1Encoding12"];
+  let PrimaryKeyName = "lookupMClassSysRegByM1Encoding12";
+}
+
+def lookupMClassSysRegByM2M3Encoding8 : SearchIndex {
+  let Table = MClassSysRegsList;
+  let Key = ["M2M3Encoding8"];
+}
+
+def lookupMClassSysRegByName : SearchIndex {
+  let Table = MClassSysRegsList;
+  let Key = ["Name"];
+}
+
 // [|i|e|x]apsr_nzcvq has alias [|i|e|x]apsr.
 //                 Mask1 Mask2 Mask3 Enc12, Name
 let Requires = [{ {ARM::FeatureDSP} }] in {
 def : MClassSysReg<0,    0,    0,    0x400, "apsr_g">;
 def : MClassSysReg<0,    1,    1,    0xc00, "apsr_nzcvqg">;
 def : MClassSysReg<0,    0,    0,    0x401, "iapsr_g">;
 def : MClassSysReg<0,    1,    1,    0xc01, "iapsr_nzcvqg">;
 def : MClassSysReg<0,    0,    0,    0x402, "eapsr_g">;

 let Requires = [{ {ARM::Feature8MSecExt} }] in {
 def : MClassSysReg<0,    0,    1,    0x894, "control_ns">;
 def : MClassSysReg<0,    0,    1,    0x898, "sp_ns">;
 }
 
 
 // Banked Registers
 //
-class BankedReg<string name,  bits<8> enc>
-               : SearchableTable {
+class BankedReg<string name,  bits<8> enc> {
   string Name;
   bits<8> Encoding;
   let Name = name;
   let Encoding = enc;
-  let SearchableFields = ["Name", "Encoding"];
+}
+
+def BankedRegsList : GenericTable {
+  let FilterClass = "BankedReg";
+  let Fields = ["Name", "Encoding"];
+
+  let PrimaryKey = ["Encoding"];
+  let PrimaryKeyName = "lookupBankedRegByEncoding";
+}
+
+def lookupBankedRegByName : SearchIndex {
+  let Table = BankedRegsList;
+  let Key = ["Name"];
 }
 
 // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM
 // and bit 5 is R.
 def : BankedReg<"r8_usr",   0x00>;
 def : BankedReg<"r9_usr",   0x01>;
 def : BankedReg<"r10_usr",  0x02>;
 def : BankedReg<"r11_usr",  0x03>;

lib/Target/ARM/Utils/ARMBaseInfo.h

struct MClassSysReg {
     }
 
     // returns true if TestFeatures are all present in FeaturesRequired
     bool isInRequiredFeatures(FeatureBitset TestFeatures) const {
       return (FeaturesRequired & TestFeatures) == TestFeatures;
     }
   };
 
-  #define GET_MCLASSSYSREG_DECL
+  #define GET_MClassSysRegValues_DECL
+  #define GET_MClassSysRegsList_DECL
   #include "ARMGenSystemRegister.inc"
 
   // lookup system register using 12-bit SYSm value.
   // Note: the search is uniqued using M1 mask
   const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm);
 
   // returns APSR with _<bits> qualifier.
   // Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
   const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm);
 
   // lookup system registers using 8-bit SYSm value
   const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm);
 
 } // end namespace ARMSysReg
 
 // Banked Registers
 namespace ARMBankedReg {
   struct BankedReg {
     const char *Name;
     uint16_t Encoding;
   };
-  #define GET_BANKEDREG_DECL
+  #define GET_BankedRegsList_DECL
   #include "ARMGenSystemRegister.inc"
 } // end namespace ARMBankedReg
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H

lib/Target/ARM/Utils/ARMBaseInfo.cpp

const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm) {
   return lookupMClassSysRegByM2M3Encoding8((1<<9)|(SYSm & 0xFF));
 }
 
 // lookup system registers using 8-bit SYSm value
 const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm) {
   return ARMSysReg::lookupMClassSysRegByM2M3Encoding8((1<<8)|(SYSm & 0xFF));
 }
 
-#define GET_MCLASSSYSREG_IMPL
+#define GET_MClassSysRegsList_IMPL
 #include "ARMGenSystemRegister.inc"
 
 } // end namespace ARMSysReg
 
 namespace ARMBankedReg {
-#define GET_BANKEDREG_IMPL
+#define GET_BankedRegsList_IMPL
 #include "ARMGenSystemRegister.inc"
 } // end namespce ARMSysReg
 } // end namespace llvm