[AArch64][SVE] Add StepVector Intrinsic

[huntergr]

Summary

Adds the following:

• experimental_vector_stepvector intrinsic, which represents a runtime vector containing a monotically increasing sequence of the form <0, 1, 2, ....n-1>, where 'n' is the total number of elements of the given type.

• AArch64ISD::SERIES_VECTOR, a target specific ISD to represent this sequence concept in the AArch64 backend, along with code to lower the stepvector intrinsic to this node.

• ISel patterns to select 'index' instructions for series_vector nodes.

• Unit tests for scalable vectors of the various integer types.

Part of the initial SVE codegen series, rfc will be posted soon. Note: this patch is currently just to support the scalable vector codegen rfc, and does not need a full review yet.

[huntergr]

Needs to be updated with better isel patterns, instead of just the bare minimum required for demonstration.

include/llvm/IR/Intrinsics.td

 
 //===----- Intrinsics that are used to provide predicate information -----===//
 
 def int_ssa_copy : Intrinsic<[llvm_any_ty], [LLVMMatchType<0>],
                              [IntrNoMem, Returned<0>]>;
 
 //===--------- Intrinsics that are used with scalable vector types --------===//
 
+def int_experimental_vector_stepvector : Intrinsic<[llvm_anyvector_ty],
+                                                   [],
+                                                   [IntrNoMem]>;
+
 def int_experimental_vector_vscale : Intrinsic<[llvm_anyint_ty],
                                                [],
                                                [IntrNoMem]>;
 
 //===----------------------------------------------------------------------===//
 // Target-specific intrinsics
 //===----------------------------------------------------------------------===//
 

lib/Target/AArch64/AArch64ISelLowering.h

enum NodeType : unsigned {
 
   // SVE specific
   /// VSCALE(IMM) - Returns the runtime scaling factor used to calculate the
   /// number of elements within a scalable vector.  IMM is a constant integer
   /// multiplier that is applied to the runtime value and is usual some
   /// multiple of MVT.getVectorNumElements().
   VSCALE,
 
+  /// SERIES_VECTOR(INITIAL, STEP) - Creates a vector, with the first lane
+  /// containing INITIAL and each subsequent lane incremented by STEP
+  SERIES_VECTOR,
+
   // NEON Load/Store with post-increment base updates
   LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
   LD3post,
   LD4post,
   ST2post,
   ST3post,
   ST4post,
   LD1x2post,

lib/Target/AArch64/AArch64ISelLowering.cpp

const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
   case AArch64ISD::ST4LANEpost:       return "AArch64ISD::ST4LANEpost";
   case AArch64ISD::SMULL:             return "AArch64ISD::SMULL";
   case AArch64ISD::UMULL:             return "AArch64ISD::UMULL";
   case AArch64ISD::FRECPE:            return "AArch64ISD::FRECPE";
   case AArch64ISD::FRECPS:            return "AArch64ISD::FRECPS";
   case AArch64ISD::FRSQRTE:           return "AArch64ISD::FRSQRTE";
   case AArch64ISD::FRSQRTS:           return "AArch64ISD::FRSQRTS";
   case AArch64ISD::VSCALE:            return "AArch64ISD::VSCALE";
+  case AArch64ISD::SERIES_VECTOR:     return "AArch64ISD::SERIES_VECTOR";
   }
   return nullptr;
 }
 
 MachineBasicBlock *
 AArch64TargetLowering::EmitF128CSEL(MachineInstr &MI,
                                     MachineBasicBlock *MBB) const {
   // We materialise the F128CSEL pseudo-instruction as some control flow and a
case Intrinsic::experimental_vector_vscale: {
     // TODO: Something smarter than just using a constant of 1
     auto VScale = DAG.getNode(AArch64ISD::VSCALE, dl, MVT::i64,
                               DAG.getConstant(1, dl, MVT::i32));
     if (VT != MVT::i64)
       VScale = DAG.getZExtOrTrunc(VScale, dl, VT);
 
     return VScale;
   }
+  case Intrinsic::experimental_vector_stepvector: {
+    auto ScalarVT = VT.getScalarType();
+    assert (ScalarVT.isInteger() &&
+            "Attempted to get a floating point stepvector");
+    // Legalize the input types; anything smaller than an i64
+    // will use the 32b w regs instead.
+    if (ScalarVT != MVT::i64)
+      ScalarVT = MVT::i32;
+    auto SeriesVec = DAG.getNode(AArch64ISD::SERIES_VECTOR, dl, VT,
+                                 DAG.getConstant(0, dl, ScalarVT),
+                                 DAG.getConstant(1, dl, ScalarVT));
+    return SeriesVec;
+  }
   }
 }
 
 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
                                               SelectionDAG &DAG) const {
   LLVM_DEBUG(dbgs() << "Custom lowering: ");
   LLVM_DEBUG(Op.dump());
 

lib/Target/AArch64/AArch64SVEInstrInfo.td

 //=- AArch64SVEInstrInfo.td -  AArch64 SVE Instructions -*- tablegen -*-----=//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // AArch64 Scalable Vector Extension (SVE) Instruction definitions.
 //
 //===----------------------------------------------------------------------===//
 
 def SDT_AArch64VScale : SDTypeProfile<1, 1, [SDTCisVT<0,i64>, SDTCisInt<1>]>; 
+def SDT_AArch64SeriesVector : SDTypeProfile<1, 2, [
+  SDTCisVec<0>, SDTCisSameAs<1,2>, SDTCisInt<2>
+]>;
 def AArch64vscale : SDNode<"AArch64ISD::VSCALE", SDT_AArch64VScale>;
+def AArch64seriesvec : SDNode<"AArch64ISD::SERIES_VECTOR", SDT_AArch64SeriesVector>;
+
 let Predicates = [HasSVE] in {
   defm ADD_ZZZ   : sve_int_bin_cons_arit_0<0b000, "add">;
   defm SUB_ZZZ   : sve_int_bin_cons_arit_0<0b001, "sub">;
 
   def AND_ZZZ : sve_int_bin_cons_log<0b00, "and">;
   def ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr">;
   def EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor">;
   def BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic">;
let Predicates = [HasSVE] in {
   def : InstAlias<"mov $Zd, $Zn",
                   (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn), 1>;
 
 
   // Simple codegen Patterns
   // Unoptimized vscale
   def : Pat<(AArch64vscale (simm6_32b:$imm)), (RDVLI_XI $imm)>;
 
+
+  // Unoptimized seriesvector patterns
+  def : Pat<(nxv16i8 (AArch64seriesvec GPR32:$start, GPR32:$step)),
+            (INDEX_RR_B $start, $step)>;
+  def : Pat<(nxv8i16 (AArch64seriesvec GPR32:$start, GPR32:$step)),
+            (INDEX_RR_H $start, $step)>;
+  def : Pat<(nxv4i32 (AArch64seriesvec GPR32:$start, GPR32:$step)),
+            (INDEX_RR_S $start, $step)>;
+  def : Pat<(nxv2i64 (AArch64seriesvec GPR64:$start, GPR64:$step)),
+            (INDEX_RR_D $start, $step)>;
+
 }

test/CodeGen/AArch64/SVE/index.ll

+; RUN: llc -verify-machineinstrs -mattr=+sve < %s | FileCheck %s
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64--linux-gnueabi"
+
+declare <scalable 16 x i8> @llvm.experimental.vector.stepvector.nxv16i8()
+declare <scalable 8 x i16> @llvm.experimental.vector.stepvector.nxv8i16()
+declare <scalable 4 x i32> @llvm.experimental.vector.stepvector.nxv4i32()
+declare <scalable 2 x i64> @llvm.experimental.vector.stepvector.nxv2i64()
+
+define <scalable 16 x i8> @index_b() {
+; CHECK-LABEL: index_b:
+; CHECK: orr [[STEP:w[0-9]+]], wzr, #0x1
+; CHECK: index z0.b, wzr, [[STEP]]
+; CHECK: ret
+  %ident = call <scalable 16 x i8> @llvm.experimental.vector.stepvector.nxv16i8()
+  ret <scalable 16 x i8> %ident
+}
+
+define <scalable 8 x i16> @index_h() {
+; CHECK-LABEL: index_h:
+; CHECK: orr [[STEP:w[0-9]+]], wzr, #0x1
+; CHECK: index z0.h, wzr, [[STEP]]
+; CHECK: ret
+  %ident = call <scalable 8 x i16> @llvm.experimental.vector.stepvector.nxv8i16()
+  ret <scalable 8 x i16> %ident
+}
+
+define <scalable 4 x i32> @index_s() {
+; CHECK-LABEL: index_s:
+; CHECK: orr [[STEP:w[0-9]+]], wzr, #0x1
+; CHECK: index z0.s, wzr, [[STEP]]
+; CHECK: ret
+  %ident = call <scalable 4 x i32> @llvm.experimental.vector.stepvector.nxv4i32()
+  ret <scalable 4 x i32> %ident
+}
+
+define <scalable 2 x i64> @index_d() {
+; CHECK-LABEL: index_d:
+; CHECK: orr w[[STEP:[0-9]+]], wzr, #0x1
+; CHECK: index z0.d, xzr, x[[STEP]]
+; CHECK: ret
+  %ident = call <scalable 2 x i64> @llvm.experimental.vector.stepvector.nxv2i64()
+  ret <scalable 2 x i64> %ident
+}