[AArch64][SVE] Enable DiagnosticPredicates for SVE LD1 instructions.

[sdesmalen]

Summary

This patch extends the PredicateMethod of AsmOperands used in SVE's
LD1 instructions with a DiagnosticPredicate. This makes them 'context
sensitive' to the operand that has been parsed and tells the user to
use the right register (with expected shift/extend), rather than telling
the immediate is out of range when it actually parsed a register.

Patch [2/2] in a series to improve assembler diagnostics for SVE:

• Patch [1/2]: https://reviews.llvm.org/D45879
• Patch [2/2]: https://reviews.llvm.org/D45880

[fhahn]

LGTM

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

509–514

Do we need this change for the patch?

[sdesmalen]

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

509–514

This keeps the diagnostic behaviour the same for instructions that use MemoryIndexSImm7. The intention of this patch is to only change the diagnostics for SVE LD1.

[rengolin]

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

527–530

I think this would be more explicit on how it returns math/no-match instead of converting a boolean to an enum.

this would prevent future changes of the enum class and implicit assumptions. same down there.

[sdesmalen]

• Made return values explicit (Match/NoMatch/NearMatch)

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

bool hasShiftExtendAmount() const {
     llvm_unreachable("Invalid access!");
   }
 
   bool isImm() const override { return Kind == k_Immediate; }
   bool isMem() const override { return false; }
 
   template <int Width> bool isSImm() const { return isSImmScaled<Width, 1>(); }
 
-  template <int Bits, int Scale> bool isSImmScaled() const {
+  template <int Scale> bool isMemoryIndexSImm7() const {
+    return (bool) isSImmScaled<7, 4>();
+  }
+
+  template <int Bits, int Scale>
+  DiagnosticPredicate isSImmScaled() const {
     if (!isImm())
-      return false;
+      return DiagnosticPredicateTy::NoMatch;
+
     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
     if (!MCE)
-      return false;
+      return DiagnosticPredicateTy::NoMatch;
 
     int64_t Shift = Bits - 1;
     int64_t MinVal = (int64_t(1) << Shift) * -Scale;
     int64_t MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
 
     int64_t Val = MCE->getValue();
-    return Val >= MinVal && Val <= MaxVal && (Val % Scale) == 0;
+    if (Val >= MinVal && Val <= MaxVal && (Val % Scale) == 0)
+      return DiagnosticPredicateTy::Match;
+
+    return DiagnosticPredicateTy::NearMatch;
   }
 
   bool isSVEPattern() const {
     if (!isImm())
       return false;
     auto *MCE = dyn_cast<MCConstantExpr>(getImm());
     if (!MCE)
       return false;
public:
   }
 
   template <unsigned RegClassID> bool isGPR64() const {
     return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
            AArch64MCRegisterClasses[RegClassID].contains(getReg());
   }
 
   template <unsigned RegClassID, int ExtWidth>
-  bool isGPR64WithShiftExtend() const {
-    if (!isGPR64<RegClassID>())
-      return false;
-
-    return getShiftExtendType() == AArch64_AM::LSL &&
-           getShiftExtendAmount() == Log2_32(ExtWidth / 8);
+  DiagnosticPredicate isGPR64WithShiftExtend() const {
+    if (Kind != k_Register)
+      return DiagnosticPredicateTy::NoMatch;
+
+    if (isGPR64<RegClassID>() && getShiftExtendType() == AArch64_AM::LSL &&
+        getShiftExtendAmount() == Log2_32(ExtWidth / 8))
+      return DiagnosticPredicateTy::Match;
+    return DiagnosticPredicateTy::NearMatch;
   }
 
   /// Is this a vector list with the type implicit (presumably attached to the
   /// instruction itself)?
   template <RegKind VectorKind, unsigned NumRegs>
   bool isImplicitlyTypedVectorList() const {
     return Kind == k_VectorList && VectorList.Count == NumRegs &&
            VectorList.NumElements == 0 &&

test/MC/AArch64/SVE/ld1b-diagnostics.s

 // CHECK-NEXT: ld1b { v0.2d }, p0/z, [x1, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + scalar addressing modes
 
 ld1b z0.b, p0/z, [x0, xzr]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
 // CHECK-NEXT: ld1b z0.b, p0/z, [x0, xzr]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1b z0.b, p0/z, [x0, x0, lsl #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
 // CHECK-NEXT: ld1b z0.b, p0/z, [x0, x0, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1b z0.b, p0/z, [x0, w0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
 // CHECK-NEXT: ld1b z0.b, p0/z, [x0, w0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1b z0.b, p0/z, [x0, w0, uxtw]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
 // CHECK-NEXT: ld1b z0.b, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1d-diagnostics.s

 // CHECK-NEXT: ld1d { v0.2d }, p0/z, [x1, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + scalar addressing modes
 
 ld1d z0.d, p0/z, [x0, x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1d z0.d, p0/z, [x0, xzr]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, xzr]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1d z0.d, p0/z, [x0, x0, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, x0, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1d z0.d, p0/z, [x0, w0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, w0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1d z0.d, p0/z, [x0, w0, uxtw]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1h-diagnostics.s

 // CHECK-NEXT: ld1h { v0.2d }, p0/z, [x1, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + scalar addressing modes
 
 ld1h z0.h, p0/z, [x0, x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
 // CHECK-NEXT: ld1h z0.h, p0/z, [x0, x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h z0.h, p0/z, [x0, xzr]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
 // CHECK-NEXT: ld1h z0.h, p0/z, [x0, xzr]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h z0.h, p0/z, [x0, x0, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
 // CHECK-NEXT: ld1h z0.h, p0/z, [x0, x0, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h z0.h, p0/z, [x0, w0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
 // CHECK-NEXT: ld1h z0.h, p0/z, [x0, w0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h z0.h, p0/z, [x0, w0, uxtw]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
 // CHECK-NEXT: ld1h z0.h, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1sb-diagnostics.s

 // CHECK-NEXT: ld1sb { v0.2d }, p0/z, [x1, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + scalar addressing modes
 
 ld1sb z0.h, p0/z, [x0, xzr]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
 // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, xzr]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sb z0.h, p0/z, [x0, x0, lsl #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
 // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, x0, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sb z0.h, p0/z, [x0, w0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
 // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, w0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sb z0.h, p0/z, [x0, w0, uxtw]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
 // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1sh-diagnostics.s

 // CHECK-NEXT: ld1sh { v0.2d }, p0/z, [x1, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + scalar addressing modes
 
 ld1sh z0.s, p0/z, [x0, x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
 // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z0.s, p0/z, [x0, xzr]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
 // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, xzr]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z0.s, p0/z, [x0, x0, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
 // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, x0, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z0.s, p0/z, [x0, w0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
 // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, w0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z0.s, p0/z, [x0, w0, uxtw]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
 // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1sw-diagnostics.s

 // CHECK-NEXT: ld1sw { v0.2d }, p0/z, [x1, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + scalar addressing modes
 
 ld1sw z0.d, p0/z, [x0, x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, xzr]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, xzr]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, x0, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, x0, lsl #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, w0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, w0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, w0, uxtw]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE/ld1w-diagnostics.s

 // CHECK-NEXT: ld1w { v0.2d }, p0/z, [x1, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 
 // --------------------------------------------------------------------------//
 // Invalid scalar + scalar addressing modes
 
 ld1w z0.s, p0/z, [x0, x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w z0.s, p0/z, [x0, xzr]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, xzr]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w z0.s, p0/z, [x0, x0, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, x0, lsl #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w z0.s, p0/z, [x0, w0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, w0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w z0.s, p0/z, [x0, w0, uxtw]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: