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Differential D36747

[Asm, ARM] Add fallback diag for multiple invalid operands
ClosedPublic

Authored by olista01 on Aug 15 2017, 8:24 AM.

Details

Reviewers
rengolin
echristo
SjoerdMeijer
javed.absar
Commits
rG7cd4db94f8ca: [Asm, ARM] Add fallback diag for multiple invalid operands
rL319649: [Asm, ARM] Add fallback diag for multiple invalid operands
Summary

This adds a "invalid operands for instruction" diagnostic for
instructions where there is an instruction encoding with the correct
mnemonic and which is available for this target, but where multiple
operands do not match those which were provided. This makes it clear
that there is some combination of operands that is valid for the current
target, which the default diagnostic of "invalid instruction" does not.

Since this is a very general error, we only emit it if we don't have a
more specific error.

Diff Detail

Event Timeline

olista01 created this revision.Aug 15 2017, 8:24 AM
Herald added subscribers: kristof.beyls, javed.absar, aemerson. · View Herald TranscriptAug 15 2017, 8:24 AM
olista01 added a parent revision: D36746: [Asm] Improve "too few operands" errors.Aug 15 2017, 8:26 AM
olista01 added a comment.Nov 21 2017, 4:01 AM

Ping

javed.absar added inline comments.Nov 21 2017, 4:10 AM
include/llvm/MC/MCParser/MCTargetAsmParser.h
192 ↗(On Diff #111174)

Would it be a good idea to have a message string with the assert, summarises expectation mismatch?

olista01 updated this revision to Diff 123896.Nov 22 2017, 3:03 AM

Add messages to assertions.

olista01 added a comment.Dec 4 2017, 2:18 AM

Ping

olista01 added a reviewer: javed.absar.Dec 4 2017, 3:12 AM
javed.absar accepted this revision.Dec 4 2017, 3:39 AM

LGTM. Thanks for this.

This revision is now accepted and ready to land.Dec 4 2017, 3:39 AM
SjoerdMeijer added inline comments.Dec 4 2017, 3:44 AM
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
10283 ↗(On Diff #123896)

nit: 'teh' spell error

Closed by commit rL319649: [Asm, ARM] Add fallback diag for multiple invalid operands (authored by olista01). · Explain WhyDec 4 2017, 4:03 AM
This revision was automatically updated to reflect the committed changes.
olista01 reopened this revision.Dec 4 2017, 5:48 AM

I've reverted this because it is causing a buildbot failure - http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/6552/steps/test-check-all/logs/stdio.

It's not clear to me what the problem is from the lit output, and I haven't been able to reproduce the failure locally by enabling expensive checks. This looks very similar to the problem Sander hit in D40011.

This revision is now accepted and ready to land.Dec 4 2017, 5:48 AM
Closed by commit rG7cd4db94f8ca: [Asm, ARM] Add fallback diag for multiple invalid operands (authored by olista01). · Explain WhyOct 7 2019, 5:06 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptOct 7 2019, 5:06 AM
Herald added a subscriber: hiraditya. · View Herald Transcript

Revision Contents

PathSize
llvm/
include/
llvm/
MC/
MCParser/
27 lines
lib/
Target/
ARM/
AsmParser/
17 lines
test/
MC/
ARM/
6 lines
24 lines
14 lines
8 lines
8 lines
8 lines
4 lines
6 lines
11 lines
12 lines
utils/
TableGen/
23 lines

Diff 223516

llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h

Show First 20 Lines • Show All 137 Lines • ▼ Show 20 Lines
// the programmer intended to use, so we want to report an error which mentions // the programmer intended to use, so we want to report an error which mentions
// each of these "near-miss" encodings. This struct contains information about // each of these "near-miss" encodings. This struct contains information about
// one such encoding, and why it did not match the parsed instruction. // one such encoding, and why it did not match the parsed instruction.
class NearMissInfo { class NearMissInfo {
public: public:
enum NearMissKind { enum NearMissKind {
NoNearMiss, NoNearMiss,
NearMissOperand, NearMissOperand,
NearMissMultipleOperands,
NearMissFeature, NearMissFeature,
NearMissPredicate, NearMissPredicate,
NearMissTooFewOperands, NearMissTooFewOperands,
}; };
// The encoding is valid for the parsed assembly string. This is only used // The encoding is valid for the parsed assembly string. This is only used
// internally to the table-generated assembly matcher. // internally to the table-generated assembly matcher.
static NearMissInfo getSuccess() { return NearMissInfo(); } static NearMissInfo getSuccess() { return NearMissInfo(); }
Show All 30 Lines static NearMissInfo getMissedOperand(unsigned OperandError,
Result.Kind = NearMissOperand; Result.Kind = NearMissOperand;
Result.MissedOperand.Error = OperandError; Result.MissedOperand.Error = OperandError;
Result.MissedOperand.Class = OperandClass; Result.MissedOperand.Class = OperandClass;
Result.MissedOperand.Opcode = Opcode; Result.MissedOperand.Opcode = Opcode;
Result.MissedOperand.Index = OperandIndex; Result.MissedOperand.Index = OperandIndex;
return Result; return Result;
} }
static NearMissInfo getMissedMultipleOperands(unsigned Opcode) {
NearMissInfo Result;
Result.Kind = NearMissMultipleOperands;
Result.MissedOperand.Opcode = Opcode;
return Result;
}
// The instruction encoding is not valid because it expects more operands // The instruction encoding is not valid because it expects more operands
// than were parsed. OperandClass is the class of the expected operand that // than were parsed. OperandClass is the class of the expected operand that
// was not provided. Opcode is the instruction encoding. // was not provided. Opcode is the instruction encoding.
static NearMissInfo getTooFewOperands(unsigned OperandClass, static NearMissInfo getTooFewOperands(unsigned OperandClass,
unsigned Opcode) { unsigned Opcode) {
NearMissInfo Result; NearMissInfo Result;
Result.Kind = NearMissTooFewOperands; Result.Kind = NearMissTooFewOperands;
Result.TooFewOperands.Class = OperandClass; Result.TooFewOperands.Class = OperandClass;
Result.TooFewOperands.Opcode = Opcode; Result.TooFewOperands.Opcode = Opcode;
return Result; return Result;
} }
operator bool() const { return Kind != NoNearMiss; } operator bool() const { return Kind != NoNearMiss; }
NearMissKind getKind() const { return Kind; } NearMissKind getKind() const { return Kind; }
// Feature flags required by the instruction, that the current target does // Feature flags required by the instruction, that the current target does
// not have. // not have.
uint64_t getFeatures() const { uint64_t getFeatures() const {
assert(Kind == NearMissFeature); assert(Kind == NearMissFeature &&
"near-miss does not have an associated target feature");
return Features; return Features;
} }
// Error code returned by the target predicate when validating this // Error code returned by the target predicate when validating this
// instruction encoding. // instruction encoding.
unsigned getPredicateError() const { unsigned getPredicateError() const {
assert(Kind == NearMissPredicate); assert(Kind == NearMissPredicate &&
"near-miss does not have an associated predicate error");
return PredicateError; return PredicateError;
} }
// MatchClassKind of the operand that we expected to see. // MatchClassKind of the operand that we expected to see.
unsigned getOperandClass() const { unsigned getOperandClass() const {
assert(Kind == NearMissOperand || Kind == NearMissTooFewOperands); assert((Kind == NearMissOperand || Kind == NearMissTooFewOperands) &&
"near-miss does not have an associated operand class");
return MissedOperand.Class; return MissedOperand.Class;
} }
// Opcode of the encoding we were trying to match. // Opcode of the encoding we were trying to match.
unsigned getOpcode() const { unsigned getOpcode() const {
assert(Kind == NearMissOperand || Kind == NearMissTooFewOperands); assert((Kind == NearMissOperand || Kind == NearMissTooFewOperands ||
Kind == NearMissMultipleOperands) &&
"near-miss does not have an associated opcode");
return MissedOperand.Opcode; return MissedOperand.Opcode;
} }
// Error code returned when validating the operand. // Error code returned when validating the operand.
unsigned getOperandError() const { unsigned getOperandError() const {
assert(Kind == NearMissOperand); assert(Kind == NearMissOperand &&
"near-miss does not have an associated operand error");
return MissedOperand.Error; return MissedOperand.Error;
} }
// Index of the actual operand we were trying to match in the list of parsed // Index of the actual operand we were trying to match in the list of parsed
// operands. // operands.
unsigned getOperandIndex() const { unsigned getOperandIndex() const {
assert(Kind == NearMissOperand); assert(Kind == NearMissOperand &&
"near-miss does not have an associated operand index");
return MissedOperand.Index; return MissedOperand.Index;
} }
private: private:
NearMissKind Kind; NearMissKind Kind;
// These two structs share a common prefix, so we can safely rely on the fact // These two structs share a common prefix, so we can safely rely on the fact
// that they overlap in the union. // that they overlap in the union.
▲ Show 20 Lines • Show All 185 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 10,128 Lines • ▼ Show 20 LinesARMAsmParser::FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
// Record some information about near-misses that we have already seen, so // Record some information about near-misses that we have already seen, so
// that we can avoid reporting redundant ones. For example, if there are // that we can avoid reporting redundant ones. For example, if there are
// variants of an instruction that take 8- and 16-bit immediates, we want // variants of an instruction that take 8- and 16-bit immediates, we want
// to only report the widest one. // to only report the widest one.
std::multimap<unsigned, unsigned> OperandMissesSeen; std::multimap<unsigned, unsigned> OperandMissesSeen;
SmallSet<uint64_t, 4> FeatureMissesSeen; SmallSet<uint64_t, 4> FeatureMissesSeen;
bool ReportedTooFewOperands = false; bool ReportedTooFewOperands = false;
bool HaveMultipleBadOperands = false;
// Process the near-misses in reverse order, so that we see more general ones // Process the near-misses in reverse order, so that we see more general ones
// first, and so can avoid emitting more specific ones. // first, and so can avoid emitting more specific ones.
for (NearMissInfo &I : reverse(NearMissesIn)) { for (NearMissInfo &I : reverse(NearMissesIn)) {
switch (I.getKind()) { switch (I.getKind()) {
case NearMissInfo::NearMissOperand: { case NearMissInfo::NearMissOperand: {
SMLoc OperandLoc = SMLoc OperandLoc =
((ARMOperand &)*Operands[I.getOperandIndex()]).getStartLoc(); ((ARMOperand &)*Operands[I.getOperandIndex()]).getStartLoc();
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Lines case NearMissInfo::NearMissPredicate: {
break; break;
default: default:
llvm_unreachable("Unhandled target predicate error"); llvm_unreachable("Unhandled target predicate error");
break; break;
} }
NearMissesOut.emplace_back(Message); NearMissesOut.emplace_back(Message);
break; break;
} }
case NearMissInfo::NearMissMultipleOperands: {
// Just record the fact that we have seen this, we will use it as a
// fall-back if we don't find a better operand error to report.
HaveMultipleBadOperands = true;
break;
}
case NearMissInfo::NearMissTooFewOperands: { case NearMissInfo::NearMissTooFewOperands: {
if (!ReportedTooFewOperands) { if (!ReportedTooFewOperands) {
SMLoc EndLoc = ((ARMOperand &)*Operands.back()).getEndLoc(); SMLoc EndLoc = ((ARMOperand &)*Operands.back()).getEndLoc();
NearMissesOut.emplace_back(NearMissMessage{ NearMissesOut.emplace_back(NearMissMessage{
EndLoc, StringRef("too few operands for instruction")}); EndLoc, StringRef("too few operands for instruction")});
ReportedTooFewOperands = true; ReportedTooFewOperands = true;
} }
break; break;
} }
case NearMissInfo::NoNearMiss: case NearMissInfo::NoNearMiss:
// This should never leave the matcher. // This should never leave the matcher.
llvm_unreachable("not a near-miss"); llvm_unreachable("not a near-miss");
break; break;
} }
} }
// If there is an encoding that missed on multiple operands (but matched the
// target features and early predicate), but we haven't been able to emit a
// more specific error for any operands, emit a generic error. This lets the
// user know that the mnemonic exists, and that some combination of operands
// would work for the current target.
if (HaveMultipleBadOperands && NearMissesOut.empty()) {
NearMissesOut.emplace_back(NearMissMessage{
IDLoc, StringRef("invalid operands for instruction")});
}
} }
void ARMAsmParser::ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses, void ARMAsmParser::ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses,
SMLoc IDLoc, OperandVector &Operands) { SMLoc IDLoc, OperandVector &Operands) {
SmallVector<NearMissMessage, 4> Messages; SmallVector<NearMissMessage, 4> Messages;
FilterNearMisses(NearMisses, Messages, IDLoc, Operands); FilterNearMisses(NearMisses, Messages, IDLoc, Operands);
if (Messages.size() == 0) { if (Messages.size() == 0) {
▲ Show 20 Lines • Show All 135 Lines • Show Last 20 Lines

llvm/test/MC/ARM/diagnostics.s

@ RUN: not llvm-mc -triple=armv7-apple-darwin < %s 2> %t RUN: not llvm-mc -triple=armv7-apple-darwin < %s 2> %t
@ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V7 < %t %s @ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V7 < %t %s
@ RUN: not llvm-mc -triple=armv8 < %s 2> %t @ RUN: not llvm-mc -triple=armv8 < %s 2> %t
@ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V8 < %t %s @ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V8 < %t %s
@ Check for various assembly diagnostic messages on invalid input. @ Check for various assembly diagnostic messages on invalid input.
@ 's' bit on an instruction that can't accept it. @ 's' bit on an instruction that can't accept it.
mlss r1, r2, r3, r4 mlss r1, r2, r3, r4
▲ Show 20 Lines • Show All 149 Lines • ▼ Show 20 Lines@ CHECK-ERRORS: ^
mcr2 p7, #8, r5, c1, c1, #4 mcr2 p7, #8, r5, c1, c1, #4
mcr2 p7, #1, r5, c1, c1, #8 mcr2 p7, #1, r5, c1, c1, #8
mcrr p7, #16, r5, r4, c1 mcrr p7, #16, r5, r4, c1
mcrr2 p7, #16, r5, r4, c1 mcrr2 p7, #16, r5, r4, c1
@ CHECK-ERRORS: operand must be an immediate in the range [0,7] @ CHECK-ERRORS: operand must be an immediate in the range [0,7]
@ CHECK-ERRORS: operand must be an immediate in the range [0,7] @ CHECK-ERRORS: operand must be an immediate in the range [0,7]
@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7] @ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7]
@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7] @ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7]
@ CHECK-ERRORS-V8: invalid instruction @ CHECK-ERRORS-V8: error: invalid operands for instruction
@ CHECK-ERRORS-V8: too many operands for instruction @ CHECK-ERRORS-V8: too many operands for instruction
@ CHECK-ERRORS: operand must be an immediate in the range [0,15] @ CHECK-ERRORS: operand must be an immediate in the range [0,15]
@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,15] @ CHECK-ERRORS-V7: operand must be an immediate in the range [0,15]
@ CHECK-ERRORS-V8: invalid instruction @ CHECK-ERRORS-V8: invalid instruction
@ p10 and p11 are reserved for NEON @ p10 and p11 are reserved for NEON
mcr p10, #2, r5, c1, c1, #4 mcr p10, #2, r5, c1, c1, #4
mcrr p11, #8, r5, r4, c1 mcrr p11, #8, r5, r4, c1
Show All 27 Lines@ CHECK-ERRORS: ^
mrc p14, #1, r1, c1, c2, #8 mrc p14, #1, r1, c1, c2, #8
mrc2 p14, #8, r1, c1, c2, #4 mrc2 p14, #8, r1, c1, c2, #4
mrc2 p14, #0, r1, c1, c2, #9 mrc2 p14, #0, r1, c1, c2, #9
mrrc p7, #16, r5, r4, c1 mrrc p7, #16, r5, r4, c1
mrrc2 p7, #17, r5, r4, c1 mrrc2 p7, #17, r5, r4, c1
@ CHECK-ERRORS: operand must be an immediate in the range [0,7] @ CHECK-ERRORS: operand must be an immediate in the range [0,7]
@ CHECK-ERRORS: operand must be an immediate in the range [0,7] @ CHECK-ERRORS: operand must be an immediate in the range [0,7]
@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7] @ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7]
@ CHECK-ERRORS-V8: invalid instruction @ CHECK-ERRORS-V8: error: invalid operands for instruction
@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7] @ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7]
@ CHECK-ERRORS-V8: too many operands for instruction @ CHECK-ERRORS-V8: too many operands for instruction
@ CHECK-ERRORS: operand must be an immediate in the range [0,15] @ CHECK-ERRORS: operand must be an immediate in the range [0,15]
@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,15] @ CHECK-ERRORS-V7: operand must be an immediate in the range [0,15]
@ CHECK-ERRORS-V8: invalid instruction @ CHECK-ERRORS-V8: invalid instruction
@ Shifter operand validation for PKH instructions. @ Shifter operand validation for PKH instructions.
pkhbt r2, r2, r3, lsl #-1 pkhbt r2, r2, r3, lsl #-1
▲ Show 20 Lines • Show All 525 Lines • Show Last 20 Lines

llvm/test/MC/ARM/invalid-fp-armv8.s

Show All 29 Lines@ V8: error: invalid instruction
vsells.f32 s3, s4, s6 vsells.f32 s3, s4, s6
@ V8: error: invalid instruction @ V8: error: invalid instruction
vsellt.f32 s3, s4, s6 vsellt.f32 s3, s4, s6
@ V8: error: invalid instruction @ V8: error: invalid instruction
vselle.f32 s3, s4, s6 vselle.f32 s3, s4, s6
@ V8: error: invalid instruction @ V8: error: invalid instruction
vseleq.f32 s0, d2, d1 vseleq.f32 s0, d2, d1
@ V8: error: invalid instruction @ V8: error: invalid operands for instruction
vselgt.f64 s3, s2, s1 vselgt.f64 s3, s2, s1
@ V8: error: invalid operand for instruction @ V8: error: invalid operand for instruction
vselgt.f32 s0, q3, q1 vselgt.f32 s0, q3, q1
@ V8: error: invalid instruction @ V8: error: invalid operands for instruction
vselgt.f64 q0, s3, q1 vselgt.f64 q0, s3, q1
@ V8: error: invalid instruction @ V8: error: invalid operands for instruction
vmaxnm.f32 s0, d2, d1 vmaxnm.f32 s0, d2, d1
@ V8: error: invalid instruction @ V8: error: invalid operands for instruction
vminnm.f64 s3, s2, s1 vminnm.f64 s3, s2, s1
@ V8: error: invalid operand for instruction @ V8: error: invalid operand for instruction
vmaxnm.f32 s0, q3, q1 vmaxnm.f32 s0, q3, q1
@ V8: error: invalid instruction @ V8: error: invalid operands for instruction
vmaxnm.f64 q0, s3, q1 vmaxnm.f64 q0, s3, q1
@ V8: error: invalid instruction @ V8: error: invalid operands for instruction
vmaxnmgt.f64 q0, s3, q1 vmaxnmgt.f64 q0, s3, q1
@ CHECK: error: instruction 'vmaxnm' is not predicable, but condition code specified @ CHECK: error: instruction 'vmaxnm' is not predicable, but condition code specified
vcvta.s32.f64 d3, s2 vcvta.s32.f64 d3, s2
@ V8: error: invalid instruction @ V8: error: invalid operands for instruction
vcvtp.s32.f32 d3, s2 vcvtp.s32.f32 d3, s2
@ V8: error: operand must be a register in range [s0, s31] @ V8: error: operand must be a register in range [s0, s31]
vcvtn.u32.f64 d3, s2 vcvtn.u32.f64 d3, s2
@ V8: error: invalid instruction @ V8: error: invalid operands for instruction
vcvtm.u32.f32 d3, s2 vcvtm.u32.f32 d3, s2
@ V8: error: operand must be a register in range [s0, s31] @ V8: error: operand must be a register in range [s0, s31]
vcvtnge.u32.f64 d3, s2 vcvtnge.u32.f64 d3, s2
@ V8: error: instruction 'vcvtn' is not predicable, but condition code specified @ V8: error: instruction 'vcvtn' is not predicable, but condition code specified
vcvtbgt.f64.f16 q0, d3 vcvtbgt.f64.f16 q0, d3
@ V8: error: invalid instruction @ V8: error: invalid operands for instruction
vcvttlt.f64.f16 s0, s3 vcvttlt.f64.f16 s0, s3
@ V8: error: invalid instruction, any one of the following would fix this: @ V8: error: invalid instruction, any one of the following would fix this:
@ V8: note: operand must be a register in range [d0, d31] @ V8: note: operand must be a register in range [d0, d31]
@ V8: note: invalid operand for instruction @ V8: note: invalid operand for instruction
vcvttvs.f16.f64 s0, s3 vcvttvs.f16.f64 s0, s3
@ V8: error: invalid instruction, any one of the following would fix this: @ V8: error: invalid instruction, any one of the following would fix this:
@ V8: note: operand must be a register in range [d0, d31] @ V8: note: operand must be a register in range [d0, d31]
@ V8: note: invalid operand for instruction @ V8: note: invalid operand for instruction
vcvtthi.f16.f64 q0, d3 vcvtthi.f16.f64 q0, d3
@ V8: error: operand must be a register in range [s0, s31] @ V8: error: operand must be a register in range [s0, s31]
vrintrlo.f32.f32 d3, q0 vrintrlo.f32.f32 d3, q0
@ V8: error: invalid instruction @ V8: error: invalid operands for instruction
vrintxcs.f32.f32 d3, d0 vrintxcs.f32.f32 d3, d0
@ V8: error: invalid instruction @ V8: error: invalid operands for instruction
vrinta.f64.f64 s3, q0 vrinta.f64.f64 s3, q0
@ V8: error: invalid instruction @ V8: error: invalid operands for instruction
vrintn.f32.f32 d3, d0 vrintn.f32.f32 d3, d0
@ V8: error: instruction requires: NEON @ V8: error: instruction requires: NEON
vrintp.f32 q3, q0 vrintp.f32 q3, q0
@ V8: error: instruction requires: NEON @ V8: error: instruction requires: NEON
vrintmlt.f32 q3, q0 vrintmlt.f32 q3, q0
@ V8: error: instruction 'vrintm' is not predicable, but condition code specified @ V8: error: instruction 'vrintm' is not predicable, but condition code specified

llvm/test/MC/ARM/invalid-neon-v8.s

@ RUN: not llvm-mc -triple armv8 -mattr=-fp-armv8 -show-encoding < %s 2>&1 | FileCheck %s @ RUN: not llvm-mc -triple armv8 -mattr=-fp-armv8 -show-encoding < %s 2>&1 | FileCheck %s
vmaxnm.f32 s4, d5, q1 vmaxnm.f32 s4, d5, q1
@ CHECK: error: invalid instruction @ CHECK: error: invalid operands for instruction
vmaxnm.f64.f64 s4, d5, q1 vmaxnm.f64.f64 s4, d5, q1
@ CHECK: error: invalid instruction @ CHECK: error: invalid operands for instruction
vmaxnmge.f64.f64 s4, d5, q1 vmaxnmge.f64.f64 s4, d5, q1
@ CHECK: error: instruction 'vmaxnm' is not predicable, but condition code specified @ CHECK: error: instruction 'vmaxnm' is not predicable, but condition code specified
vcvta.s32.f32 s1, s2 vcvta.s32.f32 s1, s2
@ CHECK: error: instruction requires: FPARMv8 @ CHECK: error: instruction requires: FPARMv8
vcvtp.u32.f32 s1, d2 vcvtp.u32.f32 s1, d2
@ CHECK: error: operand must be a register in range [d0, d31] @ CHECK: error: operand must be a register in range [d0, d31]
vcvtp.f32.u32 d1, q2 vcvtp.f32.u32 d1, q2
@ CHECK: error: invalid instruction @ CHECK: error: invalid operands for instruction
vcvtplo.f32.u32 s1, s2 vcvtplo.f32.u32 s1, s2
@ CHECK: error: instruction 'vcvtp' is not predicable, but condition code specified @ CHECK: error: instruction 'vcvtp' is not predicable, but condition code specified
vrinta.f64.f64 s3, d12 vrinta.f64.f64 s3, d12
@ CHECK: error: invalid instruction @ CHECK: error: invalid operands for instruction
vrintn.f32 d3, q12 vrintn.f32 d3, q12
@ CHECK: error: invalid instruction, any one of the following would fix this: @ CHECK: error: invalid instruction, any one of the following would fix this:
@ CHECK: note: operand must be a register in range [d0, d31] @ CHECK: note: operand must be a register in range [d0, d31]
@ CHECK: note: operand must be a register in range [q0, q15] @ CHECK: note: operand must be a register in range [q0, q15]
vrintz.f32 d3, q12 vrintz.f32 d3, q12
@ CHECK: error: invalid instruction, any one of the following would fix this: @ CHECK: error: invalid instruction, any one of the following would fix this:
@ CHECK: note: operand must be a register in range [d0, d31] @ CHECK: note: operand must be a register in range [d0, d31]
@ CHECK: note: operand must be a register in range [q0, q15] @ CHECK: note: operand must be a register in range [q0, q15]
Show All 16 Lines
sha1su1.32 q0, s1 sha1su1.32 q0, s1
@ CHECK: error: operand must be a register in range [q0, q15] @ CHECK: error: operand must be a register in range [q0, q15]
sha256su0.32 s0, q1 sha256su0.32 s0, q1
@ CHECK: error: operand must be a register in range [q0, q15] @ CHECK: error: operand must be a register in range [q0, q15]
sha1heq.32 q0, q1 sha1heq.32 q0, q1
@ CHECK: error: instruction 'sha1h' is not predicable, but condition code specified @ CHECK: error: instruction 'sha1h' is not predicable, but condition code specified
sha1c.32 s0, d1, q2 sha1c.32 s0, d1, q2
@ CHECK: error: invalid instruction @ CHECK: error: invalid operands for instruction
sha1m.32 q0, s1, q2 sha1m.32 q0, s1, q2
@ CHECK: error: operand must be a register in range [q0, q15] @ CHECK: error: operand must be a register in range [q0, q15]
sha1p.32 s0, q1, q2 sha1p.32 s0, q1, q2
@ CHECK: error: operand must be a register in range [q0, q15] @ CHECK: error: operand must be a register in range [q0, q15]
sha1su0.32 d0, q1, q2 sha1su0.32 d0, q1, q2
@ CHECK: error: operand must be a register in range [q0, q15] @ CHECK: error: operand must be a register in range [q0, q15]
sha256h.32 q0, s1, q2 sha256h.32 q0, s1, q2
@ CHECK: error: operand must be a register in range [q0, q15] @ CHECK: error: operand must be a register in range [q0, q15]
sha256h2.32 q0, q1, s2 sha256h2.32 q0, q1, s2
@ CHECK: error: operand must be a register in range [q0, q15] @ CHECK: error: operand must be a register in range [q0, q15]
sha256su1.32 s0, d1, q2 sha256su1.32 s0, d1, q2
@ CHECK: error: invalid instruction @ CHECK: error: invalid operands for instruction
sha256su1lt.32 q0, d1, q2 sha256su1lt.32 q0, d1, q2
@ CHECK: error: instruction 'sha256su1' is not predicable, but condition code specified @ CHECK: error: instruction 'sha256su1' is not predicable, but condition code specified
vmull.p64 q0, s1, s3 vmull.p64 q0, s1, s3
@ CHECK: error: invalid instruction @ CHECK: error: invalid operands for instruction
vmull.p64 s1, d2, d3 vmull.p64 s1, d2, d3
@ CHECK: error: operand must be a register in range [q0, q15] @ CHECK: error: operand must be a register in range [q0, q15]
vmullge.p64 q0, d16, d17 vmullge.p64 q0, d16, d17
@ CHECK: error: instruction 'vmull' is not predicable, but condition code specified @ CHECK: error: instruction 'vmull' is not predicable, but condition code specified
// These instructions are predicable in VFP but not in NEON // These instructions are predicable in VFP but not in NEON
vrintzeq.f32 d0, d1 vrintzeq.f32 d0, d1
vrintxgt.f32 d0, d1 vrintxgt.f32 d0, d1
@ CHECK: error: invalid operand for instruction @ CHECK: error: invalid operand for instruction
@ CHECK: error: invalid operand for instruction @ CHECK: error: invalid operand for instruction

llvm/test/MC/ARM/ldrd-strd-gnu-arm-bad-regs.s

@ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s @ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s
.text .text
.arm .arm
@ CHECK: error: invalid instruction @ CHECK: error: invalid operands for instruction
@ CHECK: ldrd r12, [r0, #512] @ CHECK: ldrd r12, [r0, #512]
ldrd r12, [r0, #512] ldrd r12, [r0, #512]
@ CHECK: error: invalid instruction @ CHECK: error: invalid operands for instruction
@ CHECK: strd r12, [r0, #512] @ CHECK: strd r12, [r0, #512]
strd r12, [r0, #512] strd r12, [r0, #512]
@ CHECK: error: invalid instruction @ CHECK: error: invalid operands for instruction
@ CHECK: ldrd r1, [r0, #512] @ CHECK: ldrd r1, [r0, #512]
ldrd r1, [r0, #512] ldrd r1, [r0, #512]
@ CHECK: error: invalid instruction @ CHECK: error: invalid operands for instruction
@ CHECK: strd r1, [r0, #512] @ CHECK: strd r1, [r0, #512]
strd r1, [r0, #512] strd r1, [r0, #512]

llvm/test/MC/ARM/ldrd-strd-gnu-bad-inst.s

@ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s @ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s
.text .text
.thumb .thumb
@ CHECK: error: too few operands for instruction @ CHECK: error: too few operands for instruction
strd strd
@ CHECK: error: too few operands for instruction @ CHECK: error: too few operands for instruction
ldrd ldrd
@ CHECK: error: too few operands for instruction @ CHECK: error: too few operands for instruction
strd r0 strd r0
@ CHECK: error: too few operands for instruction @ CHECK: error: too few operands for instruction
ldrd r0 ldrd r0
@ CHECK: error: invalid instruction @ CHECK: error: invalid operands for instruction
strd s0, [r0] strd s0, [r0]
@ CHECK: error: invalid instruction @ CHECK: error: invalid operands for instruction
ldrd s0, [r0] ldrd s0, [r0]
.arm .arm
@ CHECK: error: too few operands for instruction @ CHECK: error: too few operands for instruction
strd strd
@ CHECK: error: too few operands for instruction @ CHECK: error: too few operands for instruction
ldrd ldrd
@ CHECK: error: too few operands for instruction @ CHECK: error: too few operands for instruction
strd r0 strd r0
@ CHECK: error: too few operands for instruction @ CHECK: error: too few operands for instruction
ldrd r0 ldrd r0
@ CHECK: error: invalid instruction @ CHECK: error: invalid operands for instruction
strd s0, [r0] strd s0, [r0]
@ CHECK: error: invalid instruction @ CHECK: error: invalid operands for instruction
ldrd s0, [r0] ldrd s0, [r0]

llvm/test/MC/ARM/ldrd-strd-gnu-sp.s

// PR19320 // PR19320
// RUN: not llvm-mc -triple=armv7a-linux-gnueabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=V7 // RUN: not llvm-mc -triple=armv7a-linux-gnueabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=V7
// RUN: llvm-mc -triple=armv8a-linux-gnueabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=V8 // RUN: llvm-mc -triple=armv8a-linux-gnueabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=V8
.text .text
// This tries to use the GNU ldrd/strd alias to create an ldrd/strd instruction // This tries to use the GNU ldrd/strd alias to create an ldrd/strd instruction
// using the sp register. This is valid for V8, but not earlier architectures. // using the sp register. This is valid for V8, but not earlier architectures.
.arm .arm
// V7: error: invalid instruction // V7: error: invalid operands for instruction
// V8: ldrd r12, sp, [r0, #32] @ encoding: [0xd0,0xc2,0xc0,0xe1] // V8: ldrd r12, sp, [r0, #32] @ encoding: [0xd0,0xc2,0xc0,0xe1]
ldrd r12, [r0, #32] ldrd r12, [r0, #32]
// V7: error: invalid instruction // V7: error: invalid operands for instruction
// V8: strd r12, sp, [r0, #32] @ encoding: [0xf0,0xc2,0xc0,0xe1] // V8: strd r12, sp, [r0, #32] @ encoding: [0xf0,0xc2,0xc0,0xe1]
strd r12, [r0, #32] strd r12, [r0, #32]
.thumb .thumb
// V7: error: invalid instruction // V7: error: invalid operands for instruction
// V8: ldrd r12, sp, [r0, #32] @ encoding: [0xd0,0xe9,0x08,0xcd] // V8: ldrd r12, sp, [r0, #32] @ encoding: [0xd0,0xe9,0x08,0xcd]
ldrd r12, [r0, #32] ldrd r12, [r0, #32]
// V7: error: invalid instruction // V7: error: invalid operands for instruction
// V8: strd r12, sp, [r0, #32] @ encoding: [0xc0,0xe9,0x08,0xcd] // V8: strd r12, sp, [r0, #32] @ encoding: [0xc0,0xe9,0x08,0xcd]
strd r12, [r0, #32] strd r12, [r0, #32]

llvm/test/MC/ARM/ldrd-strd-gnu-thumb-bad-regs.s

@ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s @ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s
.text .text
.thumb .thumb
@ CHECK: error: invalid instruction @ CHECK: error: invalid operands for instruction
@ CHECK: ldrd r12, [r0, #512] @ CHECK: ldrd r12, [r0, #512]
ldrd r12, [r0, #512] ldrd r12, [r0, #512]
@ CHECK: error: invalid instruction @ CHECK: error: invalid operands for instruction
@ CHECK: strd r12, [r0, #512] @ CHECK: strd r12, [r0, #512]
strd r12, [r0, #512] strd r12, [r0, #512]

llvm/test/MC/ARM/thumb-mov.s

Show All 13 Lines// RUN: not llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V8 %s
movs r0, pc movs r0, pc
movs pc, pc movs pc, pc
// CHECK: error: operand must be a register in range [r0, r14] // CHECK: error: operand must be a register in range [r0, r14]
// CHECK-NEXT: movs pc, r0 // CHECK-NEXT: movs pc, r0
// CHECK: note: operand must be a register in range [r0, r14] // CHECK: note: operand must be a register in range [r0, r14]
// CHECK-NEXT: movs r0, pc // CHECK-NEXT: movs r0, pc
// CHECK: note: invalid operand for instruction // CHECK: note: invalid operand for instruction
// CHECK-NEXT: movs r0, pc // CHECK-NEXT: movs r0, pc
// CHECK: error: invalid instruction // CHECK: error: invalid operands for instruction
// CHECK-NEXT: movs pc, pc // CHECK-NEXT: movs pc, pc
// mov.w selects t2MOVr // mov.w selects t2MOVr
mov.w pc, r0 mov.w pc, r0
mov.w r0, pc mov.w r0, pc
mov.w pc, pc mov.w pc, pc
// CHECK: error: operand must be a register in range [r0, r14] // CHECK: error: operand must be a register in range [r0, r14]
// CHECK-NEXT: mov.w pc, r0 // CHECK-NEXT: mov.w pc, r0
// CHECK: note: operand must be a register in range [r0, r14] // CHECK: note: operand must be a register in range [r0, r14]
// CHECK-NEXT: mov.w r0, pc // CHECK-NEXT: mov.w r0, pc
// CHECK: note: invalid operand for instruction // CHECK: note: invalid operand for instruction
// CHECK-NEXT: mov.w r0, pc // CHECK-NEXT: mov.w r0, pc
// CHECK: error: invalid instruction // CHECK: error: invalid operands for instruction
// CHECK-NEXT: mov.w pc, pc // CHECK-NEXT: mov.w pc, pc
// movs.w selects t2MOVr // movs.w selects t2MOVr
movs.w pc, r0 movs.w pc, r0
movs.w r0, pc movs.w r0, pc
movs.w pc, pc movs.w pc, pc
// CHECK: error: operand must be a register in range [r0, r14] // CHECK: error: operand must be a register in range [r0, r14]
// CHECK-NEXT: movs.w pc, r0 // CHECK-NEXT: movs.w pc, r0
// CHECK: note: operand must be a register in range [r0, r14] // CHECK: note: operand must be a register in range [r0, r14]
// CHECK-NEXT: movs.w r0, pc // CHECK-NEXT: movs.w r0, pc
// CHECK: note: invalid operand for instruction // CHECK: note: invalid operand for instruction
// CHECK-NEXT: movs.w r0, pc // CHECK-NEXT: movs.w r0, pc
// CHECK: error: invalid instruction // CHECK: error: invalid operands for instruction
// CHECK-NEXT: movs.w pc, pc // CHECK-NEXT: movs.w pc, pc
// Now check instructions that are invalid before ARMv8 due to SP usage // Now check instructions that are invalid before ARMv8 due to SP usage
movs sp, r0 movs sp, r0
movs r0, sp movs r0, sp
movs sp, sp movs sp, sp
▲ Show 20 Lines • Show All 50 Lines • Show Last 20 Lines

llvm/test/MC/ARM/thumb2-diagnostics.s

Show All 37 Lines@ CHECK-ERRORS: ^
mrc2 p14, #8, r1, c1, c2, #4 mrc2 p14, #8, r1, c1, c2, #4
mrc2 p14, #0, r1, c1, c2, #9 mrc2 p14, #0, r1, c1, c2, #9
mrrc p7, #16, r5, r4, c1 mrrc p7, #16, r5, r4, c1
mrrc2 p7, #17, r5, r4, c1 mrrc2 p7, #17, r5, r4, c1
@ CHECK-ERRORS: operand must be an immediate in the range [0,7] @ CHECK-ERRORS: operand must be an immediate in the range [0,7]
@ CHECK-ERRORS: operand must be an immediate in the range [0,7] @ CHECK-ERRORS: operand must be an immediate in the range [0,7]
@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7] @ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7]
@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7] @ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7]
@ CHECK-ERRORS-V8: invalid instruction @ CHECK-ERRORS-V8: error: invalid operands for instruction
@ CHECK-ERRORS-V8: too many operands for instruction @ CHECK-ERRORS-V8: too many operands for instruction
@ CHECK-ERRORS: operand must be an immediate in the range [0,15] @ CHECK-ERRORS: operand must be an immediate in the range [0,15]
@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,15] @ CHECK-ERRORS-V7: operand must be an immediate in the range [0,15]
@ CHECK-ERRORS-V8: invalid instruction @ CHECK-ERRORS-V8: invalid instruction
isb #-1 isb #-1
isb #16 isb #16
@ CHECK-ERRORS: error: immediate value out of range @ CHECK-ERRORS: error: immediate value out of range
Show All 31 Lines
@ CHECK-ERRORS: ^ @ CHECK-ERRORS: ^
@ CHECK-ERRORS: immediate expression for mov requires :lower16: or :upper16 @ CHECK-ERRORS: immediate expression for mov requires :lower16: or :upper16
@ CHECK-ERRORS: ^ @ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: operand must be an immediate in the range [0,0xffff] or a relocatable expression @ CHECK-ERRORS: error: operand must be an immediate in the range [0,0xffff] or a relocatable expression
@ CHECK-ERRORS: error: operand must be an immediate in the range [0,0xffff] or a relocatable expression @ CHECK-ERRORS: error: operand must be an immediate in the range [0,0xffff] or a relocatable expression
and sp, r1, #80008000 and sp, r1, #80008000
and pc, r1, #80008000 and pc, r1, #80008000
@ CHECK-ERRORS: error: invalid instruction @ CHECK-ERRORS-V7: error: invalid operands for instruction
@ CHECK-ERRORS: error: invalid instruction @ CHECK-ERRORS-V8: invalid instruction, any one of the following would fix this:
@ CHECK-ERRORS-V8: note: invalid operand for instruction
@ CHECK-ERRORS-V8: note: operand must be a register in range [r0, r14]
@ CHECK-ERRORS: error: invalid operands for instruction
ssat r0, #1, r0, asr #32 ssat r0, #1, r0, asr #32
usat r0, #1, r0, asr #32 usat r0, #1, r0, asr #32
@ CHECK-ERRORS: error: 'asr #32' shift amount not allowed in Thumb mode @ CHECK-ERRORS: error: 'asr #32' shift amount not allowed in Thumb mode
@ CHECK-ERRORS: error: 'asr #32' shift amount not allowed in Thumb mode @ CHECK-ERRORS: error: 'asr #32' shift amount not allowed in Thumb mode
@ PC is not valid as shifted-rGPR @ PC is not valid as shifted-rGPR
sbc.w r2, r7, pc, lsr #16 sbc.w r2, r7, pc, lsr #16
Show All 20 Lines
@ CHECK-ERRORS: note: invalid operand for instruction @ CHECK-ERRORS: note: invalid operand for instruction
@ CHECK-ERRORS: note: instruction requires: arm-mode @ CHECK-ERRORS: note: instruction requires: arm-mode
@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
@ CHECK-ERRORS: note: invalid operand for instruction @ CHECK-ERRORS: note: invalid operand for instruction
@ CHECK-ERRORS: note: instruction requires: arm-mode @ CHECK-ERRORS: note: instruction requires: arm-mode
@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
@ CHECK-ERRORS: note: instruction requires: arm-mode @ CHECK-ERRORS: note: instruction requires: arm-mode
@ CHECK-ERRORS: note: invalid operand for instruction @ CHECK-ERRORS: note: invalid operand for instruction
@ CHECK-ERRORS: error: invalid instruction @ CHECK-ERRORS: error: invalid operands for instruction
@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
@ CHECK-ERRORS: note: invalid operand for instruction @ CHECK-ERRORS: note: invalid operand for instruction
@ CHECK-ERRORS: note: instruction requires: arm-mode @ CHECK-ERRORS: note: instruction requires: arm-mode
@ CHECK-ERRORS: error: immediate value expected for vector index @ CHECK-ERRORS: error: immediate value expected for vector index
@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
@ CHECK-ERRORS: note: instruction requires: arm-mode @ CHECK-ERRORS: note: instruction requires: arm-mode
@ CHECK-ERRORS: note: invalid operand for instruction @ CHECK-ERRORS: note: invalid operand for instruction
Show All 13 Lines

llvm/test/MC/ARM/vfp4.s

@ RUN: llvm-mc < %s -triple armv7-unknown-unknown -show-encoding -mattr=+neon,+vfp4 | FileCheck %s --check-prefix=ARM @ RUN: llvm-mc < %s -triple armv7-unknown-unknown -show-encoding -mattr=+neon,+vfp4 | FileCheck %s --check-prefix=ARM
@ RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mattr=+neon,+vfp4 | FileCheck %s --check-prefix=THUMB @ RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mattr=+neon,+vfp4 | FileCheck %s --check-prefix=THUMB
@ RUN: not llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mcpu=cortex-m4 > %t 2> %t2 @ RUN: not llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mcpu=cortex-m4 > %t 2> %t2
@ RUN: FileCheck %s < %t --check-prefix=THUMB_V7EM @ RUN: FileCheck %s < %t --check-prefix=THUMB_V7EM
@ RUN: FileCheck %s < %t2 --check-prefix=THUMB_V7EM-ERRORS @ RUN: FileCheck %s < %t2 --check-prefix=THUMB_V7EM-ERRORS
@ ARM: vfma.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xe2,0xee] @ ARM: vfma.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xe2,0xee]
@ THUMB: vfma.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xa1,0x0b] @ THUMB: vfma.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xa1,0x0b]
@ THUMB_V7EM-ERRORS: error: invalid instruction @ THUMB_V7EM-ERRORS: error: invalid operands for instruction
@ THUMB_V7EM-ERRORS-NEXT: vfma.f64 d16, d18, d17 @ THUMB_V7EM-ERRORS-NEXT: vfma.f64 d16, d18, d17
vfma.f64 d16, d18, d17 vfma.f64 d16, d18, d17
@ ARM: vfma.f32 s2, s4, s0 @ encoding: [0x00,0x1a,0xa2,0xee] @ ARM: vfma.f32 s2, s4, s0 @ encoding: [0x00,0x1a,0xa2,0xee]
@ THUMB: vfma.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x00,0x1a] @ THUMB: vfma.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x00,0x1a]
@ THUMB_V7EM: vfma.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x00,0x1a] @ THUMB_V7EM: vfma.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x00,0x1a]
vfma.f32 s2, s4, s0 vfma.f32 s2, s4, s0
@ ARM: vfma.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x42,0xf2] @ ARM: vfma.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x42,0xf2]
@ THUMB: vfma.f32 d16, d18, d17 @ encoding: [0x42,0xef,0xb1,0x0c] @ THUMB: vfma.f32 d16, d18, d17 @ encoding: [0x42,0xef,0xb1,0x0c]
@ THUMB_V7EM-ERRORS: error: invalid instruction @ THUMB_V7EM-ERRORS: error: invalid operands for instruction
@ THUMB_V7EM-ERRORS-NEXT: vfma.f32 d16, d18, d17 @ THUMB_V7EM-ERRORS-NEXT: vfma.f32 d16, d18, d17
vfma.f32 d16, d18, d17 vfma.f32 d16, d18, d17
@ ARM: vfma.f32 q2, q4, q0 @ encoding: [0x50,0x4c,0x08,0xf2] @ ARM: vfma.f32 q2, q4, q0 @ encoding: [0x50,0x4c,0x08,0xf2]
@ THUMB: vfma.f32 q2, q4, q0 @ encoding: [0x08,0xef,0x50,0x4c] @ THUMB: vfma.f32 q2, q4, q0 @ encoding: [0x08,0xef,0x50,0x4c]
@ THUMB_V7EM-ERRORS: error: instruction requires: NEON @ THUMB_V7EM-ERRORS: error: instruction requires: NEON
@ THUMB_V7EM-ERRORS-NEXT: vfma.f32 q2, q4, q0 @ THUMB_V7EM-ERRORS-NEXT: vfma.f32 q2, q4, q0
vfma.f32 q2, q4, q0 vfma.f32 q2, q4, q0
@ ARM: vfnma.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xd2,0xee] @ ARM: vfnma.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xd2,0xee]
@ THUMB: vfnma.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xe1,0x0b] @ THUMB: vfnma.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xe1,0x0b]
@ THUMB_V7EM-ERRORS: error: invalid instruction @ THUMB_V7EM-ERRORS: error: invalid operands for instruction
@ THUMB_V7EM-ERRORS-NEXT: vfnma.f64 d16, d18, d17 @ THUMB_V7EM-ERRORS-NEXT: vfnma.f64 d16, d18, d17
vfnma.f64 d16, d18, d17 vfnma.f64 d16, d18, d17
@ ARM: vfnma.f32 s2, s4, s0 @ encoding: [0x40,0x1a,0x92,0xee] @ ARM: vfnma.f32 s2, s4, s0 @ encoding: [0x40,0x1a,0x92,0xee]
@ THUMB: vfnma.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x40,0x1a] @ THUMB: vfnma.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x40,0x1a]
@ THUMB_V7EM: vfnma.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x40,0x1a] @ THUMB_V7EM: vfnma.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x40,0x1a]
vfnma.f32 s2, s4, s0 vfnma.f32 s2, s4, s0
@ ARM: vfms.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xe2,0xee] @ ARM: vfms.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xe2,0xee]
@ THUMB: vfms.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xe1,0x0b] @ THUMB: vfms.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xe1,0x0b]
@ THUMB_V7EM-ERRORS: error: invalid instruction @ THUMB_V7EM-ERRORS: error: invalid operands for instruction
@ THUMB_V7EM-ERRORS-NEXT: vfms.f64 d16, d18, d17 @ THUMB_V7EM-ERRORS-NEXT: vfms.f64 d16, d18, d17
vfms.f64 d16, d18, d17 vfms.f64 d16, d18, d17
@ ARM: vfms.f32 s2, s4, s0 @ encoding: [0x40,0x1a,0xa2,0xee] @ ARM: vfms.f32 s2, s4, s0 @ encoding: [0x40,0x1a,0xa2,0xee]
@ THUMB: vfms.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x40,0x1a] @ THUMB: vfms.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x40,0x1a]
@ THUMB_V7EM: vfms.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x40,0x1a] @ THUMB_V7EM: vfms.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x40,0x1a]
vfms.f32 s2, s4, s0 vfms.f32 s2, s4, s0
@ ARM: vfms.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x62,0xf2] @ ARM: vfms.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x62,0xf2]
@ THUMB: vfms.f32 d16, d18, d17 @ encoding: [0x62,0xef,0xb1,0x0c] @ THUMB: vfms.f32 d16, d18, d17 @ encoding: [0x62,0xef,0xb1,0x0c]
@ THUMB_V7EM-ERRORS: error: invalid instruction @ THUMB_V7EM-ERRORS: error: invalid operands for instruction
@ THUMB_V7EM-ERRORS-NEXT: vfms.f32 d16, d18, d17 @ THUMB_V7EM-ERRORS-NEXT: vfms.f32 d16, d18, d17
vfms.f32 d16, d18, d17 vfms.f32 d16, d18, d17
@ ARM: vfms.f32 q2, q4, q0 @ encoding: [0x50,0x4c,0x28,0xf2] @ ARM: vfms.f32 q2, q4, q0 @ encoding: [0x50,0x4c,0x28,0xf2]
@ THUMB: vfms.f32 q2, q4, q0 @ encoding: [0x28,0xef,0x50,0x4c] @ THUMB: vfms.f32 q2, q4, q0 @ encoding: [0x28,0xef,0x50,0x4c]
@ THUMB_V7EM-ERRORS: error: instruction requires: NEON @ THUMB_V7EM-ERRORS: error: instruction requires: NEON
@ THUMB_V7EM-ERRORS-NEXT: vfms.f32 q2, q4, q0 @ THUMB_V7EM-ERRORS-NEXT: vfms.f32 q2, q4, q0
vfms.f32 q2, q4, q0 vfms.f32 q2, q4, q0
@ ARM: vfnms.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xd2,0xee] @ ARM: vfnms.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xd2,0xee]
@ THUMB: vfnms.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xa1,0x0b] @ THUMB: vfnms.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xa1,0x0b]
@ THUMB_V7EM-ERRORS: error: invalid instruction @ THUMB_V7EM-ERRORS: error: invalid operands for instruction
@ THUMB_V7EM-ERRORS-NEXT: vfnms.f64 d16, d18, d17 @ THUMB_V7EM-ERRORS-NEXT: vfnms.f64 d16, d18, d17
vfnms.f64 d16, d18, d17 vfnms.f64 d16, d18, d17
@ ARM: vfnms.f32 s2, s4, s0 @ encoding: [0x00,0x1a,0x92,0xee] @ ARM: vfnms.f32 s2, s4, s0 @ encoding: [0x00,0x1a,0x92,0xee]
@ THUMB: vfnms.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x00,0x1a] @ THUMB: vfnms.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x00,0x1a]
@ THUMB_V7EM: vfnms.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x00,0x1a] @ THUMB_V7EM: vfnms.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x00,0x1a]
vfnms.f32 s2, s4, s0 vfnms.f32 s2, s4, s0

llvm/utils/TableGen/AsmMatcherEmitter.cpp

Show First 20 Lines • Show All 3,269 Lines • ▼ Show 20 Lines#endif
OS << " << MII.getName(it->Opcode) << \"\\n\");\n"; OS << " << MII.getName(it->Opcode) << \"\\n\");\n";
if (ReportMultipleNearMisses) { if (ReportMultipleNearMisses) {
OS << " // Some state to record ways in which this instruction did not match.\n"; OS << " // Some state to record ways in which this instruction did not match.\n";
OS << " NearMissInfo OperandNearMiss = NearMissInfo::getSuccess();\n"; OS << " NearMissInfo OperandNearMiss = NearMissInfo::getSuccess();\n";
OS << " NearMissInfo FeaturesNearMiss = NearMissInfo::getSuccess();\n"; OS << " NearMissInfo FeaturesNearMiss = NearMissInfo::getSuccess();\n";
OS << " NearMissInfo EarlyPredicateNearMiss = NearMissInfo::getSuccess();\n"; OS << " NearMissInfo EarlyPredicateNearMiss = NearMissInfo::getSuccess();\n";
OS << " NearMissInfo LatePredicateNearMiss = NearMissInfo::getSuccess();\n"; OS << " NearMissInfo LatePredicateNearMiss = NearMissInfo::getSuccess();\n";
OS << " bool MultipleInvalidOperands = false;\n";
} }
if (HasMnemonicFirst) { if (HasMnemonicFirst) {
OS << " // equal_range guarantees that instruction mnemonic matches.\n"; OS << " // equal_range guarantees that instruction mnemonic matches.\n";
OS << " assert(Mnemonic == it->getMnemonic());\n"; OS << " assert(Mnemonic == it->getMnemonic());\n";
} }
// Emit check that the subclasses match. // Emit check that the subclasses match.
Show All 22 Lines OS << " bool ThisOperandValid = (Formal == " <<"InvalidMatchClass) || "
"isSubclass(Formal, OptionalMatchClass);\n"; "isSubclass(Formal, OptionalMatchClass);\n";
OS << " if (!ThisOperandValid) {\n"; OS << " if (!ThisOperandValid) {\n";
OS << " if (!OperandNearMiss) {\n"; OS << " if (!OperandNearMiss) {\n";
OS << " // Record info about match failure for later use.\n"; OS << " // Record info about match failure for later use.\n";
OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"recording too-few-operands near miss\\n\");\n"; OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"recording too-few-operands near miss\\n\");\n";
OS << " OperandNearMiss =\n"; OS << " OperandNearMiss =\n";
OS << " NearMissInfo::getTooFewOperands(Formal, it->Opcode);\n"; OS << " NearMissInfo::getTooFewOperands(Formal, it->Opcode);\n";
OS << " } else if (OperandNearMiss.getKind() != NearMissInfo::NearMissTooFewOperands) {\n"; OS << " } else if (OperandNearMiss.getKind() != NearMissInfo::NearMissTooFewOperands) {\n";
OS << " // If more than one operand is invalid, give up on this match entry.\n"; OS << " // An invalid operand plus a missing one at the end are reported the\n";
OS << " // same way as multiple invalid operands.\n";
OS << " DEBUG_WITH_TYPE(\n"; OS << " DEBUG_WITH_TYPE(\n";
OS << " \"asm-matcher\",\n"; OS << " \"asm-matcher\",\n";
OS << " dbgs() << \"second invalid operand, giving up on this opcode\\n\");\n"; OS << " dbgs() << \"second invalid operand, giving up on this opcode\\n\");\n";
OS << " MultipleInvalidOperands = true;\n"; OS << " OperandNearMiss = NearMissInfo::getMissedMultipleOperands(it->Opcode);\n";
OS << " break;\n"; OS << " break;\n";
OS << " }\n"; OS << " }\n";
OS << " } else {\n"; OS << " } else {\n";
OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"but formal operand not required\\n\");\n"; OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"but formal operand not required\\n\");\n";
OS << " break;\n"; OS << " break;\n";
OS << " }\n"; OS << " }\n";
OS << " continue;\n"; OS << " continue;\n";
} else { } else {
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines if (ReportMultipleNearMisses) {
OS << " OperandNearMiss =\n"; OS << " OperandNearMiss =\n";
OS << " NearMissInfo::getMissedOperand(Diag, Formal, it->Opcode, ActualIdx);\n"; OS << " NearMissInfo::getMissedOperand(Diag, Formal, it->Opcode, ActualIdx);\n";
OS << " ++ActualIdx;\n"; OS << " ++ActualIdx;\n";
OS << " } else {\n"; OS << " } else {\n";
OS << " // If more than one operand is invalid, give up on this match entry.\n"; OS << " // If more than one operand is invalid, give up on this match entry.\n";
OS << " DEBUG_WITH_TYPE(\n"; OS << " DEBUG_WITH_TYPE(\n";
OS << " \"asm-matcher\",\n"; OS << " \"asm-matcher\",\n";
OS << " dbgs() << \"second operand mismatch, skipping this opcode\\n\");\n"; OS << " dbgs() << \"second operand mismatch, skipping this opcode\\n\");\n";
OS << " MultipleInvalidOperands = true;\n"; OS << " OperandNearMiss = NearMissInfo::getMissedMultipleOperands(it->Opcode);\n";
OS << " break;\n"; OS << " break;\n";
OS << " }\n"; OS << " }\n";
OS << " }\n\n"; OS << " }\n\n";
} else { } else {
OS << " // If this operand is broken for all of the instances of this\n"; OS << " // If this operand is broken for all of the instances of this\n";
OS << " // mnemonic, keep track of it so we can report loc info.\n"; OS << " // mnemonic, keep track of it so we can report loc info.\n";
OS << " // If we already had a match that only failed due to a\n"; OS << " // If we already had a match that only failed due to a\n";
OS << " // target predicate, that diagnostic is preferred.\n"; OS << " // target predicate, that diagnostic is preferred.\n";
OS << " if (!HadMatchOtherThanPredicate &&\n"; OS << " if (!HadMatchOtherThanPredicate &&\n";
OS << " (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {\n"; OS << " (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {\n";
OS << " ErrorInfo = ActualIdx;\n"; OS << " ErrorInfo = ActualIdx;\n";
OS << " // InvalidOperand is the default. Prefer specificity.\n"; OS << " // InvalidOperand is the default. Prefer specificity.\n";
OS << " if (Diag != Match_InvalidOperand)\n"; OS << " if (Diag != Match_InvalidOperand)\n";
OS << " RetCode = Diag;\n"; OS << " RetCode = Diag;\n";
OS << " }\n"; OS << " }\n";
OS << " // Otherwise, just reject this instance of the mnemonic.\n"; OS << " // Otherwise, just reject this instance of the mnemonic.\n";
OS << " OperandsValid = false;\n"; OS << " OperandsValid = false;\n";
OS << " break;\n"; OS << " break;\n";
OS << " }\n\n"; OS << " }\n\n";
} }
if (ReportMultipleNearMisses) if (!ReportMultipleNearMisses) {
OS << " if (MultipleInvalidOperands) {\n";
else
OS << " if (!OperandsValid) {\n"; OS << " if (!OperandsValid) {\n";
OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: multiple \"\n"; OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: multiple \"\n";
OS << " \"operand mismatches, ignoring \"\n"; OS << " \"operand mismatches, ignoring \"\n";
OS << " \"this opcode\\n\");\n"; OS << " \"this opcode\\n\");\n";
OS << " continue;\n"; OS << " continue;\n";
OS << " }\n"; OS << " }\n";
}
// Emit check that the required features are available. // Emit check that the required features are available.
OS << " if ((AvailableFeatures & it->RequiredFeatures) " OS << " if ((AvailableFeatures & it->RequiredFeatures) "
<< "!= it->RequiredFeatures) {\n"; << "!= it->RequiredFeatures) {\n";
if (!ReportMultipleNearMisses) if (!ReportMultipleNearMisses)
OS << " HadMatchOtherThanFeatures = true;\n"; OS << " HadMatchOtherThanFeatures = true;\n";
OS << " uint64_t NewMissingFeatures = it->RequiredFeatures & " OS << " uint64_t NewMissingFeatures = it->RequiredFeatures & "
"~AvailableFeatures;\n"; "~AvailableFeatures;\n";
▲ Show 20 Lines • Show All 177 Lines • Show Last 20 Lines