[ARM] Use table-gen'd assembly operand diags in ARM asm parser

[olista01]

Summary

This switches the ARM AsmParser to use assembly operand diagnostics from
tablegen, rather than a switch statement on the ARMMatchResultTy. It
moves the existing diagnostic strings to tablegen, but adds no new ones,
so this is NFC except for one diagnostic string that had an off-by-1 error
in the hand-written switch statement.

[rengolin]

Oh, this is *much* better, thanks!

[rengolin]

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

10089 ↗

(On Diff #93880)

Quick question: why is the switch still here if the only case is the default?

[olista01]

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

10089 ↗

(On Diff #93880)

This will be used once we have operands that need diags that differ depending on subtarget features. Most of these on ARM are register classes, which we can't currently emit diagnostics for, but I have a prototype that allows that.

[rengolin]

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

10089 ↗

(On Diff #93880)

Right. Maybe we should just remove this for now, and add it back when you add the new code.

[olista01]

Remove getCustomOperandDiag until it's actually needed.

This is dependent on D31530, so I'll commit it once that one is committed.

llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

class N3VLaneCP8<bit op23, bits<2> op21_20, bit op6, bit op4,
   let Inst{7}     = Vn{4};
   let Inst{6}     = op6;
   // Bit 5 set by sub-classes
   let Inst{4}     = op4;
   let Inst{3-0}   = Vm{3-0};
 }
 
 // Operand types for complex instructions
-class ComplexRotationOperand<int Angle, int Remainder, string Type>
+class ComplexRotationOperand<int Angle, int Remainder, string Type, string Diag>
   : AsmOperandClass {
   let PredicateMethod = "isComplexRotation<" # Angle # ", " # Remainder # ">";
-  let DiagnosticType = "InvalidComplexRotation" # Type;
+  let DiagnosticString = "complex rotation must be " # Diag;
   let Name = "ComplexRotation" # Type;
 }
 def complexrotateop : Operand<i32> {
-  let ParserMatchClass = ComplexRotationOperand<90, 0, "Even">;
+  let ParserMatchClass = ComplexRotationOperand<90, 0, "Even", "0, 90, 180 or 270">;
   let PrintMethod = "printComplexRotationOp<90, 0>";
 }
 def complexrotateopodd : Operand<i32> {
-  let ParserMatchClass = ComplexRotationOperand<180, 90, "Odd">;
+  let ParserMatchClass = ComplexRotationOperand<180, 90, "Odd", "90 or 270">;
   let PrintMethod = "printComplexRotationOp<180, 90>";
 }
 
 // Data type suffix token aliases. Implements Table A7-3 in the ARM ARM.
 def : TokenAlias<".s8", ".i8">;
 def : TokenAlias<".u8", ".i8">;
 def : TokenAlias<".s16", ".i16">;
 def : TokenAlias<".u16", ".i16">;

llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

 //===----------------------------------------------------------------------===//
 // Operand Definitions.
 //
 
 // Immediate operands with a shared generic asm render method.
 class ImmAsmOperand<int Low, int High> : AsmOperandClass {
   let RenderMethod = "addImmOperands";
   let PredicateMethod = "isImmediate<" # Low # "," # High # ">";
-  let DiagnosticType = "ImmRange" # Low # "_" # High;
+  let DiagnosticString = "immediate operand must be in the range [" # Low # "," # High # "]";
 }
 
 class ImmAsmOperandMinusOne<int Low, int High> : AsmOperandClass {
   let PredicateMethod = "isImmediate<" # Low # "," # High # ">";
   let DiagnosticType = "ImmRange" # Low # "_" # High;
+  let DiagnosticString = "immediate operand must be in the range [" # Low # "," # High # "]";
 }
 
 // Operands that are part of a memory addressing mode.
 class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; }
 
 // Branch target.
 // FIXME: rename brtarget to t2_brtarget
 def brtarget : Operand<OtherVT> {

 def Imm1_31AsmOperand: ImmAsmOperand<1,31> { let Name = "Imm1_31"; }
 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
   let ParserMatchClass = Imm1_31AsmOperand;
 }
 
 /// imm0_15 predicate - Immediate in the range [0,15].
 def Imm0_15AsmOperand: ImmAsmOperand<0,15> {
   let Name = "Imm0_15";
-  let DiagnosticType = "ImmRange0_15";
 }
 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
   return Imm >= 0 && Imm < 16;
 }]> {
   let ParserMatchClass = Imm0_15AsmOperand;
 }
 
 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
   return Imm >= 0 && Imm < 64;
 }]> {
   let ParserMatchClass = Imm0_63AsmOperand;
 }
 
 /// imm0_239 predicate - Immediate in the range [0,239].
 def Imm0_239AsmOperand : ImmAsmOperand<0,239> {
   let Name = "Imm0_239";
-  let DiagnosticType = "ImmRange0_239";
 }
 def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> {
   let ParserMatchClass = Imm0_239AsmOperand;
 }
 
 /// imm0_255 predicate - Immediate in the range [0,255].
 def Imm0_255AsmOperand : ImmAsmOperand<0,255> { let Name = "Imm0_255"; }
 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {

 }
 
 def Imm256_65535ExprAsmOperand: ImmAsmOperand<256,65535> { let Name = "Imm256_65535Expr"; }
 def imm256_65535_expr : Operand<i32> {
   let ParserMatchClass = Imm256_65535ExprAsmOperand;
 }
 
 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
-def Imm24bitAsmOperand: ImmAsmOperand<0,0xffffff> { let Name = "Imm24bit"; }
+def Imm24bitAsmOperand: ImmAsmOperand<0,0xffffff> {
+  let Name = "Imm24bit";
+  let DiagnosticString = "immediate operand must be in the range [0,0xffffff]";
+}
 def imm24b : Operand<i32>, ImmLeaf<i32, [{
   return Imm >= 0 && Imm <= 0xffffff;
 }]> {
   let ParserMatchClass = Imm24bitAsmOperand;
 }
 
 
 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
class AddrMode6Align : MemOperand,
   let EncoderMethod = "getAddrMode6AddressOpValue";
   let DecoderMethod = "DecodeAddrMode6Operand";
 }
 
 // Special version of addrmode6 to handle no allowed alignment encoding for
 // VLD/VST instructions and checking the alignment is not specified.
 def AddrMode6AlignNoneAsmOperand : AsmOperandClass {
   let Name = "AlignedMemoryNone";
-  let DiagnosticType = "AlignedMemoryRequiresNone";
+  let DiagnosticString = "alignment must be omitted";
 }
 def addrmode6alignNone : AddrMode6Align {
   // The alignment specifier can only be omitted.
   let ParserMatchClass = AddrMode6AlignNoneAsmOperand;
 }
 
 // Special version of addrmode6 to handle 16-bit alignment encoding for
 // VLD/VST instructions and checking the alignment value.
 def AddrMode6Align16AsmOperand : AsmOperandClass {
   let Name = "AlignedMemory16";
-  let DiagnosticType = "AlignedMemoryRequires16";
+  let DiagnosticString = "alignment must be 16 or omitted";
 }
 def addrmode6align16 : AddrMode6Align {
   // The alignment specifier can only be 16 or omitted.
   let ParserMatchClass = AddrMode6Align16AsmOperand;
 }
 
 // Special version of addrmode6 to handle 32-bit alignment encoding for
 // VLD/VST instructions and checking the alignment value.
 def AddrMode6Align32AsmOperand : AsmOperandClass {
   let Name = "AlignedMemory32";
-  let DiagnosticType = "AlignedMemoryRequires32";
+  let DiagnosticString = "alignment must be 32 or omitted";
 }
 def addrmode6align32 : AddrMode6Align {
   // The alignment specifier can only be 32 or omitted.
   let ParserMatchClass = AddrMode6Align32AsmOperand;
 }
 
 // Special version of addrmode6 to handle 64-bit alignment encoding for
 // VLD/VST instructions and checking the alignment value.
 def AddrMode6Align64AsmOperand : AsmOperandClass {
   let Name = "AlignedMemory64";
-  let DiagnosticType = "AlignedMemoryRequires64";
+  let DiagnosticString = "alignment must be 64 or omitted";
 }
 def addrmode6align64 : AddrMode6Align {
   // The alignment specifier can only be 64 or omitted.
   let ParserMatchClass = AddrMode6Align64AsmOperand;
 }
 
 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
 // for VLD/VST instructions and checking the alignment value.
 def AddrMode6Align64or128AsmOperand : AsmOperandClass {
   let Name = "AlignedMemory64or128";
-  let DiagnosticType = "AlignedMemoryRequires64or128";
+  let DiagnosticString = "alignment must be 64, 128 or omitted";
 }
 def addrmode6align64or128 : AddrMode6Align {
   // The alignment specifier can only be 64, 128 or omitted.
   let ParserMatchClass = AddrMode6Align64or128AsmOperand;
 }
 
 // Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment
 // encoding for VLD/VST instructions and checking the alignment value.
 def AddrMode6Align64or128or256AsmOperand : AsmOperandClass {
   let Name = "AlignedMemory64or128or256";
-  let DiagnosticType = "AlignedMemoryRequires64or128or256";
+  let DiagnosticString = "alignment must be 64, 128, 256 or omitted";
 }
 def addrmode6align64or128or256 : AddrMode6Align {
   // The alignment specifier can only be 64, 128, 256 or omitted.
   let ParserMatchClass = AddrMode6Align64or128or256AsmOperand;
 }
 
 // Special version of addrmode6 to handle alignment encoding for VLD-dup
 // instructions, specifically VLD4-dup.
class AddrMode6DupAlign : MemOperand,
   let MIOperandInfo = (ops GPR:$addr, i32imm);
   let EncoderMethod = "getAddrMode6DupAddressOpValue";
 }
 
 // Special version of addrmode6 to handle no allowed alignment encoding for
 // VLD-dup instruction and checking the alignment is not specified.
 def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass {
   let Name = "DupAlignedMemoryNone";
-  let DiagnosticType = "DupAlignedMemoryRequiresNone";
+  let DiagnosticString = "alignment must be omitted";
 }
 def addrmode6dupalignNone : AddrMode6DupAlign {
   // The alignment specifier can only be omitted.
   let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand;
 }
 
 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
 // instruction and checking the alignment value.
 def AddrMode6dupAlign16AsmOperand : AsmOperandClass {
   let Name = "DupAlignedMemory16";
-  let DiagnosticType = "DupAlignedMemoryRequires16";
+  let DiagnosticString = "alignment must be 16 or omitted";
 }
 def addrmode6dupalign16 : AddrMode6DupAlign {
   // The alignment specifier can only be 16 or omitted.
   let ParserMatchClass = AddrMode6dupAlign16AsmOperand;
 }
 
 // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
 // instruction and checking the alignment value.
 def AddrMode6dupAlign32AsmOperand : AsmOperandClass {
   let Name = "DupAlignedMemory32";
-  let DiagnosticType = "DupAlignedMemoryRequires32";
+  let DiagnosticString = "alignment must be 32 or omitted";
 }
 def addrmode6dupalign32 : AddrMode6DupAlign {
   // The alignment specifier can only be 32 or omitted.
   let ParserMatchClass = AddrMode6dupAlign32AsmOperand;
 }
 
 // Special version of addrmode6 to handle 64-bit alignment encoding for VLD
 // instructions and checking the alignment value.
 def AddrMode6dupAlign64AsmOperand : AsmOperandClass {
   let Name = "DupAlignedMemory64";
-  let DiagnosticType = "DupAlignedMemoryRequires64";
+  let DiagnosticString = "alignment must be 64 or omitted";
 }
 def addrmode6dupalign64 : AddrMode6DupAlign {
   // The alignment specifier can only be 64 or omitted.
   let ParserMatchClass = AddrMode6dupAlign64AsmOperand;
 }
 
 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
 // for VLD instructions and checking the alignment value.
 def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass {
   let Name = "DupAlignedMemory64or128";
-  let DiagnosticType = "DupAlignedMemoryRequires64or128";
+  let DiagnosticString = "alignment must be 64, 128 or omitted";
 }
 def addrmode6dupalign64or128 : AddrMode6DupAlign {
   // The alignment specifier can only be 64, 128 or omitted.
   let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand;
 }
 
 // addrmodepc := pc + reg
 //

llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
                             bool MatchingInlineAsm, bool &EmitInITBlock,
                             MCStreamer &Out);
 
   struct NearMissMessage {
     SMLoc Loc;
     SmallString<128> Message;
   };
 
-  const char *getOperandMatchFailDiag(ARMMatchResultTy Error);
   void FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
                         SmallVectorImpl<NearMissMessage> &NearMissesOut,
                         SMLoc IDLoc, OperandVector &Operands);
   void ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses, SMLoc IDLoc,
                         OperandVector &Operands);
 
   void onLabelParsed(MCSymbol *Symbol) override;
 };
extern "C" void LLVMInitializeARMAsmParser() {
   RegisterMCAsmParser<ARMAsmParser> B(getTheThumbBETarget());
 }
 
 #define GET_REGISTER_MATCHER
 #define GET_SUBTARGET_FEATURE_NAME
 #define GET_MATCHER_IMPLEMENTATION
 #include "ARMGenAsmMatcher.inc"
 
-const char *ARMAsmParser::getOperandMatchFailDiag(ARMMatchResultTy Error) {
-  switch (Error) {
-  case Match_AlignedMemoryRequiresNone:
-  case Match_DupAlignedMemoryRequiresNone:
-    return "alignment must be omitted";
-  case Match_AlignedMemoryRequires16:
-  case Match_DupAlignedMemoryRequires16:
-    return "alignment must be 16 or omitted";
-  case Match_AlignedMemoryRequires32:
-  case Match_DupAlignedMemoryRequires32:
-    return "alignment must be 32 or omitted";
-  case Match_AlignedMemoryRequires64:
-  case Match_DupAlignedMemoryRequires64:
-    return "alignment must be 64 or omitted";
-  case Match_AlignedMemoryRequires64or128:
-  case Match_DupAlignedMemoryRequires64or128:
-    return "alignment must be 64, 128 or omitted";
-  case Match_AlignedMemoryRequires64or128or256:
-    return "alignment must be 64, 128, 256 or omitted";
-  case Match_ImmRange0_1:
-    return "immediate operand must be in the range [0,1]";
-  case Match_ImmRange0_3:
-    return "immediate operand must be in the range [0,3]";
-  case Match_ImmRange0_7:
-    return "immediate operand must be in the range [0,7]";
-  case Match_ImmRange0_15:
-    return "immediate operand must be in the range [0,15]";
-  case Match_ImmRange0_31:
-    return "immediate operand must be in the range [0,31]";
-  case Match_ImmRange0_32:
-    return "immediate operand must be in the range [0,32]";
-  case Match_ImmRange0_63:
-    return "immediate operand must be in the range [0,63]";
-  case Match_ImmRange0_239:
-    return "immediate operand must be in the range [0,239]";
-  case Match_ImmRange0_255:
-    return "immediate operand must be in the range [0,255]";
-  case Match_ImmRange0_4095:
-    return "immediate operand must be in the range [0,4095]";
-  case Match_ImmRange0_65535:
-    return "immediate operand must be in the range [0,65535]";
-  case Match_ImmRange1_7:
-    return "immediate operand must be in the range [1,7]";
-  case Match_ImmRange1_8:
-    return "immediate operand must be in the range [1,8]";
-  case Match_ImmRange1_15:
-    return "immediate operand must be in the range [1,15]";
-  case Match_ImmRange1_16:
-    return "immediate operand must be in the range [1,16]";
-  case Match_ImmRange1_31:
-    return "immediate operand must be in the range [1,31]";
-  case Match_ImmRange1_32:
-    return "immediate operand must be in the range [1,32]";
-  case Match_ImmRange1_64:
-    return "immediate operand must be in the range [1,64]";
-  case Match_ImmRange8_8:
-    return "immediate operand must be 8.";
-  case Match_ImmRange16_16:
-    return "immediate operand must be 16.";
-  case Match_ImmRange32_32:
-    return "immediate operand must be 32.";
-  case Match_ImmRange256_65535:
-    return "immediate operand must be in the range [255,65535]";
-  case Match_ImmRange0_16777215:
-    return "immediate operand must be in the range [0,0xffffff]";
-  case Match_InvalidComplexRotationEven:
-      return "complex rotation must be 0, 90, 180 or 270";
-  case Match_InvalidComplexRotationOdd:
-      return "complex rotation must be 90 or 270";
-  default:
-    return nullptr;
-  }
-}
-
 // Process the list of near-misses, throwing away ones we don't want to report
 // to the user, and converting the rest to a source location and string that
 // should be reported.
 void
 ARMAsmParser::FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
                                SmallVectorImpl<NearMissMessage> &NearMissesOut,
                                SMLoc IDLoc, OperandVector &Operands) {
   // TODO: If operand didn't match, sub in a dummy one and run target
ARMAsmParser::FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
   // Process the near-misses in reverse order, so that we see more general ones
   // first, and so can avoid emitting more specific ones.
   for (NearMissInfo &I : reverse(NearMissesIn)) {
     switch (I.getKind()) {
     case NearMissInfo::NearMissOperand: {
       SMLoc OperandLoc =
           ((ARMOperand &)*Operands[I.getOperandIndex()]).getStartLoc();
       const char *OperandDiag =
-          getOperandMatchFailDiag((ARMMatchResultTy)I.getOperandError());
+          getMatchKindDiag((ARMMatchResultTy)I.getOperandError());
 
       // If we have already emitted a message for a superclass, don't also report
       // the sub-class. We consider all operand classes that we don't have a
       // specialised diagnostic for to be equal for the propose of this check,
       // so that we don't report the generic error multiple times on the same
       // operand.
       unsigned DupCheckMatchClass = OperandDiag ? I.getOperandClass() : ~0U;
       auto PrevReports = OperandMissesSeen.equal_range(I.getOperandIndex());

llvm/trunk/test/MC/ARM/lsl-zero-errors.s

 // CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
 // CHECK-NONARM-NEXT: mov pc, r0, lsl #0
 // CHECK-NONARM: invalid operand for instruction
 // CHECK-NONARM: invalid operand for instruction
 // CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
 // CHECK-NONARM-NEXT: mov r0, pc, lsl #0
 // CHECK-NONARM: invalid operand for instruction
 // CHECK-NONARM: invalid operand for instruction
-// CHECK-NONARM: immediate operand must be in the range [255,65535]
+// CHECK-NONARM: immediate operand must be in the range [256,65535]
 // CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
 // CHECK-NONARM-NEXT: mov pc, pc, lsl #0
 // CHECK-NONARM: invalid operand for instruction
 // CHECK-NONARM: invalid operand for instruction
 // CHECK-NONARM: error: invalid operand for instruction
 // CHECK-NONARM-NEXT: movs pc, r0, lsl #0
 // CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
 // CHECK-NONARM-NEXT: movs r0, pc, lsl #0

llvm/trunk/test/MC/ARM/t2-modified-immediate-fixup-error2.s

 @ PR28647
 @ RUN: not llvm-mc -triple=thumbv7a-linux-gnueabi -filetype=obj < %s 2>&1 | FileCheck %s
     .text
     .syntax unified
     .balign 2
 
 @ mov with :upper16: or :lower16: should not match mov with modified immediate
     mov r0, :upper16: sym0
 @ CHECK: error: invalid instruction, any one of the following would fix this:
 @ CHECK: note: instruction requires: arm-mode
 @ CHECK: note: invalid operand for instruction
-@ CHECK: note: immediate operand must be in the range [255,65535]
+@ CHECK: note: immediate operand must be in the range [256,65535]
     mov r0, :lower16: sym0
 @ CHECK: error: invalid instruction, any one of the following would fix this:
 @ CHECK: note: instruction requires: arm-mode
 @ CHECK: note: invalid operand for instruction
-@ CHECK: note: immediate operand must be in the range [255,65535]
+@ CHECK: note: immediate operand must be in the range [256,65535]
     .equ sym0, 0x01abcdef