[DAG] optimize negation of bool

[spatel]

Summary

Use mask and and negate for legalization of i1 source type with SIGN_EXTEND_INREG.

[zvi]

Sanjay, can you please a RUN: and CHECK:'s for a 32-bit target?

[efriedma]

Can we do this in SelectionDAGLegalize::ExpandNode instead? I suppose in theory some platform might prefer to lower this using shifts, but I can't think of any off the top of my head.

lib/Target/X86/X86ISelLowering.cpp

16343 ↗

(On Diff #74289)

Given "SIGN_EXTEND_INREG(X, i1)", you can transform it to "-(X&1)". But you can't assume the input is zero-extended. I think your patch misbehaves for the following testcase:

define void @_Z1fbi(i1 zeroext %a, i32 %b, i8* %p) local_unnamed_addr #0 {
entry:
  %conv = trunc i32 %b to i1
  %or = or i1 %a, %conv
  %s = sext i1 %or to i8
  store i8 %s, i8* %p
  ret void
}

[spatel]

In D25485#568598, @efriedma wrote:

Can we do this in SelectionDAGLegalize::ExpandNode instead? I suppose in theory some platform might prefer to lower this using shifts, but I can't think of any off the top of my head.

Would we still need to do the 'and' masking op though? In that case, there's probably no win?

lib/Target/X86/X86ISelLowering.cpp

16343 ↗

(On Diff #74289)

Ah, I misunderstood the meaning/guarantee of the source value type of ISD::SIGN_EXTEND_INREG.
So for the given example, we get:

orb   %dil, %sil
shlb   $7, %sil
sarb   $7, %sil
movb   %sil, (%rdx)

But with this patch:

orb   %dil, %sil
negb   %sil
movb   %sil, (%rdx)

And that's wrong if any of the higher bits of %b / %sil are set.

[efriedma]

DAGCombine can eliminate the mask instruction in a lot of cases (if the value is in fact zero-extended). Also, the mask+neg is probably slightly more efficient than two shifts on most processors.

[spatel]

In D25485#568525, @zvi wrote:

Sanjay, can you please a RUN: and CHECK:'s for a 32-bit target?

Sure, that's:
https://reviews.llvm.org/rL284124

[spatel]

In D25485#568808, @efriedma wrote:

DAGCombine can eliminate the mask instruction in a lot of cases (if the value is in fact zero-extended). Also, the mask+neg is probably slightly more efficient than two shifts on most processors.

Yes, you're correct - thanks!

So I tried the SelectionDAGLegalize::ExpandNode suggestion, and I see one problem case: micromips.
I don't know micromips (cc'ing @sdardis and @dsanders), but it doesn't appear to have a negate instruction. If we legalize to and+negate, the code grows from something like:

sll	$1, $1, 31
jr	$ra
sra	$2, $1, 31

To:

andi16	$2, $2, 1
li16	$3, 0
subu16	$2, $3, $2
jrc	$ra

Given this potential regression, I'd like to proceed with the x86-only solution for now (I will add a TODO comment about making it more general). As noted in the initial summary, I have filed bugs for the PPC and ARM folks and linked to this patch, so they are aware of what is needed to pursue the common solution.

[spatel]

Patch updated:
This is still an x86-only solution, but now we correctly mask the operand before negation. As Eli noted, the mask is optimized away when we know the operand's top bits are already zero (via zeroext on the input parameter in the test cases).

[sdardis]

We don't have a negate instruction, we use "nor $dst, $src, $zero" instead. "nor" present in all our ISAs except mips16 which has an actual negate instruction.

Did that regression hit general MIPS code or just microMIPS? It's possible that we have a missing pattern for microMIPS in that case. I'll give this patch a whirl.

[spatel]

In D25485#569279, @sdardis wrote:

We don't have a negate instruction, we use "nor $dst, $src, $zero" instead. "nor" present in all our ISAs except mips16 which has an actual negate instruction.

Did that regression hit general MIPS code or just microMIPS? It's possible that we have a missing pattern for microMIPS in that case. I'll give this patch a whirl.

I only saw the regression for a RUN with the micromips attribute specified. Here are the tests that were affected by the LegalizeDAG patch which I'll attach here if you'd like to try it:

LLVM :: CodeGen/Mips/llvm-ir/add.ll
 LLVM :: CodeGen/Mips/llvm-ir/mul.ll
 LLVM :: CodeGen/Mips/llvm-ir/sdiv.ll
 LLVM :: CodeGen/Mips/llvm-ir/srem.ll
 LLVM :: CodeGen/Mips/llvm-ir/sub.ll
 LLVM :: CodeGen/Mips/llvm-ir/urem.ll
 LLVM :: CodeGen/Mips/select.ll
 LLVM :: CodeGen/SystemZ/branch-07.ll
 LLVM :: CodeGen/SystemZ/risbg-01.ll
 LLVM :: CodeGen/SystemZ/shift-10.ll
 LLVM :: CodeGen/X86/negate-i1.ll

[spatel]

sext_in_reg_legalize.patch21 KBDownload

patch for LegalizeDAG

[dsanders]

In D25485#569279, @sdardis wrote:

We don't have a negate instruction, we use "nor $dst, $src, $zero" instead. "nor" present in all our ISAs except mips16 which has an actual negate instruction.

Did that regression hit general MIPS code or just microMIPS? It's possible that we have a missing pattern for microMIPS in that case. I'll give this patch a whirl.

Arithmetic and bitwise negation are equivalent in this case but just to mention it. The arithmetic negation is 'sub $dst, $zero, $src'. IIRC, GAS has a 'neg' alias for this but I don't think it's implemented in LLVM yet.

[sdardis]

There are some neg<-> aliases in LLVM for MIPS which is what you're seeing in the produced assembly. The main reason for the different is it's not possible to use $zero with the 16 bit instructions.

As Daniel pointed out, you can use subtraction in that case. The produced assembly from that selection dag patch is actually better than what we're currently getting in terms of size as li16, subu16 are 16 bits each, the two constant shifts are 32bits each. The optimal case would be to use a 32bit microMIPS instruction with the register $zero (better than current in terms of size and # instructions). The new instruction pattern for microMIPS should be easy to fold away.

[spatel]

In D25485#569347, @sdardis wrote:

As Daniel pointed out, you can use subtraction in that case. The produced assembly from that selection dag patch is actually better than what we're currently getting in terms of size as li16, subu16 are 16 bits each, the two constant shifts are 32bits each. The optimal case would be to use a 32bit microMIPS instruction with the register $zero (better than current in terms of size and # instructions). The new instruction pattern for microMIPS should be easy to fold away.

Ah, so if the LegalizeDAG patch is an improvement anyway (if not always optimal) for MIPS, then I'll update this patch to use that along with all of the regression test updates.

[spatel]

Looking closer at the SystemZ regression test differences, we have more instructions with the LegalizeDAG patch, so I think that target is missing a pattern ( cc'ing @uweigand and @jonpa ).

Example - the current code for test 'f7' in test/CodeGen/SystemZ/branch-07.ll is:

cr  %r2, %r3
ipm %r0
afi %r0, -268435456
sra %r0, 31
srlg  %r1, %r3, 32
srlg  %r2, %r2, 32
cr  %r2, %r1
ipm %r1
afi %r1, -268435456
sra %r1, 31
sllg  %r2, %r1, 32
lr  %r2, %r0
br  %r14

With the LegalizeDAG patch, it becomes:

cr  %r2, %r3
ipm %r0
afi %r0, -268435456
srl %r0, 31
lcr %r0, %r0
srlg  %r1, %r3, 32
srlg  %r2, %r2, 32
cr  %r2, %r1
ipm %r1
afi %r1, -268435456
srl %r1, 31
lcr %r1, %r1
sllg  %r2, %r1, 32
lr  %r2, %r0
br  %r14

[spatel]

In D25485#569404, @spatel wrote:

Looking closer at the SystemZ regression test differences, we have more instructions with the LegalizeDAG patch, so I think that target is missing a pattern ( cc'ing @uweigand and @jonpa ).

On 2nd thought, this is a missing combine for all targets:

define i32 @topbit(i32 %x) {
  %sra = ashr i32 %x, 31
  %neg = sub i32 0, %sra
  ret i32 %neg
}

Should be simplified to:

%neg = lshr i32 %x, 31

[spatel]

A patch for the missing DAGCombines of shifts was committed here:
rL284239
and improved:
rL284269

So now I'm trying for the universal (not just x86) fix and added tests for PR30660/30661:
rL284279
rL284280

[spatel]

Patch upated:
Use mask+negate universally via LegalizeDAG.

There are improvements in the tests for x86, PPC, ARM, and MIPS.
SystemZ looks neutral to me, but I have no experience with that target. I assume it would see the same improvement (optimize away the mask) if we added tests for that.
There's an extra 'negu' in the MIPS select test. I didn't check to see what is going on there.
Based on the earlier comments, I think we're ok with an added instruction in the microMIPS cases as long as there's a reduction in the code size.

[zvi]

test/CodeGen/X86/negate-i1.ll

131 ↗

(On Diff #74742)

This SAR is redundant. Does DAGCombine know that SAR(all_ones/allzeros) is redundant?

[uweigand]

Yes, the SystemZ changes now look fine to me.

[spatel]

test/CodeGen/X86/negate-i1.ll

131 ↗

(On Diff #74742)

It knows sometimes, but of course it missed this one. I'll work on that patch now.

[spatel]

Patch updated:
Rebased after rL284395 so we no longer have the unnecessary 'sar' in the x86-32 test as noted by Zvi.
The vector side of that fold needs more work and is currently up for review with D25685.

[spatel]

In D25485#570870, @spatel wrote:

There's an extra 'negu' in the MIPS select test. I didn't check to see what is going on there.

This isn't extra. The existing CHECK lines don't include the sll/sra pair, so this is actually a win, not a regression.

Before:

mtc1	$5, $f1
mtc1	$6, $f2
sltu	$1, $zero, $4
sll	$1, $1, 31
sra	$1, $1, 31
mtc1	$1, $f0
jr	 $ra
sel.s	$f0, $f2, $f1

After:

sltu	$1, $zero, $4
negu	 $1, $1   <--- the 'and' mask was folded away, so we saved an instruction
mtc1	$5, $f1
mtc1	$6, $f2
mtc1	$1, $f0
jr	 $ra
sel.s	$f0, $f2, $f1

Based on the earlier comments, I think we're ok with an added instruction in the microMIPS cases as long as there's a reduction in the code size.

@sdardis / @dsanders : do you see any common folds that are missing based on the MIPS diffs? I don't think you want me trying any MIPS-specific hacks, so if there's a net win already, we should be ok to proceed?

[zvi]

The changes to the legalizer + X86 tests LGTM. Thanks!

[sdardis]

LGTM, unless ARM/PPC backend maintainers want to jump in. Two comments inlined.

do you see any common folds that are missing based on the MIPS diffs?

I'm happy with codesize reduction in the microMIPS case, the missing fold/optimization case is subtraction by zero but that shouldn't hold this patch up. I'll deal with/work on the instruction count reduction change later.

Thanks,
Simon

test/CodeGen/Mips/llvm-ir/add.ll

48–49 ↗

(On Diff #74870)

Add a comment above here along the lines of:

; FIXME: This code sequence is inefficient as it should be 'subu $[[T0]], $zero, $[[T0]'. This sequence is even better as it's a single instruction. See D25485 for the rest of the cases where this sequence occurs.

test/CodeGen/Mips/llvm-ir/mul.ll

23–26 ↗

(On Diff #74742)

Unnecessary change.

[spatel]

Thanks, Simon. I'll make the suggested changes and get this in.

Note that the MIPS tests for sdiv/urem/srem with i1 values *are* universal folds (can't divide by zero, so these disappear?), but I'm wondering how those patterns would appear in the backend. We do have IR-level folds for those in InstSimplify.

[sdardis]

Thanks.

Looking at the existing test output for division by i1 leads me to believe they're correct but perhaps not optimal in the sense of "division by zero => undefined behaviour". Taking that view, division of an i1 by an i1 should yield the numerator always, as for MIPS division by zero yields an undefined result and hence division by an i1 should be folded away (unless -mcheck-zero-division is active).

I'll investigate that issue in a bit, but it's an optimization issue, not a correctness issue.

Thanks,
Simon

[amehsan]

test/CodeGen/PowerPC/negate-i1.ll

2–4 ↗

(On Diff #74870)

please add -verify-machineinstrs to RUN command line. We make sure that we add it to all tests in our backend. Also -mtriple=powerpc64le-unknown-linux-gnu is a more common triple.

[hfinkel]

LGTM, unless ARM/PPC backend maintainers want to jump in. Two comments inlined.

LGTM too.

[amehsan]

test/CodeGen/PowerPC/negate-i1.ll

2–4 ↗

(On Diff #74870)

(I believe you just created and committed this in r284279. That is why I am asking to make a change in a place that is not modified in this patch :)

[spatel]

test/CodeGen/PowerPC/negate-i1.ll

2–4 ↗

(On Diff #74870)

Correct - I added the test, so we could close PR30661 when this patch is committed.

Note that the comment on line 1 gives away why I used the apple-darwin triple; I thought that would be an easier regex hack while adapting the script that we use for x86 auto-generation of CHECK lines. :)

Thank you for pointing out the improvements - I'll fix these up.

[spatel]

Patch updated:

1. Added FIXME comment to Mips test file to note optimization opportunity.
2. Removed inadvertent changes to RUN lines in Mips test file.
3. Added -verify-machineinstrs option for PPC test.
4. Changed PPC test triple to powerpc64le-unknown-linux-gnu.

I'll let this sit a bit in case there is any feedback from the ARM coders.

llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

case ISD::BITCAST:
     break;
   case ISD::FP_EXTEND:
     Tmp1 = EmitStackConvert(Node->getOperand(0),
                             Node->getOperand(0).getValueType(),
                             Node->getValueType(0), dl);
     Results.push_back(Tmp1);
     break;
   case ISD::SIGN_EXTEND_INREG: {
-    // NOTE: we could fall back on load/store here too for targets without
-    // SAR.  However, it is doubtful that any exist.
     EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
     EVT VT = Node->getValueType(0);
+
+    // An in-register sign-extend of a boolean is a negation:
+    // 'true' (1) sign-extended is -1.
+    // 'false' (0) sign-extended is 0.
+    // However, we must mask the high bits of the source operand because the
+    // SIGN_EXTEND_INREG does not guarantee that the high bits are already zero.
+
+    // TODO: Do this for vectors too?
+    if (ExtraVT.getSizeInBits() == 1) {
+      SDValue One = DAG.getConstant(1, dl, VT);
+      SDValue And = DAG.getNode(ISD::AND, dl, VT, Node->getOperand(0), One);
+      SDValue Zero = DAG.getConstant(0, dl, VT);
+      SDValue Neg = DAG.getNode(ISD::SUB, dl, VT, Zero, And);
+      Results.push_back(Neg);
+      break;
+    }
+
+    // NOTE: we could fall back on load/store here too for targets without
+    // SRA.  However, it is doubtful that any exist.
     EVT ShiftAmountTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
     if (VT.isVector())
       ShiftAmountTy = VT;
     unsigned BitsDiff = VT.getScalarSizeInBits() -
                         ExtraVT.getScalarSizeInBits();
     SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
     Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
                        Node->getOperand(0), ShiftCst);

llvm/trunk/test/CodeGen/ARM/negate-i1.ll

 ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
 
 ; PR30660 - https://llvm.org/bugs/show_bug.cgi?id=30660
 
 define i32 @select_i32_neg1_or_0(i1 %a) {
 ; CHECK-LABEL: select_i32_neg1_or_0:
 ; CHECK-NEXT:  @ BB#0:
-; CHECK-NEXT:    lsl r0, r0, #31
-; CHECK-NEXT:    asr r0, r0, #31
+; CHECK-NEXT:    and r0, r0, #1
+; CHECK-NEXT:    rsb r0, r0, #0
 ; CHECK-NEXT:    mov pc, lr
 ;
   %b = sext i1 %a to i32
   ret i32 %b
 }
 
 define i32 @select_i32_neg1_or_0_zeroext(i1 zeroext %a) {
 ; CHECK-LABEL: select_i32_neg1_or_0_zeroext:
 ; CHECK-NEXT:  @ BB#0:
-; CHECK-NEXT:    lsl r0, r0, #31
-; CHECK-NEXT:    asr r0, r0, #31
+; CHECK-NEXT:    rsb r0, r0, #0
 ; CHECK-NEXT:    mov pc, lr
 ;
   %b = sext i1 %a to i32
   ret i32 %b
 }
 

llvm/trunk/test/CodeGen/Mips/llvm-ir/add.ll

 ; RUN:    -check-prefixes=ALL,R2-R6,GP64
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -O2 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MMR6,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MMR6,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -O2 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MMR6,MM64
 
+
+; FIXME: This code sequence is inefficient as it should be 'subu $[[T0]], $zero, $[[T0]'. 
+; This sequence is even better as it's a single instruction. See D25485 for the rest of 
+; the cases where this sequence occurs.
+
 define signext i1 @add_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: add_i1:
 
-  ; NOT-R2-R6:  addu    $[[T0:[0-9]+]], $4, $5
-  ; NOT-R2-R6:  sll     $[[T0]], $[[T0]], 31
-  ; NOT-R2-R6:  sra     $2, $[[T0]], 31
+  ; NOT-R2-R6:  addu   $[[T0:[0-9]+]], $4, $5
+  ; NOT-R2-R6:  andi   $[[T0]], $[[T0]], 1
+  ; NOT-R2-R6:  negu   $2, $[[T0]]
 
-  ; R2-R6:      addu    $[[T0:[0-9]+]], $4, $5
-  ; R2-R6:      sll     $[[T0]], $[[T0]], 31
-  ; R2-R6:      sra     $2, $[[T0]], 31
+  ; R2-R6:      addu   $[[T0:[0-9]+]], $4, $5
+  ; R2-R6:      andi   $[[T0]], $[[T0]], 1
+  ; R2-R6:      negu   $2, $[[T0]]
 
   ; MMR6:       addu16  $[[T0:[0-9]+]], $4, $5
-  ; MMR6:       sll     $[[T1:[0-9]+]], $[[T0]], 31
-  ; MMR6:       sra     $2, $[[T1]], 31
+  ; MMR6:       andi16  $[[T0]], $[[T0]], 1
+  ; MMR6:       li16    $[[T1:[0-9]+]], 0
+  ; MMR6:       subu16  $[[T0]], $[[T1]], $[[T0]]
 
   %r = add i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @add_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: add_i8:
; ALL-LABEL: add_i128_4:
   ; MM64:       daddu   $2, $4, $[[T1]]
 
   %r = add i128 4, %a
   ret i128 %r
 }
 
 define signext i1 @add_i1_3(i1 signext %a) {
 ; ALL-LABEL: add_i1_3:
-
-  ; ALL:        sll     $[[T0:[0-9]+]], $4, 31
-  ; ALL:        lui     $[[T1:[0-9]+]], 32768
-
-  ; GP32:       addu    $[[T0]], $[[T0]], $[[T1]]
-  ; GP32:       sra     $[[T1]], $[[T0]], 31
-
-  ; GP64:       addu    $[[T0]], $[[T0]], $[[T1]]
-  ; GP64:       sra     $[[T1]], $[[T0]], 31
-
-  ; MMR6:       addu16  $[[T0]], $[[T0]], $[[T1]]
-  ; MMR6:       sra     $[[T0]], $[[T0]], 31
+  ; GP32:        addiu  $[[T0:[0-9]+]], $4, 1
+  ; GP32:        andi   $[[T0]], $[[T0]], 1
+  ; GP32:        negu   $2, $[[T0]]
+
+  ; GP64:        addiu  $[[T0:[0-9]+]], $4, 1
+  ; GP64:        andi   $[[T0]], $[[T0]], 1
+  ; GP64:        negu   $2, $[[T0]]
+
+  ; MMR6:        addiur2 $[[T0:[0-9]+]], $4, 1
+  ; MMR6:        andi16  $[[T0]], $[[T0]], 1
+  ; MMR6:        li16    $[[T1:[0-9]+]], 0
+  ; MMR6:        subu16  $2, $[[T1]], $[[T0]]
 
   %r = add i1 3, %a
   ret i1 %r
 }
 
 define signext i8 @add_i8_3(i8 signext %a) {
 ; ALL-LABEL: add_i8_3:
 

llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll

 ; RUN:   FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | \
 ; RUN:   FileCheck %s -check-prefixes=ALL,64R6
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | \
 ; RUN:   FileCheck %s -check-prefixes=MM32,MM32R3
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | \
 ; RUN:   FileCheck %s -check-prefixes=MM32,MM32R6
 ; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | \
-; RUN:   FileCheck %s -check-prefix=64R6
+; RUN:   FileCheck %s -check-prefix=MM64R6
 
 define signext i1 @mul_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: mul_i1:
 
   ; M2:         mult    $4, $5
   ; M2:         mflo    $[[T0:[0-9]+]]
-  ; M2:         sll     $[[T0]], $[[T0]], 31
-  ; M2:         sra     $2, $[[T0]], 31
+  ; M2:         andi    $[[T0]], $[[T0]], 1
+  ; M2:         negu    $2, $[[T0]]
 
   ; 32R1-R5:    mul     $[[T0:[0-9]+]], $4, $5
-  ; 32R1-R5:    sll     $[[T0]], $[[T0]], 31
-  ; 32R1-R5:    sra     $2, $[[T0]], 31
+  ; 32R1-R5:    andi    $[[T0]], $[[T0]], 1
+  ; 32R1-R5:    negu    $2, $[[T0]]
 
   ; 32R6:       mul     $[[T0:[0-9]+]], $4, $5
-  ; 32R6:       sll     $[[T0]], $[[T0]], 31
-  ; 32R6:       sra     $2, $[[T0]], 31
+  ; 32R6:       andi    $[[T0]], $[[T0]], 1
+  ; 32R6:       negu    $2, $[[T0]]
 
   ; M4:         mult    $4, $5
   ; M4:         mflo    $[[T0:[0-9]+]]
-  ; M4:         sll     $[[T0]], $[[T0]], 31
-  ; M4:         sra     $2, $[[T0]], 31
+  ; M4:         andi    $[[T0]], $[[T0]], 1
+  ; M4:         negu    $2, $[[T0]]
 
   ; 64R1-R5:    mul     $[[T0:[0-9]+]], $4, $5
-  ; 64R1-R5:    sll     $[[T0]], $[[T0]], 31
-  ; 64R1-R5:    sra     $2, $[[T0]], 31
+  ; 64R1-R5:    andi    $[[T0]], $[[T0]], 1
+  ; 64R1-R5:    negu    $2, $[[T0]]
 
   ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
-  ; 64R6:       sll     $[[T0]], $[[T0]], 31
-  ; 64R6:       sra     $2, $[[T0]], 31
+  ; 64R6:       andi    $[[T0]], $[[T0]], 1
+  ; 64R6:       negu    $2, $[[T0]]
+
+  ; MM64R6:     mul     $[[T0:[0-9]+]], $4, $5
+  ; MM64R6:     andi16  $[[T0]], $[[T0]], 1
+  ; MM64R6:     li16    $[[T1:[0-9]+]], 0
+  ; MM64R6:     subu16  $2, $[[T1]], $[[T0]]
 
   ; MM32:       mul     $[[T0:[0-9]+]], $4, $5
-  ; MM32:       sll     $[[T0]], $[[T0]], 31
-  ; MM32:       sra     $2, $[[T0]], 31
+  ; MM32:       andi16  $[[T0]], $[[T0]], 1
+  ; MM32:       li16    $[[T1:[0-9]+]], 0
+  ; MM32:       subu16  $2, $[[T1]], $[[T0]]
 
   %r = mul i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @mul_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: mul_i8:
; ALL-LABEL: mul_i8:
   ; 64R1:       sra     $2, $[[T0]], 24
 
   ; 64R2:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R2:       seb     $2, $[[T0]]
 
   ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R6:       seb     $2, $[[T0]]
 
+  ; MM64R6:     mul     $[[T0:[0-9]+]], $4, $5
+  ; MM64R6:     seb     $2, $[[T0]]
+
   ; MM32:       mul     $[[T0:[0-9]+]], $4, $5
   ; MM32:       seb     $2, $[[T0]]
 
   %r = mul i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @mul_i16(i16 signext %a, i16 signext %b) {
; ALL-LABEL: mul_i16:
   ; 64R1:       sra     $2, $[[T0]], 16
 
   ; 64R2:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R2:       seh     $2, $[[T0]]
 
   ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R6:       seh     $2, $[[T0]]
 
+  ; MM64R6:     mul     $[[T0:[0-9]+]], $4, $5
+  ; MM64R6:     seh     $2, $[[T0]]
+
   ; MM32:       mul     $[[T0:[0-9]+]], $4, $5
   ; MM32:       seh     $2, $[[T0]]
 
   %r = mul i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @mul_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: mul_i32:
 
   ; M2:         mult    $4, $5
   ; M2:         mflo    $2
 
   ; 32R1-R5:    mul     $2, $4, $5
   ; 32R6:       mul     $2, $4, $5
 
   ; 64R1-R5:    mul     $2, $4, $5
   ; 64R6:       mul     $2, $4, $5
+  ; MM64R6:     mul     $2, $4, $5
 
   ; MM32:       mul     $2, $4, $5
 
   %r = mul i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @mul_i64(i64 signext %a, i64 signext %b) {
; ALL-LABEL: mul_i64:
 
   ; M4:         dmult   $4, $5
   ; M4:         mflo    $2
 
   ; 64R1-R5:    dmult   $4, $5
   ; 64R1-R5:    mflo    $2
 
   ; 64R6:       dmul    $2, $4, $5
+  ; MM64R6:     dmul    $2, $4, $5
 
   ; MM32R3:     multu   $[[T0:[0-9]+]], $7
   ; MM32R3:     mflo    $[[T1:[0-9]+]]
   ; MM32R3:     mfhi    $[[T2:[0-9]+]]
   ; MM32R3:     mul     $[[T0]], $[[T0]], $6
   ; MM32R3:     addu16  $2, $[[T2]], $[[T0]]
   ; MM32R3:     mul     $[[T3:[0-9]+]], $4, $7
   ; MM32R3:     addu16  $[[T2]], $[[T2]], $[[T3]]
; ALL-LABEL: mul_i128:
 
   ; 64R6-DAG:       dmul    $[[T1:[0-9]+]], $5, $6
   ; 64R6:           dmuhu   $[[T2:[0-9]+]], $5, $7
   ; 64R6:           daddu   $[[T3:[0-9]+]], $[[T2]], $[[T1]]
   ; 64R6-DAG:       dmul    $[[T0:[0-9]+]], $4, $7
   ; 64R6:           daddu   $2, $[[T1]], $[[T0]]
   ; 64R6-DAG:       dmul    $3, $5, $7
 
+  ; MM64R6-DAG:     dmul    $[[T1:[0-9]+]], $5, $6
+  ; MM64R6:         dmuhu   $[[T2:[0-9]+]], $5, $7
+  ; MM64R6:         daddu   $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; MM64R6-DAG:     dmul    $[[T0:[0-9]+]], $4, $7
+  ; MM64R6:         daddu   $2, $[[T1]], $[[T0]]
+  ; MM64R6-DAG:     dmul    $3, $5, $7
+
   ; MM32:           lw      $25, %call16(__multi3)($16)
 
   %r = mul i128 %a, %b
   ret i128 %r
 }

llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll

 
 define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: sdiv_i1:
 
   ; NOT-R6:       div     $zero, $4, $5
   ; NOT-R6:       teq     $5, $zero, 7
   ; NOT-R6:       mflo    $[[T0:[0-9]+]]
-  ; FIXME: The sll/sra instructions are redundant since div is signed.
-  ; NOT-R6:       sll     $[[T1:[0-9]+]], $[[T0]], 31
-  ; NOT-R6:       sra     $2, $[[T1]], 31
+  ; FIXME: The andi/negu instructions are redundant since div is signed.
+  ; NOT-R6:       andi    $[[T0]], $[[T0]], 1
+  ; NOT-R6:       negu    $2, $[[T0]]
 
   ; R6:           div     $[[T0:[0-9]+]], $4, $5
   ; R6:           teq     $5, $zero, 7
-  ; FIXME: The sll/sra instructions are redundant since div is signed.
-  ; R6:           sll     $[[T1:[0-9]+]], $[[T0]], 31
-  ; R6:           sra     $2, $[[T1]], 31
+  ; FIXME: The andi/negu instructions are redundant since div is signed.
+  ; R6:           andi    $[[T0]], $[[T0]], 1
+  ; R6:           negu    $2, $[[T0]]
 
   ; MMR3:         div     $zero, $4, $5
   ; MMR3:         teq     $5, $zero, 7
   ; MMR3:         mflo    $[[T0:[0-9]+]]
-  ; MMR3:         sll     $[[T1:[0-9]+]], $[[T0]], 31
-  ; MMR3:         sra     $2, $[[T1]], 31
+  ; MMR3:         andi16  $[[T0]], $[[T0]], 1
+  ; MMR3:         li16    $[[T1:[0-9]+]], 0
+  ; MMR3:         subu16  $2, $[[T1]], $[[T0]]
 
   ; MMR6:         div     $[[T0:[0-9]+]], $4, $5
   ; MMR6:         teq     $5, $zero, 7
-  ; MMR6:         sll     $[[T1:[0-9]+]], $[[T0]], 31
-  ; MMR6:         sra     $2, $[[T1]], 31
+  ; MMR6:         andi16  $[[T0]], $[[T0]], 1
+  ; MMR6:         li16    $[[T1:[0-9]+]], 0
+  ; MMR6:         subu16  $2, $[[T1]], $[[T0]]
 
   %r = sdiv i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @sdiv_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: sdiv_i8:

llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll

 
 define signext i1 @srem_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: srem_i1:
 
   ; NOT-R6:       div     $zero, $4, $5
   ; NOT-R6:       teq     $5, $zero, 7
   ; NOT-R6:       mfhi    $[[T0:[0-9]+]]
-  ; NOT-R6:       sll     $[[T1:[0-9]+]], $[[T0]], 31
-  ; NOT-R6:       sra     $2, $[[T1]], 31
+  ; NOT-R6:       andi    $[[T0]], $[[T0]], 1
+  ; NOT-R6:       negu    $2, $[[T0]]
 
   ; R6:           mod     $[[T0:[0-9]+]], $4, $5
   ; R6:           teq     $5, $zero, 7
-  ; R6:           sll     $[[T3:[0-9]+]], $[[T0]], 31
-  ; R6:           sra     $2, $[[T3]], 31
+  ; R6:           andi    $[[T0]], $[[T0]], 1
+  ; R6:           negu    $2, $[[T0]]
 
   ; MMR3:         div     $zero, $4, $5
   ; MMR3:         teq     $5, $zero, 7
   ; MMR3:         mfhi    $[[T0:[0-9]+]]
-  ; MMR3:         sll     $[[T1:[0-9]+]], $[[T0]], 31
-  ; MMR3:         sra     $2, $[[T1]], 31
+  ; MMR3:         andi16  $[[T0]], $[[T0]], 1
+  ; MMR3:         li16    $[[T1:[0-9]+]], 0
+  ; MMR3:         subu16  $2, $[[T1]], $[[T0]]
 
   ; MMR6:         mod     $[[T0:[0-9]+]], $4, $5
   ; MMR6:         teq     $5, $zero, 7
-  ; MMR6:         sll     $[[T1:[0-9]+]], $[[T0]], 31
-  ; MMR6:         sra     $2, $[[T1]], 31
+  ; MMR6:         andi16  $[[T0]], $[[T0]], 1
+  ; MMR6:         li16    $[[T1:[0-9]+]], 0
+  ; MMR6:         subu16  $2, $[[T1]], $[[T0]]
 
   %r = srem i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @srem_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: srem_i8:

llvm/trunk/test/CodeGen/Mips/llvm-ir/sub.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=GP64,MM
 
 define signext i1 @sub_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: sub_i1:
 
   ; NOT-MM:         subu    $[[T0:[0-9]+]], $4, $5
-  ; NOT-MM:         sll     $[[T0]], $[[T0]], 31
-  ; NOT-MM:         sra     $2, $[[T0]], 31
+  ; NOT-MM:         andi    $[[T0]], $[[T0]], 1
+  ; NOT-MM:         negu    $2, $[[T0]]
 
   ; MM:             subu16  $[[T0:[0-9]+]], $4, $5
-  ; MM:             sll     $[[T1:[0-9]+]], $[[T0]], 31
-  ; MM:             sra     $[[T0]], $[[T1]], 31
+  ; MM:             andi16  $[[T0]], $[[T0]], 1
+  ; MM:             li16    $[[T1:[0-9]+]], 0
+  ; MM:             subu16  $2, $[[T1]], $[[T0]]
 
   %r = sub i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @sub_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: sub_i8:

llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll

 entry:
 ; ALL-LABEL: urem_i1:
 
   ; NOT-R6:       andi    $[[T0:[0-9]+]], $5, 1
   ; NOT-R6:       andi    $[[T1:[0-9]+]], $4, 1
   ; NOT-R6:       divu    $zero, $[[T1]], $[[T0]]
   ; NOT-R6:       teq     $[[T0]], $zero, 7
   ; NOT-R6:       mfhi    $[[T2:[0-9]+]]
-  ; NOT-R6:       sll     $[[T3:[0-9]+]], $[[T2]], 31
-  ; NOT-R6:       sra     $2, $[[T3]], 31
+  ; NOT-R6:       andi    $[[T0]], $[[T0]], 1
+  ; NOT-R6:       negu    $2, $[[T0]]
 
   ; R6:           andi    $[[T0:[0-9]+]], $5, 1
   ; R6:           andi    $[[T1:[0-9]+]], $4, 1
   ; R6:           modu    $[[T2:[0-9]+]], $[[T1]], $[[T0]]
   ; R6:           teq     $[[T0]], $zero, 7
-  ; R6:           sll     $[[T3:[0-9]+]], $[[T2]], 31
-  ; R6:           sra     $2, $[[T3]], 31
+  ; R6:           negu    $2, $[[T2]]
 
   ; MMR3:         andi16  $[[T0:[0-9]+]], $5, 1
   ; MMR3:         andi16  $[[T1:[0-9]+]], $4, 1
   ; MMR3:         divu    $zero, $[[T1]], $[[T0]]
   ; MMR3:         teq     $[[T0]], $zero, 7
   ; MMR3:         mfhi    $[[T2:[0-9]+]]
-  ; MMR3:         sll     $[[T3:[0-9]+]], $[[T2]], 31
-  ; MMR3:         sra     $2, $[[T3]], 31
+  ; MMR3:         andi16  $[[T0]], $[[T0]], 1
+  ; MMR3:         li16    $[[T1:[0-9]+]], 0
+  ; MMR3:         subu16  $2, $[[T1]], $[[T0]]
 
   ; MMR6:         andi16  $[[T0:[0-9]+]], $5, 1
   ; MMR6:         andi16  $[[T1:[0-9]+]], $4, 1
   ; MMR6:         modu    $[[T2:[0-9]+]], $[[T1]], $[[T0]]
   ; MMR6:         teq     $[[T0]], $zero, 7
-  ; MMR6:         sll     $[[T3:[0-9]+]], $[[T2]], 31
-  ; MMR6:         sra     $2, $[[T3]], 31
+  ; MMR6:         li16    $[[T3:[0-9]+]], 0
+  ; MMR6:         subu16  $2, $[[T3]], $[[T2]]
 
   %r = urem i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @urem_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: urem_i8:

llvm/trunk/test/CodeGen/Mips/select.ll

 ; 32-DAG:        mtc1 $5, $[[F0:f[0-9]+]]
 ; 32-DAG:        mtc1 $6, $[[F1:f0]]
 ; 32:            movn.s $[[F1]], $[[F0]], $4
 
 ; 32R2-DAG:      mtc1 $5, $[[F0:f[0-9]+]]
 ; 32R2-DAG:      mtc1 $6, $[[F1:f0]]
 ; 32R2:          movn.s $[[F1]], $[[F0]], $4
 
+; 32R6:          sltu $[[T0:[0-9]+]], $zero, $4
+; 32R6:          negu $[[T0]], $[[T0]]
 ; 32R6-DAG:      mtc1 $5, $[[F0:f[0-9]+]]
 ; 32R6-DAG:      mtc1 $6, $[[F1:f[0-9]+]]
-; 32R6:          sltu $[[T0:[0-9]+]], $zero, $4
 ; 32R6:          mtc1 $[[T0]], $[[CC:f0]]
 ; 32R6:          sel.s $[[CC]], $[[F1]], $[[F0]]
 
 ; 64:            movn.s $f14, $f13, $4
 ; 64:            mov.s $f0, $f14
 
 ; 64R2:          movn.s $f14, $f13, $4
 ; 64R2:          mov.s $f0, $f14

llvm/trunk/test/CodeGen/PowerPC/negate-i1.ll

-; RUN: llc < %s -mtriple=powerpc64-apple-darwin | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
 
 ; PR30661 - https://llvm.org/bugs/show_bug.cgi?id=30661
 
 define i32 @select_i32_neg1_or_0(i1 %a) {
 ; CHECK-LABEL: select_i32_neg1_or_0:
-; CHECK:       ; BB#0:
-; CHECK-NEXT:    sldi r2, r3, 63
-; CHECK-NEXT:    sradi r3, r2, 63
+; CHECK:       # BB#0:
+; CHECK-NEXT:    clrldi 3, 3, 63
+; CHECK-NEXT:    neg 3, 3
 ; CHECK-NEXT:    blr
 ;
   %b = sext i1 %a to i32
   ret i32 %b
 }
 
 define i32 @select_i32_neg1_or_0_zeroext(i1 zeroext %a) {
 ; CHECK-LABEL: select_i32_neg1_or_0_zeroext:
-; CHECK:       ; BB#0:
-; CHECK-NEXT:    sldi r2, r3, 63
-; CHECK-NEXT:    sradi r3, r2, 63
+; CHECK:       # BB#0:
+; CHECK-NEXT:    neg 3, 3
 ; CHECK-NEXT:    blr
 ;
   %b = sext i1 %a to i32
   ret i32 %b
 }
 

llvm/trunk/test/CodeGen/SystemZ/branch-07.ll

; CHECK: br %r14
   ret i64 %ret
 }
 
 ; Test a vector of 0/-1 results for i64 EQ.
 define void @f9(i64 %a, i64 %b, <2 x i64> *%dest) {
 ; CHECK-LABEL: f9:
 ; CHECK: ipm [[REG:%r[0-5]]]
 ; CHECK: afi [[REG]], -268435456
-; CHECK: sllg [[REG2:%r[0-5]]], [[REG]], 32
-; CHECK: srag {{%r[0-5]}}, [[REG2]], 63
+; CHECK: risbg [[REG2:%r[0-5]]], [[REG]], 63, 191, 33
+; CHECK: lcgr  {{%r[0-5]}}, [[REG2]]
 ; CHECK: br %r14
   %avec = bitcast i64 %a to <2 x i32>
   %bvec = bitcast i64 %b to <2 x i32>
   %cmp = icmp eq <2 x i32> %avec, %bvec
   %ext = sext <2 x i1> %cmp to <2 x i64>
   store <2 x i64> %ext, <2 x i64> *%dest
   ret void
 }
 
 ; Test a vector of 0/-1 results for i64 NE.
 define void @f10(i64 %a, i64 %b, <2 x i64> *%dest) {
 ; CHECK-LABEL: f10:
 ; CHECK: ipm [[REG:%r[0-5]]]
 ; CHECK: afi [[REG]], 1879048192
-; CHECK: sllg [[REG2:%r[0-5]]], [[REG]], 32
-; CHECK: srag {{%r[0-5]}}, [[REG2]], 63
+; CHECK: risbg [[REG2:%r[0-5]]], [[REG]], 63, 191, 33
+; CHECK: lcgr  {{%r[0-5]}}, [[REG2]]
 ; CHECK: br %r14
   %avec = bitcast i64 %a to <2 x i32>
   %bvec = bitcast i64 %b to <2 x i32>
   %cmp = icmp ne <2 x i32> %avec, %bvec
   %ext = sext <2 x i1> %cmp to <2 x i64>
   store <2 x i64> %ext, <2 x i64> *%dest
   ret void
 }

llvm/trunk/test/CodeGen/SystemZ/risbg-01.ll

; CHECK: br %r14
   ret i64 %ext
 }
 
 ; In this case the sign extension is converted to a pair of 32-bit shifts,
 ; which is then extended to 64 bits.  We previously used the wrong bit size
 ; when testing whether the shifted-in bits of the shift right were significant.
 define i64 @f42(i1 %x) {
 ; CHECK-LABEL: f42:
-; CHECK: sll %r2, 31
-; CHECK: sra %r2, 31
-; CHECK: llgcr %r2, %r2
+; CHECK: nilf  %r2, 1
+; CHECK: lcr %r0, %r2
+; CHECK: llgcr %r2, %r0
 ; CHECK: br %r14
   %ext = sext i1 %x to i8
   %ext2 = zext i8 %ext to i64
   ret i64 %ext2
 }
 
 ; Check that we get the case where a 64-bit shift is used by a 32-bit and.
 define signext i32 @f43(i64 %x) {

llvm/trunk/test/CodeGen/SystemZ/shift-10.ll

 ; Test compound shifts.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Test a shift right followed by a sign extension.  This can use two shifts.
 define i64 @f1(i32 %a) {
 ; CHECK-LABEL: f1:
-; CHECK: sllg [[REG:%r[0-5]]], %r2, 62
-; CHECK: srag %r2, [[REG]], 63
+; CHECK: risbg %r0, %r2, 63, 191, 63
+; CHECK: lcgr  %r2, %r0
 ; CHECK: br %r14
   %shr = lshr i32 %a, 1
   %trunc = trunc i32 %shr to i1
   %ext = sext i1 %trunc to i64
   ret i64 %ext
 }
 
 ; ...and again with the highest shift count that doesn't reduce to an
 ; ashr/sext pair.
 define i64 @f2(i32 %a) {
 ; CHECK-LABEL: f2:
-; CHECK: sllg [[REG:%r[0-5]]], %r2, 33
-; CHECK: srag %r2, [[REG]], 63
+; CHECK: risbg %r0, %r2, 63, 191, 34
+; CHECK: lcgr  %r2, %r0
 ; CHECK: br %r14
   %shr = lshr i32 %a, 30
   %trunc = trunc i32 %shr to i1
   %ext = sext i1 %trunc to i64
   ret i64 %ext
 }
 
 ; Test a left shift that of an extended right shift in a case where folding

llvm/trunk/test/CodeGen/X86/negate-i1.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
 ; RUN: llc < %s -mtriple=i386-unknown-unknown   | FileCheck %s --check-prefix=X32
 
 define i8 @select_i8_neg1_or_0(i1 %a) {
 ; X64-LABEL: select_i8_neg1_or_0:
 ; X64:       # BB#0:
-; X64-NEXT:    shlb $7, %dil
-; X64-NEXT:    sarb $7, %dil
+; X64-NEXT:    andb $1, %dil
+; X64-NEXT:    negb %dil
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: select_i8_neg1_or_0:
 ; X32:       # BB#0:
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
-; X32-NEXT:    shlb $7, %al
-; X32-NEXT:    sarb $7, %al
+; X32-NEXT:    andb $1, %al
+; X32-NEXT:    negb %al
 ; X32-NEXT:    retl
 ;
   %b = sext i1 %a to i8
   ret i8 %b
 }
 
 define i8 @select_i8_neg1_or_0_zeroext(i1 zeroext %a) {
 ; X64-LABEL: select_i8_neg1_or_0_zeroext:
 ; X64:       # BB#0:
-; X64-NEXT:    shlb $7, %dil
-; X64-NEXT:    sarb $7, %dil
+; X64-NEXT:    negb %dil
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: select_i8_neg1_or_0_zeroext:
 ; X32:       # BB#0:
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
-; X32-NEXT:    shlb $7, %al
-; X32-NEXT:    sarb $7, %al
+; X32-NEXT:    negb %al
 ; X32-NEXT:    retl
 ;
   %b = sext i1 %a to i8
   ret i8 %b
 }
 
 define i16 @select_i16_neg1_or_0(i1 %a) {
 ; X64-LABEL: select_i16_neg1_or_0:
 ; X64:       # BB#0:
-; X64-NEXT:    shll $15, %edi
-; X64-NEXT:    sarw $15, %di
+; X64-NEXT:    andl $1, %edi
+; X64-NEXT:    negl %edi
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: select_i16_neg1_or_0:
 ; X32:       # BB#0:
-; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    shll $15, %eax
-; X32-NEXT:    sarw $15, %ax
+; X32-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    andl $1, %eax
+; X32-NEXT:    negl %eax
 ; X32-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
 ; X32-NEXT:    retl
 ;
   %b = sext i1 %a to i16
   ret i16 %b
 }
 
 define i16 @select_i16_neg1_or_0_zeroext(i1 zeroext %a) {
 ; X64-LABEL: select_i16_neg1_or_0_zeroext:
 ; X64:       # BB#0:
 ; X64-NEXT:    movzbl %dil, %eax
-; X64-NEXT:    shll $15, %eax
-; X64-NEXT:    sarw $15, %ax
+; X64-NEXT:    negl %eax
 ; X64-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: select_i16_neg1_or_0_zeroext:
 ; X32:       # BB#0:
 ; X32-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    shll $15, %eax
-; X32-NEXT:    sarw $15, %ax
+; X32-NEXT:    negl %eax
 ; X32-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
 ; X32-NEXT:    retl
 ;
   %b = sext i1 %a to i16
   ret i16 %b
 }
 
 define i32 @select_i32_neg1_or_0(i1 %a) {
 ; X64-LABEL: select_i32_neg1_or_0:
 ; X64:       # BB#0:
-; X64-NEXT:    shll $31, %edi
-; X64-NEXT:    sarl $31, %edi
+; X64-NEXT:    andl $1, %edi
+; X64-NEXT:    negl %edi
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: select_i32_neg1_or_0:
 ; X32:       # BB#0:
-; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    shll $31, %eax
-; X32-NEXT:    sarl $31, %eax
+; X32-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    andl $1, %eax
+; X32-NEXT:    negl %eax
 ; X32-NEXT:    retl
 ;
   %b = sext i1 %a to i32
   ret i32 %b
 }
 
 define i32 @select_i32_neg1_or_0_zeroext(i1 zeroext %a) {
 ; X64-LABEL: select_i32_neg1_or_0_zeroext:
 ; X64:       # BB#0:
 ; X64-NEXT:    movzbl %dil, %eax
-; X64-NEXT:    shll $31, %eax
-; X64-NEXT:    sarl $31, %eax
+; X64-NEXT:    negl %eax
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: select_i32_neg1_or_0_zeroext:
 ; X32:       # BB#0:
 ; X32-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    shll $31, %eax
-; X32-NEXT:    sarl $31, %eax
+; X32-NEXT:    negl %eax
 ; X32-NEXT:    retl
 ;
   %b = sext i1 %a to i32
   ret i32 %b
 }
 
 define i64 @select_i64_neg1_or_0(i1 %a) {
 ; X64-LABEL: select_i64_neg1_or_0:
 ; X64:       # BB#0:
 ; X64-NEXT:    # kill: %EDI<def> %EDI<kill> %RDI<def>
-; X64-NEXT:    shlq $63, %rdi
-; X64-NEXT:    sarq $63, %rdi
+; X64-NEXT:    andl $1, %edi
+; X64-NEXT:    negq %rdi
 ; X64-NEXT:    movq %rdi, %rax
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: select_i64_neg1_or_0:
 ; X32:       # BB#0:
-; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    shll $31, %eax
-; X32-NEXT:    sarl $31, %eax
+; X32-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    andl $1, %eax
+; X32-NEXT:    negl %eax
 ; X32-NEXT:    movl %eax, %edx
 ; X32-NEXT:    retl
 ;
   %b = sext i1 %a to i64
   ret i64 %b
 }
 
 define i64 @select_i64_neg1_or_0_zeroext(i1 zeroext %a) {
 ; X64-LABEL: select_i64_neg1_or_0_zeroext:
 ; X64:       # BB#0:
 ; X64-NEXT:    movzbl %dil, %eax
-; X64-NEXT:    shlq $63, %rax
-; X64-NEXT:    sarq $63, %rax
+; X64-NEXT:    negq %rax
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: select_i64_neg1_or_0_zeroext:
 ; X32:       # BB#0:
 ; X32-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    shll $31, %eax
-; X32-NEXT:    sarl $31, %eax
+; X32-NEXT:    negl %eax
 ; X32-NEXT:    movl %eax, %edx
 ; X32-NEXT:    retl
 ;
   %b = sext i1 %a to i64
   ret i64 %b
 }