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delena (Elena Demikhovsky)
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User Since
Mar 5 2014, 12:39 AM (249 w, 6 d)

Recent Activity

Oct 30 2018

delena accepted D52609: [SROA] Use offset sizes from the DataLayout instead of the pointer siezes..
Oct 30 2018, 4:12 AM

Oct 17 2018

delena added a comment to D53161: Fix some cases where the index size was used instead of the pointer size.

I explained why there's no test. The following commit (linked in the stack) has a test case which crashes without this change.

You've dropped the following commit.

Oct 17 2018, 5:37 AM

Oct 12 2018

delena added a comment to D53162: [DataLayout] Add bit width of pointers to global values.

Can you use the "address space" to distinguish between global and local in Data Layout?

Oct 12 2018, 2:38 AM
delena added a comment to D52609: [SROA] Use offset sizes from the DataLayout instead of the pointer siezes..

I'm ok with the code itself. I agree with Eli that you should add CHECKs.

Oct 12 2018, 2:35 AM
delena added a comment to D53161: Fix some cases where the index size was used instead of the pointer size.

Add a test, please.

Oct 12 2018, 2:28 AM

Aug 27 2018

delena removed a reviewer for D51313: [LV] Fix code gen for conditionally executed uniform loads: delena.
Aug 27 2018, 11:50 AM

Aug 7 2018

delena accepted D50374: [SelectionDAG] When splitting scatter nodes during DAGCombine, create a serial chain dependency..

Yes. The scatter operation should be in-order after split.

Aug 7 2018, 12:50 AM

Jul 12 2018

delena added a comment to D48323: Derive GEP index type from Data Layout (cont).

Ping

Jul 12 2018, 9:55 AM

Jul 9 2018

delena accepted D49068: Fixing builtin __atomic_fetch_min definition.
Jul 9 2018, 5:33 AM

Jul 1 2018

delena added a comment to D48323: Derive GEP index type from Data Layout (cont).

Ping.., Can anybody complete the review, please?

Jul 1 2018, 11:31 PM

Jun 25 2018

delena updated the diff for D48323: Derive GEP index type from Data Layout (cont).

Added more tests for BasicAA.

Jun 25 2018, 10:44 PM
delena added a comment to D48323: Derive GEP index type from Data Layout (cont).

I looked at the code in SeparateConstOffsetFromGEP::canonicalizeArrayIndicesToPointerSize
The DL->getIntPtrType() does the right job for the "custom" GEP. I added a test that covers canonicalizeArrayIndicesToPointerSize().
I'll try to add a test to the constantOffsetHeuristic() as well.

Jun 25 2018, 7:57 AM
delena updated the diff for D48323: Derive GEP index type from Data Layout (cont).

I separated the CodeGen and middle-end changes.
I added one more test for SeparateConstOffsetFromGEP.

Jun 25 2018, 7:45 AM

Jun 24 2018

delena added a comment to D48323: Derive GEP index type from Data Layout (cont).

AFAIK BasicAA assumes that all GEP indices have a common type. So "normalization" is for example needed before passes like GVN that uses MemoryDependenceResults, that is using BasicAA. Or maybe that is a bug in BasicAA?

Passes like InstCombine might skip doing rewrites in some basic blocks (e.g. if they are unreachable from entry). So I do not think that we can't rely on InstCombine doing a normalization for all GEP:s in the function.
So are we moving towards always using the "normalized" type from scratch (in all passes) when creating a GEP, or what is the plan here?

Jun 24 2018, 11:06 AM

Jun 20 2018

delena added inline comments to D48323: Derive GEP index type from Data Layout (cont).
Jun 20 2018, 1:14 AM

Jun 19 2018

delena updated the diff for D48323: Derive GEP index type from Data Layout (cont).

The new test is auto-generated now.

Jun 19 2018, 11:53 PM
delena added inline comments to D48323: Derive GEP index type from Data Layout (cont).
Jun 19 2018, 11:09 PM
delena created D48323: Derive GEP index type from Data Layout (cont).
Jun 19 2018, 7:33 AM

Jun 6 2018

delena committed rL334075: Added documentation for Masked Vector Expanding Load and Compressing Store….
Added documentation for Masked Vector Expanding Load and Compressing Store…
Jun 6 2018, 2:17 AM
delena closed D26743: Expandload and Compressing store - documentation update.
Jun 6 2018, 2:17 AM

Jun 4 2018

delena added a comment to D26743: Expandload and Compressing store - documentation update.

I wrote this documentation after implementation. I don't work on X86 about a year, but I doubt that somebody touched this code.

Jun 4 2018, 11:46 PM

Jun 2 2018

delena added a comment to D47680: [Docs] Add the missing documentation for expandload and compressstore intrinsics.

I tried to add documentation a while ago https://reviews.llvm.org/D26743

Jun 2 2018, 11:40 PM

May 14 2018

delena accepted D43441: [X86][AVX512DQ] Use packed instructions for scalar FP<->i64 conversions on 32-bit targets (PR31630).

Or we'd have to use undef for the upper elts and add a DAG combine to turn insert into undef into a broadcast if its foldable.

I think it is simpler than load folding in td. You can open a bugzilla ticket for possible optimization.

May 14 2018, 10:58 PM
delena added inline comments to D43441: [X86][AVX512DQ] Use packed instructions for scalar FP<->i64 conversions on 32-bit targets (PR31630).
May 14 2018, 1:56 PM

May 13 2018

delena committed rC332193: Added atomic_fetch_min, max, umin, umax intrinsics to clang..
Added atomic_fetch_min, max, umin, umax intrinsics to clang.
May 13 2018, 12:52 AM
delena committed rL332193: Added atomic_fetch_min, max, umin, umax intrinsics to clang..
Added atomic_fetch_min, max, umin, umax intrinsics to clang.
May 13 2018, 12:50 AM
delena closed D46386: Adding __atomic_fetch_min/max intrinsics to clang.
May 13 2018, 12:49 AM

May 12 2018

delena added a comment to D46386: Adding __atomic_fetch_min/max intrinsics to clang.

The actual semantic parts of the diff seem to have disappeared from the patch posted to Phabricator, for what it's worth.

It is not disappeared by itself, I removed it. I understood that you don't see any added value in the entire memory model description inside.
Thank you.

May 12 2018, 6:25 AM

May 11 2018

delena updated the diff for D46386: Adding __atomic_fetch_min/max intrinsics to clang.

Added a line about *load-store* semantics of these two intrinsics.
Removed the common description of memory modeling.

May 11 2018, 10:07 PM

May 10 2018

delena updated the diff for D46386: Adding __atomic_fetch_min/max intrinsics to clang.

Given more clarification about memory model of atomic operations.

May 10 2018, 12:33 AM

May 8 2018

delena updated the diff for D46386: Adding __atomic_fetch_min/max intrinsics to clang.

Removed the unsigned version of atomics. Enhanced semantics check.
Added more tests.
Added documentation.

May 8 2018, 1:34 AM

May 4 2018

delena added a comment to D46386: Adding __atomic_fetch_min/max intrinsics to clang.

Is this some sort of a vendor extension then? OpenCL 1.2 atomic builtins don't have ordering parameter.

May 4 2018, 4:54 AM

May 3 2018

delena added inline comments to D46386: Adding __atomic_fetch_min/max intrinsics to clang.
May 3 2018, 12:44 PM
delena created D46386: Adding __atomic_fetch_min/max intrinsics to clang.
May 3 2018, 5:48 AM

Feb 14 2018

delena accepted D43087: [SelectionDAG][X86] Fix incorrect offset generated for VMASKMOV.
Feb 14 2018, 7:25 AM
delena added a comment to D43087: [SelectionDAG][X86] Fix incorrect offset generated for VMASKMOV.

no context in the patch

Feb 14 2018, 5:31 AM
delena added a reviewer for D43087: [SelectionDAG][X86] Fix incorrect offset generated for VMASKMOV: RKSimon.
Feb 14 2018, 4:53 AM
delena added a comment to D43087: [SelectionDAG][X86] Fix incorrect offset generated for VMASKMOV.

Are there MIR changes only? What changes do you expect in the asm code?

Feb 14 2018, 2:50 AM

Feb 13 2018

delena committed rL325102: Adding a width of the GEP index to the Data Layout..
Adding a width of the GEP index to the Data Layout.
Feb 13 2018, 11:00 PM
delena closed D42123: Derive GEP index type from Data Layout.
Feb 13 2018, 11:00 PM

Feb 12 2018

delena updated the diff for D42123: Derive GEP index type from Data Layout.

Added more tests with custom data layout.

Feb 12 2018, 5:35 AM

Feb 8 2018

delena updated the diff for D42123: Derive GEP index type from Data Layout.

Updated according to the latest comments.

Feb 8 2018, 2:23 AM

Feb 7 2018

delena accepted D42989: [X86] When doing callee save/restore for k-registers make sure we don't use KMOVQ on non-BWI targets.
Feb 7 2018, 12:41 PM

Feb 6 2018

delena added inline comments to D42989: [X86] When doing callee save/restore for k-registers make sure we don't use KMOVQ on non-BWI targets.
Feb 6 2018, 11:52 PM
delena added inline comments to D42989: [X86] When doing callee save/restore for k-registers make sure we don't use KMOVQ on non-BWI targets.
Feb 6 2018, 10:46 PM
delena added a comment to D42123: Derive GEP index type from Data Layout.

I don't see these tests in this current version of the patch.

All tests that you see *-custom.ll" go through the scev calculations.

Feb 6 2018, 9:37 PM
delena accepted D42737: [LegalizeDAG] Truncate condition operand of ISD::SELECT.
Feb 6 2018, 11:34 AM
delena added inline comments to D42737: [LegalizeDAG] Truncate condition operand of ISD::SELECT.
Feb 6 2018, 4:28 AM

Feb 5 2018

delena added inline comments to D42737: [LegalizeDAG] Truncate condition operand of ISD::SELECT.
Feb 5 2018, 10:58 PM
delena added a comment to D42123: Derive GEP index type from Data Layout.

@theraven , the latest uploaded version is aligned with what you implemented out of the tree. Could you, please, take a look?

Feb 5 2018, 10:50 PM

Feb 1 2018

delena added a comment to D42123: Derive GEP index type from Data Layout.
" > We have addressed this by adding explicit PTRADD SelectionDAG nodes, which perform pointer + integer addition. For complex addressing modes, we end up with (ptradd base (some complex integer ops)). This works well as long as the underlying hardware supports address register + integer register addressing, which I presume is the case for Intel (it is for all Harvard architectures that I've come across)."

Yes, we also added ADDPTR node for SelectionDAG and we have more changes related to the special pointer type. Apparently, the codegen does not work with MVT::Ptr.
We can try to upstream the part of DAG builder, that makes ADDPTR from GEP.

Feb 1 2018, 4:10 AM

Jan 31 2018

delena accepted D42781: [X86] Remove custom lowering vXi1 extending loads and truncating stores..
Jan 31 2018, 10:56 PM
delena added inline comments to D42123: Derive GEP index type from Data Layout.
Jan 31 2018, 1:46 AM

Jan 30 2018

delena updated the diff for D42123: Derive GEP index type from Data Layout.

Added index width specification to the DataLayout. Updated the langref.
Fixed Pointer vs Index sizes in the code.
Added more tests.

Jan 30 2018, 6:08 AM

Jan 25 2018

delena added a comment to D42123: Derive GEP index type from Data Layout.

I looked at your code:
/ Return the size in bits of the specified type, for which isSCEVable must
/ return true.
uint64_t ScalarEvolution::getTypeSizeInBits(Type *Ty) const {

assert(isSCEVable(Ty) && "Type is not SCEVable!");
const DataLayout &DL = getDataLayout();
if (PointerType *PT = dyn_cast<PointerType>(Ty))
  return DL.getPointerBaseSizeInBits(PT->getPointerAddressSpace());
return DL.getTypeSizeInBits(Ty);

}
I can't say that size of pointer is smaller that it is. I can't truncate pointer to integer in order to expand all SCEV expressions.

Jan 25 2018, 5:19 AM
delena added a comment to D42123: Derive GEP index type from Data Layout.

I want to deprecate SCEVs for pointers if the index size is not equal to pointer size.
What do you think?

Jan 25 2018, 2:59 AM

Jan 19 2018

delena added a comment to D42123: Derive GEP index type from Data Layout.

I don't like this patch as is, for several reasons.

  1. It's adding a hack that assumes that the offset should be the width of the widest integer operation. This is probably true in most cases (it is for us), but if we're going to introduce the idea that an address offset is distinct from the size of the pointer then we should do it properly and add that to the TargetInfo string explicitly (defaulting to the same size, if not specified).

So you propose to extend Data Layout string and add index size to it, right? It was one of options that Hal suggested. Ok.

Jan 19 2018, 10:20 AM
delena updated the diff for D42123: Derive GEP index type from Data Layout.

Updated, following Craig's comments.

Jan 19 2018, 6:18 AM

Jan 17 2018

delena updated the diff for D42123: Derive GEP index type from Data Layout.

Added tests for a data layout, where pointer is wider than the largest supported integer type.

Jan 17 2018, 5:10 AM

Jan 16 2018

delena updated the diff for D42123: Derive GEP index type from Data Layout.

Fixed 2 "assert" messages.

Jan 16 2018, 10:41 PM
delena created D42123: Derive GEP index type from Data Layout.
Jan 16 2018, 12:06 PM

Jan 10 2018

delena accepted D40055: [SelectionDAG][X86] Explicitly store the scale in the gather/scatter ISD nodes.
Jan 10 2018, 11:06 AM

Jan 3 2018

delena committed rL321785: Changes in the branch relaxation algorithm..
Changes in the branch relaxation algorithm.
Jan 3 2018, 11:10 PM
delena closed D41634: Branch relaxation - non invertible condition.
Jan 3 2018, 11:10 PM
delena added a comment to D41634: Branch relaxation - non invertible condition.

I understand that if it is a out-of-tree target, the testcase is problematic,
but no testcase at all is worrying. Maybe unit-test can help?

Jan 3 2018, 10:47 AM

Jan 2 2018

delena accepted D41691: [X86] Use ANY_EXTEND instead of SIGN_EXTEND in lowerMasksToReg.

+ minor comment

Jan 2 2018, 10:41 PM

Dec 30 2017

delena updated the diff for D41634: Branch relaxation - non invertible condition.

Re-arranged the code to avoid duplication.
Fixed Debug prints.

Dec 30 2017, 8:11 AM

Dec 29 2017

delena created D41634: Branch relaxation - non invertible condition.
Dec 29 2017, 1:40 PM

Nov 19 2017

delena accepted D35772: [LV][X86] Support of AVX2 Gathers code generation and update the LV with this.
Nov 19 2017, 1:29 PM

Nov 18 2017

delena added inline comments to D40215: [X86][AVX512] Use PACKSS/PACKUS for vXi16->vXi8 truncations without BWI..
Nov 18 2017, 10:44 PM

Nov 16 2017

delena added inline comments to D40055: [SelectionDAG][X86] Explicitly store the scale in the gather/scatter ISD nodes.
Nov 16 2017, 9:40 PM

Nov 13 2017

delena accepted D39927: [X86] Allow X86ISD::Wrapper to be folded into the base of gather/scatter address.
Nov 13 2017, 1:51 AM

Nov 11 2017

delena added inline comments to D39927: [X86] Allow X86ISD::Wrapper to be folded into the base of gather/scatter address.
Nov 11 2017, 12:14 PM

Nov 10 2017

delena accepted D39911: [SelectionDAG] Teach SelectionDAGBuilder's getUniformBase for gather/scatter handling to accept GEPs with more than 2 operands if the middle operands are all 0s.
Nov 10 2017, 2:20 PM
delena added inline comments to D39911: [SelectionDAG] Teach SelectionDAGBuilder's getUniformBase for gather/scatter handling to accept GEPs with more than 2 operands if the middle operands are all 0s.
Nov 10 2017, 1:09 PM

Nov 5 2017

delena accepted D35772: [LV][X86] Support of AVX2 Gathers code generation and update the LV with this.
Nov 5 2017, 2:03 AM

Nov 1 2017

delena added inline comments to D35772: [LV][X86] Support of AVX2 Gathers code generation and update the LV with this.
Nov 1 2017, 10:39 AM
delena added inline comments to D35772: [LV][X86] Support of AVX2 Gathers code generation and update the LV with this.
Nov 1 2017, 2:40 AM

Oct 29 2017

delena added inline comments to D35772: [LV][X86] Support of AVX2 Gathers code generation and update the LV with this.
Oct 29 2017, 6:46 AM

Oct 23 2017

delena added a comment to D34141: [X86] Recognize constant arrays with special values and replace loads from it with subtract and shift instructions, which then will be replaced by X86 BZHI machine instruction..

Please submit the same test cases before optimization.

Oct 23 2017, 1:36 AM

Oct 14 2017

delena added a comment to D38932: [X86] Lower vselect with constant condition to vector_shuffle even with AVX512 instructions..

I suggest to open a ticket in bugzilla about possible replacement of "select" with constant mask with shuffle to avoid mask instructions on AVX-512.

Oct 14 2017, 11:41 PM
delena accepted D38714: [AVX512] Don't mark EXTLOAD as legal with AVX512. Continue using custom lowering..
Oct 14 2017, 11:38 PM
delena accepted D38932: [X86] Lower vselect with constant condition to vector_shuffle even with AVX512 instructions..
Oct 14 2017, 11:28 PM
delena added inline comments to D38714: [AVX512] Don't mark EXTLOAD as legal with AVX512. Continue using custom lowering..
Oct 14 2017, 2:11 PM

Oct 11 2017

delena added a comment to D38318: [X86][SSE] Match PSHUFLW/PSHUFHW + PSHUFD vXi16 shuffle patterns (PR34686).

In this case we need to add "SlowShuffle.." property to these two targets. I don't see any other way to distinguish. Or "Fast" to HSW, but I suggest the fist variant, because less instructions is more obvious.

Oct 11 2017, 9:24 AM
delena added a comment to D38318: [X86][SSE] Match PSHUFLW/PSHUFHW + PSHUFD vXi16 shuffle patterns (PR34686).

@delena @zvi What do you want to do with this. IMO we shouldn't be prematurely combining to variable mask shuffles, and this should be performed later as a scheduler based decision. But that will involve a lot of work that I don't think we're ready for (D26855 tried to move some other code to the MC and hit a lot of issues).

What we could do is add a FeatureFastVariableShuffle feature flag to Haswell and later Intel CPUs and perform the decision in combineX86ShuffleChain off that?

Oct 11 2017, 2:53 AM

Oct 10 2017

delena added inline comments to D38762: Cost calculation for interleave load/store patterns {v8i8,v16i8,v32i8,v64i8}.
Oct 10 2017, 10:36 PM

Sep 29 2017

delena abandoned D27044: Compilation crash after node replacement.
Sep 29 2017, 4:43 AM

Sep 27 2017

delena added inline comments to D38318: [X86][SSE] Match PSHUFLW/PSHUFHW + PSHUFD vXi16 shuffle patterns (PR34686).
Sep 27 2017, 10:49 AM

Sep 25 2017

delena accepted D35320: [X86][SSE] Add support for extending bool vectors bitcasted from scalars..

LGTM. Thank you.

Sep 25 2017, 5:02 AM

Sep 19 2017

delena accepted D38022: [X86] Convert X86ISD::SELECT to ISD::VSELECT just before instruction selection to avoid duplicate patterns.
Sep 19 2017, 12:54 AM
delena added a comment to D38022: [X86] Convert X86ISD::SELECT to ISD::VSELECT just before instruction selection to avoid duplicate patterns.

I did remove the usages from the td patterns. It wasn't used in very many places.

I meant X86InstrFragmentsSIMD.td.

Sep 19 2017, 12:42 AM
delena added a comment to D38022: [X86] Convert X86ISD::SELECT to ISD::VSELECT just before instruction selection to avoid duplicate patterns.

Yes, I saw this comment. We create a custom node in order to avoid an additional "entrance" to LowerSELECT(), right?
In general, this approach is generic - create a custom node to stop the lowering process.
If we'll keep a table of custom-to-common last-minute replacement, it'd be, probably, more robust.
It may be implemented later.

Sep 19 2017, 12:26 AM

Sep 18 2017

delena added a comment to D38022: [X86] Convert X86ISD::SELECT to ISD::VSELECT just before instruction selection to avoid duplicate patterns.

Ok. This is NFC. Why we can't generate (or stay with) ISD::SELECT from the beginning?

Sep 18 2017, 11:49 PM
delena added a comment to D38022: [X86] Convert X86ISD::SELECT to ISD::VSELECT just before instruction selection to avoid duplicate patterns.

Please add a test.

Sep 18 2017, 11:26 PM
delena accepted D37849: [SelectionDAG] Add BITCAST handling to ComputeNumSignBits for splatted sign bits..
Sep 18 2017, 9:26 AM

Sep 17 2017

delena added inline comments to D37849: [SelectionDAG] Add BITCAST handling to ComputeNumSignBits for splatted sign bits..
Sep 17 2017, 5:52 AM

Sep 16 2017

delena added inline comments to D37849: [SelectionDAG] Add BITCAST handling to ComputeNumSignBits for splatted sign bits..
Sep 16 2017, 11:04 PM

Sep 15 2017

delena accepted D37734: [GlobalISel][X86] G_FCONSTANT support..
Sep 15 2017, 10:34 AM

Sep 13 2017

delena accepted D37799: [X86][Skylake] Replacing -mcpu=skx by -mattr in a codegen test. NFC..
Sep 13 2017, 4:33 AM