[RISCV 3/10] Add stub backend

[asb]

Summary

This contains just enough for lib/Target/RISCV to compile. Notably a basic RISCVTargetMachine and RISCVTargetInfo. At this point you can attempt llc -march=riscv32 myinput.ll and will find it fails due to the lack of MCAsmInfo.

[t.p.northover]

lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp

19 ↗

(On Diff #68186)

Does it support JIT? I'd have thought you'd flip this when implementing the pseudo-linker under lib/ExecutionEngine.

[asb]

Address review comment from @t.p.northover

lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp

19 ↗

(On Diff #68186)

That's an error - good catch! Thanks.

[jyknight]

lib/Target/RISCV/RISCVTargetMachine.cpp

40 ↗

(On Diff #68378)

Default model is expected to be PIC instead of static? That's different from most general purpose targets. Perhaps deserves a comment? Or a note in the nonexistent psABI doc. :)

[asb]

Address review comment from @jyknight, match RISC-V gcc's behaviour in defaulting to Reloc::Static.

[reames]

lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp

27 ↗

(On Diff #68685)

Might want to add an assert(false && "not yet implemented").

[asb]

Add a link to the RISC-V ISA docs in CompilerWriterInfo.rst

lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp

27 ↗

(On Diff #68685)

llvm_unreachable would be even better. However in this specific case we actually need to define LLVMInitializeRISCVTargetMC as a no-op. llc will call the initialisation functions for all backends that were compiled in, so if this function is made to assert it means that all codegen tests for other archs will fail.

I've modified the comment to be clear it's not purely a matter of being present for linking.

[theraven]

A couple of small nits inline.

CMakeLists.txt

276 ↗

(On Diff #69347)

Not really an objection, but MIPS and SPARC are both capitalised as if they were words. It would be more consistent to call the back end RiscV, though this would be ugly.

docs/CompilerWriterInfo.rst

86 ↗

(On Diff #69347)

Please also add a link to the ABI spec here.

lib/Target/RISCV/RISCVTargetMachine.cpp

34 ↗

(On Diff #69347)

Please assert TT.isArch32Bit() here, so that we catch fire if someone tries to use this back end for the 128-bit RISC-V variant in the future.

[asb]

assert if trying to compile for RV128 (or at least, a RISC-V that is neither 32-bit or 64-bit).

CMakeLists.txt

276 ↗

(On Diff #69347)

Yes, after considering the alternatives I decided RISCV would be least ugly. Plus ARM of course goes for all caps too.

docs/CompilerWriterInfo.rst

86 ↗

(On Diff #69347)

What exists of the ABI spec is contained within the user-level ISA specification (chapter 20). The separate ABI doc was an extract from the user-level ISA that was put out because the ABI supported by the tools was changed in-between ISA releases. The v2.1 spec contains the most up to date and complete ABI specification.

[t.p.northover]

I think everything here looks reasonable now. I only had a minor comment though so it may be good to check others are happy.

[asb]

Refresh patch to follow the changes made to other backends in rL283702, moving TheRISCV32Target and TheRISCV64Target behind an accessor function.

llvm/trunk/CMakeLists.txt

set(LLVM_ALL_TARGETS
   ARM
   BPF
   Hexagon
   Lanai
   Mips
   MSP430
   NVPTX
   PowerPC
+  RISCV
   Sparc
   SystemZ
   X86
   XCore
   )
 
 # List of targets with JIT support:
 set(LLVM_TARGETS_WITH_JIT X86 PowerPC AArch64 ARM Mips SystemZ)

llvm/trunk/CODE_OWNERS.TXT

 E: [e-mail]
 D: LLVM Bitcode (lib/Bitcode/* include/llvm/Bitcode/*)
 
 N: Justin Bogner
 E: [e-mail]
 D: InstrProfiling and related parts of ProfileData
 D: SelectionDAG (lib/CodeGen/SelectionDAG/*)
 
+N: Alex Bradbury
+E: [e-mail]
+D: RISC-V backend (lib/Target/RISCV/*)
+
 N: Chandler Carruth
 E: [e-mail]
 E: [e-mail]
 D: Config, ADT, Support, inlining & related passes, SROA/mem2reg & related passes, CMake, library layering
 
 N: Evan Cheng
 E: [e-mail]
 D: parts of code generator not covered by someone else

llvm/trunk/docs/CompilerWriterInfo.rst

 * `AMD Cayman/Trinity shader ISA <http://developer.amd.com/wordpress/media/2012/10/AMD_HD_6900_Series_Instruction_Set_Architecture.pdf>`_
 * `AMD Southern Islands Series ISA <http://developer.amd.com/wordpress/media/2012/12/AMD_Southern_Islands_Instruction_Set_Architecture.pdf>`_
 * `AMD Sea Islands Series ISA <http://developer.amd.com/wordpress/media/2013/07/AMD_Sea_Islands_Instruction_Set_Architecture.pdf>`_
 * `AMD GCN3 Instruction Set Architecture <http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2013/12/AMD_GCN3_Instruction_Set_Architecture_rev1.1.pdf>`__
 * `AMD GPU Programming Guide <http://developer.amd.com/download/AMD_Accelerated_Parallel_Processing_OpenCL_Programming_Guide.pdf>`_
 * `AMD Compute Resources <http://developer.amd.com/tools/heterogeneous-computing/amd-accelerated-parallel-processing-app-sdk/documentation/>`_
 * `AMDGPU Compute Application Binary Interface <https://github.com/RadeonOpenCompute/ROCm-ComputeABI-Doc/blob/master/AMDGPU-ABI.md>`__
 
+RISC-V
+------
+* `RISC-V User-Level ISA Specification <https://riscv.org/specifications/>`_
+
 SPARC
 -----
 
 * `SPARC standards <http://sparc.org/standards>`_
 * `SPARC V9 ABI <http://sparc.org/standards/64.psabi.1.35.ps.Z>`_
 * `SPARC V8 ABI <http://sparc.org/standards/psABI3rd.pdf>`_
 
 SystemZ

llvm/trunk/lib/Target/LLVMBuild.txt

  AVR
  BPF
  Lanai
  Hexagon
  MSP430
  NVPTX
  Mips
  PowerPC
+ RISCV
  Sparc
  SystemZ
  WebAssembly
  X86
  XCore
 
 ; This is a special group whose required libraries are extended (by llvm-build)
 ; with the best execution engine (the native JIT, if available, or the

llvm/trunk/lib/Target/RISCV/CMakeLists.txt

+add_llvm_target(RISCVCodeGen
+  RISCVTargetMachine.cpp
+  )
+
+add_subdirectory(TargetInfo)

llvm/trunk/lib/Target/RISCV/LLVMBuild.txt

+;===- ./lib/Target/RISCV/LLVMBuild.txt -------------------------*- Conf -*--===;
+;
+;                     The LLVM Compiler Infrastructure
+;
+; This file is distributed under the University of Illinois Open Source
+; License. See LICENSE.TXT for details.
+;
+;===------------------------------------------------------------------------===;
+;
+; This is an LLVMBuild description file for the components in this subdirectory.
+;
+; For more information on the LLVMBuild system, please see:
+;
+;   http://llvm.org/docs/LLVMBuild.html
+;
+;===------------------------------------------------------------------------===;
+
+[common]
+subdirectories = TargetInfo
+
+[component_0]
+type = TargetGroup
+name = RISCV
+parent = Target
+
+[component_1]
+type = Library
+name = RISCVCodeGen
+parent = RISCV
+required_libraries = Core CodeGen RISCVInfo Support Target
+add_to_library_groups = RISCV

llvm/trunk/lib/Target/RISCV/RISCVTargetMachine.h

+//===-- RISCVTargetMachine.h - Define TargetMachine for RISCV ---*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the RISCV specific subclass of TargetMachine.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_RISCV_RISCVTARGETMACHINE_H
+#define LLVM_LIB_TARGET_RISCV_RISCVTARGETMACHINE_H
+
+#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/IR/DataLayout.h"
+
+namespace llvm {
+class RISCVTargetMachine : public LLVMTargetMachine {
+  std::unique_ptr<TargetLoweringObjectFile> TLOF;
+
+public:
+  RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
+                     StringRef FS, const TargetOptions &Options,
+                     Optional<Reloc::Model> RM, CodeModel::Model CM,
+                     CodeGenOpt::Level OL);
+
+  TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
+
+  TargetLoweringObjectFile *getObjFileLowering() const override {
+    return TLOF.get();
+  }
+};
+Target &getTheRISCV32Target();
+Target &getTheRISCV64Target();
+}
+
+#endif

llvm/trunk/lib/Target/RISCV/RISCVTargetMachine.cpp

+//===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// Implements the info about RISCV target spec.
+//
+//===----------------------------------------------------------------------===//
+
+#include "RISCVTargetMachine.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
+#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/IR/LegacyPassManager.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/Support/FormattedStream.h"
+#include "llvm/Support/TargetRegistry.h"
+#include "llvm/Target/TargetOptions.h"
+using namespace llvm;
+
+extern "C" void LLVMInitializeRISCVTarget() {
+  RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
+  RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
+}
+
+static std::string computeDataLayout(const Triple &TT) {
+  if (TT.isArch64Bit()) {
+    return "e-m:e-i64:64-n32:64-S128";
+  } else {
+    assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
+    return "e-m:e-i64:64-n32-S128";
+  }
+}
+
+static Reloc::Model getEffectiveRelocModel(const Triple &TT,
+                                           Optional<Reloc::Model> RM) {
+  if (!RM.hasValue())
+    return Reloc::Static;
+  return *RM;
+}
+
+RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
+                                       StringRef CPU, StringRef FS,
+                                       const TargetOptions &Options,
+                                       Optional<Reloc::Model> RM,
+                                       CodeModel::Model CM,
+                                       CodeGenOpt::Level OL)
+    : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
+                        getEffectiveRelocModel(TT, RM), CM, OL),
+      TLOF(make_unique<TargetLoweringObjectFileELF>()) {}
+
+TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
+  return new TargetPassConfig(this, PM);
+}

llvm/trunk/lib/Target/RISCV/TargetInfo/CMakeLists.txt

+add_llvm_library(LLVMRISCVInfo
+  RISCVTargetInfo.cpp
+  )

llvm/trunk/lib/Target/RISCV/TargetInfo/LLVMBuild.txt

+;===- ./lib/Target/RISCV/TargetInfo/LLVMBuild.txt --------------*- Conf -*--===;
+;
+;                     The LLVM Compiler Infrastructure
+;
+; This file is distributed under the University of Illinois Open Source
+; License. See LICENSE.TXT for details.
+;
+;===------------------------------------------------------------------------===;
+;
+; This is an LLVMBuild description file for the components in this subdirectory.
+;
+; For more information on the LLVMBuild system, please see:
+;
+;   http://llvm.org/docs/LLVMBuild.html
+;
+;===------------------------------------------------------------------------===;
+
+[component_0]
+type = Library
+name = RISCVInfo
+parent = RISCV
+required_libraries = Support
+add_to_library_groups = RISCV

llvm/trunk/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp

+//===-- RISCVTargetInfo.cpp - RISCV Target Implementation -----------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Support/TargetRegistry.h"
+using namespace llvm;
+
+namespace llvm {
+Target &getTheRISCV32Target() {
+  static Target TheRISCV32Target;
+  return TheRISCV32Target;
+}
+
+Target &getTheRISCV64Target() {
+  static Target TheRISCV64Target;
+  return TheRISCV64Target;
+}
+}
+
+extern "C" void LLVMInitializeRISCVTargetInfo() {
+  RegisterTarget<Triple::riscv32> X(getTheRISCV32Target(), "riscv32",
+                                    "32-bit RISC-V");
+  RegisterTarget<Triple::riscv64> Y(getTheRISCV64Target(), "riscv64",
+                                    "64-bit RISC-V");
+}
+
+// FIXME: Temporary stub - this function must be defined for linking
+// to succeed and will be called unconditionally by llc, so must be a no-op.
+// Remove once this function is properly implemented.
+extern "C" void LLVMInitializeRISCVTargetMC() {}