[RFC] Generate long nop instructions depending on function-specific subtarget info (version 2)

[aturetsk]

Summary

1. Use SubtargetInfo (not CPU name) to control nop emission. For now we still use CPU name, but get it from SubtargetInfo. In the future new nop-related FeatureBits are supposed to be used instead.
2. Support function multi-versioning, so that every function could have different nop padding depending on the target for which the function is compiled (e.g. through attribute "target").
3. Compile path .ll -> .s -> .o must lead to the same result as .ll -> .o. That's why a new assembly directive '.arch' is introduced. The issue appears because of multi-versioning support: nop padding is done during object file creation, so compiler need to preserve target information till that moment (even in .s file). Because it hurts compatibility with other assemblies, it's done only if -asm-preserve-alignment option is specified.

[aturetsk]

lib/MC/MCELFStreamer.cpp

85

Since we can end up merging two fragments with different STI (e.g. by using multiple '.arch' directives), we need a more general solution here. Didn't want to spend much time on this without being sure if the whole approach is OK...

lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

36

This is a placeholder for nop-related features I'm planning to add (FeatureLongNop, FeatureFastNop7).

[aturetsk]

Any comments?

[jyknight]

This is a continuation of D21374 I assume? (Perhaps mark that one abandoned if so).

[aturetsk]

This is a new version of D21374 which takes into account the remark about .ll -> .s -> .o and .ll -> .o compile paths having different result.

[jyknight]

lib/MC/MCObjectStreamer.cpp

540

Why is this in generic code. Is .arch a generic directive? This syntax is x86-specific.

lib/MC/MCStreamer.cpp

33

I think this should be done so that it's compatible with gas. Is there some reason it can't be?

lib/Target/X86/AsmParser/X86AsmParser.cpp

3049

These features are LLVM features (right?), not the feature strings that are used with .arch. So this isn't really okay as is, unless the llvm features happened to align with the .arch features. Which they don't.

(.arch syntax in gas: https://sourceware.org/binutils/docs/as/i386_002dArch.html#i386_002dArch)

include/llvm/MC/MCAsmBackend.h

public:
   /// @}
 
   /// Returns the minimum size of a nop in bytes on this target. The assembler
   /// will use this to emit excess padding in situations where the padding
   /// required for simple alignment would be less than the minimum nop size.
   ///
   virtual unsigned getMinimumNopSize() const { return 1; }
 
-  /// Write an (optimal) nop sequence of Count bytes to the given output. If the
-  /// target cannot generate such a sequence, it should return an error.
+  /// \brief Returns a list of tokens to be used with .arch directive to specify
+  /// preferences for expanding .p2align into nop instructions.
+  virtual SmallVector<std::string, 1>
+  getNopPrefs(const MCSubtargetInfo &STI) const {
+    return SmallVector<std::string, 1>();
+  }
+
+  /// Write an (optimal for \p STI subtarget) nop sequence of \p Count bytes to
+  /// the given output. If the target cannot generate such a sequence, it should
+  /// return an error.
   ///
   /// \return - True on success.
-  virtual bool writeNopData(uint64_t Count, MCObjectWriter *OW) const = 0;
+  virtual bool writeNopData(uint64_t Count, const MCSubtargetInfo &STI,
+                            MCObjectWriter *OW) const = 0;
 
   /// Give backend an opportunity to finish layout after relaxation
   virtual void finishLayout(MCAssembler const &Asm,
                             MCAsmLayout &Layout) const {}
 
   /// Handle any target-specific assembler flags. By default, do nothing.
   virtual void handleAssemblerFlag(MCAssemblerFlag Flag) {}
 

include/llvm/MC/MCFragment.h

static bool classof(const MCFragment *F) {
     return Kind == MCFragment::FT_Relaxable || Kind == MCFragment::FT_Data ||
            Kind == MCFragment::FT_CVDefRange;
   }
 };
 
 /// Fragment for data and encoded instructions.
 ///
 class MCDataFragment : public MCEncodedFragmentWithFixups<32, 4> {
+  /// STI - The MCSubtargetInfo for padding emission.
+  const MCSubtargetInfo *STI;
+
 public:
   MCDataFragment(MCSection *Sec = nullptr)
-      : MCEncodedFragmentWithFixups<32, 4>(FT_Data, false, Sec) {}
+      : MCEncodedFragmentWithFixups<32, 4>(FT_Data, false, Sec), STI(nullptr) {}
+
+  void setHasInstructions(bool V, const MCSubtargetInfo *S) {
+    HasInstructions = V;
+    STI = S;
+  }
 
-  void setHasInstructions(bool V) { HasInstructions = V; }
+  const MCSubtargetInfo *getSubtargetInfo() const { return STI; }
 
   static bool classof(const MCFragment *F) {
     return F->getKind() == MCFragment::FT_Data;
   }
 };
 
 /// This is a compact (memory-size-wise) fragment for holding an encoded
 /// instruction (non-relaxable) that has no fixups registered. When applicable,
 /// it can be used instead of MCDataFragment and lead to lower memory
 /// consumption.
 ///
 class MCCompactEncodedInstFragment : public MCEncodedFragmentWithContents<4> {
+  /// STI - The MCSubtargetInfo for padding emission.
+  const MCSubtargetInfo &STI;
+
 public:
-  MCCompactEncodedInstFragment(MCSection *Sec = nullptr)
-      : MCEncodedFragmentWithContents(FT_CompactEncodedInst, true, Sec) {
-  }
+  MCCompactEncodedInstFragment(const MCSubtargetInfo &STI,
+                               MCSection *Sec = nullptr)
+      : MCEncodedFragmentWithContents(FT_CompactEncodedInst, true, Sec),
+        STI(STI) {}
+
+  const MCSubtargetInfo &getSubtargetInfo() const { return STI; }
 
   static bool classof(const MCFragment *F) {
     return F->getKind() == MCFragment::FT_CompactEncodedInst;
   }
 };
 
 /// A relaxable fragment holds on to its MCInst, since it may need to be
 /// relaxed during the assembler layout and relaxation stage.
public:
   MCRelaxableFragment(const MCInst &Inst, const MCSubtargetInfo &STI,
                       MCSection *Sec = nullptr)
       : MCEncodedFragmentWithFixups(FT_Relaxable, true, Sec),
         Inst(Inst), STI(STI) {}
 
   const MCInst &getInst() const { return Inst; }
   void setInst(const MCInst &Value) { Inst = Value; }
 
-  const MCSubtargetInfo &getSubtargetInfo() { return STI; }
+  const MCSubtargetInfo &getSubtargetInfo() const { return STI; }
 
   static bool classof(const MCFragment *F) {
     return F->getKind() == MCFragment::FT_Relaxable;
   }
 };
 
 class MCAlignFragment : public MCFragment {
 
class MCAlignFragment : public MCFragment {
 
   /// ValueSize - The size of the integer (in bytes) of \p Value.
   unsigned ValueSize;
 
   /// MaxBytesToEmit - The maximum number of bytes to emit; if the alignment
   /// cannot be satisfied in this width then this fragment is ignored.
   unsigned MaxBytesToEmit;
 
+  /// STI - Subtarget info to specify which nop instructions to emit.
+  const MCSubtargetInfo &STI;
+
 public:
   MCAlignFragment(unsigned Alignment, int64_t Value, unsigned ValueSize,
-                  unsigned MaxBytesToEmit, MCSection *Sec = nullptr)
+                  unsigned MaxBytesToEmit, const MCSubtargetInfo &STI,
+                  MCSection *Sec = nullptr)
       : MCFragment(FT_Align, false, 0, Sec), Alignment(Alignment),
-        EmitNops(false), Value(Value),
-        ValueSize(ValueSize), MaxBytesToEmit(MaxBytesToEmit) {}
+        EmitNops(false), Value(Value), ValueSize(ValueSize),
+        MaxBytesToEmit(MaxBytesToEmit), STI(STI) {}
 
   /// \name Accessors
   /// @{
 
   unsigned getAlignment() const { return Alignment; }
 
   int64_t getValue() const { return Value; }
 
   unsigned getValueSize() const { return ValueSize; }
 
   unsigned getMaxBytesToEmit() const { return MaxBytesToEmit; }
 
+  const MCSubtargetInfo &getSubtargetInfo() const { return STI; }
+
   bool hasEmitNops() const { return EmitNops; }
   void setEmitNops(bool Value) { EmitNops = Value; }
 
   /// @}
 
   static bool classof(const MCFragment *F) {
     return F->getKind() == MCFragment::FT_Align;
   }

include/llvm/MC/MCObjectStreamer.h

public:
   bool EmitRelocDirective(const MCExpr &Offset, StringRef Name,
                           const MCExpr *Expr, SMLoc Loc) override;
   using MCStreamer::emitFill;
   void emitFill(uint64_t NumBytes, uint8_t FillValue) override;
   void emitFill(const MCExpr &NumBytes, uint64_t FillValue,
                 SMLoc Loc = SMLoc()) override;
   void emitFill(const MCExpr &NumValues, int64_t Size, int64_t Expr,
                 SMLoc Loc = SMLoc()) override;
+  void EmitArch(StringRef Token) override;
 
   void FinishImpl() override;
 
   /// Emit the absolute difference between two symbols if possible.
   ///
   /// Emit the absolute difference between \c Hi and \c Lo, as long as we can
   /// compute it.  Currently, that requires that both symbols are in the same
   /// data fragment.  Otherwise, do nothing and return \c false.

include/llvm/MC/MCStreamer.h

class MCStreamer {
 
   /// The next unique ID to use when creating a WinCFI-related section (.pdata
   /// or .xdata). This ID ensures that we have a one-to-one mapping from
   /// code section to unwind info section, which MSVC's incremental linker
   /// requires.
   unsigned NextWinCFIID = 0;
 
 protected:
+  const MCSubtargetInfo *STI = nullptr;
+
+protected:
   MCStreamer(MCContext &Ctx);
 
   virtual void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame);
   virtual void EmitCFIEndProcImpl(MCDwarfFrameInfo &CurFrame);
 
   WinEH::FrameInfo *getCurrentWinFrameInfo() {
     return CurrentWinFrameInfo;
   }
 
   virtual void EmitWindowsUnwindTables();
 
   virtual void EmitRawTextImpl(StringRef String);
 
 public:
   virtual ~MCStreamer();
 
   void visitUsedExpr(const MCExpr &Expr);
   virtual void visitUsedSymbol(const MCSymbol &Sym);
 
   void setTargetStreamer(MCTargetStreamer *TS) {
     TargetStreamer.reset(TS);
   }
 
+  const MCSubtargetInfo &getSubtarget() const {
+    assert(STI && "STI object should be always available.");
+    return *STI;
+  }
+
+  void setSubtarget(const MCSubtargetInfo &S) { STI = &S; }
+
   /// State management
   ///
   virtual void reset();
 
   MCContext &getContext() const { return Context; }
 
   MCTargetStreamer *getTargetStreamer() {
     return TargetStreamer.get();
public:
   virtual void EmitWinCFISaveReg(unsigned Register, unsigned Offset);
   virtual void EmitWinCFISaveXMM(unsigned Register, unsigned Offset);
   virtual void EmitWinCFIPushFrame(bool Code);
   virtual void EmitWinCFIEndProlog();
 
   virtual void EmitWinEHHandler(const MCSymbol *Sym, bool Unwind, bool Except);
   virtual void EmitWinEHHandlerData();
 
+  virtual void EmitArch(StringRef Token);
+  void EmitArchForAlignment(const MCAsmBackend &MAB);
+
   /// Get the .pdata section used for the given section. Typically the given
   /// section is either the main .text section or some other COMDAT .text
   /// section, but it may be any section containing code.
   MCSection *getAssociatedPDataSection(const MCSection *TextSec);
 
   /// Get the .xdata section used for the given section.
   MCSection *getAssociatedXDataSection(const MCSection *TextSec);
 

include/llvm/MC/MCSubtargetInfo.h

MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
                   const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
                   const MCReadAdvanceEntry *RA, const InstrStage *IS,
                   const unsigned *OC, const unsigned *FP);
 
   /// getTargetTriple - Return the target triple string.
   const Triple &getTargetTriple() const { return TargetTriple; }
 
   /// getCPU - Return the CPU string.
-  StringRef getCPU() const {
-    return CPU;
-  }
+  StringRef getCPU() const { return CPU; }
+
+  /// setCPU - Set the CPU string.
+  void setCPU(const StringRef NewCPU) { CPU = NewCPU.str(); }
 
   /// getFeatureBits - Return the feature bits.
   ///
   const FeatureBitset& getFeatureBits() const {
     return FeatureBits;
   }
 
   /// setFeatureBits - Set the feature bits.
public:
   /// Initialize an InstrItineraryData instance.
   void initInstrItins(InstrItineraryData &InstrItins) const;
 
   /// Check whether the CPU string is valid.
   bool isCPUStringValid(StringRef CPU) const {
     auto Found = std::lower_bound(ProcDesc.begin(), ProcDesc.end(), CPU);
     return Found != ProcDesc.end() && StringRef(Found->Key) == CPU;
   }
+
+  /// Check whether the Feature string is valid.
+  bool isFeatureStringValid(StringRef Feature) const {
+    auto Found = std::lower_bound(ProcFeatures.begin(), ProcFeatures.end(), Feature);
+    return Found != ProcFeatures.end() && StringRef(Found->Key) == Feature;
+  }
 };
 
 } // End llvm namespace
 
 #endif

include/llvm/Support/TargetRegistry.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_SUPPORT_TARGETREGISTRY_H
 #define LLVM_SUPPORT_TARGETREGISTRY_H
 
 #include "llvm-c/Disassembler.h"
 #include "llvm/ADT/Optional.h"
 #include "llvm/ADT/Triple.h"
+#include "llvm/MC/MCStreamer.h"
 #include "llvm/Support/CodeGen.h"
 #include "llvm/Support/FormattedStream.h"
 #include <cassert>
 #include <memory>
 #include <string>
 
 namespace llvm {
 class AsmPrinter;
 class MCAsmBackend;
 class MCAsmInfo;
 class MCAsmParser;
 class MCCodeEmitter;
 class MCContext;
 class MCDisassembler;
 class MCInstrAnalysis;
 class MCInstPrinter;
 class MCInstrInfo;
 class MCRegisterInfo;
-class MCStreamer;
 class MCSubtargetInfo;
 class MCSymbolizer;
 class MCRelocationInfo;
 class MCTargetAsmParser;
 class MCTargetOptions;
 class MCTargetStreamer;
 class TargetMachine;
 class TargetOptions;
case Triple::ELF:
       if (ELFStreamerCtorFn)
         S = ELFStreamerCtorFn(T, Ctx, TAB, OS, Emitter, RelaxAll);
       else
         S = createELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
       break;
     }
     if (ObjectTargetStreamerCtorFn)
       ObjectTargetStreamerCtorFn(*S, STI);
+    S->setSubtarget(STI);
     return S;
   }
 
   MCStreamer *createAsmStreamer(MCContext &Ctx,
                                 std::unique_ptr<formatted_raw_ostream> OS,
                                 bool IsVerboseAsm, bool UseDwarfDirectory,
                                 MCInstPrinter *InstPrint, MCCodeEmitter *CE,
-                                MCAsmBackend *TAB, bool ShowInst) const {
+                                MCAsmBackend *TAB, bool ShowInst,
+                                const MCSubtargetInfo &STI) const {
     formatted_raw_ostream &OSRef = *OS;
     MCStreamer *S = llvm::createAsmStreamer(Ctx, std::move(OS), IsVerboseAsm,
                                             UseDwarfDirectory, InstPrint, CE,
                                             TAB, ShowInst);
     createAsmTargetStreamer(*S, OSRef, InstPrint, IsVerboseAsm);
+    S->setSubtarget(STI);
     return S;
   }
 
   MCTargetStreamer *createAsmTargetStreamer(MCStreamer &S,
                                             formatted_raw_ostream &OS,
                                             MCInstPrinter *InstPrint,
                                             bool IsVerboseAsm) const {
     if (AsmTargetStreamerCtorFn)

lib/CodeGen/AsmPrinter/AsmPrinter.cpp

 MCSymbol *AsmPrinter::getCurExceptionSym() {
   if (!CurExceptionSym)
     CurExceptionSym = createTempSymbol("exception");
   return CurExceptionSym;
 }
 
 void AsmPrinter::SetupMachineFunction(MachineFunction &MF) {
   this->MF = &MF;
+
+  // Pass STI to the streamer to be able to generate long nops according to
+  // the function-specific subtarget information.
+  OutStreamer->setSubtarget(MF.getSubtarget());
+
   // Get the function symbol.
   CurrentFnSym = getSymbol(MF.getFunction());
   CurrentFnSymForSize = CurrentFnSym;
   CurrentFnBegin = nullptr;
   CurExceptionSym = nullptr;
   bool NeedsLocalForSize = MAI->needsLocalForSize();
   if (!MMI->getLandingPads().empty() || MMI->hasDebugInfo() ||
       MMI->hasEHFunclets() || NeedsLocalForSize) {

lib/CodeGen/LLVMTargetMachine.cpp

case CGFT_AssemblyFile: {
 
     MCAsmBackend *MAB =
         getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU,
                                        Options.MCOptions);
     auto FOut = llvm::make_unique<formatted_raw_ostream>(Out);
     MCStreamer *S = getTarget().createAsmStreamer(
         *Context, std::move(FOut), Options.MCOptions.AsmVerbose,
         Options.MCOptions.MCUseDwarfDirectory, InstPrinter, MCE, MAB,
-        Options.MCOptions.ShowMCInst);
+        Options.MCOptions.ShowMCInst, STI);
     AsmStreamer.reset(S);
     break;
   }
   case CGFT_ObjectFile: {
     // Create the code emitter for the target if it exists.  If not, .o file
     // emission fails.
     MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, *Context);
     MCAsmBackend *MAB =

lib/MC/MCAsmStreamer.cpp

public:
   bool EmitRelocDirective(const MCExpr &Offset, StringRef Name,
                           const MCExpr *Expr, SMLoc Loc) override;
 
   /// EmitRawText - If this file is backed by an assembly streamer, this dumps
   /// the specified string in the output .s file.  This capability is
   /// indicated by the hasRawTextSupport() predicate.
   void EmitRawTextImpl(StringRef String) override;
 
+  void EmitArch(StringRef Token) override;
+
   void FinishImpl() override;
 };
 
 } // end anonymous namespace.
 
 /// AddComment - Add a comment that can be emitted to the generated .s
 /// file if applicable as a QoI issue to make the output of the compiler
 /// more readable.  This only affects the MCAsmStreamer, and only when
void MCAsmStreamer::emitFill(const MCExpr &NumValues, int64_t Size,
   OS << ", " << Size << ", 0x";
   OS.write_hex(truncateToSize(Expr, 4));
   EmitEOL();
 }
 
 void MCAsmStreamer::EmitValueToAlignment(unsigned ByteAlignment, int64_t Value,
                                          unsigned ValueSize,
                                          unsigned MaxBytesToEmit) {
+  if (AsmBackend)
+    EmitArchForAlignment(*AsmBackend);
+
   // Some assemblers don't support non-power of two alignments, so we always
   // emit alignments as a power of two if possible.
   if (isPowerOf2_32(ByteAlignment)) {
     switch (ValueSize) {
     default:
       llvm_unreachable("Invalid size for machine code value!");
     case 1:
       OS << "\t.p2align\t";

 /// indicated by the hasRawTextSupport() predicate.
 void MCAsmStreamer::EmitRawTextImpl(StringRef String) {
   if (!String.empty() && String.back() == '\n')
     String = String.substr(0, String.size()-1);
   OS << String;
   EmitEOL();
 }
 
+void MCAsmStreamer::EmitArch(StringRef Token) {
+  OS << "\t.arch\t" << Token;
+  EmitEOL();
+}
+
 void MCAsmStreamer::FinishImpl() {
   // If we are generating dwarf for assembly source files dump out the sections.
   if (getContext().getGenDwarfForAssembly())
     MCGenDwarfInfo::Emit(this);
 
   // Emit the label for the line table, if requested - since the rest of the
   // line table will be defined by .loc/.file directives, and not emitted
   // directly, the label is the only work required here.

lib/MC/MCAssembler.cpp

void MCAssembler::registerSymbol(const MCSymbol &Symbol, bool *Created) {
   }
 }
 
 void MCAssembler::writeFragmentPadding(const MCFragment &F, uint64_t FSize,
                                        MCObjectWriter *OW) const {
   // Should NOP padding be written out before this fragment?
   unsigned BundlePadding = F.getBundlePadding();
   if (BundlePadding > 0) {
+    const MCSubtargetInfo *STI;
+
     assert(isBundlingEnabled() &&
            "Writing bundle padding with disabled bundling");
     assert(F.hasInstructions() &&
            "Writing bundle padding for a fragment without instructions");
 
+    // Get subtarget information for emitting padding.
+    switch (F.getKind()) {
+    case MCFragment::FT_CompactEncodedInst:
+      STI = &cast<MCCompactEncodedInstFragment>(F).getSubtargetInfo();
+      break;
+    case MCFragment::FT_Data:
+      STI = cast<MCDataFragment>(F).getSubtargetInfo();
+      break;
+    case MCFragment::FT_Relaxable:
+      STI = &cast<MCRelaxableFragment>(F).getSubtargetInfo();
+      break;
+    default:
+      llvm_unreachable("Unexpected fragment kind.");
+    }
+
+    assert(STI && "Subtarget information must be available.");
+
     unsigned TotalLength = BundlePadding + static_cast<unsigned>(FSize);
     if (F.alignToBundleEnd() && TotalLength > getBundleAlignSize()) {
       // If the padding itself crosses a bundle boundary, it must be emitted
       // in 2 pieces, since even nop instructions must not cross boundaries.
       //             v--------------v   <- BundleAlignSize
       //        v---------v             <- BundlePadding
       // ----------------------------
       // | Prev |####|####|    F    |
       // ----------------------------
       //        ^-------------------^   <- TotalLength
       unsigned DistanceToBoundary = TotalLength - getBundleAlignSize();
-      if (!getBackend().writeNopData(DistanceToBoundary, OW))
+      if (!getBackend().writeNopData(DistanceToBoundary, *STI, OW))
           report_fatal_error("unable to write NOP sequence of " +
                              Twine(DistanceToBoundary) + " bytes");
       BundlePadding -= DistanceToBoundary;
     }
-    if (!getBackend().writeNopData(BundlePadding, OW))
+    if (!getBackend().writeNopData(BundlePadding, *STI, OW))
       report_fatal_error("unable to write NOP sequence of " +
                          Twine(BundlePadding) + " bytes");
   }
 }
 
 /// \brief Write the fragment \p F to the output file.
 static void writeFragment(const MCAssembler &Asm, const MCAsmLayout &Layout,
                           const MCFragment &F) {
if (Count * AF.getValueSize() != FragmentSize)
                         "' is not a divisor of padding size '" +
                         Twine(FragmentSize) + "'");
 
     // See if we are aligning with nops, and if so do that first to try to fill
     // the Count bytes.  Then if that did not fill any bytes or there are any
     // bytes left to fill use the Value and ValueSize to fill the rest.
     // If we are aligning with nops, ask that target to emit the right data.
     if (AF.hasEmitNops()) {
-      if (!Asm.getBackend().writeNopData(Count, OW))
+      if (!Asm.getBackend().writeNopData(Count, AF.getSubtargetInfo(), OW))
         report_fatal_error("unable to write nop sequence of " +
                           Twine(Count) + " bytes");
       break;
     }
 
     // Otherwise, write out in multiples of the value size.
     for (uint64_t i = 0; i != Count; ++i) {
       switch (AF.getValueSize()) {

lib/MC/MCELFStreamer.cpp

void MCELFStreamer::mergeFragment(MCDataFragment *DF,
 
   flushPendingLabels(DF, DF->getContents().size());
 
   for (unsigned i = 0, e = EF->getFixups().size(); i != e; ++i) {
     EF->getFixups()[i].setOffset(EF->getFixups()[i].getOffset() +
                                  DF->getContents().size());
     DF->getFixups().push_back(EF->getFixups()[i]);
   }
-  DF->setHasInstructions(true);
+  DF->setHasInstructions(true, &getSubtarget());
   DF->getContents().append(EF->getContents().begin(), EF->getContents().end());
 }
 
 void MCELFStreamer::InitSections(bool NoExecStack) {
   MCContext &Ctx = getContext();
   SwitchSection(Ctx.getObjectFileInfo()->getTextSection());
   EmitCodeAlignment(4);
 
if (Assembler.isBundlingEnabled()) {
     else if (isBundleLocked() && !Sec.isBundleGroupBeforeFirstInst())
       // If we are bundle-locked, we re-use the current fragment.
       // The bundle-locking directive ensures this is a new data fragment.
       DF = cast<MCDataFragment>(getCurrentFragment());
     else if (!isBundleLocked() && Fixups.size() == 0) {
       // Optimize memory usage by emitting the instruction to a
       // MCCompactEncodedInstFragment when not in a bundle-locked group and
       // there are no fixups registered.
-      MCCompactEncodedInstFragment *CEIF = new MCCompactEncodedInstFragment();
+      MCCompactEncodedInstFragment *CEIF =
+          new MCCompactEncodedInstFragment(getSubtarget());
       insert(CEIF);
       CEIF->getContents().append(Code.begin(), Code.end());
       return;
     } else {
       DF = new MCDataFragment();
       insert(DF);
     }
     if (Sec.getBundleLockState() == MCSection::BundleLockedAlignToEnd) {
if (Assembler.isBundlingEnabled()) {
     DF = getOrCreateDataFragment();
   }
 
   // Add the fixups and data.
   for (unsigned i = 0, e = Fixups.size(); i != e; ++i) {
     Fixups[i].setOffset(Fixups[i].getOffset() + DF->getContents().size());
     DF->getFixups().push_back(Fixups[i]);
   }
-  DF->setHasInstructions(true);
+  DF->setHasInstructions(true, &getSubtarget());
   DF->getContents().append(Code.begin(), Code.end());
 
   if (Assembler.isBundlingEnabled() && Assembler.getRelaxAll()) {
     if (!isBundleLocked()) {
       mergeFragment(getOrCreateDataFragment(), DF);
       delete DF;
     }
   }

lib/MC/MCMachOStreamer.cpp

void MCMachOStreamer::EmitZerofill(MCSection *Section, MCSymbol *Symbol,
   assert(Section->isVirtualSection() && "Section does not have zerofill type!");
 
   assert(Symbol->isUndefined() && "Cannot define a symbol twice!");
 
   getAssembler().registerSymbol(*Symbol);
 
   // Emit an align fragment if necessary.
   if (ByteAlignment != 1)
-    new MCAlignFragment(ByteAlignment, 0, 0, ByteAlignment, Section);
+    new MCAlignFragment(ByteAlignment, 0, 0, ByteAlignment, getSubtarget(),
+                        Section);
 
   MCFragment *F = new MCFillFragment(0, Size, Section);
   Symbol->setFragment(F);
 
   // Update the maximum alignment on the zero fill section if necessary.
   if (ByteAlignment > Section->getAlignment())
     Section->setAlignment(ByteAlignment);
 }

lib/MC/MCObjectStreamer.cpp

void MCObjectStreamer::EmitBytes(StringRef Data) {
   flushPendingLabels(DF, DF->getContents().size());
   DF->getContents().append(Data.begin(), Data.end());
 }
 
 void MCObjectStreamer::EmitValueToAlignment(unsigned ByteAlignment,
                                             int64_t Value,
                                             unsigned ValueSize,
                                             unsigned MaxBytesToEmit) {
+  EmitArchForAlignment(Assembler->getBackend());
+
   if (MaxBytesToEmit == 0)
     MaxBytesToEmit = ByteAlignment;
-  insert(new MCAlignFragment(ByteAlignment, Value, ValueSize, MaxBytesToEmit));
+  insert(new MCAlignFragment(ByteAlignment, Value, ValueSize, MaxBytesToEmit,
+                             getSubtarget()));
 
   // Update the maximum alignment on the current section if necessary.
   MCSection *CurSec = getCurrentSection().first;
   if (ByteAlignment > CurSec->getAlignment())
     CurSec->setAlignment(ByteAlignment);
 }
 
 void MCObjectStreamer::EmitCodeAlignment(unsigned ByteAlignment,
getContext().getSourceManager()->PrintMessage(
         Loc, SourceMgr::DK_Warning,
         "'.fill' directive with negative repeat count has no effect");
     return;
   }
 
   MCStreamer::emitFill(IntNumValues, Size, Expr);
 }
 
+void MCObjectStreamer::EmitArch(StringRef Token) {
+  assert(Token.find(' ') == std::string::npos &&
+         Token.find('\t') == std::string::npos &&
+         ".arch directive has too many arguments.");
+
+  MCSubtargetInfo &NewSTI = getContext().getSubtargetCopy(getSubtarget());
+
+  if (Token.startswith(".")) {
+    // .arch is used to enable/disable a CPU feature.
+    StringRef Feature = Token.substr(1);
+
+    bool EnableFeature = true;
+    if (Feature.startswith_lower("no")) {
+      EnableFeature = false;
+      Feature = Feature.substr(2);
+    }
+
+    assert(NewSTI.isFeatureStringValid(Feature) && "Unknown CPU feature.");
+    NewSTI.ApplyFeatureFlag((EnableFeature ? "+" : "-") + Feature.str());
+  } else {
+    // .arch is used to specify target CPU.
+    assert(NewSTI.isCPUStringValid(Token) && "Unknown CPU name.");
+    NewSTI.setDefaultFeatures(Token, "");
+    NewSTI.setCPU(Token);
+  }
+
+  setSubtarget(NewSTI);
+}
+
 void MCObjectStreamer::FinishImpl() {
   // If we are generating dwarf for assembly source files dump out the sections.
   if (getContext().getGenDwarfForAssembly())
     MCGenDwarfInfo::Emit(this);
 
   // Dump out the dwarf file & directory tables and line tables.
   MCDwarfLineTable::Emit(this, getAssembler().getDWARFLinetableParams());
 
   flushPendingLabels(nullptr);
   getAssembler().Finish();
 }

lib/MC/MCStreamer.cpp

 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCObjectFileInfo.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCSection.h"
 #include "llvm/MC/MCSectionCOFF.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/MC/MCWin64EH.h"
 #include "llvm/Support/COFF.h"
+#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/LEB128.h"
 #include "llvm/Support/raw_ostream.h"
 #include <cstdlib>
 using namespace llvm;
 
+// Emitting .arch directive hurts compatibility with assemblers other than LLVM,
+// so don't preserve alignment instructions across assembly by default.
+static cl::opt<bool>
+    AsmPreserveAlignment("asm-preserve-alignment", cl::Hidden,
+                         cl::desc("Preserve alignment instructions across "
+                                  "assembly by emitting .arch directive"),
+                         cl::init(false));
+
 // Pin the vtables to this file.
 MCTargetStreamer::~MCTargetStreamer() {}
 
 MCTargetStreamer::MCTargetStreamer(MCStreamer &S) : Streamer(S) {
   S.setTargetStreamer(this);
 }
 
 void MCTargetStreamer::emitLabel(MCSymbol *Symbol) {}

 }
 
 void MCStreamer::EmitWinEHHandlerData() {
   EnsureValidWinFrameInfo();
   if (CurrentWinFrameInfo->ChainedParent)
     report_fatal_error("Chained unwind areas can't have handlers!");
 }
 
+void MCStreamer::EmitArch(StringRef Token) {}
+
+void MCStreamer::EmitArchForAlignment(const MCAsmBackend &MAB) {
+  if (!AsmPreserveAlignment)
+    return;
+
+  assert(STI && "Subtarget info must be available.");
+  SmallVector<std::string, 1> Prefs = MAB.getNopPrefs(*STI);
+  for (auto T : Prefs)
+    EmitArch(T);
+}
+
 static MCSection *getWinCFISection(MCContext &Context, unsigned *NextWinCFIID,
                                    MCSection *MainCFISec,
                                    const MCSection *TextSec) {
   // If this is the main .text section, use the main unwind info section.
   if (TextSec == Context.getObjectFileInfo()->getTextSection())
     return MainCFISec;
 
   const auto *TextSecCOFF = cast<MCSectionCOFF>(TextSec);

lib/MC/WinCOFFStreamer.cpp

void MCWinCOFFStreamer::EmitLocalCommonSymbol(MCSymbol *S, uint64_t Size,
   if (Section->getAlignment() < ByteAlignment)
     Section->setAlignment(ByteAlignment);
 
   getAssembler().registerSymbol(*Symbol);
   Symbol->setExternal(false);
 
   if (ByteAlignment != 1)
     new MCAlignFragment(ByteAlignment, /*Value=*/0, /*ValueSize=*/0,
-                        ByteAlignment, Section);
+                        ByteAlignment, getSubtarget(), Section);
 
   MCFillFragment *Fragment = new MCFillFragment(
       /*Value=*/0, Size, Section);
   Symbol->setFragment(Fragment);
 }
 
 void MCWinCOFFStreamer::EmitZerofill(MCSection *Section, MCSymbol *Symbol,
                                      uint64_t Size, unsigned ByteAlignment) {

lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp

void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
                   uint64_t Value, bool IsPCRel) const override;
 
   bool mayNeedRelaxation(const MCInst &Inst) const override;
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override;
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                         MCInst &Res) const override;
-  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+  bool writeNopData(uint64_t Count, const MCSubtargetInfo &STI,
+                    MCObjectWriter *OW) const override;
 
   void HandleAssemblerFlag(MCAssemblerFlag Flag) {}
 
   unsigned getPointerSize() const { return 8; }
 
   unsigned getFixupKindContainereSizeInBytes(unsigned Kind) const;
 };
 

 }
 
 void AArch64AsmBackend::relaxInstruction(const MCInst &Inst,
                                          const MCSubtargetInfo &STI,
                                          MCInst &Res) const {
   llvm_unreachable("AArch64AsmBackend::relaxInstruction() unimplemented");
 }
 
-bool AArch64AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
+bool AArch64AsmBackend::writeNopData(uint64_t Count, const MCSubtargetInfo &STI,
+                                     MCObjectWriter *OW) const {
   // If the count is not 4-byte aligned, we must be writing data into the text
   // section (otherwise we have unaligned instructions, and thus have far
   // bigger problems), so just write zeros instead.
   OW->WriteZeros(Count % 4);
 
   // We are properly aligned, so write NOPs as requested.
   Count /= 4;
   for (uint64_t i = 0; i != Count; ++i)

lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCAsmLayout &Layout) const override {
     return false;
   }
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                         MCInst &Res) const override {
     assert(!"Not implemented");
   }
   bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
-  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+  bool writeNopData(uint64_t Count, const MCSubtargetInfo &STI,
+                    MCObjectWriter *OW) const override;
 
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
 };
 
 } //End anonymous namespace
 
 void AMDGPUMCObjectWriter::writeObject(MCAssembler &Asm,
                                        const MCAsmLayout &Layout) {
const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
   };
 
   if (Kind < FirstTargetFixupKind)
     return MCAsmBackend::getFixupKindInfo(Kind);
 
   return Infos[Kind - FirstTargetFixupKind];
 }
 
-bool AMDGPUAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
+bool AMDGPUAsmBackend::writeNopData(uint64_t Count, const MCSubtargetInfo &STI,
+                                    MCObjectWriter *OW) const {
   OW->WriteZeros(Count);
 
   return true;
 }
 
 //===----------------------------------------------------------------------===//
 // ELFAMDGPUAsmBackend class
 //===----------------------------------------------------------------------===//

lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h

public:
 
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override;
 
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                         MCInst &Res) const override;
 
-  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+  bool writeNopData(uint64_t Count, const MCSubtargetInfo &STI,
+                    MCObjectWriter *OW) const override;
 
   void handleAssemblerFlag(MCAssemblerFlag Flag) override;
 
   unsigned getPointerSize() const { return 4; }
   bool isThumb() const { return isThumbMode; }
   void setIsThumb(bool it) { isThumbMode = it; }
   bool isLittle() const { return IsLittleEndian; }
 };
 } // end namespace llvm
 
 #endif

lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

void ARMAsmBackend::relaxInstruction(const MCInst &Inst,
   }
 
   // The rest of instructions we're relaxing have the same operands.
   // We just need to update to the proper opcode.
   Res = Inst;
   Res.setOpcode(RelaxedOp);
 }
 
-bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
+bool ARMAsmBackend::writeNopData(uint64_t Count, const MCSubtargetInfo &STI,
+                                 MCObjectWriter *OW) const {
   const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
   const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
   const uint32_t ARMv4_NopEncoding = 0xe1a00000;   // using MOV r0,r0
   const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
   if (isThumb()) {
     const uint16_t nopEncoding =
         hasNOP() ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding;
     uint64_t NumNops = Count / 2;

lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp

public:
 
   unsigned getNumFixupKinds() const override { return 1; }
 
   bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
 
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                         MCInst &Res) const override {}
 
-  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+  bool writeNopData(uint64_t Count, const MCSubtargetInfo &STI,
+                    MCObjectWriter *OW) const override;
 };
 
-bool BPFAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
+bool BPFAsmBackend::writeNopData(uint64_t Count, const MCSubtargetInfo &STI,
+                                 MCObjectWriter *OW) const {
   if ((Count % 8) != 0)
     return false;
 
   for (uint64_t i = 0; i < Count; i += 8)
     OW->write64(0x15000000);
 
   return true;
 }

lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp

for (auto &I : HexagonMCInstrInfo::bundleInstructions(Inst)) {
       }
       // now copy over the original instruction(the one we may have extended)
       Res.addOperand(MCOperand::createInst(I.getInst()));
     }
     (void)Update;
     assert(Update && "Didn't find relaxation target");
   }
 
-  bool writeNopData(uint64_t Count,
-                    MCObjectWriter * OW) const override {
+  bool writeNopData(uint64_t Count, const MCSubtargetInfo &STI,
+                    MCObjectWriter *OW) const override {
     static const uint32_t Nopcode  = 0x7f000000, // Hard-coded NOP.
                           ParseIn  = 0x00004000, // In packet parse-bits.
                           ParseEnd = 0x0000c000; // End of packet parse-bits.
 
     while(Count % HEXAGON_INSTR_SIZE) {
       DEBUG(dbgs() << "Alignment not a multiple of the instruction size:" <<
           Count % HEXAGON_INSTR_SIZE << "/" << HEXAGON_INSTR_SIZE << "\n");
       --Count;

lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp

public:
   bool mayNeedRelaxation(const MCInst & /*Inst*/) const override {
     return false;
   }
 
   void relaxInstruction(const MCInst & /*Inst*/,
                         const MCSubtargetInfo & /*STI*/,
                         MCInst & /*Res*/) const override {}
 
-  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+  bool writeNopData(uint64_t Count, const MCSubtargetInfo &STI,
+                    MCObjectWriter *OW) const override;
 };
 
-bool LanaiAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
+bool LanaiAsmBackend::writeNopData(uint64_t Count, const MCSubtargetInfo &STI,
+                                   MCObjectWriter *OW) const {
   if ((Count % 4) != 0)
     return false;
 
   for (uint64_t i = 0; i < Count; i += 4)
     OW->write32(0x15000000);
 
   return true;
 }

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h

public:
   /// \param Inst - The instruction to relax, which may be the same
   /// as the output.
   /// \param [out] Res On return, the relaxed instruction.
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                         MCInst &Res) const override {}
 
   /// @}
 
-  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+  bool writeNopData(uint64_t Count, const MCSubtargetInfo &STI,
+                    MCObjectWriter *OW) const override;
 
   void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
                          const MCFixup &Fixup, const MCFragment *DF,
                          const MCValue &Target, uint64_t &Value,
                          bool &IsResolved) override;
 
 }; // class MipsAsmBackend
 
 } // namespace
 
 #endif

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

getFixupKindInfo(MCFixupKind Kind) const {
   return BigEndianInfos[Kind - FirstTargetFixupKind];
 }
 
 /// WriteNopData - Write an (optimal) nop sequence of Count bytes
 /// to the given output. If the target cannot generate such a sequence,
 /// it should return an error.
 ///
 /// \return - True on success.
-bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
+bool MipsAsmBackend::writeNopData(uint64_t Count, const MCSubtargetInfo &STI,
+                                  MCObjectWriter *OW) const {
   // Check for a less than instruction size number of bytes
   // FIXME: 16 bit instructions are not handled yet here.
   // We shouldn't be using a hard coded number for instruction size.
 
   // If the count is not 4-byte aligned, we must be writing data into the text
   // section (otherwise we have unaligned instructions, and thus have far
   // bigger problems), so just write zeros instead.
   OW->WriteZeros(Count);

lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp

public:
   }
 
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                         MCInst &Res) const override {
     // FIXME.
     llvm_unreachable("relaxInstruction() unimplemented");
   }
 
-  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override {
+  bool writeNopData(uint64_t Count, const MCSubtargetInfo &STI,
+                    MCObjectWriter *OW) const override {
     uint64_t NumNops = Count / 4;
     for (uint64_t i = 0; i != NumNops; ++i)
       OW->write32(0x60000000);
 
     OW->WriteZeros(Count % 4);
 
     return true;
   }

lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

bool fixupNeedsRelaxation(const MCFixup &Fixup,
       return false;
     }
     void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                           MCInst &Res) const override {
       // FIXME.
       llvm_unreachable("relaxInstruction() unimplemented");
     }
 
-    bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override {
+    bool writeNopData(uint64_t Count, const MCSubtargetInfo &STI,
+                      MCObjectWriter *OW) const override {
       // Cannot emit NOP with size not multiple of 32 bits.
       if (Count % 4 != 0)
         return false;
 
       uint64_t NumNops = Count / 4;
       for (uint64_t i = 0; i != NumNops; ++i)
         OW->write32(0x01000000);
 

lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp

bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *Fragment,
                             const MCAsmLayout &Layout) const override {
     return false;
   }
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                         MCInst &Res) const override {
     llvm_unreachable("SystemZ does do not have assembler relaxation");
   }
-  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+  bool writeNopData(uint64_t Count, const MCSubtargetInfo &STI,
+                    MCObjectWriter *OW) const override;
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createSystemZObjectWriter(OS, OSABI);
   }
 };
 } // end anonymous namespace
 
 const MCFixupKindInfo &
 SystemZMCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
void SystemZMCAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
   unsigned ShiftValue = (Size * 8) - 8;
   for (unsigned I = 0; I != Size; ++I) {
     Data[Offset + I] |= uint8_t(Value >> ShiftValue);
     ShiftValue -= 8;
   }
 }
 
 bool SystemZMCAsmBackend::writeNopData(uint64_t Count,
+                                       const MCSubtargetInfo &STI,
                                        MCObjectWriter *OW) const {
   for (uint64_t I = 0; I != Count; ++I)
     OW->write8(7);
   return true;
 }
 
 MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T,
                                               const MCRegisterInfo &MRI,
                                               const Triple &TT, StringRef CPU,
                                               const MCTargetOptions &Options) {
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
   return new SystemZMCAsmBackend(OSABI);
 }

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp

unsigned getNumFixupKinds() const override {
     return 0;
   }
 
   bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
 
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                         MCInst &Res) const override {}
 
-  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+  bool writeNopData(uint64_t Count, const MCSubtargetInfo &STI,
+                    MCObjectWriter *OW) const override;
 };
 
 bool WebAssemblyAsmBackend::writeNopData(uint64_t Count,
+                                         const MCSubtargetInfo &STI,
                                          MCObjectWriter *OW) const {
   if (Count == 0)
     return true;
 
   // FIXME: Do something.
   return false;
 }
 

lib/Target/X86/AsmParser/X86AsmParser.cpp

private:
   CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
                         unsigned IndexReg, unsigned Scale, SMLoc Start,
                         SMLoc End, unsigned Size, StringRef Identifier,
                         InlineAsmIdentifierInfo &Info);
 
   bool parseDirectiveEven(SMLoc L);
   bool ParseDirectiveWord(unsigned Size, SMLoc L);
   bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
+  bool ParseDirectiveArch(SMLoc L);
 
   bool processInstruction(MCInst &Inst, const OperandVector &Ops);
 
   /// Wrapper around MCStreamer::EmitInstruction(). Possibly adds
   /// instrumentation around Inst.
   void EmitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out);
 
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
if (getLexer().isNot(AsmToken::EndOfStatement)) {
       else if (Parser.getTok().getString() == "prefix")
         return Error(DirectiveID.getLoc(), "'.intel_syntax prefix' is not "
                                            "supported: registers must not have "
                                            "a '%' prefix in .intel_syntax");
     }
     return false;
   } else if (IDVal == ".even")
     return parseDirectiveEven(DirectiveID.getLoc());
+  else if (IDVal == ".arch")
+    return ParseDirectiveArch(DirectiveID.getLoc());
   return true;
 }
 
 /// parseDirectiveEven
 ///  ::= .even
 bool X86AsmParser::parseDirectiveEven(SMLoc L) {
   const MCSection *Section = getStreamer().getCurrentSection().first;
   if (getLexer().isNot(AsmToken::EndOfStatement)) {
     TokError("unexpected token in directive");
     return false;  
   }
   if (!Section) {
     getStreamer().InitSections(false);
     Section = getStreamer().getCurrentSection().first;
   }
   if (Section->UseCodeAlign())
     getStreamer().EmitCodeAlignment(2, 0);
   else
     getStreamer().EmitValueToAlignment(2, 0, 1, 0);
   return false;
 }
+
 /// ParseDirectiveWord
 ///  ::= .word [ expression (, expression)* ]
 bool X86AsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
   MCAsmParser &Parser = getParser();
   if (getLexer().isNot(AsmToken::EndOfStatement)) {
     for (;;) {
       const MCExpr *Value;
       SMLoc ExprLoc = getLexer().getLoc();
bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
   } else {
     Error(L, "unknown directive " + IDVal);
     return false;
   }
 
   return false;
 }
 
+/// ParseDirectiveArch
+///  ::= .arch cpu
+///  ::= .arch .[no]feature
+bool X86AsmParser::ParseDirectiveArch(SMLoc L) {
+  // Use parseStringToEndOfStatement rather than getTok sequence to handle
+  // feature names containing '-' character more easily.
+  StringRef Token = getParser().parseStringToEndOfStatement().trim();
+
+  // Make sure .arch has only one argument.
+  if (Token.find(' ') != std::string::npos ||
+      Token.find('\t') != std::string::npos) {
+    Error(L, "unexpected number of arguments in .arch directive");
+    return false;
+  }
+
+  MCSubtargetInfo &NewSTI = copySTI();
+
+  if (Token.startswith(".")) {
+    // .arch is used to enable/disable a CPU feature.
+    StringRef Feature = Token.substr(1);
+
+    bool EnableFeature = true;
+    if (Feature.startswith_lower("no")) {
+      EnableFeature = false;
+      Feature = Feature.substr(2);
+    }
+
+    if (!NewSTI.isFeatureStringValid(Feature)) {
+      Error(L, "unrecognized feature \'" + Feature + "\' in .arch directive");
+      return false;
+    }
+
+    NewSTI.ApplyFeatureFlag((EnableFeature ? "+" : "-") + Feature.str());
+  } else {
+    // .arch is used to specify target CPU.
+    // Preserve mode bit.
+    StringRef Mode = is64BitMode()
+                         ? "+64bit-mode"
+                         : (is32BitMode() ? "+32bit-mode" : "+16bit-mode");
+
+    if (!NewSTI.isCPUStringValid(Token)) {
+      Error(L, "unrecognized CPU \'" + Token + "\' in .arch directive");
+      return false;
+    }
+
+    NewSTI.setDefaultFeatures(Token, Mode);
+    NewSTI.setCPU(Token);
+  }
+
+  getParser().getStreamer().EmitArch(Token);
+
+  return false;
+}
+
 // Force static initialization.
 extern "C" void LLVMInitializeX86AsmParser() {
   RegisterMCAsmParser<X86AsmParser> X(TheX86_32Target);
   RegisterMCAsmParser<X86AsmParser> Y(TheX86_64Target);
 }
 
 #define GET_REGISTER_MATCHER
 #define GET_MATCHER_IMPLEMENTATION
 #define GET_SUBTARGET_FEATURE_NAME
 #include "X86GenAsmMatcher.inc"

lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/ELF.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MachO.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
+// Long nop related feature bits.
+const struct LongNopDesc {
+  unsigned Bit;
+  StringRef Name;
+} LongNopFeatures[0] = {};
+
 static unsigned getFixupKindLog2Size(unsigned Kind) {
   switch (Kind) {
   default:
     llvm_unreachable("invalid fixup kind!");
   case FK_PCRel_1:
   case FK_SecRel_1:
   case FK_Data_1:
     return 0;

 class X86ELFObjectWriter : public MCELFObjectTargetWriter {
 public:
   X86ELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine,
                      bool HasRelocationAddend, bool foobar)
     : MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, HasRelocationAddend) {}
 };
 
 class X86AsmBackend : public MCAsmBackend {
-  const StringRef CPU;
-  bool HasNopl;
-  const uint64_t MaxNopLength;
-public:
-  X86AsmBackend(const Target &T, StringRef CPU)
-      : MCAsmBackend(), CPU(CPU),
-        MaxNopLength((CPU == "slm" || CPU == "lakemont") ? 7 : 15) {
-    HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" &&
-              CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" &&
-              CPU != "i686" && CPU != "k6" && CPU != "k6-2" && CPU != "k6-3" &&
-              CPU != "geode" && CPU != "winchip-c6" && CPU != "winchip2" &&
-              CPU != "c3" && CPU != "c3-2";
-  }
+public:
+  X86AsmBackend(const Target &T) : MCAsmBackend() {}
 
   unsigned getNumFixupKinds() const override {
     return X86::NumTargetFixupKinds;
   }
 
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
     const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
         {"reloc_riprel_4byte", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
public:
 
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override;
 
   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
                         MCInst &Res) const override;
 
-  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+  bool writeNopData(uint64_t Count, const MCSubtargetInfo &STI,
+                    MCObjectWriter *OW) const override;
+
+  SmallVector<std::string, 1> getNopPrefs(const MCSubtargetInfo &STI) const {
+    SmallVector<std::string, 1> Prefs;
+
+    // Emit ".arch" directive only for valid CPUs.
+    if (!STI.isCPUStringValid(STI.getCPU()))
+      return Prefs;
+
+    // Emit ".arch cpu".
+    Prefs.push_back(STI.getCPU().str());
+
+    // Emit ".arch .[no]feature" if some of the long nop related features were
+    // explicitly changed from the default values.
+    MCSubtargetInfo DefaultSTI = MCSubtargetInfo(STI);
+    DefaultSTI.setDefaultFeatures(STI.getCPU(), "");
+    for (auto Desc : LongNopFeatures) {
+      bool Enabled = STI.getFeatureBits()[Desc.Bit];
+      if (DefaultSTI.getFeatureBits()[Desc.Bit] != Enabled)
+        Prefs.push_back((Enabled ? "." : ".no") + Desc.Name.str());
+    }
+
+    return Prefs;
+  }
 };
 } // end anonymous namespace
 
 static unsigned getRelaxedOpcodeBranch(const MCInst &Inst, bool is16BitMode) {
   unsigned Op = Inst.getOpcode();
   switch (Op) {
   default:
     return Op;
void X86AsmBackend::relaxInstruction(const MCInst &Inst,
 
   Res = Inst;
   Res.setOpcode(RelaxedOp);
 }
 
 /// \brief Write a sequence of optimal nops to the output, covering \p Count
 /// bytes.
 /// \return - true on success, false on failure
-bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
+bool X86AsmBackend::writeNopData(uint64_t Count, const MCSubtargetInfo &STI,
+                                 MCObjectWriter *OW) const {
+  const StringRef CPU = STI.getCPU();
+  const bool HasNopl =
+      CPU != "generic" && CPU != "i386" && CPU != "i486" && CPU != "i586" &&
+      CPU != "pentium" && CPU != "pentium-mmx" && CPU != "i686" &&
+      CPU != "k6" && CPU != "k6-2" && CPU != "k6-3" && CPU != "geode" &&
+      CPU != "winchip-c6" && CPU != "winchip2" && CPU != "c3" && CPU != "c3-2";
+  const uint64_t MaxNopLength = (CPU == "slm" || CPU == "lakemont") ? 7 : 15;
+
   static const uint8_t Nops[10][10] = {
       // nop
       {0x90},
       // xchg %ax,%ax
       {0x66, 0x90},
       // nopl (%[re]ax)
       {0x0f, 0x1f, 0x00},
       // nopl 0(%[re]ax)
       {0x0f, 0x1f, 0x40, 0x00},
       // nopl 0(%[re]ax,%[re]ax,1)
       {0x0f, 0x1f, 0x44, 0x00, 0x00},
       // nopw 0(%[re]ax,%[re]ax,1)
       {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
       // nopl 0L(%[re]ax)
       {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
       // nopl 0L(%[re]ax,%[re]ax,1)
       {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
       // nopw 0L(%[re]ax,%[re]ax,1)
       {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
       // nopw %cs:0L(%[re]ax,%[re]ax,1)
       {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
   };
 
   // This CPU doesn't support long nops. If needed add more.
   // FIXME: Can we get this from the subtarget somehow?
   // FIXME: We could generated something better than plain 0x90.
   if (!HasNopl) {
     for (uint64_t i = 0; i < Count; ++i)
       OW->write8(0x90);

 
 /* *** */
 
 namespace {
 
 class ELFX86AsmBackend : public X86AsmBackend {
 public:
   uint8_t OSABI;
-  ELFX86AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
-      : X86AsmBackend(T, CPU), OSABI(OSABI) {}
+  ELFX86AsmBackend(const Target &T, uint8_t OSABI)
+      : X86AsmBackend(T), OSABI(OSABI) {}
 };
 
 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
 public:
-  ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
-    : ELFX86AsmBackend(T, OSABI, CPU) {}
+  ELFX86_32AsmBackend(const Target &T, uint8_t OSABI)
+      : ELFX86AsmBackend(T, OSABI) {}
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, ELF::EM_386);
   }
 };
 
 class ELFX86_X32AsmBackend : public ELFX86AsmBackend {
 public:
-  ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
-      : ELFX86AsmBackend(T, OSABI, CPU) {}
+  ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI)
+      : ELFX86AsmBackend(T, OSABI) {}
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI,
                                     ELF::EM_X86_64);
   }
 };
 
 class ELFX86_IAMCUAsmBackend : public ELFX86AsmBackend {
 public:
-  ELFX86_IAMCUAsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
-      : ELFX86AsmBackend(T, OSABI, CPU) {}
+  ELFX86_IAMCUAsmBackend(const Target &T, uint8_t OSABI)
+      : ELFX86AsmBackend(T, OSABI) {}
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI,
                                     ELF::EM_IAMCU);
   }
 };
 
 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
 public:
-  ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
-    : ELFX86AsmBackend(T, OSABI, CPU) {}
+  ELFX86_64AsmBackend(const Target &T, uint8_t OSABI)
+      : ELFX86AsmBackend(T, OSABI) {}
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
-    return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, ELF::EM_X86_64);
+    return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI,
+                                    ELF::EM_X86_64);
   }
 };
 
 class WindowsX86AsmBackend : public X86AsmBackend {
   bool Is64Bit;
 
 public:
-  WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU)
-    : X86AsmBackend(T, CPU)
-    , Is64Bit(is64Bit) {
-  }
+  WindowsX86AsmBackend(const Target &T, bool is64Bit)
+      : X86AsmBackend(T), Is64Bit(is64Bit) {}
 
   Optional<MCFixupKind> getFixupKind(StringRef Name) const override {
     return StringSwitch<Optional<MCFixupKind>>(Name)
         .Case("dir32", FK_Data_4)
         .Case("secrel32", FK_SecRel_4)
         .Case("secidx", FK_SecRel_2)
         .Default(MCAsmBackend::getFixupKind(Name));
   }
uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned RegCount) const {
     }
 
     assert((permutationEncoding & 0x3FF) == permutationEncoding &&
            "Invalid compact register encoding!");
     return permutationEncoding;
   }
 
 public:
-  DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU,
-                      bool Is64Bit)
-    : X86AsmBackend(T, CPU), MRI(MRI), Is64Bit(Is64Bit) {
+  DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, bool Is64Bit)
+      : X86AsmBackend(T), MRI(MRI), Is64Bit(Is64Bit) {
     memset(SavedRegs, 0, sizeof(SavedRegs));
     OffsetSize = Is64Bit ? 8 : 4;
     MoveInstrSize = Is64Bit ? 3 : 2;
     StackDivide = Is64Bit ? 8 : 4;
   }
 };
 
 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
 public:
-  DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                         StringRef CPU)
-      : DarwinX86AsmBackend(T, MRI, CPU, false) {}
+  DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI)
+      : DarwinX86AsmBackend(T, MRI, false) {}
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
                                      MachO::CPU_TYPE_I386,
                                      MachO::CPU_SUBTYPE_I386_ALL);
   }
 
   /// \brief Generate the compact unwind encoding for the CFI instructions.
   uint32_t generateCompactUnwindEncoding(
-                             ArrayRef<MCCFIInstruction> Instrs) const override {
     return generateCompactUnwindEncodingImpl(Instrs);
   }
 };
 
 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
   const MachO::CPUSubTypeX86 Subtype;
+
 public:
   DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                         StringRef CPU, MachO::CPUSubTypeX86 st)
-      : DarwinX86AsmBackend(T, MRI, CPU, true), Subtype(st) {}
+                         MachO::CPUSubTypeX86 st)
+      : DarwinX86AsmBackend(T, MRI, true), Subtype(st) {}
 
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
                                      MachO::CPU_TYPE_X86_64, Subtype);
   }
 
   /// \brief Generate the compact unwind encoding for the CFI instructions.
   uint32_t generateCompactUnwindEncoding(
-                             ArrayRef<MCCFIInstruction> Instrs) const override {
     return generateCompactUnwindEncodingImpl(Instrs);
   }
 };
 
 } // end anonymous namespace
 
 MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
                                            const MCRegisterInfo &MRI,
                                            const Triple &TheTriple,
                                            StringRef CPU,
                                            const MCTargetOptions &Options) {
   if (TheTriple.isOSBinFormatMachO())
-    return new DarwinX86_32AsmBackend(T, MRI, CPU);
+    return new DarwinX86_32AsmBackend(T, MRI);
 
   if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF())
-    return new WindowsX86AsmBackend(T, false, CPU);
+    return new WindowsX86AsmBackend(T, false);
 
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
 
   if (TheTriple.isOSIAMCU())
-    return new ELFX86_IAMCUAsmBackend(T, OSABI, CPU);
+    return new ELFX86_IAMCUAsmBackend(T, OSABI);
 
-  return new ELFX86_32AsmBackend(T, OSABI, CPU);
+  return new ELFX86_32AsmBackend(T, OSABI);
 }
 
 MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
                                            const MCRegisterInfo &MRI,
                                            const Triple &TheTriple,
                                            StringRef CPU,
                                            const MCTargetOptions &Options) {
   if (TheTriple.isOSBinFormatMachO()) {
     MachO::CPUSubTypeX86 CS =
         StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName())
             .Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H)
             .Default(MachO::CPU_SUBTYPE_X86_64_ALL);
-    return new DarwinX86_64AsmBackend(T, MRI, CPU, CS);
+    return new DarwinX86_64AsmBackend(T, MRI, CS);
   }
 
   if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF())
-    return new WindowsX86AsmBackend(T, true, CPU);
+    return new WindowsX86AsmBackend(T, true);
 
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
 
   if (TheTriple.getEnvironment() == Triple::GNUX32)
-    return new ELFX86_X32AsmBackend(T, OSABI, CPU);
-  return new ELFX86_64AsmBackend(T, OSABI, CPU);
+    return new ELFX86_X32AsmBackend(T, OSABI);
+  return new ELFX86_64AsmBackend(T, OSABI);
 }

test/CodeGen/X86/multiversioning-long-nops.ll

+; .ll -> .o
+; RUN: llc < %s -mtriple i386-unknown-linux -filetype=obj -o - \
+; RUN:  | llvm-objdump -d -no-show-raw-insn - \
+; RUN:  | FileCheck %s
+
+; .ll -> .s -> .o
+; RUN: llc < %s -mtriple i386-unknown-linux -asm-preserve-alignment -o %t
+; RUN: cat %t | FileCheck -check-prefix=ASM %s
+; RUN: llvm-mc < %t -triple i386-unknown-linux -filetype=obj -o - \
+; RUN:  | llvm-objdump -d -no-show-raw-insn - \
+; RUN:  | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
+target triple = "i386-unknown-linux-gnu"
+
+module asm "inc %eax"
+module asm ".p2align 3"
+module asm "inc %eax"
+
+; CHECK:  incl    %eax
+; CHECK:  nop
+; CHECK:  nop
+; CHECK:  nop
+; CHECK:  nop
+; CHECK:  nop
+; CHECK:  nop
+; CHECK:  nop
+; CHECK:  incl    %eax
+
+; ASM:    incl    %eax
+; ASM:    .arch   generic
+; ASM-NEXT:   .p2align        3, 0x90
+; ASM:    incl    %eax
+
+define void @test1() #0 {
+entry:
+  call void asm sideeffect "inc %eax", "~{dirflag},~{fpsr},~{flags}"()
+  call void asm sideeffect ".p2align 5", "~{dirflag},~{fpsr},~{flags}"()
+  call void asm sideeffect "inc %eax", "~{dirflag},~{fpsr},~{flags}"()
+  ret void
+
+; CHECK-LABEL: test1:
+; CHECK:  incl    %eax
+; CHECK:  nopw    %cs:(%eax,%eax)
+; CHECK:  incl    %eax
+
+; ASM-LABEL: test1:
+; ASM:    incl    %eax
+; ASM:    .arch   pentium4
+; ASM-NEXT:   .p2align        5, 0x90
+; ASM:    incl    %eax
+}
+
+define void @test2() #1 {
+entry:
+  call void asm sideeffect "inc %eax", "~{dirflag},~{fpsr},~{flags}"()
+  call void asm sideeffect ".p2align 5", "~{dirflag},~{fpsr},~{flags}"()
+  call void asm sideeffect "inc %eax", "~{dirflag},~{fpsr},~{flags}"()
+  ret void
+
+; CHECK-LABEL: test2:
+; CHECK:  incl    %eax
+; CHECK:  nopw    %cs:(%eax,%eax)
+; CHECK:  incl    %eax
+
+; ASM-LABEL: test2:
+; ASM:    incl    %eax
+; ASM:    .arch   core-avx2
+; ASM-NEXT:   .p2align        5, 0x90
+; ASM:    incl    %eax
+}
+
+define void @test3() #2 {
+entry:
+  call void asm sideeffect "inc %eax", "~{dirflag},~{fpsr},~{flags}"()
+  call void asm sideeffect ".p2align 5", "~{dirflag},~{fpsr},~{flags}"()
+  call void asm sideeffect "inc %eax", "~{dirflag},~{fpsr},~{flags}"()
+  ret void
+
+; CHECK-LABEL: test3:
+; CHECK:  incl    %eax
+; CHECK:  nopl    (%eax)
+; CHECK:  nopl    (%eax)
+; CHECK:  incl    %eax
+
+; ASM-LABEL: test3:
+; ASM:    incl    %eax
+; ASM:    .arch   slm
+; ASM-NEXT:   .p2align        5, 0x90
+; ASM:    incl    %eax
+}
+
+attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="core-avx2" "target-features"="+aes,+avx,+avx2,+bmi,+bmi2,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+lzcnt,+mmx,+movbe,+pclmul,+popcnt,+rdrnd,+rtm,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="slm" "target-features"="+aes,+cx16,+fxsr,+mmx,+pclmul,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" }

test/MC/COFF/align-nops.s

-// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | llvm-readobj -s -sd | FileCheck %s
+// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 -mcpu=pentium4 %s | llvm-readobj -s -sd | FileCheck %s
 
 // Test that we get optimal nops in text
     .text
 f0:
     .long 0
     .align  8, 0x90
     .long 0
     .align  8

test/MC/ELF/align-nops.s

-// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck %s
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 %s -o - | llvm-readobj -s -sd | FileCheck %s
 
 // Test that we get optimal nops in text
     .text
 f0:
     .long 0
     .align  8, 0x00000090
     .long 0
     .align  8

test/MC/MachO/x86_32-optimal_nop.s

-// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o - | llvm-readobj -file-headers -s -sd -r -t -macho-segment -macho-dysymtab -macho-indirect-symbols | FileCheck %s
+// RUN: llvm-mc -triple i386-apple-darwin9 -mcpu=pentium4 %s -filetype=obj -o - | llvm-readobj -file-headers -s -sd -r -t -macho-segment -macho-dysymtab -macho-indirect-symbols | FileCheck %s
 
 # 1 byte nop test
         .align 4, 0 # start with 16 byte alignment filled with zeros
         ret
         # nop
         # 0x90
         .align 1, 0x90
         ret

test/MC/X86/AlignedBundling/different-sections.s

-# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \
+# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 %s -o - \
 # RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
-# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \
+# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 -mc-relax-all %s -o - \
 # RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
 
 # Test two different executable sections with bundling.
 
   .bundle_align_mode 3
   .section text1, "x"
 # CHECK: section text1
   imull $17, %ebx, %ebp

test/MC/X86/AlignedBundling/long-nop-pad.s

-# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \
+# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 %s -o - \
 # RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
-# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \
+# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 -mc-relax-all %s -o - \
 # RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
 
 # Test that long nops are generated for padding where possible.
 
   .text
 foo:
   .bundle_align_mode 5
 

test/MC/X86/AlignedBundling/misaligned-bundle-group.s

-# RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - \
+# RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -mcpu=pentium4 %s -o - \
 # RUN:   | llvm-objdump -disassemble -no-show-raw-insn - \
 # RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-OPT %s
-# RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -mc-relax-all %s -o - \
+# RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -mcpu=pentium4 -mc-relax-all %s -o - \
 # RUN:   | llvm-objdump -disassemble -no-show-raw-insn - \
 # RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-RELAX %s
 
         .text
 foo:
         .bundle_align_mode 5
         push    %ebp # 1 byte
         .align  16

test/MC/X86/AlignedBundling/misaligned-bundle.s

-# RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - \
+# RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -mcpu=pentium4 %s -o - \
 # RUN:   | llvm-objdump -disassemble -no-show-raw-insn - \
 # RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-OPT %s
-# RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -mc-relax-all %s -o - \
+# RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -mcpu=pentium4 -mc-relax-all %s -o - \
 # RUN:   | llvm-objdump -disassemble -no-show-raw-insn - \
 # RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-RELAX %s
 
         .text
 foo:
         .bundle_align_mode 5
         push    %ebp          # 1 byte
         .align  16

test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s

-# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \
+# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 %s -o - \
 # RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
-# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \
+# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 -mc-relax-all %s -o - \
 # RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
 
 # Test some variations of padding to the end of a bundle.
 
   .text
 foo:
   .bundle_align_mode 4
 

test/MC/X86/AlignedBundling/pad-bundle-groups.s

-# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \
+# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 %s -o - \
 # RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
-# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \
+# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 -mc-relax-all %s -o - \
 # RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
 
 # Test some variations of padding for bundle-locked groups.
 
   .text
 foo:
   .bundle_align_mode 4
 

test/MC/X86/AlignedBundling/relax-in-bundle-group.s

-# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \
+# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 %s -o - \
 # RUN:   | llvm-objdump -disassemble - | FileCheck %s
-# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \
+# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 -mc-relax-all %s -o - \
 # RUN:   | llvm-objdump -disassemble - | FileCheck %s
 
 # Test that instructions inside bundle-locked groups are relaxed even if their
 # fixup is short enough not to warrant relaxation on its own.
 
   .text
 foo:
   .bundle_align_mode 4

test/MC/X86/AlignedBundling/single-inst-bundling.s

-# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \
+# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 %s -o - \
 # RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck -check-prefix=CHECK -check-prefix=CHECK-OPT %s
-# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \
+# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 -mc-relax-all %s -o - \
 # RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck -check-prefix=CHECK -check-prefix=CHECK-RELAX %s
 
 # Test simple NOP insertion for single instructions.
 
   .text
 foo:
   # Will be bundle-aligning to 16 byte boundaries
   .bundle_align_mode 4

test/MC/X86/arch-directive.s

+# RUN: not llvm-mc -filetype=asm -triple x86_64-pc-linux-gnu %s 2>%t -o - | FileCheck %s
+# RUN: FileCheck < %t %s --check-prefix=CHECK-ERR
+
+# CHECK: .text
+.arch core-avx2
+# CHECK: .arch core-avx2
+.arch .avx512f
+# CHECK: .arch .avx512f
+.arch .noavx2
+# CHECK: .arch .noavx2
+
+addq  $1, %rax
+# CHECK: addq $1, %rax
+
+.arch i386
+# CHECK: .arch i386
+.arch .noavx
+# CHECK: .arch .noavx
+.arch .x87
+# CHECK: .arch .x87
+.arch .no64bit-mode
+# CHECK: .arch .no64bit-mode
+.arch .32bit-mode
+# CHECK: .arch .32bit-mode
+
+addq  $1, %rax
+# CHECK-NOT: addq $1, %rax
+# CHECK-ERR: error: register %rax is only available in 64-bit mode
+
+.arch fake-cpu
+# CHECK-NOT: .arch fake-cpu
+# CHECK-ERR: error: unrecognized CPU 'fake-cpu' in .arch directive
+.arch .fake-feature
+# CHECK-NOT: .arch .fake-feature
+# CHECK-ERR: error: unrecognized feature 'fake-feature' in .arch directive
+.arch .nofake-feature
+# CHECK-NOT: .arch .nofake-feature
+# CHECK-ERR: error: unrecognized feature 'fake-feature' in .arch directive
+
+.arch something unexpected
+# CHECK-NOT: .arch something unexpected
+# CHECK-ERR: error: unexpected number of arguments in .arch directive

test/MC/X86/x86_long_nop.s

-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-apple-darwin10.0 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-apple-darwin8 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=pentium4 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=core-avx2 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-apple-darwin10.0 -mcpu=k8 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-apple-darwin8 -mcpu=barcelona %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=slm %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP7 %s
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=lakemont %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP7 %s
 
 # Ensure alignment directives also emit sequences of 15-byte NOPs on processors
 # capable of using long NOPs.
 inc %eax
 .p2align 5
 inc %eax

test/MC/X86/x86_long_nop_arch.s

+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
+
+# Ensure .arch directive affects long nop emission.
+
+incl    %eax
+
+.arch   i386
+.p2align  4
+
+incl    %eax
+
+.arch   pentium4
+.p2align  4
+
+incl    %eax
+
+.arch   slm
+.p2align  4
+
+incl    %eax
+
+# CHECK:      0:    incl
+# CHECK-NEXT: 1:    nop
+# CHECK-NEXT: 2:    nop
+# CHECK-NEXT: 3:    nop
+# CHECK-NEXT: 4:    nop
+# CHECK-NEXT: 5:    nop
+# CHECK-NEXT: 6:    nop
+# CHECK-NEXT: 7:    nop
+# CHECK-NEXT: 8:    nop
+# CHECK-NEXT: 9:    nop
+# CHECK-NEXT: a:    nop
+# CHECK-NEXT: b:    nop
+# CHECK-NEXT: c:    nop
+# CHECK-NEXT: d:    nop
+# CHECK-NEXT: e:    nop
+# CHECK-NEXT: f:    nop
+# CHECK-NEXT: 10:   incl
+# CHECK-NEXT: 11:   nopw
+# CHECK-NEXT: 20:   incl
+# CHECK-NEXT: 21:   nopl
+# CHECK-NEXT: 28:   nopl
+# CHECK-NEXT: 2f:   nop
+# CHECK-NEXT: 30:   incl

tools/llvm-mc/llvm-mc.cpp

if (FileType == OFT_AssemblyFile) {
     MCAsmBackend *MAB = nullptr;
     if (ShowEncoding) {
       CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
       MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU, MCOptions);
     }
     auto FOut = llvm::make_unique<formatted_raw_ostream>(*OS);
     Str.reset(TheTarget->createAsmStreamer(
         Ctx, std::move(FOut), /*asmverbose*/ true,
-        /*useDwarfDirectory*/ true, IP, CE, MAB, ShowInst));
+        /*useDwarfDirectory*/ true, IP, CE, MAB, ShowInst, *STI));
 
   } else if (FileType == OFT_Null) {
     Str.reset(TheTarget->createNullStreamer(Ctx));
   } else {
     assert(FileType == OFT_ObjectFile && "Invalid file type!");
 
     // Don't waste memory on names of temp labels.
     Ctx.setUseNamesOnTempLabels(false);