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aturetsk (Andrey Turetskiy)
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Jul 6 2015, 6:03 AM (309 w, 4 d)

Recent Activity

Sep 23 2016

aturetsk added a comment to D23506: [RFC] Generate long nop instructions depending on function-specific subtarget info (version 2).

This is a new version of D21374 which takes into account the remark about .ll -> .s -> .o and .ll -> .o compile paths having different result.

Sep 23 2016, 12:21 PM
aturetsk abandoned D21374: [RFC] Generate long nop instructions depending on function-specific subtarget info.

New version in https://reviews.llvm.org/D23506

Sep 23 2016, 12:15 PM
aturetsk abandoned D17573: [X86] PR26554: Use not all set of alternative nops in 64 bit mode, but only those which are correct.

New version in https://reviews.llvm.org/D21374

Sep 23 2016, 12:15 PM
aturetsk abandoned D21066: Pass MCSubtargetInfo instead of CPU and Triple to createMCAsmBackend.

New version in https://reviews.llvm.org/D21374

Sep 23 2016, 12:14 PM

Sep 22 2016

aturetsk added a comment to D23506: [RFC] Generate long nop instructions depending on function-specific subtarget info (version 2).

Any comments?

Sep 22 2016, 1:48 PM

Sep 1 2016

aturetsk committed rL280402: [X86] Loosen memory folding requirements for cvtdq2pd and cvtps2pd instructions..
[X86] Loosen memory folding requirements for cvtdq2pd and cvtps2pd instructions.
Sep 1 2016, 11:58 AM
aturetsk closed D23919: [X86] Loosen memory folding requirements for cvtdq2pd and cvtps2pd instructions by committing rL280402: [X86] Loosen memory folding requirements for cvtdq2pd and cvtps2pd instructions..
Sep 1 2016, 11:58 AM

Aug 30 2016

aturetsk updated the diff for D23919: [X86] Loosen memory folding requirements for cvtdq2pd and cvtps2pd instructions.

Change -mcpu=slm with -mattr=+sse4.2.

Aug 30 2016, 8:17 AM

Aug 29 2016

aturetsk added a comment to D23919: [X86] Loosen memory folding requirements for cvtdq2pd and cvtps2pd instructions.

Hi Simon,

Aug 29 2016, 5:44 AM
aturetsk updated the diff for D23919: [X86] Loosen memory folding requirements for cvtdq2pd and cvtps2pd instructions.

Improve the test.

Aug 29 2016, 5:43 AM

Aug 26 2016

aturetsk retitled D23919: [X86] Loosen memory folding requirements for cvtdq2pd and cvtps2pd instructions from to [X86] Loosen memory folding requirements for cvtdq2pd and cvtps2pd instructions.
Aug 26 2016, 5:22 AM

Aug 15 2016

aturetsk updated subscribers of D23506: [RFC] Generate long nop instructions depending on function-specific subtarget info (version 2).
Aug 15 2016, 6:56 AM
aturetsk added inline comments to D23506: [RFC] Generate long nop instructions depending on function-specific subtarget info (version 2).
Aug 15 2016, 6:14 AM
aturetsk retitled D23506: [RFC] Generate long nop instructions depending on function-specific subtarget info (version 2) from to [RFC] Generate long nop instructions depending on function-specific subtarget info (version 2).
Aug 15 2016, 5:59 AM

Jul 20 2016

aturetsk added a comment to D18898: [Loop Rotation] Make default max rotation header size threshold dependent on target CPU.

OK.

Jul 20 2016, 4:57 AM

Jul 18 2016

aturetsk added a comment to D18898: [Loop Rotation] Make default max rotation header size threshold dependent on target CPU.

Ping.

Jul 18 2016, 8:33 AM

Jul 7 2016

aturetsk added a comment to D18898: [Loop Rotation] Make default max rotation header size threshold dependent on target CPU.

Ping.

Jul 7 2016, 6:16 AM
aturetsk added a comment to D21374: [RFC] Generate long nop instructions depending on function-specific subtarget info.

James, thanks for pointing this directive out! I'll look at it closely.

Jul 7 2016, 6:15 AM

Jul 4 2016

aturetsk added a comment to D21374: [RFC] Generate long nop instructions depending on function-specific subtarget info.

Can we use llvm.ident metadata which is stored and loaded from an assembly file to keep function-specific subtarget information across assembly?
For example we could store "llvm/multiversioning/symbol_name/cpu_name/feature_bits_hex" string in ident metadata for functions which subtarget info differs from module's info in AsmPrinter::FinalizeMachineFunction.

Jul 4 2016, 6:57 AM

Jun 29 2016

aturetsk committed rL274119: Use ArgList::hasFlag to check if -miamcu/-mno-iamcu is passed. NFC..
Use ArgList::hasFlag to check if -miamcu/-mno-iamcu is passed. NFC.
Jun 29 2016, 4:04 AM
aturetsk closed D21641: Use ArgList::hasFlag to check if -miamcu/-mno-iamcu is passed. NFC. by committing rL274119: Use ArgList::hasFlag to check if -miamcu/-mno-iamcu is passed. NFC..
Jun 29 2016, 4:04 AM

Jun 23 2016

aturetsk added a comment to D21641: Use ArgList::hasFlag to check if -miamcu/-mno-iamcu is passed. NFC..

Hi Bruno,
As you suggested I changed -miamcu/-mno-iamcu handling code to use hasFlag.

Jun 23 2016, 4:21 AM
aturetsk retitled D21641: Use ArgList::hasFlag to check if -miamcu/-mno-iamcu is passed. NFC. from to Use ArgList::hasFlag to check if -miamcu/-mno-iamcu is passed. NFC..
Jun 23 2016, 4:19 AM

Jun 20 2016

aturetsk committed rL273147: [X86] Add -mno-iamcu option..
[X86] Add -mno-iamcu option.
Jun 20 2016, 3:38 AM
aturetsk closed D21469: Add -mno-iamcu option by committing rL273147: [X86] Add -mno-iamcu option..
Jun 20 2016, 3:38 AM

Jun 17 2016

aturetsk retitled D21469: Add -mno-iamcu option from to Add -mno-iamcu option.
Jun 17 2016, 6:23 AM
aturetsk updated the diff for D18898: [Loop Rotation] Make default max rotation header size threshold dependent on target CPU.

Rebased.

Jun 17 2016, 6:14 AM

Jun 16 2016

aturetsk committed rL272887: Patch "Compilation for Intel MCU (Part 2/3)" caused the clang-x64-ninja-win7.
Patch "Compilation for Intel MCU (Part 2/3)" caused the clang-x64-ninja-win7
Jun 16 2016, 5:33 AM
aturetsk committed rL272885: Compilation for Intel MCU (Part 3/3).
Compilation for Intel MCU (Part 3/3)
Jun 16 2016, 3:56 AM
aturetsk closed D20675: Compilation for Intel MCU (Part 3/3) by committing rL272885: Compilation for Intel MCU (Part 3/3).
Jun 16 2016, 3:56 AM
aturetsk committed rL272883: Compilation for Intel MCU (Part 2/3).
Compilation for Intel MCU (Part 2/3)
Jun 16 2016, 3:43 AM
aturetsk closed D19274: Compilation for Intel MCU (Part 2/3) by committing rL272883: Compilation for Intel MCU (Part 2/3).
Jun 16 2016, 3:43 AM

Jun 15 2016

aturetsk added inline comments to D19274: Compilation for Intel MCU (Part 2/3).
Jun 15 2016, 7:03 AM
aturetsk added a comment to D18898: [Loop Rotation] Make default max rotation header size threshold dependent on target CPU.

Ping.

Jun 15 2016, 7:01 AM
aturetsk updated D21374: [RFC] Generate long nop instructions depending on function-specific subtarget info.
Jun 15 2016, 5:42 AM
aturetsk added a comment to D21374: [RFC] Generate long nop instructions depending on function-specific subtarget info.

I've been thinking about a way to generate function-specific long nop instructions and here is what I came up with:

  1. Function-specific subtarget info seems to be available only during machine function passes. However I don't think we can start generating long nops somewhere there, so during the pass which creates MCFragments (AsmPrinter) we store the info in the fragments which hold the function.
  2. We generate long nops in MCAssembler as we've been doing so far, just additionally pass the function subtarget info to the writeNopData function.
  3. Unfortunately I didn't find a better way to pass a module subtarget info to the writeNopData other that in the rejected http://reviews.llvm.org/D17573 (so to work correctly this patch is applied on top of it). Eric suggested to move writeNopData from AsmBackend somewhere else, but I didn't find a better place with module subtarget info available there. Also, I didn't find a way to reach module subtarget info from MCAssembler. I'd appreciate any advise on how to do that any other way than http://reviews.llvm.org/D17573.
Jun 15 2016, 5:42 AM
aturetsk retitled D21374: [RFC] Generate long nop instructions depending on function-specific subtarget info from to [RFC] Generate long nop instructions depending on function-specific subtarget info.
Jun 15 2016, 5:20 AM

Jun 7 2016

aturetsk committed rL272019: Quick fix for the test from rL272014 "[LAA] Improve non-wrapping pointer.
Quick fix for the test from rL272014 "[LAA] Improve non-wrapping pointer
Jun 7 2016, 8:59 AM
aturetsk committed rL272014: [LAA] Improve non-wrapping pointer detection by handling loop-invariant case..
[LAA] Improve non-wrapping pointer detection by handling loop-invariant case.
Jun 7 2016, 8:02 AM
aturetsk closed D17268: [LAA] Function 'isStridedPtr' returns additional result “Loop *Lp” via function argument and add appropriate checks out of the 'isStridedPtr'. by committing rL272014: [LAA] Improve non-wrapping pointer detection by handling loop-invariant case..
Jun 7 2016, 8:02 AM
aturetsk added a comment to D17573: [X86] PR26554: Use not all set of alternative nops in 64 bit mode, but only those which are correct.

I modified the patch as Simon suggested: AsmBackend now gets Triple and CPU from MCSubtargetInfo.
Note that the CPU from MCSubtargetInfo is a bit different from the CPU we used to pass as argument: if -mcpu isn't specified the CPU used to be "", but now it's "generic". I think that this is actually how it should be, however the change in behavior required to fix a couple of tests by specifying -mcpu option (the tests were expecting long nop generation but "generic" doesn't support them).

Jun 7 2016, 4:59 AM
aturetsk retitled D21066: Pass MCSubtargetInfo instead of CPU and Triple to createMCAsmBackend from to Pass MCSubtargetInfo instead of CPU and Triple to createMCAsmBackend.
Jun 7 2016, 4:59 AM
aturetsk updated the diff for D17573: [X86] PR26554: Use not all set of alternative nops in 64 bit mode, but only those which are correct.

Get Triple and CPU from STI in AsmBackend.

Jun 7 2016, 4:39 AM

Jun 3 2016

aturetsk retitled D17573: [X86] PR26554: Use not all set of alternative nops in 64 bit mode, but only those which are correct from [X86] PR26554: Enable using of true long nops for x86-64 for every CPU to [X86] PR26554: Use not all set of alternative nops in 64 bit mode, but only those which are correct.
Jun 3 2016, 10:25 AM
aturetsk added a comment to D17573: [X86] PR26554: Use not all set of alternative nops in 64 bit mode, but only those which are correct.

I made AsmBackend to use subtarget features to determine whether true long nops are supported or not, as suggested.
Yet to fix the PR we still need additional code, see lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp : 61.
The most part of the patch is adding MCSubtargetInfo as argument for AsmBackend creator functions for all targets, that's why the patch is so big. But I didn't find any way to do it better.

Jun 3 2016, 10:22 AM
aturetsk updated the diff for D17573: [X86] PR26554: Use not all set of alternative nops in 64 bit mode, but only those which are correct.

Use subtarget features to determine whether true long nops are supported or not.

Jun 3 2016, 10:11 AM

May 26 2016

aturetsk added inline comments to D19274: Compilation for Intel MCU (Part 2/3).
May 26 2016, 11:38 AM
aturetsk added inline comments to D17573: [X86] PR26554: Use not all set of alternative nops in 64 bit mode, but only those which are correct.
May 26 2016, 7:15 AM
aturetsk retitled D20675: Compilation for Intel MCU (Part 3/3) from to Compilation for Intel MCU (Part 3/3).
May 26 2016, 5:31 AM
aturetsk added inline comments to D19274: Compilation for Intel MCU (Part 2/3).
May 26 2016, 5:23 AM

May 25 2016

aturetsk added a comment to D18898: [Loop Rotation] Make default max rotation header size threshold dependent on target CPU.

Ping.

May 25 2016, 7:11 AM
aturetsk added a comment to D17573: [X86] PR26554: Use not all set of alternative nops in 64 bit mode, but only those which are correct.

Ping.

May 25 2016, 7:10 AM
aturetsk added a comment to D19274: Compilation for Intel MCU (Part 2/3).

Ping.

May 25 2016, 7:08 AM

May 19 2016

aturetsk committed rL270036: [X86] Enable RRL part of the LEA optimization pass for -O2..
[X86] Enable RRL part of the LEA optimization pass for -O2.
May 19 2016, 3:28 AM
aturetsk closed D19659: [X86] Enable RRL part of the LEA optimization pass for -O2 by committing rL270036: [X86] Enable RRL part of the LEA optimization pass for -O2..
May 19 2016, 3:24 AM

May 18 2016

aturetsk added inline comments to D19659: [X86] Enable RRL part of the LEA optimization pass for -O2.
May 18 2016, 5:14 AM
aturetsk updated the diff for D19659: [X86] Enable RRL part of the LEA optimization pass for -O2.

Improve the test.

May 18 2016, 5:13 AM

May 17 2016

aturetsk added inline comments to D19659: [X86] Enable RRL part of the LEA optimization pass for -O2.
May 17 2016, 2:05 AM
aturetsk updated the diff for D19659: [X86] Enable RRL part of the LEA optimization pass for -O2.

Add a test for the case when the LEA pass is disabled. (Take #2).

May 17 2016, 1:53 AM
aturetsk updated the diff for D19659: [X86] Enable RRL part of the LEA optimization pass for -O2.

Add a test for the case when the LEA pass is disabled.

May 17 2016, 1:25 AM

May 16 2016

aturetsk added a comment to D19659: [X86] Enable RRL part of the LEA optimization pass for -O2.

Hi Quentin,

May 16 2016, 6:16 AM

May 12 2016

aturetsk added a comment to D17573: [X86] PR26554: Use not all set of alternative nops in 64 bit mode, but only those which are correct.

Hi Bruno,

May 12 2016, 6:54 AM
aturetsk added a comment to D19274: Compilation for Intel MCU (Part 2/3).

Hi Bruno,
Thanks for the review.

May 12 2016, 4:30 AM
aturetsk updated the diff for D19274: Compilation for Intel MCU (Part 2/3).

Fix the remarks.

May 12 2016, 4:23 AM
aturetsk added a comment to D18898: [Loop Rotation] Make default max rotation header size threshold dependent on target CPU.

All formatting weirdnesses you mentioned are the product of clang-format.
Unless I missed something all the changes were clang-formatted.

May 12 2016, 3:27 AM

May 11 2016

aturetsk added reviewers for D17573: [X86] PR26554: Use not all set of alternative nops in 64 bit mode, but only those which are correct: bruno, echristo.
May 11 2016, 7:13 AM
aturetsk added a comment to D19274: Compilation for Intel MCU (Part 2/3).

Ping.

May 11 2016, 7:06 AM
aturetsk updated the diff for D18898: [Loop Rotation] Make default max rotation header size threshold dependent on target CPU.
  1. Rebased to the newer trunk.
  2. The loop rotation pass has been ported to the new pass manager. Extend this patch for the new version of the pass as well.
  3. Use approach #3 (with bool variable keeping information about the createLoopRotatePass argument).
May 11 2016, 7:04 AM

May 5 2016

aturetsk added a comment to D18898: [Loop Rotation] Make default max rotation header size threshold dependent on target CPU.

Hi Eric,
Thanks for the review.

May 5 2016, 5:55 AM
aturetsk updated the diff for D18898: [Loop Rotation] Make default max rotation header size threshold dependent on target CPU.

Added a comment in the X86TTIImpl::getLoopRotationDefaultThreshold.

May 5 2016, 5:34 AM

May 4 2016

aturetsk added a comment to D19659: [X86] Enable RRL part of the LEA optimization pass for -O2.

Note that the generated test is really LEA-specific, the majority of machine instructions gets modified by the pass. That's why the LEA pass takes ~25% of total compile time in this test.

May 4 2016, 8:57 AM
aturetsk added a comment to D19659: [X86] Enable RRL part of the LEA optimization pass for -O2.

The RRL part of the LEA pass takes a sane amount of compile time.
Here are the measurements.

May 4 2016, 8:43 AM
aturetsk added a comment to D19658: [X86] Add -m[no-]x87 and -m[no-]80387 options to control FeatureX87.

Hi,
Thanks for the review.

May 4 2016, 4:36 AM
aturetsk committed rL268489: [X86] Add -m[no-]x87 and -m[no-]80387 options to control FeatureX87..
[X86] Add -m[no-]x87 and -m[no-]80387 options to control FeatureX87.
May 4 2016, 4:34 AM
aturetsk committed rL268488: Add missing -mno-cx16 driver option..
Add missing -mno-cx16 driver option.
May 4 2016, 4:25 AM
aturetsk committed rL268487: Add a test for driver options from m_x86_Features_Group..
Add a test for driver options from m_x86_Features_Group.
May 4 2016, 4:16 AM
aturetsk closed D19658: [X86] Add -m[no-]x87 and -m[no-]80387 options to control FeatureX87 by committing rL268487: Add a test for driver options from m_x86_Features_Group..
May 4 2016, 4:16 AM

Apr 29 2016

aturetsk added a comment to D19659: [X86] Enable RRL part of the LEA optimization pass for -O2.

Hi Bruno,
I tried Geekbench, Coremark-Pro, Spec2000 and Spec2006.

Apr 29 2016, 5:21 AM
aturetsk added a comment to D19658: [X86] Add -m[no-]x87 and -m[no-]80387 options to control FeatureX87.

Hi,
Thanks for the review.
All m_x86_Features_Group options are handled in function handleTargetFeaturesGroup from lib/Driver/Tools.cpp, so there is no additional code needed.
There was no test for this, so I added a new one trying to cover all options from m_x86_Features_Group.

Apr 29 2016, 5:19 AM
aturetsk updated the diff for D19658: [X86] Add -m[no-]x87 and -m[no-]80387 options to control FeatureX87.

Add a missing option and a test.

Apr 29 2016, 5:16 AM
aturetsk added a comment to D18898: [Loop Rotation] Make default max rotation header size threshold dependent on target CPU.

Hi,
Thanks for the review. I used 'Optional<unsigned>' as suggested.

Apr 29 2016, 5:14 AM
aturetsk updated the diff for D18898: [Loop Rotation] Make default max rotation header size threshold dependent on target CPU.

Use Optional<unsigned>.

Apr 29 2016, 5:13 AM

Apr 28 2016

aturetsk updated D19659: [X86] Enable RRL part of the LEA optimization pass for -O2.
Apr 28 2016, 7:17 AM
aturetsk retitled D19659: [X86] Enable RRL part of the LEA optimization pass for -O2 from to [X86] Enable RRL part of the LEA optimization pass for -O2.
Apr 28 2016, 7:11 AM
aturetsk retitled D19658: [X86] Add -m[no-]x87 and -m[no-]80387 options to control FeatureX87 from to [X86] Add -m[no-]x87 and -m[no-]80387 options to control FeatureX87.
Apr 28 2016, 6:59 AM

Apr 27 2016

aturetsk added a comment to D17573: [X86] PR26554: Use not all set of alternative nops in 64 bit mode, but only those which are correct.

Ping.

Apr 27 2016, 3:58 AM
aturetsk added a comment to D18898: [Loop Rotation] Make default max rotation header size threshold dependent on target CPU.

Ping.

Apr 27 2016, 3:58 AM

Apr 26 2016

aturetsk added a comment to D19409: [X86] Handle MachineBasicBlock as a memory displacement operand in the LEA optimization pass.

Thanks for the review.
You are right, the REQUIRES line is redundant for tests to pass, so I removed them.

Apr 26 2016, 5:25 AM
aturetsk committed rL267551: [X86] PR27502: Fix the LEA optimization pass..
[X86] PR27502: Fix the LEA optimization pass.
Apr 26 2016, 5:24 AM
aturetsk closed D19409: [X86] Handle MachineBasicBlock as a memory displacement operand in the LEA optimization pass by committing rL267551: [X86] PR27502: Fix the LEA optimization pass..
Apr 26 2016, 5:24 AM

Apr 25 2016

aturetsk updated the diff for D19409: [X86] Handle MachineBasicBlock as a memory displacement operand in the LEA optimization pass.

Mention the PR# in the test.

Apr 25 2016, 4:43 AM
aturetsk updated subscribers of D19409: [X86] Handle MachineBasicBlock as a memory displacement operand in the LEA optimization pass.

The corresponding bug was filed yesterday (https://llvm.org/bugs/show_bug.cgi?id=27502).

Apr 25 2016, 3:59 AM

Apr 22 2016

aturetsk added inline comments to D19409: [X86] Handle MachineBasicBlock as a memory displacement operand in the LEA optimization pass.
Apr 22 2016, 5:16 AM
aturetsk retitled D19409: [X86] Handle MachineBasicBlock as a memory displacement operand in the LEA optimization pass from to [X86] Handle MachineBasicBlock as a memory displacement operand in the LEA optimization pass.
Apr 22 2016, 5:15 AM

Apr 21 2016

aturetsk committed rL266972: Compilation for Intel MCU (Part 1/3).
Compilation for Intel MCU (Part 1/3)
Apr 21 2016, 3:22 AM

Apr 20 2016

aturetsk added a comment to D19274: Compilation for Intel MCU (Part 2/3).

Hi Mandeep,
Thanks for the review.

Apr 20 2016, 4:39 AM
aturetsk updated the diff for D19274: Compilation for Intel MCU (Part 2/3).

Fixed the remarks.

Apr 20 2016, 4:27 AM

Apr 19 2016

aturetsk retitled D19274: Compilation for Intel MCU (Part 2/3) from to Compilation for Intel MCU (Part 2/3).
Apr 19 2016, 10:51 AM
aturetsk committed rL266753: Revert r266747 (Compilation for Intel MCU (Part 1/3)) since it breaks a few….
Revert r266747 (Compilation for Intel MCU (Part 1/3)) since it breaks a few…
Apr 19 2016, 9:31 AM
aturetsk committed rL266747: Compilation for Intel MCU (Part 1/3).
Compilation for Intel MCU (Part 1/3)
Apr 19 2016, 8:56 AM