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Differential D159530

[RISCV] Add tests for memory constraint A
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Authored by wangpc on Mon, Sep 18, 10:25 PM.

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asb
jrtc27
craig.topper
kito-cheng
luismarques
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rG61d819dd52f8: [RISCV] Add tests for memory constraint A
Summary

We should not optimize it in D158062. This adds the test coverage.

And unneeded attributes nonnull and inbounds are removed.

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Event Timeline

wangpc created this revision.Mon, Sep 18, 10:25 PM
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Herald added subscribers: jobnoorman, luke, sunshaoce and 24 others. · View Herald Transcript
wangpc requested review of this revision.Mon, Sep 18, 10:25 PM
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wangpc added a child revision: D158062: [RISCV] Teach RISCVMergeBaseOffset to handle inline asm.Mon, Sep 18, 10:25 PM
Harbormaster completed remote builds in B257375: Diff 556996.Mon, Sep 18, 10:39 PM
asb accepted this revision.Tue, Sep 19, 4:19 AM

LGTM, one minor nit. You're consistent with other tests in this file with using nonnull and inbounds, but I'd typically drop any attributes that don't alter the output of the test.

This revision is now accepted and ready to land.Tue, Sep 19, 4:19 AM
wangpc updated this revision to Diff 557031.Tue, Sep 19, 4:49 AM

Remove nonnull and inbounds.

wangpc edited the summary of this revision. (Show Details)Tue, Sep 19, 4:49 AM
This revision was landed with ongoing or failed builds.Tue, Sep 19, 4:56 AM
Closed by commit rG61d819dd52f8: [RISCV] Add tests for memory constraint A (authored by wangpc). · Explain Why
This revision was automatically updated to reflect the committed changes.
wangpc added a commit: rG61d819dd52f8: [RISCV] Add tests for memory constraint A.
Harbormaster completed remote builds in B257402: Diff 557031.Tue, Sep 19, 5:18 AM
jrtc27 added a comment.Tue, Sep 19, 7:55 AM

Read the banner at the top of every Phabricator page. New revisions should be submitted via GitHub.

asb added a comment.Tue, Sep 19, 7:59 AM
In D159530#4648110, @jrtc27 wrote:

Read the banner at the top of every Phabricator page. New revisions should be submitted via GitHub.

Yes, but I think this was posted here rather than as a PR as it's a pre-requisite for a patch that had already started review on Phabricator. So it seems reasonable enough in this instance.

jrtc27 added a comment.Tue, Sep 19, 7:47 PM
In D159530#4648115, @asb wrote:
In D159530#4648110, @jrtc27 wrote:

Read the banner at the top of every Phabricator page. New revisions should be submitted via GitHub.

Yes, but I think this was posted here rather than as a PR as it's a pre-requisite for a patch that had already started review on Phabricator. So it seems reasonable enough in this instance.

Oh, I thought I had checked for the Stack button as I guessed that might be the case, but seems I managed to miss it. My bad.

Revision Contents
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llvm/
test/
CodeGen/
RISCV/
714 lines

Diff 557032

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llvm/test/CodeGen/RISCV/inline-asm-mem-constraint.ll

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