[RISCV] Fix `vmsge{u}.vx` lowering by not adding the mask operand if `vd == v0`

[imkiva]

Summary

According to riscv-v-spec-1.0.pdf page 52:

masked va >= x, vd == v0
   pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
   expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt

The resulting vmslt{u}.vx is not masked. This patch fixes the logic in RISCVAsmParser, to make the behavior consistent with the case "masked va >= x, any vd" in the later part of the code, where no mask op is added.

[imkiva]

Reformat some comments so they look nicer.

[craig.topper]

LGTM

Does binutils have the same issue? https://godbolt.org/z/zMf6xqeo7

[imkiva]

In D158392#4605627, @craig.topper wrote:

Does binutils have the same issue? https://godbolt.org/z/zMf6xqeo7

Probably yes.

But I still think the mask operand should be transitive as lowering a masked instruction to an unmasked one may break certain constraints (?) and look wired 😕. I will post further information here when I know more.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

if (Inst.getNumOperands() == 3) {
     assert(Inst.getOperand(0).getReg() == RISCV::V0 &&
            "The destination register should be V0.");
     assert(Inst.getOperand(1).getReg() != RISCV::V0 &&
            "The temporary vector register should not be V0.");
     emitToStreamer(Out, MCInstBuilder(Opcode)
                             .addOperand(Inst.getOperand(1))
                             .addOperand(Inst.getOperand(2))
                             .addOperand(Inst.getOperand(3))
-                            .addOperand(Inst.getOperand(4)));
+                            .addReg(RISCV::NoRegister));
     emitToStreamer(Out, MCInstBuilder(RISCV::VMANDN_MM)
                             .addOperand(Inst.getOperand(0))
                             .addOperand(Inst.getOperand(0))
                             .addOperand(Inst.getOperand(1)));
   } else if (Inst.getNumOperands() == 5) {
     // masked va >= x, any vd
     //
     // pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
-    // expansion: vmslt{u}.vx vt, va, x; vmandn.mm vt, v0, vt; vmandn.mm vd,
-    // vd, v0; vmor.mm vd, vt, vd
+    // expansion: vmslt{u}.vx vt, va, x; vmandn.mm vt, v0, vt;
+    //            vmandn.mm vd, vd, v0;  vmor.mm vd, vt, vd
     assert(Inst.getOperand(1).getReg() != RISCV::V0 &&
            "The temporary vector register should not be V0.");
     emitToStreamer(Out, MCInstBuilder(Opcode)
                             .addOperand(Inst.getOperand(1))
                             .addOperand(Inst.getOperand(2))
                             .addOperand(Inst.getOperand(3))
                             .addReg(RISCV::NoRegister));
     emitToStreamer(Out, MCInstBuilder(RISCV::VMANDN_MM)

llvm/test/MC/RISCV/rvv/compare.s

 # CHECK-INST: vmxor.mm v8, v8, v0
 # CHECK-ENCODING: [0x57,0x44,0x45,0x6c]
 # CHECK-ENCODING: [0x57,0x24,0x80,0x6e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
 # CHECK-UNKNOWN: 57 44 45 6c <unknown>
 # CHECK-UNKNOWN: 57 24 80 6e <unknown>
 
 vmsgeu.vx v0, v4, a0, v0.t, v2
-# CHECK-INST: vmsltu.vx v2, v4, a0, v0.t
+# CHECK-INST: vmsltu.vx v2, v4, a0
 # CHECK-INST: vmandn.mm v0, v0, v2
-# CHECK-ENCODING: [0x57,0x41,0x45,0x68]
+# CHECK-ENCODING: [0x57,0x41,0x45,0x6a]
 # CHECK-ENCODING: [0x57,0x20,0x01,0x62]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
-# CHECK-UNKNOWN: 57 41 45 68 <unknown>
+# CHECK-UNKNOWN: 57 41 45 6a <unknown>
 # CHECK-UNKNOWN: 57 20 01 62 <unknown>
 
 vmsge.vx v0, v4, a0, v0.t, v2
-# CHECK-INST: vmslt.vx v2, v4, a0, v0.t
+# CHECK-INST: vmslt.vx v2, v4, a0
 # CHECK-INST: vmandn.mm v0, v0, v2
-# CHECK-ENCODING: [0x57,0x41,0x45,0x6c]
+# CHECK-ENCODING: [0x57,0x41,0x45,0x6e]
 # CHECK-ENCODING: [0x57,0x20,0x01,0x62]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
-# CHECK-UNKNOWN: 57 41 45 6c <unknown>
+# CHECK-UNKNOWN: 57 41 45 6e <unknown>
 # CHECK-UNKNOWN: 57 20 01 62 <unknown>
 
 vmsgeu.vx v9, v4, a0, v0.t, v2
 # CHECK-INST: vmsltu.vx v2, v4, a0
 # CHECK-INST: vmandn.mm v2, v0, v2
 # CHECK-INST: vmandn.mm v9, v9, v0
 # CHECK-INST: vmor.mm v9, v2, v9
 # CHECK-ENCODING: [0x57,0x41,0x45,0x6a]