This is an archive of the discontinued LLVM Phabricator instance.

[RISCV] Fix `vmsge{u}.vx` lowering by not adding the mask operand if `vd == v0`

Authored by imkiva on Aug 21 2023, 12:39 AM.



According to riscv-v-spec-1.0.pdf page 52:

masked va >= x, vd == v0
   pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
   expansion: vmslt{u}.vx vt, va, x; vd, vd, vt

The resulting vmslt{u}.vx is not masked. This patch fixes the logic in RISCVAsmParser, to make the behavior consistent with the case "masked va >= x, any vd" in the later part of the code, where no mask op is added.

Diff Detail

Event Timeline

imkiva created this revision.Aug 21 2023, 12:39 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 21 2023, 12:39 AM
imkiva requested review of this revision.Aug 21 2023, 12:39 AM
imkiva updated this revision to Diff 551917.Aug 21 2023, 12:44 AM

Reformat some comments so they look nicer.

craig.topper accepted this revision.Aug 21 2023, 11:07 PM


Does binutils have the same issue?

This revision is now accepted and ready to land.Aug 21 2023, 11:07 PM

Does binutils have the same issue?

Probably yes.

But I still think the mask operand should be transitive as lowering a masked instruction to an unmasked one may break certain constraints (?) and look wired 😕. I will post further information here when I know more.