[RISCV] Teach VSETVLIInserter to not demand tail policy when there is no tail element

[jacquesguan]

Summary

If avl is vlmax and lmul is not fractional, there is no tail element so that no need to demand tail policy.

[luke]

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

380

The VL operand can be stale here because this is called from doLocalPostpass, after the pseudo has been expanded and the vsetvlis are inserted. Is it possible to move this into needVSETVLI?

[craig.topper]

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

375

This is incorrect for vcompress, reductions, and vmv.s.x.

[jacquesguan]

Address comment.

[jacquesguan]

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

375

Done, exclude these instructions.

380

Done, moved to needVSETVLI.

[jacquesguan]

change switch to equal.

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

585

Wouldn't we want ta instead of tu since there is no tail?

[jacquesguan]

Use tail agnostic.

[jacquesguan]

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

585

Done.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

820

!decodeVLMUL(VLMul).second

973

!decodeVLMUL(VLMul).second

[jacquesguan]

Address comment.

[jacquesguan]

ping.

[reames]

Taking a step back from the code, can you say a little about the motivation for this? I don't see anything particularly compelling in the test diffs. Why do you think this is an interesting optimization to implement?

Also, you definitely need more meaningful test coverage before this is reviewable. However, let's start with the motivation as I don't want to waste your time on writing tests if we're going to end up taking a different approach anyways.

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

static bool isVSlideInstr(const MachineInstr &MI) {
   case RISCV::VSLIDEDOWN_VX:
   case RISCV::VSLIDEDOWN_VI:
   case RISCV::VSLIDEUP_VX:
   case RISCV::VSLIDEUP_VI:
     return true;
   }
 }
 
+static bool isCompressInstr(const MachineInstr &MI) {
+  return getRVVMCOpcode(MI.getOpcode()) == RISCV::VCOMPRESS_VM;
+}
+
+static bool isReductionInstr(const MachineInstr &MI) {
+  switch (getRVVMCOpcode(MI.getOpcode())) {
+  default:
+    return false;
+  case RISCV::VREDSUM_VS:
+  case RISCV::VREDMAXU_VS:
+  case RISCV::VREDMAX_VS:
+  case RISCV::VREDMINU_VS:
+  case RISCV::VREDMIN_VS:
+  case RISCV::VREDAND_VS:
+  case RISCV::VREDOR_VS:
+  case RISCV::VREDXOR_VS:
+  case RISCV::VWREDSUMU_VS:
+  case RISCV::VWREDSUM_VS:
+  case RISCV::VFREDOSUM_VS:
+  case RISCV::VFREDUSUM_VS:
+  case RISCV::VFREDMIN_VS:
+  case RISCV::VFREDMAX_VS:
+  case RISCV::VFWREDOSUM_VS:
+  case RISCV::VFWREDUSUM_VS:
+    return true;
+  }
+}
+
 /// Get the EEW for a load or store instruction.  Return std::nullopt if MI is
 /// not a load or store which ignores SEW.
 static std::optional<unsigned> getEEWForLoadStore(const MachineInstr &MI) {
   switch (getRVVMCOpcode(MI.getOpcode())) {
   default:
     return std::nullopt;
   case RISCV::VLE8_V:
   case RISCV::VLSE8_V:
DemandedFields getDemanded(const MachineInstr &MI,
   }
 
   // Store instructions don't use the policy fields.
   if (RISCVII::hasSEWOp(TSFlags) && MI.getNumExplicitDefs() == 0) {
     Res.TailPolicy = false;
     Res.MaskPolicy = false;
   }
 
   // If this is a mask reg operation, it only cares about VLMAX.
   // TODO: Possible extensions to this logic
   // * Probably ok if available VLMax is larger than demanded
   // * The policy bits can probably be ignored..
   if (isMaskRegOp(MI)) {
     Res.SEW = DemandedFields::SEWNone;
     Res.LMUL = false;
   }
 
   // For vmv.s.x and vfmv.s.f, there are only two behaviors, VL = 0 and VL > 0.
   if (isScalarMoveInstr(MI)) {
     Res.LMUL = false;
     Res.SEWLMULRatio = false;
     Res.VLAny = false;

 #ifndef NDEBUG
   if (std::optional<unsigned> EEW = getEEWForLoadStore(MI)) {
     assert(SEW == EEW && "Initial SEW doesn't match expected EEW");
   }
 #endif
   InstrInfo.setVTYPE(VLMul, SEW, TailAgnostic, MaskAgnostic);
 
   return InstrInfo;
 }
 
 void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB, MachineInstr &MI,
                                        const VSETVLIInfo &Info,
                                        const VSETVLIInfo &PrevInfo) {
   DebugLoc DL = MI.getDebugLoc();
   insertVSETVLI(MBB, MachineBasicBlock::iterator(&MI), DL, Info, PrevInfo);
 }
 
bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
   if (isVSlideInstr(MI) && Require.hasAVLImm() && Require.getAVLImm() == 1 &&
       isLMUL1OrSmaller(CurInfo.getVLMUL()) && hasUndefinedMergeOp(MI, *MRI)) {
     Used.VLAny = false;
     Used.VLZeroness = true;
     Used.LMUL = false;
     Used.TailPolicy = false;
   }
 
+  // For most instructions, tail element is defined as:
+  // tail(x) = (vl <= x < max(VLMAX,VLEN/SEW))
+  // So if the avl is VLMAX, and LMUL is not fractional, there is no tail
+  // element, so it doesn't need tail policy.
+  if (!isScalarMoveInstr(MI) && !isReductionInstr(MI) && !isCompressInstr(MI))
+    if (RISCVII::hasVLOp(MI.getDesc().TSFlags)) {
+      RISCVII::VLMUL VLMul = RISCVII::getLMul(MI.getDesc().TSFlags);
+      // Fractional LMULs always require tail policy.
+      if (VLMul < RISCVII::LMUL_RESERVED) {
+        const MachineOperand &VLOp = MI.getOperand(getVLOpNum(MI));
+        if (VLOp.isImm()) {
+          int64_t Imm = VLOp.getImm();
+          if (Imm == RISCV::VLMaxSentinel)
+            Used.TailPolicy = false;
+        } else if (VLOp.getReg() == RISCV::X0) {
+          Used.TailPolicy = false;
+        }
+      }
+    }
+
   // A tail undefined vmv.v.i/x or vfmv.v.f with VL=1 can be treated in the same
   // semantically as vmv.s.x.  This is particularly useful since we don't have an
   // immediate form of vmv.s.x, and thus frequently use vmv.v.i in it's place.
   // Since a splat is non-constant time in LMUL, we do need to be careful to not
   // increase the number of active vector registers (unlike for vmv.s.x.)
   if (isScalarSplatInstr(MI) && Require.hasAVLImm() && Require.getAVLImm() == 1 &&
       isLMUL1OrSmaller(CurInfo.getVLMUL()) && hasUndefinedMergeOp(MI, *MRI)) {
     Used.LMUL = false;

llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll

 
 ; This shouldn't be folded because we need to preserve exceptions with
 ; "fpexcept.strict" exception behaviour, and masking may hide them.
 define <vscale x 2 x float> @vpmerge_constrained_fadd_vlmax(<vscale x 2 x float> %passthru, <vscale x 2 x float> %x, <vscale x 2 x float> %y, <vscale x 2 x i1> %m) strictfp {
 ; CHECK-LABEL: vpmerge_constrained_fadd_vlmax:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
 ; CHECK-NEXT:    vfadd.vv v9, v9, v10
-; CHECK-NEXT:    vsetvli zero, zero, e32, m1, tu, ma
 ; CHECK-NEXT:    vmerge.vvm v8, v8, v9, v0
 ; CHECK-NEXT:    ret
   %a = call <vscale x 2 x float> @llvm.experimental.constrained.fadd(<vscale x 2 x float> %x, <vscale x 2 x float> %y, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   %b = call <vscale x 2 x float> @llvm.riscv.vmerge.nxv2f32.nxv2f32(<vscale x 2 x float> %passthru, <vscale x 2 x float> %passthru, <vscale x 2 x float> %a, <vscale x 2 x i1> %m, i64 -1) strictfp
   ret <vscale x 2 x float> %b
 }
 
 ; Test conversion by fptosi.

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

entry:
   %2 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
     <vscale x 1 x double> undef,
     <vscale x 1 x double> %1,
     <vscale x 1 x double> %c,
     i64 7, i64 %0)
   ret <vscale x 1 x double> %2
 }
 
+define <vscale x 1 x i64> @test21(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, <vscale x 1 x i1> %mask) nounwind {
+; CHECK-LABEL: test21:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, zero, e64, m1, tu, mu
+; CHECK-NEXT:    vadd.vv v8, v8, v8, v0.t
+; CHECK-NEXT:    vadd.vv v9, v9, v8, v0.t
+; CHECK-NEXT:    vmv1r.v v8, v9
+; CHECK-NEXT:    ret
+entry:
+  %x = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %a,
+    <vscale x 1 x i64> %a,
+    <vscale x 1 x i64> %a,
+    <vscale x 1 x i1> %mask,
+    i64 -1,
+    i64 0)
+  %y = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %b,
+    <vscale x 1 x i64> %b,
+    <vscale x 1 x i64> %x,
+    <vscale x 1 x i1> %mask,
+    i64 -1,
+    i64 1)
+  ret <vscale x 1 x i64> %y
+}
+
 ; This used to fail the machine verifier due to the vsetvli being removed
 ; while the add was still using it.
 define i64 @bad_removal(<2 x i64> %arg) {
 ; CHECK-LABEL: bad_removal:
 ; CHECK:       # %bb.0: # %bb
 ; CHECK-NEXT:    vsetivli zero, 16, e64, m1, ta, ma
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    vsetivli a1, 16, e64, m1, ta, ma