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Differential D156799

Update generic scheduling to use A510 scheduling model
ClosedPublic

Authored by harviniriawan on Aug 1 2023, 7:47 AM.

Details

Reviewers
dmgreen
SjoerdMeijer
samtebbs
t.p.northover
tmatheson
Summary

Refresh of the generic scheduling model to use A510 instead of A55.
Main benefits are to the little core, and introducing SVE scheduling information.
Changes tested on various OoO cores, no performance degradation is seen.

Diff Detail

Event Timeline

harviniriawan created this revision.Aug 1 2023, 7:47 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 1 2023, 7:47 AM
Herald added subscribers: ctetreau, armkevincheng, sjarus and 5 others. · View Herald Transcript
harviniriawan requested review of this revision.Aug 1 2023, 7:47 AM
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Harbormaster completed remote builds in B249491: Diff 546061.Aug 1 2023, 7:48 AM
Matt added a subscriber: Matt.Aug 1 2023, 2:28 PM
dmgreen added reviewers: SjoerdMeijer, samtebbs, t.p.northover, tmatheson.Aug 2 2023, 2:37 AM

Sounds great. The change certainly sounds like a good idea.

There are a lot of test updates needed though, and some of them might be better not-auto-generated, or could otherwise do with a bit of a cleanup. I remember when changing to the A55 scheduling model that I just manually updated some of the tests, it might be better to do the same here. I haven't gone through everything, but have marked some of the tests that could do with some cleanup.

llvm/test/CodeGen/AArch64/128bit_load_store.ll
1 ↗(On Diff #546061)

I'm not sure why this needed updating, but the check lines OK here.

llvm/test/CodeGen/AArch64/2s-complement-asm.ll
1 ↗(On Diff #546061)

This one isn't needed, and seems to not have updated the actual tests.

llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll
1

I think this is one that is best left manually updated.

llvm/test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll
1 ↗(On Diff #546061)

Probably not needed.

llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
2277

There is an extra spill here, but that kind of things is expected given enough code.

llvm/test/CodeGen/AArch64/logical_shifted_reg.ll
261–263

This looks like it no longer decides to ifcvt. Given the test that sound fine I think.

llvm/test/CodeGen/AArch64/memcpy-scoped-aa.ll
137–138

Things like this can be removed too, so long as there are check lines elsewhere.

llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
1

This doesn't look right. Should it be using -mcpu=cortex-a55 instead?

llvm/test/CodeGen/AArch64/misched-fusion-lit.ll
1

This is likely best checked manually.

llvm/test/CodeGen/AArch64/named-vector-shuffles-neon.ll
114

Some of these have less movs thanks to the lower latencies, which is nice.

llvm/test/CodeGen/AArch64/wineh-bti.ll
1

This has test CHECK line elsewhere in the file.

harviniriawan updated this revision to Diff 546501.Aug 2 2023, 9:09 AM
harviniriawan marked 11 inline comments as done.
Herald added a subscriber: arichardson. · View Herald TranscriptAug 2 2023, 9:09 AM
harviniriawan added inline comments.Aug 2 2023, 9:09 AM
llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
1

shouldn't it be a510 as it's the default scheduling policy now?

Harbormaster completed remote builds in B249800: Diff 546501.Aug 2 2023, 9:10 AM
harviniriawan updated this revision to Diff 546509.Aug 2 2023, 9:33 AM
Harbormaster completed remote builds in B249807: Diff 546509.Aug 2 2023, 9:34 AM
harviniriawan updated this revision to Diff 546520.Aug 2 2023, 9:48 AM
Harbormaster completed remote builds in B249818: Diff 546520.Aug 2 2023, 9:49 AM
harviniriawan updated this revision to Diff 546739.Aug 3 2023, 1:22 AM
Harbormaster completed remote builds in B249981: Diff 546739.Aug 3 2023, 2:48 AM
dmgreen added a comment.Aug 3 2023, 4:00 AM

Thanks. If you can clean up these tests, then this looks good to me.

llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
86

This looks like it would be better with the manual check lines below.

llvm/test/CodeGen/AArch64/arm64-ld1.ll
1

This doesn't look like it has generated properly.

llvm/test/CodeGen/AArch64/arm64-promote-const-complex-initializers.ll
12

This doesn't look like it is checking everything it did in the past.

llvm/test/CodeGen/AArch64/arm64_32.ll
17

This file might be better manually generated. Some of the check lines and comments are deliberately placed.

llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
36

It looks like ths RUN line for CHECK-REG is trying to check that there are no invalid register formed. You might be able to change it to --check-prefixes=CHECK,CHECK-REG

llvm/test/CodeGen/AArch64/bfis-in-loop.ll
13

This doesn't look right

llvm/test/CodeGen/AArch64/f16-instructions.ll
13

This one needs to be done manually.

llvm/test/CodeGen/AArch64/fmlal-loreg.ll
3

I'm not sure why these blank lines were removed? I think they can be kept in.

llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
29

This file can specify -mcpu=cortex-a55 to keep the test as it was before.

llvm/test/CodeGen/AArch64/nontemporal-load.ll
5

These newlines and blank ; lines look funny.

llvm/test/CodeGen/AArch64/shrink-wrapping-vla.ll
18

Manual update might be better.

llvm/test/CodeGen/AArch64/sme2-intrinsics-min.ll
140

This doesn't look right.

llvm/test/CodeGen/AArch64/sme2-intrinsics-rshl.ll
53

This doesn't look right.

llvm/test/CodeGen/AArch64/sme2-intrinsics-sqdmulh.ll
54

This doesn't look right.

llvm/test/CodeGen/AArch64/speculation-hardening-loads.ll
5

Manual update might be better.

llvm/test/CodeGen/AArch64/split-vector-insert.ll
13

This was testing the debug output before.

llvm/test/CodeGen/AArch64/stack-guard-sysreg.ll
1

Can you explain this one? Are the two versions now too different to keep the same?

llvm/test/CodeGen/AArch64/sve-fixed-length-build-vector.ll
56

Keep this

llvm/test/CodeGen/AArch64/sve-split-int-pred-reduce.ll
25

This is nice :)

llvm/test/CodeGen/AArch64/swift-return.ll
7

Manually update this one may be best.

llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
10

These need to keep checking the constant pools

llvm/test/CodeGen/AArch64/vec-combine-compare-truncate-store.ll
5

These too.

llvm/test/CodeGen/AArch64/zext-to-tbl.ll
5

These too.

harviniriawan updated this revision to Diff 546884.Aug 3 2023, 8:16 AM
harviniriawan marked 23 inline comments as done.
Herald added a project: Restricted Project. · View Herald TranscriptAug 3 2023, 8:16 AM
Herald added a subscriber: cfe-commits. · View Herald Transcript
harviniriawan added inline comments.Aug 3 2023, 8:16 AM
llvm/test/CodeGen/AArch64/stack-guard-sysreg.ll
1

Yes indeed. the ones with CHECK-ADD annoyingly is scheduled slightly differently due to it being ADD instead of LDR

Harbormaster completed remote builds in B250083: Diff 546884.Aug 3 2023, 10:16 AM
dmgreen accepted this revision.Aug 3 2023, 1:11 PM

Thanks. Looks good. You may need to rebase over new tests, make sure everything is still passing when you do.

LGTM

llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
1

Sorry I forgot to reply to the old comment. AFAIU this is testing some of the info in the scheduling model, not which model is being used. So pinning it to the A55 makes sense for keeping the old testing in place.

This revision is now accepted and ready to land.Aug 3 2023, 1:11 PM
harviniriawan updated this revision to Diff 551951.Aug 21 2023, 3:08 AM
Harbormaster completed remote builds in B253799: Diff 551951.Aug 21 2023, 3:09 AM
harviniriawan marked an inline comment as done.Aug 21 2023, 3:09 AM
harviniriawan updated this revision to Diff 551953.Aug 21 2023, 3:16 AM
Harbormaster completed remote builds in B253801: Diff 551953.Aug 21 2023, 3:58 AM
harviniriawan closed this revision.Aug 21 2023, 4:27 AM
harviniriawan updated this revision to Diff 551978.
Harbormaster completed remote builds in B253816: Diff 551978.Aug 21 2023, 4:28 AM
aeubanks added a subscriber: aeubanks.Aug 21 2023, 8:50 AM
aeubanks added inline comments.
llvm/test/CodeGen/AArch64/stack-guard-sysreg.ll
1

this test is broken, without the split-file the other files won't exist in a clean build, please fix or revert if it takes time to fix

Large Diff

This large diff affects 597 files. Files without inline comments have been collapsed. Expand All Files

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Diff 551978

clang/test/CodeGen/aarch64-ABI-align-packed-assembly.c

llvm/lib/Target/AArch64/AArch64.td

llvm/test/Analysis/CostModel/AArch64/vector-select.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2_lse128.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-outline_atomics.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc3.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8_1a.ll

llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a.ll

llvm/test/CodeGen/AArch64/GlobalISel/aapcs_vararg_frame.ll

llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll

llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll

llvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll

llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll

llvm/test/CodeGen/AArch64/GlobalISel/select-bitfield-insert.ll

llvm/test/CodeGen/AArch64/GlobalISel/stacksave-stackrestore.ll

llvm/test/CodeGen/AArch64/GlobalISel/store-merging.ll

llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll

Context not available.
; "caller2" is the caller of "foo", it calls "foo" inside a loop. ; "caller2" is the caller of "foo", it calls "foo" inside a loop.
define float @caller2(ptr %error_ref) { define float @caller2(ptr %error_ref) {
; CHECK-LABEL: caller2: ; CHECK-LABEL: caller2:
; CHECK: mov [[ID:x[0-9]+]], x0
; CHECK: fmov [[CMP:s[0-9]+]], #1.0 ; CHECK: fmov [[CMP:s[0-9]+]], #1.0
; CHECK: mov [[ID:x[0-9]+]], x0
; CHECK: mov x21, xzr ; CHECK: mov x21, xzr
; CHECK: bl {{.*}}foo ; CHECK: bl {{.*}}foo
; CHECK: cbnz x21 ; CHECK: cbnz x21
Context not available.
; CHECK-DAG: mov w0, #16 ; CHECK-DAG: mov w0, #16
; CHECK: malloc ; CHECK: malloc
; CHECK: mov [[ID:w[0-9]+]], #1 ; CHECK: mov [[ID:w[0-9]+]], #1
; CHECK: mov x21, x0
; CHECK: strb [[ID]], [x0, #8] ; CHECK: strb [[ID]], [x0, #8]
; CHECK: mov x21, x0
; CHECK: str w{{.*}}, [{{.*}}[[SRET]], #4] ; CHECK: str w{{.*}}, [{{.*}}[[SRET]], #4]
; CHECK-NOT: x21 ; CHECK-NOT: x21
Context not available.
; CHECK: mov w0, #16 ; CHECK: mov w0, #16
; CHECK: malloc ; CHECK: malloc
; CHECK: mov [[ID:w[0-9]+]], #1 ; CHECK: mov [[ID:w[0-9]+]], #1
; CHECK: mov x21, x0
; CHECK-NOT: x21
; CHECK: strb [[ID]], [x0, #8] ; CHECK: strb [[ID]], [x0, #8]
; CHECK: mov x21, x0
; CHECK-NOT: x21 ; CHECK-NOT: x21
; First vararg ; First vararg
Context not available.
; CHECK: str xzr, [sp] ; CHECK: str xzr, [sp]
; CHECK: bl _params_in_reg2 ; CHECK: bl _params_in_reg2
; Restore original arguments for next call. ; Restore original arguments for next call.
; CHECK: ldr x8, [sp, #24]
; CHECK: mov x1, x20 ; CHECK: mov x1, x20
; CHECK: mov x2, x22 ; CHECK: mov x2, x22
; CHECK: mov x3, x23 ; CHECK: mov x3, x23
Context not available.
; CHECK: mov x7, x27 ; CHECK: mov x7, x27
; Restore original swiftself argument and swifterror %err. ; Restore original swiftself argument and swifterror %err.
; CHECK: mov x21, x28 ; CHECK: mov x21, x28
; CHECK: ldr x8, [sp
; CHECK: bl _params_in_reg2 ; CHECK: bl _params_in_reg2
; Restore calle save registers but don't clober swifterror x21. ; Restore calle save registers but don't clober swifterror x21.
; CHECK-NOT: x21 ; CHECK-NOT: x21
; CHECK: ldp x29, x30, [sp ; CHECK: ldp x29, x30, [sp
; CHECK-NOT: x21 ; CHECK-NOT: x21
; CHECK: ldr x28, [sp
; CHECK-NOT: x21
; CHECK: ldp x20, x19, [sp ; CHECK: ldp x20, x19, [sp
; CHECK-NOT: x21 ; CHECK-NOT: x21
; CHECK: ldp x23, x22, [sp ; CHECK: ldp x23, x22, [sp
Context not available.
; CHECK-NOT: x21 ; CHECK-NOT: x21
; CHECK: ldp x27, x26, [sp ; CHECK: ldp x27, x26, [sp
; CHECK-NOT: x21 ; CHECK-NOT: x21
; CHECK: ldr x28, [sp
; CHECK-NOT: x21
; CHECK: ret ; CHECK: ret
define swiftcc void @params_in_reg(i64, i64, i64, i64, i64, i64, i64, i64, ptr, ptr nocapture swifterror %err) { define swiftcc void @params_in_reg(i64, i64, i64, i64, i64, i64, i64, i64, ptr, ptr nocapture swifterror %err) {
%error_ptr_ref = alloca swifterror ptr, align 8 %error_ptr_ref = alloca swifterror ptr, align 8
Context not available.
; CHECK-LABEL: params_and_return_in_reg ; CHECK-LABEL: params_and_return_in_reg
; Store callee saved registers. ; Store callee saved registers.
; CHECK: stp x28, x21, [sp, #16 ; CHECK: stp x28, x0, [sp, #16
; CHECK: stp x27, x26, [sp ; CHECK: stp x27, x26, [sp
; CHECK: stp x25, x24, [sp ; CHECK: stp x25, x24, [sp
; CHECK: stp x23, x22, [sp ; CHECK: stp x23, x22, [sp
Context not available.
; CHECK: mov x21, xzr ; CHECK: mov x21, xzr
; CHECK: bl _params_in_reg2 ; CHECK: bl _params_in_reg2
; Store swifterror %error_ptr_ref. ; Store swifterror %error_ptr_ref.
; CHECK: ldr x0, [sp, #24]
; CHECK: stp {{x[0-9]+}}, x21, [sp] ; CHECK: stp {{x[0-9]+}}, x21, [sp]
; Setup call arguments from original arguments. ; Setup call arguments from original arguments.
; CHECK: mov x0, x19
; CHECK: mov x1, x20 ; CHECK: mov x1, x20
; CHECK: mov x2, x22 ; CHECK: mov x2, x22
; CHECK: mov x3, x23 ; CHECK: mov x3, x23
Context not available.
; CHECK: mov x5, x25 ; CHECK: mov x5, x25
; CHECK: mov x6, x26 ; CHECK: mov x6, x26
; CHECK: mov x7, x27 ; CHECK: mov x7, x27
; CHECK: ldr x21, [sp, #24 ; CHECK: mov x21, x28
; CHECK: bl _params_and_return_in_reg2 ; CHECK: bl _params_and_return_in_reg2
; CHECK: mov x19, x21
; CHECK: ldr x21, [sp, #8
; Store return values. ; Store return values.
; CHECK: mov x19, x0 ; CHECK: mov x20, x0
; CHECK: mov x20, x1 ; CHECK: mov x22, x1
; CHECK: mov x22, x2 ; CHECK: mov x23, x2
; CHECK: mov x23, x3 ; CHECK: mov x24, x3
; CHECK: mov x24, x4 ; CHECK: mov x25, x4
; CHECK: mov x25, x5 ; CHECK: mov x26, x5
; CHECK: mov x26, x6 ; CHECK: mov x27, x6
; CHECK: mov x27, x7 ; CHECK: mov x28, x7
; Save swifterror %err.
; CHECK: mov x28, x21
; Setup call. ; Setup call.
; CHECK: mov w0, #1 ; CHECK: mov w0, #1
; CHECK: mov w1, #2 ; CHECK: mov w1, #2
Context not available.
; CHECK: mov w5, #6 ; CHECK: mov w5, #6
; CHECK: mov w6, #7 ; CHECK: mov w6, #7
; CHECK: mov w7, #8 ; CHECK: mov w7, #8
; ... setup call with swiferror %error_ptr_ref. ; CHECK: str xzr, [sp]
; CHECK: ldr x21, [sp, #8]
; CHECK: bl _params_in_reg2 ; CHECK: bl _params_in_reg2
; Restore return values for return from this function. ; Restore return values for return from this function.
; CHECK: mov x0, x19 ; CHECK: mov x0, x20
; CHECK: mov x1, x20 ; CHECK: mov x1, x22
; CHECK: mov x2, x22 ; CHECK: mov x2, x23
; CHECK: mov x3, x23 ; CHECK: mov x3, x24
; CHECK: mov x4, x24 ; CHECK: mov x4, x25
; CHECK: mov x5, x25 ; CHECK: mov x5, x26
; CHECK: mov x6, x26 ; CHECK: mov x6, x27
; CHECK: mov x7, x27 ; CHECK: mov x21, x19
; CHECK: ldp x29, x30, [sp ; CHECK: mov x7, x28
; CHECK: mov x21, x28 ; CHECK: ldp x29, x30, [sp, #96] ; 16-byte Folded Reload
; Restore callee save registers. ; CHECK: ldr x28, [sp, #16] ; 8-byte Folded Reload
; CHECK: ldp x20, x19, [sp ; CHECK: ldp x20, x19, [sp, #80] ; 16-byte Folded Reload
; CHECK: ldp x23, x22, [sp ; CHECK: ldp x23, x22, [sp, #64] ; 16-byte Folded Reload
; CHECK: ldp x25, x24, [sp ; CHECK: ldp x25, x24, [sp, #48] ; 16-byte Folded Reload
; CHECK: ldp x27, x26, [sp ; CHECK: ldp x27, x26, [sp, #32] ; 16-byte Folded Reload
; CHECK: ldr x28, [sp ; CHECK: add sp, sp, #112
; CHECK: ret ; CHECK: ret
define swiftcc { i64, i64, i64, i64, i64, i64, i64, i64 } @params_and_return_in_reg(i64, i64, i64, i64, i64, i64, i64, i64, ptr , ptr nocapture swifterror %err) { define swiftcc { i64, i64, i64, i64, i64, i64, i64, i64 } @params_and_return_in_reg(i64, i64, i64, i64, i64, i64, i64, i64, ptr , ptr nocapture swifterror %err) {
%error_ptr_ref = alloca swifterror ptr, align 8 %error_ptr_ref = alloca swifterror ptr, align 8
Context not available.

llvm/test/CodeGen/AArch64/a57-csel.ll

llvm/test/CodeGen/AArch64/aarch64-addv.ll

llvm/test/CodeGen/AArch64/aarch64-be-bv.ll

llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll

llvm/test/CodeGen/AArch64/aarch64-combine-add-sub-mul.ll

llvm/test/CodeGen/AArch64/aarch64-dup-ext-scalable.ll

llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll

llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll

Context not available.
; CHECK: .cfi_offset w20, -16 ; CHECK: .cfi_offset w20, -16
; CHECK: .cfi_offset w30, -24 ; CHECK: .cfi_offset w30, -24
; CHECK: .cfi_offset w29, -32 ; CHECK: .cfi_offset w29, -32
; Check correct reservation of 16-byte aligned VLA (size in w0) on stack
; CHECK: ubfiz x8, x0, #2, #32
; Check correct access to arguments passed on the stack, through frame pointer ; Check correct access to arguments passed on the stack, through frame pointer
; CHECK: ldr w[[IARG:[0-9]+]], [x29, #40] ; CHECK: ldr w[[IARG:[0-9]+]], [x29, #40]
; Check correct reservation of 16-byte aligned VLA (size in w0) on stack
; CHECK: ubfiz x9, x0, #2, #32
; CHECK: add x9, x9, #15
; CHECK: ldr d[[DARG:[0-9]+]], [x29, #56] ; CHECK: ldr d[[DARG:[0-9]+]], [x29, #56]
; CHECK: and x9, x9, #0x7fffffff0 ; CHECK: add x8, x8, #15
; CHECK: and x8, x8, #0x7fffffff0
; CHECK: mov x10, sp ; CHECK: mov x10, sp
; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9 ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x8
; CHECK: mov sp, x[[VLASPTMP]] ; CHECK: mov sp, x[[VLASPTMP]]
; Check correct access to local variable, through frame pointer ; Check correct access to local variable, through frame pointer
; CHECK: ldur w[[ILOC:[0-9]+]], [x29, #-4] ; CHECK: ldur w[[ILOC:[0-9]+]], [x29, #-4]
Context not available.
; Check that space is reserved on the stack for the local variable, ; Check that space is reserved on the stack for the local variable,
; rounded up to a multiple of 16 to keep the stack pointer 16-byte aligned. ; rounded up to a multiple of 16 to keep the stack pointer 16-byte aligned.
; CHECK: sub sp, sp, #16 ; CHECK: sub sp, sp, #16
; Check correct reservation of 16-byte aligned VLA (size in w0) on stack
; CHECK: ubfiz x8, x0, #2, #32
; Check correctness of cfi pseudo-instructions ; Check correctness of cfi pseudo-instructions
; Check correct access to arguments passed on the stack, through frame pointer ; Check correct access to arguments passed on the stack, through frame pointer
; CHECK: ldr w[[IARG:[0-9]+]], [x29, #24] ; CHECK: ldr w[[IARG:[0-9]+]], [x29, #24]
; Check correct reservation of 16-byte aligned VLA (size in w0) on stack
; CHECK: ubfiz x9, x0, #2, #32
; CHECK: add x9, x9, #15
; CHECK: ldr d[[DARG:[0-9]+]], [x29, #40] ; CHECK: ldr d[[DARG:[0-9]+]], [x29, #40]
; CHECK: and x9, x9, #0x7fffffff0 ; CHECK: add x8, x8, #15
; CHECK: and x8, x8, #0x7fffffff0
; CHECK: mov x10, sp ; CHECK: mov x10, sp
; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9 ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x8
; CHECK: mov sp, x[[VLASPTMP]] ; CHECK: mov sp, x[[VLASPTMP]]
; Check correct access to local variable, through frame pointer ; Check correct access to local variable, through frame pointer
; CHECK: ldur w[[ILOC:[0-9]+]], [x29, #-4] ; CHECK: ldur w[[ILOC:[0-9]+]], [x29, #-4]
Context not available.
; CHECK: .cfi_offset w21, -32 ; CHECK: .cfi_offset w21, -32
; CHECK: .cfi_offset w30, -40 ; CHECK: .cfi_offset w30, -40
; CHECK: .cfi_offset w29, -48 ; CHECK: .cfi_offset w29, -48
; Check correct access to arguments passed on the stack, through frame pointer
; CHECK: ldr w[[IARG:[0-9]+]], [x29, #56]
; Check correct reservation of 16-byte aligned VLA (size in w0) on stack ; Check correct reservation of 16-byte aligned VLA (size in w0) on stack
; and set-up of base pointer (x19). ; and set-up of base pointer (x19).
; CHECK: ubfiz x9, x0, #2, #32 ; CHECK: ubfiz x8, x0, #2, #32
; CHECK: add x9, x9, #15 ; Check correct access to arguments passed on the stack, through frame pointer
; CHECK: ldr w[[IARG:[0-9]+]], [x29, #56]
; CHECK: ldr d[[DARG:[0-9]+]], [x29, #72] ; CHECK: ldr d[[DARG:[0-9]+]], [x29, #72]
; CHECK: and x9, x9, #0x7fffffff0 ; CHECK: add x8, x8, #15
; CHECK: and x8, x8, #0x7fffffff0
; CHECK: mov x10, sp ; CHECK: mov x10, sp
; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9 ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x8
; CHECK: mov sp, x[[VLASPTMP]] ; CHECK: mov sp, x[[VLASPTMP]]
; Check correct access to local variable, through base pointer ; Check correct access to local variable, through base pointer
; CHECK: ldr w[[ILOC:[0-9]+]], [x19] ; CHECK: ldr w[[ILOC:[0-9]+]], [x19]
Context not available.
; CHECK-MACHO: .cfi_offset w20, -32 ; CHECK-MACHO: .cfi_offset w20, -32
; CHECK-MACHO: .cfi_offset w21, -40 ; CHECK-MACHO: .cfi_offset w21, -40
; CHECK-MACHO: .cfi_offset w22, -48 ; CHECK-MACHO: .cfi_offset w22, -48
; Check correct access to arguments passed on the stack, through frame pointer
; CHECK-MACHO: ldr w[[IARG:[0-9]+]], [x29, #20]
; Check correct reservation of 16-byte aligned VLA (size in w0) on stack ; Check correct reservation of 16-byte aligned VLA (size in w0) on stack
; and set-up of base pointer (x19). ; and set-up of base pointer (x19).
; CHECK-MACHO: ubfiz x9, x0, #2, #32 ; CHECK-MACHO: ubfiz x8, x0, #2, #32
; CHECK-MACHO: add x9, x9, #15 ; Check correct access to arguments passed on the stack, through frame pointer
; CHECK-MACHO: ldr w[[IARG:[0-9]+]], [x29, #20]
; CHECK-MACHO: ldr d[[DARG:[0-9]+]], [x29, #32] ; CHECK-MACHO: ldr d[[DARG:[0-9]+]], [x29, #32]
; CHECK-MACHO: and x9, x9, #0x7fffffff0 ; CHECK-MACHO: add x8, x8, #15
; CHECK-MACHO: and x8, x8, #0x7fffffff0
; CHECK-MACHO: mov x10, sp ; CHECK-MACHO: mov x10, sp
; CHECK-MACHO: sub x[[VLASPTMP:[0-9]+]], x10, x9 ; CHECK-MACHO: sub x[[VLASPTMP:[0-9]+]], x10, x8
; CHECK-MACHO: mov sp, x[[VLASPTMP]] ; CHECK-MACHO: mov sp, x[[VLASPTMP]]
; Check correct access to local variable, through base pointer ; Check correct access to local variable, through base pointer
; CHECK-MACHO: ldr w[[ILOC:[0-9]+]], [x19] ; CHECK-MACHO: ldr w[[ILOC:[0-9]+]], [x19]
Context not available.
; CHECK: sub x9, sp, #96 ; CHECK: sub x9, sp, #96
; CHECK: and sp, x9, #0xffffffffffffff80 ; CHECK: and sp, x9, #0xffffffffffffff80
; CHECK: mov x19, sp ; CHECK: mov x19, sp
; Check correct access to arguments passed on the stack, through frame pointer
; CHECK: ldr w[[IARG:[0-9]+]], [x29, #40]
; Check correct reservation of 16-byte aligned VLA (size in w0) on stack ; Check correct reservation of 16-byte aligned VLA (size in w0) on stack
; and set-up of base pointer (x19). ; and set-up of base pointer (x19).
; CHECK: ubfiz x9, x0, #2, #32 ; CHECK: ubfiz x8, x0, #2, #32
; CHECK: add x9, x9, #15 ; Check correct access to arguments passed on the stack, through frame pointer
; CHECK: ldr w[[IARG:[0-9]+]], [x29, #40]
; CHECK: ldr d[[DARG:[0-9]+]], [x29, #56] ; CHECK: ldr d[[DARG:[0-9]+]], [x29, #56]
; CHECK: and x9, x9, #0x7fffffff0 ; CHECK: add x8, x8, #15
; CHECK: and x8, x8, #0x7fffffff0
; CHECK: mov x10, sp ; CHECK: mov x10, sp
; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9 ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x8
; CHECK: mov sp, x[[VLASPTMP]] ; CHECK: mov sp, x[[VLASPTMP]]
; Check correct access to local variable, through base pointer ; Check correct access to local variable, through base pointer
; CHECK: ldr w[[ILOC:[0-9]+]], [x19] ; CHECK: ldr w[[ILOC:[0-9]+]], [x19]
Context not available.
; CHECK-MACHO: sub x9, sp, #96 ; CHECK-MACHO: sub x9, sp, #96
; CHECK-MACHO: and sp, x9, #0xffffffffffffff80 ; CHECK-MACHO: and sp, x9, #0xffffffffffffff80
; CHECK-MACHO: mov x19, sp ; CHECK-MACHO: mov x19, sp
; Check correct access to arguments passed on the stack, through frame pointer
; CHECK-MACHO: ldr w[[IARG:[0-9]+]], [x29, #20]
; Check correct reservation of 16-byte aligned VLA (size in w0) on stack ; Check correct reservation of 16-byte aligned VLA (size in w0) on stack
; and set-up of base pointer (x19). ; and set-up of base pointer (x19).
; CHECK-MACHO: ubfiz x9, x0, #2, #32 ; CHECK-MACHO: ubfiz x8, x0, #2, #32
; CHECK-MACHO: add x9, x9, #15 ; Check correct access to arguments passed on the stack, through frame pointer
; CHECK-MACHO: ldr w[[IARG:[0-9]+]], [x29, #20]
; CHECK-MACHO: ldr d[[DARG:[0-9]+]], [x29, #32] ; CHECK-MACHO: ldr d[[DARG:[0-9]+]], [x29, #32]
; CHECK-MACHO: and x9, x9, #0x7fffffff0 ; CHECK-MACHO: add x8, x8, #15
; CHECK-MACHO: and x8, x8, #0x7fffffff0
; CHECK-MACHO: mov x10, sp ; CHECK-MACHO: mov x10, sp
; CHECK-MACHO: sub x[[VLASPTMP:[0-9]+]], x10, x9 ; CHECK-MACHO: sub x[[VLASPTMP:[0-9]+]], x10, x8
; CHECK-MACHO: mov sp, x[[VLASPTMP]] ; CHECK-MACHO: mov sp, x[[VLASPTMP]]
; Check correct access to local variable, through base pointer ; Check correct access to local variable, through base pointer
; CHECK-MACHO: ldr w[[ILOC:[0-9]+]], [x19] ; CHECK-MACHO: ldr w[[ILOC:[0-9]+]], [x19]
Context not available.
; CHECK: sub x9, sp, #7, lsl #12 ; CHECK: sub x9, sp, #7, lsl #12
; CHECK: and sp, x9, #0xffffffffffff8000 ; CHECK: and sp, x9, #0xffffffffffff8000
; CHECK: mov x19, sp ; CHECK: mov x19, sp
; Check correct access to arguments passed on the stack, through frame pointer
; CHECK: ldr w[[IARG:[0-9]+]], [x29, #40]
; Check correct reservation of 16-byte aligned VLA (size in w0) on stack ; Check correct reservation of 16-byte aligned VLA (size in w0) on stack
; and set-up of base pointer (x19). ; and set-up of base pointer (x19).
; CHECK: ubfiz x9, x0, #2, #32 ; CHECK: ubfiz x8, x0, #2, #32
; CHECK: add x9, x9, #15 ; Check correct access to arguments passed on the stack, through frame pointer
; CHECK: ldr w[[IARG:[0-9]+]], [x29, #40]
; CHECK: ldr d[[DARG:[0-9]+]], [x29, #56] ; CHECK: ldr d[[DARG:[0-9]+]], [x29, #56]
; CHECK: and x9, x9, #0x7fffffff0 ; CHECK: add x8, x8, #15
; CHECK: and x8, x8, #0x7fffffff0
; CHECK: mov x10, sp ; CHECK: mov x10, sp
; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9 ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x8
; CHECK: mov sp, x[[VLASPTMP]] ; CHECK: mov sp, x[[VLASPTMP]]
; Check correct access to local variable, through base pointer ; Check correct access to local variable, through base pointer
; CHECK: ldr w[[ILOC:[0-9]+]], [x19] ; CHECK: ldr w[[ILOC:[0-9]+]], [x19]
Context not available.
; CHECK-MACHO: sub x9, sp, #7, lsl #12 ; CHECK-MACHO: sub x9, sp, #7, lsl #12
; CHECK-MACHO: and sp, x9, #0xffffffffffff8000 ; CHECK-MACHO: and sp, x9, #0xffffffffffff8000
; CHECK-MACHO: mov x19, sp ; CHECK-MACHO: mov x19, sp
; Check correct access to arguments passed on the stack, through frame pointer
; CHECK-MACHO: ldr w[[IARG:[0-9]+]], [x29, #20]
; Check correct reservation of 16-byte aligned VLA (size in w0) on stack ; Check correct reservation of 16-byte aligned VLA (size in w0) on stack
; and set-up of base pointer (x19). ; and set-up of base pointer (x19).
; CHECK-MACHO: ubfiz x9, x0, #2, #32 ; CHECK-MACHO: ubfiz x8, x0, #2, #32
; CHECK-MACHO: add x9, x9, #15 ; Check correct access to arguments passed on the stack, through frame pointer
; CHECK-MACHO: ldr w[[IARG:[0-9]+]], [x29, #20]
; CHECK-MACHO: ldr d[[DARG:[0-9]+]], [x29, #32] ; CHECK-MACHO: ldr d[[DARG:[0-9]+]], [x29, #32]
; CHECK-MACHO: and x9, x9, #0x7fffffff0 ; CHECK-MACHO: add x8, x8, #15
; CHECK-MACHO: and x8, x8, #0x7fffffff0
; CHECK-MACHO: mov x10, sp ; CHECK-MACHO: mov x10, sp
; CHECK-MACHO: sub x[[VLASPTMP:[0-9]+]], x10, x9 ; CHECK-MACHO: sub x[[VLASPTMP:[0-9]+]], x10, x8
; CHECK-MACHO: mov sp, x[[VLASPTMP]] ; CHECK-MACHO: mov sp, x[[VLASPTMP]]
; Check correct access to local variable, through base pointer ; Check correct access to local variable, through base pointer
; CHECK-MACHO: ldr w[[ILOC:[0-9]+]], [x19] ; CHECK-MACHO: ldr w[[ILOC:[0-9]+]], [x19]
Context not available.

llvm/test/CodeGen/AArch64/aarch64-fixup-statepoint-regs-crash.ll

llvm/test/CodeGen/AArch64/aarch64-fold-lslfast.ll

llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll

llvm/test/CodeGen/AArch64/aarch64-isel-csinc.ll

llvm/test/CodeGen/AArch64/aarch64-load-ext.ll

llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll

llvm/test/CodeGen/AArch64/aarch64-mops-consecutive.ll

llvm/test/CodeGen/AArch64/aarch64-mops.ll

llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll

llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll

llvm/test/CodeGen/AArch64/aarch64-pmull2.ll

llvm/test/CodeGen/AArch64/aarch64-smull.ll

llvm/test/CodeGen/AArch64/aarch64-uzp1-combine.ll

llvm/test/CodeGen/AArch64/aarch64-wide-mul.ll

llvm/test/CodeGen/AArch64/aarch64_fnmadd.ll

llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll

llvm/test/CodeGen/AArch64/abd-combine.ll

llvm/test/CodeGen/AArch64/active_lane_mask.ll

llvm/test/CodeGen/AArch64/add-extract.ll

llvm/test/CodeGen/AArch64/addcarry-crash.ll

llvm/test/CodeGen/AArch64/addsub-constant-folding.ll

llvm/test/CodeGen/AArch64/addsub.ll

llvm/test/CodeGen/AArch64/align-down.ll

llvm/test/CodeGen/AArch64/and-mask-removal.ll

llvm/test/CodeGen/AArch64/andorbrcompare.ll

llvm/test/CodeGen/AArch64/argument-blocks-array-of-struct.ll

llvm/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll

llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll

llvm/test/CodeGen/AArch64/arm64-addrmode.ll

llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll

llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll

llvm/test/CodeGen/AArch64/arm64-cse.ll

llvm/test/CodeGen/AArch64/arm64-csel.ll

llvm/test/CodeGen/AArch64/arm64-dup.ll

llvm/test/CodeGen/AArch64/arm64-fcopysign.ll

llvm/test/CodeGen/AArch64/arm64-fmadd.ll

llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-no-helper.ll

llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll

llvm/test/CodeGen/AArch64/arm64-inline-asm.ll

llvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll

llvm/test/CodeGen/AArch64/arm64-ld1.ll

Context not available.
define void @ld1r_2s_from_dup(ptr nocapture %a, ptr nocapture %b, ptr nocapture %diff) nounwind ssp { define void @ld1r_2s_from_dup(ptr nocapture %a, ptr nocapture %b, ptr nocapture %diff) nounwind ssp {
entry: entry:
; CHECK: ld1r_2s_from_dup ; CHECK: ld1r_2s_from_dup
; CHECK: ld1r.2s { [[ARG2:v[0-9]+]] }, [x1] ; CHECK: ld1r.2s { [[ARG1:v[0-9]+]] }, [x0]
; CHECK-NEXT: ld1r.2s { [[ARG1:v[0-9]+]] }, [x0] ; CHECK-NEXT: ld1r.2s { [[ARG2:v[0-9]+]] }, [x1]
; CHECK-NEXT: usubl.8h v[[RESREGNUM:[0-9]+]], [[ARG1]], [[ARG2]] ; CHECK-NEXT: usubl.8h v[[RESREGNUM:[0-9]+]], [[ARG1]], [[ARG2]]
; CHECK-NEXT: str d[[RESREGNUM]], [x2] ; CHECK-NEXT: str d[[RESREGNUM]], [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
Context not available.

llvm/test/CodeGen/AArch64/arm64-ldp.ll

llvm/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll

llvm/test/CodeGen/AArch64/arm64-mul.ll

llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll

llvm/test/CodeGen/AArch64/arm64-neon-mul-div.ll

llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll

llvm/test/CodeGen/AArch64/arm64-non-pow2-ldst.ll

llvm/test/CodeGen/AArch64/arm64-nvcast.ll

llvm/test/CodeGen/AArch64/arm64-promote-const-complex-initializers.ll

Context not available.
; CHECK-NEXT: Lloh3: ; CHECK-NEXT: Lloh3:
; CHECK-NEXT: ldr q1, [x8, lCPI1_0@PAGEOFF] ; CHECK-NEXT: ldr q1, [x8, lCPI1_0@PAGEOFF]
; CHECK-NEXT: mov s2, v1[1] ; CHECK-NEXT: mov s2, v1[1]
; CHECK-NEXT: mov s3, v1[2]
; CHECK-NEXT: fneg s0, s1 ; CHECK-NEXT: fneg s0, s1
; CHECK-NEXT: mov s3, v1[2]
; CHECK-NEXT: mov s1, v1[3] ; CHECK-NEXT: mov s1, v1[3]
; CHECK-NEXT: fneg s2, s2 ; CHECK-NEXT: fneg s2, s2
; CHECK-NEXT: fneg s3, s3 ; CHECK-NEXT: fneg s3, s3
Context not available.

llvm/test/CodeGen/AArch64/arm64-register-pairing.ll

llvm/test/CodeGen/AArch64/arm64-rev.ll

llvm/test/CodeGen/AArch64/arm64-setcc-int-to-fp-combine.ll

llvm/test/CodeGen/AArch64/arm64-setcc-swap-infloop.ll

llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll

llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll

llvm/test/CodeGen/AArch64/arm64-tbl.ll

llvm/test/CodeGen/AArch64/arm64-vabs.ll

llvm/test/CodeGen/AArch64/arm64-vector-ldst.ll

llvm/test/CodeGen/AArch64/arm64-vhadd.ll

llvm/test/CodeGen/AArch64/arm64-vmul.ll

llvm/test/CodeGen/AArch64/arm64-vshift.ll

llvm/test/CodeGen/AArch64/arm64-xaluo.ll

llvm/test/CodeGen/AArch64/arm64-zip.ll

llvm/test/CodeGen/AArch64/arm64_32-addrs.ll

llvm/test/CodeGen/AArch64/arm64_32.ll

Context not available.
define void @test_memset(i64 %in, i8 %value) { define void @test_memset(i64 %in, i8 %value) {
; CHECK-LABEL: test_memset: ; CHECK-LABEL: test_memset:
; CHECK-DAG: and x8, x0, #0xffffffff
; CHECK-DAG: lsr x2, x0, #32 ; CHECK-DAG: lsr x2, x0, #32
; CHECK-DAG: mov x0, x8 ; CHECK-DAG: and x0, x0, #0xffffffff
; CHECK: b _memset ; CHECK: b _memset
%ptr.i32 = trunc i64 %in to i32 %ptr.i32 = trunc i64 %in to i32
Context not available.

llvm/test/CodeGen/AArch64/arm64ec-reservedregs.ll

llvm/test/CodeGen/AArch64/atomic-ops-lse.ll

Context not available.
; CHECK-LABEL: test_atomic_load_umin_i8: ; CHECK-LABEL: test_atomic_load_umin_i8:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i8: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i8:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xff ; OUTLINE-ATOMICS-NEXT: adrp x8, var8
; OUTLINE-ATOMICS-NEXT: adrp x9, var8 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, ls ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umin_i16: ; CHECK-LABEL: test_atomic_load_umin_i16:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i16: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i16:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xffff ; OUTLINE-ATOMICS-NEXT: adrp x8, var16
; OUTLINE-ATOMICS-NEXT: adrp x9, var16 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xffff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, ls ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umax_i8: ; CHECK-LABEL: test_atomic_load_umax_i8:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i8: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i8:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xff ; OUTLINE-ATOMICS-NEXT: adrp x8, var8
; OUTLINE-ATOMICS-NEXT: adrp x9, var8 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, hi ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, hi
; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umax_i16: ; CHECK-LABEL: test_atomic_load_umax_i16:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i16: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i16:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xffff ; OUTLINE-ATOMICS-NEXT: adrp x8, var16
; OUTLINE-ATOMICS-NEXT: adrp x9, var16 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xffff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, hi ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, hi
; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umax_i8_acq_rel: ; CHECK-LABEL: test_atomic_load_umax_i8_acq_rel:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i8_acq_rel: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i8_acq_rel:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xff ; OUTLINE-ATOMICS-NEXT: adrp x8, var8
; OUTLINE-ATOMICS-NEXT: adrp x9, var8 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, hi ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, hi
; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umax_i16_acq_rel: ; CHECK-LABEL: test_atomic_load_umax_i16_acq_rel:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i16_acq_rel: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i16_acq_rel:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xffff ; OUTLINE-ATOMICS-NEXT: adrp x8, var16
; OUTLINE-ATOMICS-NEXT: adrp x9, var16 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xffff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, hi ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, hi
; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umax_i8_acquire: ; CHECK-LABEL: test_atomic_load_umax_i8_acquire:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i8_acquire: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i8_acquire:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xff ; OUTLINE-ATOMICS-NEXT: adrp x8, var8
; OUTLINE-ATOMICS-NEXT: adrp x9, var8 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, hi ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, hi
; OUTLINE-ATOMICS-NEXT: stxrb w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stxrb w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umax_i16_acquire: ; CHECK-LABEL: test_atomic_load_umax_i16_acquire:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i16_acquire: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i16_acquire:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xffff ; OUTLINE-ATOMICS-NEXT: adrp x8, var16
; OUTLINE-ATOMICS-NEXT: adrp x9, var16 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xffff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, hi ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, hi
; OUTLINE-ATOMICS-NEXT: stxrh w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stxrh w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umax_i8_monotonic: ; CHECK-LABEL: test_atomic_load_umax_i8_monotonic:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i8_monotonic: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i8_monotonic:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xff ; OUTLINE-ATOMICS-NEXT: adrp x8, var8
; OUTLINE-ATOMICS-NEXT: adrp x9, var8 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxrb w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldxrb w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, hi ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, hi
; OUTLINE-ATOMICS-NEXT: stxrb w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stxrb w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umax_i16_monotonic: ; CHECK-LABEL: test_atomic_load_umax_i16_monotonic:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i16_monotonic: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i16_monotonic:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xffff ; OUTLINE-ATOMICS-NEXT: adrp x8, var16
; OUTLINE-ATOMICS-NEXT: adrp x9, var16 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xffff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxrh w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldxrh w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, hi ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, hi
; OUTLINE-ATOMICS-NEXT: stxrh w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stxrh w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umax_i8_release: ; CHECK-LABEL: test_atomic_load_umax_i8_release:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i8_release: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i8_release:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xff ; OUTLINE-ATOMICS-NEXT: adrp x8, var8
; OUTLINE-ATOMICS-NEXT: adrp x9, var8 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxrb w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldxrb w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, hi ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, hi
; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umax_i16_release: ; CHECK-LABEL: test_atomic_load_umax_i16_release:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i16_release: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i16_release:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xffff ; OUTLINE-ATOMICS-NEXT: adrp x8, var16
; OUTLINE-ATOMICS-NEXT: adrp x9, var16 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xffff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxrh w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldxrh w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, hi ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, hi
; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umax_i8_seq_cst: ; CHECK-LABEL: test_atomic_load_umax_i8_seq_cst:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i8_seq_cst: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i8_seq_cst:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xff ; OUTLINE-ATOMICS-NEXT: adrp x8, var8
; OUTLINE-ATOMICS-NEXT: adrp x9, var8 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, hi ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, hi
; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umax_i16_seq_cst: ; CHECK-LABEL: test_atomic_load_umax_i16_seq_cst:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i16_seq_cst: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i16_seq_cst:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xffff ; OUTLINE-ATOMICS-NEXT: adrp x8, var16
; OUTLINE-ATOMICS-NEXT: adrp x9, var16 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xffff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, hi ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, hi
; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umin_i8_acq_rel: ; CHECK-LABEL: test_atomic_load_umin_i8_acq_rel:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i8_acq_rel: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i8_acq_rel:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xff ; OUTLINE-ATOMICS-NEXT: adrp x8, var8
; OUTLINE-ATOMICS-NEXT: adrp x9, var8 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, ls ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umin_i16_acq_rel: ; CHECK-LABEL: test_atomic_load_umin_i16_acq_rel:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i16_acq_rel: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i16_acq_rel:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xffff ; OUTLINE-ATOMICS-NEXT: adrp x8, var16
; OUTLINE-ATOMICS-NEXT: adrp x9, var16 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xffff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, ls ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umin_i8_acquire: ; CHECK-LABEL: test_atomic_load_umin_i8_acquire:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i8_acquire: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i8_acquire:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xff ; OUTLINE-ATOMICS-NEXT: adrp x8, var8
; OUTLINE-ATOMICS-NEXT: adrp x9, var8 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, ls ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
; OUTLINE-ATOMICS-NEXT: stxrb w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stxrb w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umin_i16_acquire: ; CHECK-LABEL: test_atomic_load_umin_i16_acquire:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i16_acquire: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i16_acquire:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xffff ; OUTLINE-ATOMICS-NEXT: adrp x8, var16
; OUTLINE-ATOMICS-NEXT: adrp x9, var16 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xffff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, ls ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
; OUTLINE-ATOMICS-NEXT: stxrh w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stxrh w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umin_i8_monotonic: ; CHECK-LABEL: test_atomic_load_umin_i8_monotonic:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i8_monotonic: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i8_monotonic:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xff ; OUTLINE-ATOMICS-NEXT: adrp x8, var8
; OUTLINE-ATOMICS-NEXT: adrp x9, var8 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxrb w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldxrb w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, ls ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
; OUTLINE-ATOMICS-NEXT: stxrb w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stxrb w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umin_i16_monotonic: ; CHECK-LABEL: test_atomic_load_umin_i16_monotonic:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i16_monotonic: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i16_monotonic:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xffff ; OUTLINE-ATOMICS-NEXT: adrp x8, var16
; OUTLINE-ATOMICS-NEXT: adrp x9, var16 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xffff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxrh w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldxrh w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, ls ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
; OUTLINE-ATOMICS-NEXT: stxrh w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stxrh w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umin_i8_release: ; CHECK-LABEL: test_atomic_load_umin_i8_release:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i8_release: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i8_release:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xff ; OUTLINE-ATOMICS-NEXT: adrp x8, var8
; OUTLINE-ATOMICS-NEXT: adrp x9, var8 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxrb w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldxrb w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, ls ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umin_i16_release: ; CHECK-LABEL: test_atomic_load_umin_i16_release:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i16_release: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i16_release:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xffff ; OUTLINE-ATOMICS-NEXT: adrp x8, var16
; OUTLINE-ATOMICS-NEXT: adrp x9, var16 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xffff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxrh w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldxrh w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, ls ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umin_i8_seq_cst: ; CHECK-LABEL: test_atomic_load_umin_i8_seq_cst:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i8_seq_cst: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i8_seq_cst:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xff ; OUTLINE-ATOMICS-NEXT: adrp x8, var8
; OUTLINE-ATOMICS-NEXT: adrp x9, var8 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, ls ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.
; CHECK-LABEL: test_atomic_load_umin_i16_seq_cst: ; CHECK-LABEL: test_atomic_load_umin_i16_seq_cst:
; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i16_seq_cst: ; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i16_seq_cst:
; OUTLINE-ATOMICS: // %bb.0: ; OUTLINE-ATOMICS: // %bb.0:
; OUTLINE-ATOMICS-NEXT: and w8, w0, #0xffff ; OUTLINE-ATOMICS-NEXT: adrp x8, var16
; OUTLINE-ATOMICS-NEXT: adrp x9, var16 ; OUTLINE-ATOMICS-NEXT: add x8, x8, :lo12:var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16 ; OUTLINE-ATOMICS-NEXT: and w9, w0, #0xffff
; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start ; OUTLINE-ATOMICS-NEXT: .LBB[[LOOPSTART:.*]]: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1 ; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x9] ; OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w8 ; OUTLINE-ATOMICS-NEXT: cmp w0, w9
; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, ls ; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9] ; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]] ; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB[[LOOPSTART]]
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end ; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0 ; OUTLINE-ATOMICS-NEXT: // kill: def $w0 killed $w0 killed $x0
Context not available.

llvm/test/CodeGen/AArch64/atomic-ops-msvc.ll

llvm/test/CodeGen/AArch64/atomic-ops.ll

llvm/test/CodeGen/AArch64/bcmp-inline-small.ll

llvm/test/CodeGen/AArch64/bcmp.ll

llvm/test/CodeGen/AArch64/bf16-shuffle.ll

llvm/test/CodeGen/AArch64/bfis-in-loop.ll

Context not available.
define i64 @bfis_in_loop_zero() { define i64 @bfis_in_loop_zero() {
dmgreenUnsubmitted
Done
ReplyInline Actions

This doesn't look right

dmgreen: This doesn't look right
; CHECK-LABEL: bfis_in_loop_zero: ; CHECK-LABEL: bfis_in_loop_zero:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x9, :got:global ; CHECK-NEXT: adrp x8, :got:global
; CHECK-NEXT: mov x0, xzr ; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: mov w8, wzr ; CHECK-NEXT: mov w9, wzr
; CHECK-NEXT: ldr x9, [x9, :got_lo12:global] ; CHECK-NEXT: ldr x8, [x8, :got_lo12:global]
; CHECK-NEXT: ldr x9, [x9] ; CHECK-NEXT: ldr x8, [x8]
; CHECK-NEXT: .LBB0_1: // %midblock ; CHECK-NEXT: .LBB0_1: // %midblock
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldrh w10, [x9, #72] ; CHECK-NEXT: ldrh w10, [x8, #72]
; CHECK-NEXT: cmp w10, #0 ; CHECK-NEXT: ldr x13, [x8, #8]
; CHECK-NEXT: ubfx x11, x10, #8, #24 ; CHECK-NEXT: ubfx x11, x10, #8, #24
; CHECK-NEXT: cset w12, ne ; CHECK-NEXT: cmp w10, #0
; CHECK-NEXT: csel w8, w8, w11, eq ; CHECK-NEXT: and x10, x10, #0xff
; CHECK-NEXT: ldr x11, [x9, #8] ; CHECK-NEXT: cset w12, ne
; CHECK-NEXT: and x9, x10, #0xff ; CHECK-NEXT: ldr x8, [x13, #16]
; CHECK-NEXT: and x10, x0, #0xffffffff00000000 ; CHECK-NEXT: csel w9, w9, w11, eq
; CHECK-NEXT: orr x9, x9, x8, lsl #8 ; CHECK-NEXT: and x11, x0, #0xffffffff00000000
; CHECK-NEXT: orr x10, x10, x12, lsl #16 ; CHECK-NEXT: orr x10, x10, x9, lsl #8
; CHECK-NEXT: orr x0, x10, x9 ; CHECK-NEXT: orr x11, x11, x12, lsl #16
; CHECK-NEXT: ldr x9, [x11, #16] ; CHECK-NEXT: orr x0, x11, x10
; CHECK-NEXT: cbnz x11, .LBB0_1 ; CHECK-NEXT: cbnz x13, .LBB0_1
; CHECK-NEXT: // %bb.2: // %exit ; CHECK-NEXT: // %bb.2: // %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Context not available.
define i64 @bfis_in_loop_undef() { define i64 @bfis_in_loop_undef() {
; CHECK-LABEL: bfis_in_loop_undef: ; CHECK-LABEL: bfis_in_loop_undef:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x9, :got:global ; CHECK-NEXT: adrp x9, :got:global
; CHECK-NEXT: mov w8, wzr ; CHECK-NEXT: mov w8, wzr
; CHECK-NEXT: // implicit-def: $x0 ; CHECK-NEXT: // implicit-def: $x0
; CHECK-NEXT: ldr x9, [x9, :got_lo12:global] ; CHECK-NEXT: ldr x9, [x9, :got_lo12:global]
; CHECK-NEXT: ldr x9, [x9] ; CHECK-NEXT: ldr x9, [x9]
; CHECK-NEXT: .LBB1_1: // %midblock ; CHECK-NEXT: .LBB1_1: // %midblock
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldrh w10, [x9, #72] ; CHECK-NEXT: ldrh w10, [x9, #72]
; CHECK-NEXT: cmp w10, #0 ; CHECK-NEXT: ldr x13, [x9, #8]
; CHECK-NEXT: ubfx x11, x10, #8, #24 ; CHECK-NEXT: ubfx x11, x10, #8, #24
; CHECK-NEXT: cset w12, ne ; CHECK-NEXT: cmp w10, #0
; CHECK-NEXT: csel w8, w8, w11, eq ; CHECK-NEXT: and x10, x10, #0xff
; CHECK-NEXT: ldr x11, [x9, #8] ; CHECK-NEXT: cset w12, ne
; CHECK-NEXT: and x9, x10, #0xff ; CHECK-NEXT: ldr x9, [x13, #16]
; CHECK-NEXT: and x10, x0, #0xffffffff00000000 ; CHECK-NEXT: csel w8, w8, w11, eq
; CHECK-NEXT: orr x9, x9, x8, lsl #8 ; CHECK-NEXT: and x11, x0, #0xffffffff00000000
; CHECK-NEXT: orr x10, x10, x12, lsl #16 ; CHECK-NEXT: orr x10, x10, x8, lsl #8
; CHECK-NEXT: orr x0, x10, x9 ; CHECK-NEXT: orr x11, x11, x12, lsl #16
; CHECK-NEXT: ldr x9, [x11, #16] ; CHECK-NEXT: orr x0, x11, x10
; CHECK-NEXT: cbnz x11, .LBB1_1 ; CHECK-NEXT: cbnz x13, .LBB1_1
; CHECK-NEXT: // %bb.2: // %exit ; CHECK-NEXT: // %bb.2: // %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Context not available.

llvm/test/CodeGen/AArch64/bitfield-insert.ll

llvm/test/CodeGen/AArch64/bool-ext-inc.ll

llvm/test/CodeGen/AArch64/branch-relax-alignment.ll

llvm/test/CodeGen/AArch64/branch-relax-bcc.ll

llvm/test/CodeGen/AArch64/build-one-lane.ll

llvm/test/CodeGen/AArch64/build-vector-to-extract-subvec-crash.ll

llvm/test/CodeGen/AArch64/build-vector-two-dup.ll

llvm/test/CodeGen/AArch64/cgp-usubo.ll

llvm/test/CodeGen/AArch64/cmp-chains.ll

llvm/test/CodeGen/AArch64/cmp-select-sign.ll

llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll

llvm/test/CodeGen/AArch64/combine-andintoload.ll

llvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-fixed-contract.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-fixed-fast.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-contract.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add-scalable.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add-scalable.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul-scalable.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-add-scalable.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-add.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul-scalable.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-add-scalable.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-mul-scalable.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-i32-add-scalable.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-i32-mul-scalable.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-i64-add-scalable.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-i64-mul-scalable.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-i8-add-scalable.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-mixed-cases.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-splat.ll

llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll

llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll

llvm/test/CodeGen/AArch64/cond-br-tuning.ll

llvm/test/CodeGen/AArch64/consthoist-gep.ll

llvm/test/CodeGen/AArch64/copyprop.ll

llvm/test/CodeGen/AArch64/ctpop-nonean.ll

llvm/test/CodeGen/AArch64/dag-combine-concat-vectors.ll

llvm/test/CodeGen/AArch64/dag-combine-select.ll

llvm/test/CodeGen/AArch64/dag-combine-setcc.ll

llvm/test/CodeGen/AArch64/dag-numsignbits.ll

llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-signed.ll

llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-unsigned.ll

llvm/test/CodeGen/AArch64/double_reduct.ll

llvm/test/CodeGen/AArch64/expand-select.ll

llvm/test/CodeGen/AArch64/expand-vector-rot.ll

llvm/test/CodeGen/AArch64/extbinopload.ll

llvm/test/CodeGen/AArch64/extend_inreg_of_concat_subvectors.ll

llvm/test/CodeGen/AArch64/extract-bits.ll

llvm/test/CodeGen/AArch64/extract-lowbits.ll

llvm/test/CodeGen/AArch64/f16-instructions.ll

Context not available.
; CHECK-CVT-NEXT: fmov s2, #5.00000000 ; CHECK-CVT-NEXT: fmov s2, #5.00000000
; CHECK-CVT-NEXT: fcmp s1, s2 ; CHECK-CVT-NEXT: fcmp s1, s2
; CHECK-CVT-NEXT: fmov s2, #8.00000000 ; CHECK-CVT-NEXT: fmov s2, #8.00000000
; CHECK-CVT-NEXT: adrp x8
; CHECK-CVT-NEXT: fccmp s1, s2, #4, mi ; CHECK-CVT-NEXT: fccmp s1, s2, #4, mi
; CHECK-CVT-NEXT: adrp x8
; CHECK-CVT-NEXT: ldr h1, [x8, ; CHECK-CVT-NEXT: ldr h1, [x8,
; CHECK-CVT-NEXT: fcsel s0, s0, s1, gt ; CHECK-CVT-NEXT: fcsel s0, s0, s1, gt
; CHECK-CVT-NEXT: str h0, [x0] ; CHECK-CVT-NEXT: str h0, [x0]
Context not available.

llvm/test/CodeGen/AArch64/fabs.ll

llvm/test/CodeGen/AArch64/fadd-combines.ll

llvm/test/CodeGen/AArch64/faddp-half.ll

llvm/test/CodeGen/AArch64/faddp.ll

llvm/test/CodeGen/AArch64/fast-isel-addressing-modes.ll

llvm/test/CodeGen/AArch64/fast-isel-gep.ll

llvm/test/CodeGen/AArch64/fast-isel-memcpy.ll

llvm/test/CodeGen/AArch64/fast-isel-shift.ll

llvm/test/CodeGen/AArch64/fcopysign.ll

llvm/test/CodeGen/AArch64/fcvt.ll

llvm/test/CodeGen/AArch64/fcvt_combine.ll

llvm/test/CodeGen/AArch64/fdiv-combine.ll

llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll

llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll

llvm/test/CodeGen/AArch64/flags-multiuse.ll

llvm/test/CodeGen/AArch64/fmaximum-legalization.ll

llvm/test/CodeGen/AArch64/fminimummaximum.ll

llvm/test/CodeGen/AArch64/fminmax.ll

llvm/test/CodeGen/AArch64/fmlal-loreg.ll

Context not available.
; CHECK-LABEL: loop: ; CHECK-LABEL: loop:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov w8, w3
; CHECK-NEXT: movi v1.2d, #0000000000000000 ; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: mov w8, w3
; CHECK-NEXT: .LBB1_1: // %for.body ; CHECK-NEXT: .LBB1_1: // %for.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr q2, [x1], #2 ; CHECK-NEXT: ldr q2, [x1], #2
; CHECK-NEXT: ldr q3, [x2], #2
; CHECK-NEXT: subs x8, x8, #1 ; CHECK-NEXT: subs x8, x8, #1
; CHECK-NEXT: ldr q3, [x2], #2
; CHECK-NEXT: fmlal v0.4s, v3.4h, v2.h[0] ; CHECK-NEXT: fmlal v0.4s, v3.4h, v2.h[0]
; CHECK-NEXT: fmlal2 v1.4s, v3.4h, v2.h[0] ; CHECK-NEXT: fmlal2 v1.4s, v3.4h, v2.h[0]
; CHECK-NEXT: b.ne .LBB1_1 ; CHECK-NEXT: b.ne .LBB1_1
Context not available.
; CHECK-LABEL: sink: ; CHECK-LABEL: sink:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v1.2d, #0000000000000000 ; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: mov w8, w3
; CHECK-NEXT: movi v2.2d, #0000000000000000 ; CHECK-NEXT: movi v2.2d, #0000000000000000
; CHECK-NEXT: mov w8, w3
; CHECK-NEXT: .LBB2_1: // %for.body ; CHECK-NEXT: .LBB2_1: // %for.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr q3, [x2], #2 ; CHECK-NEXT: ldr q3, [x2], #2
Context not available.

llvm/test/CodeGen/AArch64/fold-csel-cttz-and.ll

llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll

llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll

llvm/test/CodeGen/AArch64/fp16-v16-instructions.ll

llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll

llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll

llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll

llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll

llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll

Context not available.
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov d1, v0.d[1] ; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: fcvtzu w8, d0 ; CHECK-NEXT: fcvtzu w8, d0
; CHECK-NEXT: fcvtzu w9, d1
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: fcvtzu w8, d1 ; CHECK-NEXT: mov v0.s[1], w9
; CHECK-NEXT: mov v0.s[1], w8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i32> @llvm.fptoui.sat.v2f64.v2i32(<2 x double> %f) %x = call <2 x i32> @llvm.fptoui.sat.v2f64.v2i32(<2 x double> %f)
Context not available.
; CHECK-LABEL: test_unsigned_v3f64_v3i32: ; CHECK-LABEL: test_unsigned_v3f64_v3i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu w8, d0 ; CHECK-NEXT: fcvtzu w8, d0
; CHECK-NEXT: fcvtzu w9, d1
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: fcvtzu w8, d1
; CHECK-NEXT: mov v0.s[1], w8
; CHECK-NEXT: fcvtzu w8, d2 ; CHECK-NEXT: fcvtzu w8, d2
; CHECK-NEXT: mov v0.s[1], w9
; CHECK-NEXT: mov v0.s[2], w8 ; CHECK-NEXT: mov v0.s[2], w8
; CHECK-NEXT: fcvtzu w8, d0 ; CHECK-NEXT: fcvtzu w8, d0
; CHECK-NEXT: mov v0.s[3], w8 ; CHECK-NEXT: mov v0.s[3], w8
Context not available.
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov d2, v0.d[1] ; CHECK-NEXT: mov d2, v0.d[1]
; CHECK-NEXT: fcvtzu w8, d0 ; CHECK-NEXT: fcvtzu w8, d0
; CHECK-NEXT: fcvtzu w9, d2
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: fcvtzu w8, d2
; CHECK-NEXT: mov v0.s[1], w8
; CHECK-NEXT: fcvtzu w8, d1 ; CHECK-NEXT: fcvtzu w8, d1
; CHECK-NEXT: mov d1, v1.d[1] ; CHECK-NEXT: mov d1, v1.d[1]
; CHECK-NEXT: mov v0.s[1], w9
; CHECK-NEXT: mov v0.s[2], w8 ; CHECK-NEXT: mov v0.s[2], w8
; CHECK-NEXT: fcvtzu w8, d1 ; CHECK-NEXT: fcvtzu w8, d1
; CHECK-NEXT: mov v0.s[3], w8 ; CHECK-NEXT: mov v0.s[3], w8
Context not available.
; CHECK-NEXT: adrp x8, .LCPI14_1 ; CHECK-NEXT: adrp x8, .LCPI14_1
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_1]
; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: cmp w0, #0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csinv w8, w19, wzr, le ; CHECK-NEXT: csinv w8, w19, wzr, le
Context not available.
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
; CHECK-NEXT: .cfi_offset w30, -32 ; CHECK-NEXT: .cfi_offset w30, -32
; CHECK-NEXT: adrp x8, .LCPI15_0
; CHECK-NEXT: stp q1, q0, [sp, #32] // 32-byte Folded Spill
; CHECK-NEXT: mov v2.16b, v1.16b ; CHECK-NEXT: mov v2.16b, v1.16b
; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: stp q1, q0, [sp, #32] // 32-byte Folded Spill
; CHECK-NEXT: adrp x8, .LCPI15_0
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_0]
; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: str q1, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
Context not available.
; CHECK-NEXT: adrp x8, .LCPI15_1 ; CHECK-NEXT: adrp x8, .LCPI15_1
; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_1]
; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csinv w20, w19, wzr, le ; CHECK-NEXT: csinv w20, w19, wzr, le
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixunstfsi ; CHECK-NEXT: bl __fixunstfsi
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, wzr, w0, lt ; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: cmp w0, #0 ; CHECK-NEXT: cmp w0, #0
Context not available.
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
; CHECK-NEXT: .cfi_offset w30, -32 ; CHECK-NEXT: .cfi_offset w30, -32
; CHECK-NEXT: adrp x8, .LCPI16_0
; CHECK-NEXT: stp q0, q2, [sp, #48] // 32-byte Folded Spill ; CHECK-NEXT: stp q0, q2, [sp, #48] // 32-byte Folded Spill
; CHECK-NEXT: mov v2.16b, v1.16b ; CHECK-NEXT: mov v2.16b, v1.16b
; CHECK-NEXT: adrp x8, .LCPI16_0
; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill
; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_0]
; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: str q1, [sp, #32] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp, #32] // 16-byte Folded Spill
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
Context not available.
; CHECK-NEXT: adrp x8, .LCPI16_1 ; CHECK-NEXT: adrp x8, .LCPI16_1
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: str q1, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload ; CHECK-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload
Context not available.
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixunstfsi ; CHECK-NEXT: bl __fixunstfsi
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, wzr, w0, lt ; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: cmp w0, #0 ; CHECK-NEXT: cmp w0, #0
Context not available.
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixunstfsi ; CHECK-NEXT: bl __fixunstfsi
; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, wzr, w0, lt ; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: cmp w0, #0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: csinv w8, w19, wzr, le
; CHECK-NEXT: ldr x30, [sp, #80] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #80] // 8-byte Folded Reload
; CHECK-NEXT: csinv w8, w19, wzr, le
; CHECK-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload
; CHECK-NEXT: mov v0.s[2], w8 ; CHECK-NEXT: mov v0.s[2], w8
; CHECK-NEXT: add sp, sp, #112 ; CHECK-NEXT: add sp, sp, #112
Context not available.
; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w20, -16 ; CHECK-NEXT: .cfi_offset w20, -16
; CHECK-NEXT: .cfi_offset w30, -32 ; CHECK-NEXT: .cfi_offset w30, -32
; CHECK-NEXT: adrp x8, .LCPI17_0
; CHECK-NEXT: stp q0, q2, [sp, #16] // 32-byte Folded Spill ; CHECK-NEXT: stp q0, q2, [sp, #16] // 32-byte Folded Spill
; CHECK-NEXT: mov v2.16b, v1.16b ; CHECK-NEXT: mov v2.16b, v1.16b
; CHECK-NEXT: adrp x8, .LCPI17_0
; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill
; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: str q3, [sp, #80] // 16-byte Folded Spill
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_0]
; CHECK-NEXT: str q3, [sp, #80] // 16-byte Folded Spill
; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: str q1, [sp, #64] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp, #64] // 16-byte Folded Spill
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
Context not available.
; CHECK-NEXT: adrp x8, .LCPI17_1 ; CHECK-NEXT: adrp x8, .LCPI17_1
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0 ; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_1]
; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: str q1, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: str q1, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: ldr q1, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csinv w20, w19, wzr, le ; CHECK-NEXT: csinv w20, w19, wzr, le
; CHECK-NEXT: bl __getf2 ; CHECK-NEXT: bl __getf2
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixunstfsi ; CHECK-NEXT: bl __fixunstfsi
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: ldr q1, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, wzr, w0, lt ; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: cmp w0, #0 ; CHECK-NEXT: cmp w0, #0
Context not available.
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl __fixunstfsi ; CHECK-NEXT: bl __fixunstfsi
; CHECK-NEXT: ldr q0, [sp, #80] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: ldr q1, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: cmp w19, #0
; CHECK-NEXT: csel w19, wzr, w0, lt ; CHECK-NEXT: csel w19, wzr, w0, lt
; CHECK-NEXT: bl __gttf2 ; CHECK-NEXT: bl __gttf2
; CHECK-NEXT: cmp w0, #0 ; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: csinv w8, w19, wzr, le
; CHECK-NEXT: ldr x30, [sp, #96] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #96] // 8-byte Folded Reload
; CHECK-NEXT: csinv w8, w19, wzr, le
; CHECK-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
; CHECK-NEXT: mov v0.s[3], w8 ; CHECK-NEXT: mov v0.s[3], w8
; CHECK-NEXT: add sp, sp, #128 ; CHECK-NEXT: add sp, sp, #128
Context not available.
; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: mov w1, v1.s[1] ; CHECK-NEXT: mov w1, v1.s[1]
; CHECK-NEXT: mov w2, v1.s[2] ; CHECK-NEXT: mov w2, v1.s[2]
; CHECK-NEXT: mov w3, v1.s[3]
; CHECK-NEXT: mov w5, v0.s[1] ; CHECK-NEXT: mov w5, v0.s[1]
; CHECK-NEXT: fmov w0, s1 ; CHECK-NEXT: mov w3, v1.s[3]
; CHECK-NEXT: fmov w4, s0 ; CHECK-NEXT: fmov w4, s0
; CHECK-NEXT: fmov w0, s1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <6 x i32> @llvm.fptoui.sat.v6f16.v6i32(<6 x half> %f) %x = call <6 x i32> @llvm.fptoui.sat.v6f16.v6i32(<6 x half> %f)
ret <6 x i32> %x ret <6 x i32> %x
Context not available.
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov s1, v0.s[1] ; CHECK-NEXT: mov s1, v0.s[1]
; CHECK-NEXT: fcvtzu x8, s0 ; CHECK-NEXT: fcvtzu x8, s0
; CHECK-NEXT: fcvtzu x9, s1
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: fcvtzu x8, s1 ; CHECK-NEXT: mov v0.d[1], x9
; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i64> @llvm.fptoui.sat.v2f32.v2i64(<2 x float> %f) %x = call <2 x i64> @llvm.fptoui.sat.v2f32.v2i64(<2 x float> %f)
ret <2 x i64> %x ret <2 x i64> %x
Context not available.
; CHECK-NEXT: mov w8, #1904214015 // =0x717fffff ; CHECK-NEXT: mov w8, #1904214015 // =0x717fffff
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
; CHECK-NEXT: mov x21, #68719476735 // =0xfffffffff ; CHECK-NEXT: mov x21, #68719476735 // =0xfffffffff
; CHECK-NEXT: fmov s9, w8
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: fmov s9, w8
; CHECK-NEXT: csel x8, xzr, x0, lt ; CHECK-NEXT: csel x8, xzr, x0, lt
; CHECK-NEXT: csel x9, xzr, x1, lt ; CHECK-NEXT: csel x9, xzr, x1, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
Context not available.
; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: csinv x8, x8, xzr, le ; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: csel x1, x21, x9, gt ; CHECK-NEXT: csel x1, x21, x9, gt
; CHECK-NEXT: ldp x30, x21, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ldp x30, x21, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #64 ; CHECK-NEXT: add sp, sp, #64
Context not available.
; CHECK-NEXT: mov w8, #2139095039 // =0x7f7fffff ; CHECK-NEXT: mov w8, #2139095039 // =0x7f7fffff
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: fmov s9, w8 ; CHECK-NEXT: fmov s9, w8
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: csel x8, xzr, x1, lt ; CHECK-NEXT: csel x8, xzr, x1, lt
; CHECK-NEXT: csel x9, xzr, x0, lt ; CHECK-NEXT: csel x9, xzr, x0, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
Context not available.
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: mov x2, x19 ; CHECK-NEXT: mov x2, x19
; CHECK-NEXT: mov x3, x20 ; CHECK-NEXT: mov x3, x20
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: fcmp s0, #0.0 ; CHECK-NEXT: fcmp s0, #0.0
; CHECK-NEXT: csel x8, xzr, x0, lt ; CHECK-NEXT: csel x8, xzr, x0, lt
; CHECK-NEXT: csel x9, xzr, x1, lt ; CHECK-NEXT: csel x9, xzr, x1, lt
Context not available.
; CHECK-LABEL: test_unsigned_v4f32_v4i50: ; CHECK-LABEL: test_unsigned_v4f32_v4i50:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
; CHECK-NEXT: mov s3, v0.s[1] ; CHECK-NEXT: mov s3, v0.s[1]
; CHECK-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
; CHECK-NEXT: fcvtzu x11, s0 ; CHECK-NEXT: fcvtzu x11, s0
; CHECK-NEXT: mov s2, v1.s[1] ; CHECK-NEXT: mov s2, v1.s[1]
; CHECK-NEXT: fcvtzu x9, s1 ; CHECK-NEXT: fcvtzu x9, s1
; CHECK-NEXT: fcvtzu x12, s3 ; CHECK-NEXT: fcvtzu x12, s3
; CHECK-NEXT: cmp x9, x8
; CHECK-NEXT: fcvtzu x10, s2 ; CHECK-NEXT: fcvtzu x10, s2
; CHECK-NEXT: cmp x9, x8
; CHECK-NEXT: csel x2, x9, x8, lo ; CHECK-NEXT: csel x2, x9, x8, lo
; CHECK-NEXT: cmp x10, x8 ; CHECK-NEXT: cmp x10, x8
; CHECK-NEXT: csel x3, x10, x8, lo ; CHECK-NEXT: csel x3, x10, x8, lo
Context not available.
; CHECK-NEXT: fcvtzu x9, s0 ; CHECK-NEXT: fcvtzu x9, s0
; CHECK-NEXT: mov s2, v1.s[1] ; CHECK-NEXT: mov s2, v1.s[1]
; CHECK-NEXT: fcvtzu x8, s1 ; CHECK-NEXT: fcvtzu x8, s1
; CHECK-NEXT: fcvtzu x11, s3
; CHECK-NEXT: fmov d0, x9 ; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: fcvtzu x9, s3 ; CHECK-NEXT: fcvtzu x10, s2
; CHECK-NEXT: fmov d1, x8 ; CHECK-NEXT: fmov d1, x8
; CHECK-NEXT: fcvtzu x8, s2 ; CHECK-NEXT: mov v0.d[1], x11
; CHECK-NEXT: mov v0.d[1], x9 ; CHECK-NEXT: mov v1.d[1], x10
; CHECK-NEXT: mov v1.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <4 x i64> @llvm.fptoui.sat.v4f32.v4i64(<4 x float> %f) %x = call <4 x i64> @llvm.fptoui.sat.v4f32.v4i64(<4 x float> %f)
ret <4 x i64> %x ret <4 x i64> %x
Context not available.
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: mov w8, #1904214015 // =0x717fffff ; CHECK-NEXT: mov w8, #1904214015 // =0x717fffff
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
; CHECK-NEXT: mov x25, #68719476735 // =0xfffffffff ; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: fmov s9, w8 ; CHECK-NEXT: fmov s9, w8
; CHECK-NEXT: mov x25, #68719476735 // =0xfffffffff
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: csel x8, xzr, x0, lt ; CHECK-NEXT: csel x8, xzr, x0, lt
; CHECK-NEXT: csel x9, xzr, x1, lt ; CHECK-NEXT: csel x9, xzr, x1, lt
Context not available.
; CHECK-NEXT: fcmp s0, #0.0 ; CHECK-NEXT: fcmp s0, #0.0
; CHECK-NEXT: mov x7, x23 ; CHECK-NEXT: mov x7, x23
; CHECK-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: csel x8, xzr, x0, lt ; CHECK-NEXT: csel x8, xzr, x0, lt
; CHECK-NEXT: csel x9, xzr, x1, lt ; CHECK-NEXT: csel x9, xzr, x1, lt
; CHECK-NEXT: fcmp s0, s9 ; CHECK-NEXT: fcmp s0, s9
; CHECK-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload ; CHECK-NEXT: ldp x24, x23, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: csinv x8, x8, xzr, le ; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: csel x1, x25, x9, gt ; CHECK-NEXT: csel x1, x25, x9, gt
; CHECK-NEXT: ldp x24, x23, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ldp x30, x25, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x25, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #112 ; CHECK-NEXT: add sp, sp, #112
; CHECK-NEXT: ret ; CHECK-NEXT: ret
Context not available.
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: mov w8, #2139095039 // =0x7f7fffff ; CHECK-NEXT: mov w8, #2139095039 // =0x7f7fffff
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: fmov s9, w8 ; CHECK-NEXT: fmov s9, w8
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: csel x8, xzr, x1, lt ; CHECK-NEXT: csel x8, xzr, x1, lt
Context not available.
; CHECK-NEXT: mov x6, x23 ; CHECK-NEXT: mov x6, x23
; CHECK-NEXT: fcmp s0, #0.0 ; CHECK-NEXT: fcmp s0, #0.0
; CHECK-NEXT: mov x7, x24 ; CHECK-NEXT: mov x7, x24
; CHECK-NEXT: ldr x30, [sp, #48] // 8-byte Folded Reload
; CHECK-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: csel x8, xzr, x0, lt ; CHECK-NEXT: csel x8, xzr, x0, lt
; CHECK-NEXT: csel x9, xzr, x1, lt ; CHECK-NEXT: csel x9, xzr, x1, lt
; CHECK-NEXT: fcmp s0, s9 ; CHECK-NEXT: fcmp s0, s9
; CHECK-NEXT: ldr x30, [sp, #48] // 8-byte Folded Reload ; CHECK-NEXT: ldp x24, x23, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: csinv x8, x8, xzr, le ; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: csinv x1, x9, xzr, le ; CHECK-NEXT: csinv x1, x9, xzr, le
; CHECK-NEXT: ldp x24, x23, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #112 ; CHECK-NEXT: add sp, sp, #112
Context not available.
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov d1, v0.d[1] ; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: fcvtzu w8, d0 ; CHECK-NEXT: fcvtzu w8, d0
; CHECK-NEXT: fcvtzu w9, d1
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: fcvtzu w8, d1 ; CHECK-NEXT: mov v0.s[1], w9
; CHECK-NEXT: mov v0.s[1], w8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <2 x i32> @llvm.fptoui.sat.v2f64.v2i32(<2 x double> %f) %x = call <2 x i32> @llvm.fptoui.sat.v2f64.v2i32(<2 x double> %f)
Context not available.
; CHECK-NEXT: mov x8, #5057542381537067007 // =0x462fffffffffffff ; CHECK-NEXT: mov x8, #5057542381537067007 // =0x462fffffffffffff
; CHECK-NEXT: fcmp d8, #0.0 ; CHECK-NEXT: fcmp d8, #0.0
; CHECK-NEXT: mov x21, #68719476735 // =0xfffffffff ; CHECK-NEXT: mov x21, #68719476735 // =0xfffffffff
; CHECK-NEXT: fmov d9, x8
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: fmov d9, x8
; CHECK-NEXT: csel x8, xzr, x0, lt ; CHECK-NEXT: csel x8, xzr, x0, lt
; CHECK-NEXT: csel x9, xzr, x1, lt ; CHECK-NEXT: csel x9, xzr, x1, lt
; CHECK-NEXT: fcmp d8, d9 ; CHECK-NEXT: fcmp d8, d9
Context not available.
; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: csinv x8, x8, xzr, le ; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: csel x1, x21, x9, gt ; CHECK-NEXT: csel x1, x21, x9, gt
; CHECK-NEXT: ldp x30, x21, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ldp x30, x21, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #64 ; CHECK-NEXT: add sp, sp, #64
Context not available.
; CHECK-NEXT: mov x8, #5183643171103440895 // =0x47efffffffffffff ; CHECK-NEXT: mov x8, #5183643171103440895 // =0x47efffffffffffff
; CHECK-NEXT: fcmp d8, #0.0 ; CHECK-NEXT: fcmp d8, #0.0
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: fmov d9, x8 ; CHECK-NEXT: fmov d9, x8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: csel x8, xzr, x1, lt ; CHECK-NEXT: csel x8, xzr, x1, lt
; CHECK-NEXT: csel x9, xzr, x0, lt ; CHECK-NEXT: csel x9, xzr, x0, lt
; CHECK-NEXT: fcmp d8, d9 ; CHECK-NEXT: fcmp d8, d9
Context not available.
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: mov x2, x19 ; CHECK-NEXT: mov x2, x19
; CHECK-NEXT: mov x3, x20 ; CHECK-NEXT: mov x3, x20
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: fcmp d0, #0.0 ; CHECK-NEXT: fcmp d0, #0.0
; CHECK-NEXT: csel x8, xzr, x0, lt ; CHECK-NEXT: csel x8, xzr, x0, lt
; CHECK-NEXT: csel x9, xzr, x1, lt ; CHECK-NEXT: csel x9, xzr, x1, lt
Context not available.
; CHECK-CVT-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-CVT-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-CVT-NEXT: mov h1, v0.h[1] ; CHECK-CVT-NEXT: mov h1, v0.h[1]
; CHECK-CVT-NEXT: mov h2, v0.h[2] ; CHECK-CVT-NEXT: mov h2, v0.h[2]
; CHECK-CVT-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
; CHECK-CVT-NEXT: mov h3, v0.h[3] ; CHECK-CVT-NEXT: mov h3, v0.h[3]
; CHECK-CVT-NEXT: fcvt s0, h0 ; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcvtzu x9, s0 ; CHECK-CVT-NEXT: fcvtzu x9, s0
; CHECK-CVT-NEXT: fcvtzu x10, s1 ; CHECK-CVT-NEXT: fcvtzu x10, s1
; CHECK-CVT-NEXT: fcvtzu x11, s2 ; CHECK-CVT-NEXT: fcvtzu x11, s2
; CHECK-CVT-NEXT: cmp x9, x8
; CHECK-CVT-NEXT: fcvtzu x12, s3 ; CHECK-CVT-NEXT: fcvtzu x12, s3
; CHECK-CVT-NEXT: cmp x9, x8
; CHECK-CVT-NEXT: csel x0, x9, x8, lo ; CHECK-CVT-NEXT: csel x0, x9, x8, lo
; CHECK-CVT-NEXT: cmp x10, x8 ; CHECK-CVT-NEXT: cmp x10, x8
; CHECK-CVT-NEXT: csel x1, x10, x8, lo ; CHECK-CVT-NEXT: csel x1, x10, x8, lo
Context not available.
; CHECK-FP16-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-FP16-NEXT: mov h1, v0.h[1] ; CHECK-FP16-NEXT: mov h1, v0.h[1]
; CHECK-FP16-NEXT: mov h2, v0.h[2] ; CHECK-FP16-NEXT: mov h2, v0.h[2]
; CHECK-FP16-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
; CHECK-FP16-NEXT: mov h3, v0.h[3] ; CHECK-FP16-NEXT: mov h3, v0.h[3]
; CHECK-FP16-NEXT: fcvtzu x9, h0 ; CHECK-FP16-NEXT: fcvtzu x9, h0
; CHECK-FP16-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
; CHECK-FP16-NEXT: fcvtzu x10, h1 ; CHECK-FP16-NEXT: fcvtzu x10, h1
; CHECK-FP16-NEXT: fcvtzu x11, h2 ; CHECK-FP16-NEXT: fcvtzu x11, h2
; CHECK-FP16-NEXT: cmp x9, x8
; CHECK-FP16-NEXT: fcvtzu x12, h3 ; CHECK-FP16-NEXT: fcvtzu x12, h3
; CHECK-FP16-NEXT: cmp x9, x8
; CHECK-FP16-NEXT: csel x0, x9, x8, lo ; CHECK-FP16-NEXT: csel x0, x9, x8, lo
; CHECK-FP16-NEXT: cmp x10, x8 ; CHECK-FP16-NEXT: cmp x10, x8
; CHECK-FP16-NEXT: csel x1, x10, x8, lo ; CHECK-FP16-NEXT: csel x1, x10, x8, lo
Context not available.
; CHECK-CVT-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-CVT-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-CVT-NEXT: mov h1, v0.h[2] ; CHECK-CVT-NEXT: mov h1, v0.h[2]
; CHECK-CVT-NEXT: mov h2, v0.h[1] ; CHECK-CVT-NEXT: mov h2, v0.h[1]
; CHECK-CVT-NEXT: fcvt s3, h0 ; CHECK-CVT-NEXT: mov h3, v0.h[3]
; CHECK-CVT-NEXT: mov h0, v0.h[3] ; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvtzu x8, s3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcvt s3, h0 ; CHECK-CVT-NEXT: fcvtzu x8, s0
; CHECK-CVT-NEXT: fcvtzu x9, s1 ; CHECK-CVT-NEXT: fcvtzu x9, s1
; CHECK-CVT-NEXT: fcvtzu x10, s2
; CHECK-CVT-NEXT: fcvtzu x11, s3
; CHECK-CVT-NEXT: fmov d0, x8 ; CHECK-CVT-NEXT: fmov d0, x8
; CHECK-CVT-NEXT: fcvtzu x8, s2
; CHECK-CVT-NEXT: fmov d1, x9 ; CHECK-CVT-NEXT: fmov d1, x9
; CHECK-CVT-NEXT: fcvtzu x9, s3 ; CHECK-CVT-NEXT: mov v0.d[1], x10
; CHECK-CVT-NEXT: mov v0.d[1], x8 ; CHECK-CVT-NEXT: mov v1.d[1], x11
; CHECK-CVT-NEXT: mov v1.d[1], x9
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_unsigned_v4f16_v4i64: ; CHECK-FP16-LABEL: test_unsigned_v4f16_v4i64:
Context not available.
; CHECK-FP16-NEXT: mov h3, v0.h[3] ; CHECK-FP16-NEXT: mov h3, v0.h[3]
; CHECK-FP16-NEXT: fcvtzu x8, h0 ; CHECK-FP16-NEXT: fcvtzu x8, h0
; CHECK-FP16-NEXT: fcvtzu x9, h1 ; CHECK-FP16-NEXT: fcvtzu x9, h1
; CHECK-FP16-NEXT: fcvtzu x10, h2
; CHECK-FP16-NEXT: fcvtzu x11, h3
; CHECK-FP16-NEXT: fmov d0, x8 ; CHECK-FP16-NEXT: fmov d0, x8
; CHECK-FP16-NEXT: fcvtzu x8, h2
; CHECK-FP16-NEXT: fmov d1, x9 ; CHECK-FP16-NEXT: fmov d1, x9
; CHECK-FP16-NEXT: fcvtzu x9, h3 ; CHECK-FP16-NEXT: mov v0.d[1], x10
; CHECK-FP16-NEXT: mov v0.d[1], x8 ; CHECK-FP16-NEXT: mov v1.d[1], x11
; CHECK-FP16-NEXT: mov v1.d[1], x9
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%x = call <4 x i64> @llvm.fptoui.sat.v4f16.v4i64(<4 x half> %f) %x = call <4 x i64> @llvm.fptoui.sat.v4f16.v4i64(<4 x half> %f)
ret <4 x i64> %x ret <4 x i64> %x
Context not available.
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: mov w8, #1904214015 // =0x717fffff ; CHECK-NEXT: mov w8, #1904214015 // =0x717fffff
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
; CHECK-NEXT: fmov s9, w8
; CHECK-NEXT: mov x25, #68719476735 // =0xfffffffff ; CHECK-NEXT: mov x25, #68719476735 // =0xfffffffff
; CHECK-NEXT: mov h0, v0.h[1] ; CHECK-NEXT: mov h0, v0.h[1]
; CHECK-NEXT: fmov s9, w8 ; CHECK-NEXT: csel x9, xzr, x0, lt
; CHECK-NEXT: csel x8, xzr, x0, lt ; CHECK-NEXT: csel x8, xzr, x1, lt
; CHECK-NEXT: csel x9, xzr, x1, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
; CHECK-NEXT: csel x19, x25, x9, gt ; CHECK-NEXT: csel x19, x25, x8, gt
; CHECK-NEXT: csinv x20, x8, xzr, le ; CHECK-NEXT: csinv x20, x9, xzr, le
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
Context not available.
; CHECK-NEXT: mov x4, x20 ; CHECK-NEXT: mov x4, x20
; CHECK-NEXT: mov x5, x19 ; CHECK-NEXT: mov x5, x19
; CHECK-NEXT: mov x6, x24 ; CHECK-NEXT: mov x6, x24
; CHECK-NEXT: mov x7, x23
; CHECK-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: csel x8, xzr, x0, lt ; CHECK-NEXT: csel x8, xzr, x0, lt
; CHECK-NEXT: csel x9, xzr, x1, lt ; CHECK-NEXT: csel x9, xzr, x1, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: mov x7, x23 ; CHECK-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload ; CHECK-NEXT: ldp x24, x23, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: csinv x8, x8, xzr, le ; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: csel x1, x25, x9, gt ; CHECK-NEXT: csel x1, x25, x9, gt
; CHECK-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ldp x24, x23, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: ldp x30, x25, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldp x30, x25, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #96 ; CHECK-NEXT: add sp, sp, #96
; CHECK-NEXT: ret ; CHECK-NEXT: ret
Context not available.
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: mov w8, #2139095039 // =0x7f7fffff ; CHECK-NEXT: mov w8, #2139095039 // =0x7f7fffff
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
; CHECK-NEXT: mov h0, v0.h[2]
; CHECK-NEXT: fmov s9, w8 ; CHECK-NEXT: fmov s9, w8
; CHECK-NEXT: csel x8, xzr, x1, lt ; CHECK-NEXT: mov h0, v0.h[2]
; CHECK-NEXT: csel x9, xzr, x0, lt ; CHECK-NEXT: csel x9, xzr, x1, lt
; CHECK-NEXT: csel x8, xzr, x0, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
; CHECK-NEXT: csinv x19, x9, xzr, le ; CHECK-NEXT: csinv x19, x8, xzr, le
; CHECK-NEXT: csinv x20, x8, xzr, le ; CHECK-NEXT: csinv x20, x9, xzr, le
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
Context not available.
; CHECK-NEXT: mov x4, x21 ; CHECK-NEXT: mov x4, x21
; CHECK-NEXT: mov x5, x22 ; CHECK-NEXT: mov x5, x22
; CHECK-NEXT: mov x6, x23 ; CHECK-NEXT: mov x6, x23
; CHECK-NEXT: mov x7, x24
; CHECK-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: csel x8, xzr, x0, lt ; CHECK-NEXT: csel x8, xzr, x0, lt
; CHECK-NEXT: csel x9, xzr, x1, lt ; CHECK-NEXT: csel x9, xzr, x1, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: mov x7, x24
; CHECK-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: csinv x1, x9, xzr, le
; CHECK-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: ldp x24, x23, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldp x24, x23, [sp, #48] // 16-byte Folded Reload
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: csinv x1, x9, xzr, le
; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: add sp, sp, #96 ; CHECK-NEXT: add sp, sp, #96
; CHECK-NEXT: ret ; CHECK-NEXT: ret
Context not available.
; CHECK-CVT-NEXT: mov s2, v1.s[1] ; CHECK-CVT-NEXT: mov s2, v1.s[1]
; CHECK-CVT-NEXT: mov s3, v1.s[2] ; CHECK-CVT-NEXT: mov s3, v1.s[2]
; CHECK-CVT-NEXT: mov s4, v1.s[3] ; CHECK-CVT-NEXT: mov s4, v1.s[3]
; CHECK-CVT-NEXT: mov s5, v0.s[1]
; CHECK-CVT-NEXT: fcvtzu w9, s1 ; CHECK-CVT-NEXT: fcvtzu w9, s1
; CHECK-CVT-NEXT: fcvtzu w10, s0 ; CHECK-CVT-NEXT: fcvtzu w13, s0
; CHECK-CVT-NEXT: mov s1, v0.s[2] ; CHECK-CVT-NEXT: mov s1, v0.s[2]
; CHECK-CVT-NEXT: mov s0, v0.s[3]
; CHECK-CVT-NEXT: fcvtzu w8, s2 ; CHECK-CVT-NEXT: fcvtzu w8, s2
; CHECK-CVT-NEXT: fcvtzu w11, s3 ; CHECK-CVT-NEXT: mov s2, v0.s[1]
; CHECK-CVT-NEXT: fcvtzu w12, s4 ; CHECK-CVT-NEXT: fcvtzu w10, s3
; CHECK-CVT-NEXT: fcvtzu w13, s5 ; CHECK-CVT-NEXT: fcvtzu w11, s4
; CHECK-CVT-NEXT: fcvtzu w14, s1
; CHECK-CVT-NEXT: mov s0, v0.s[3]
; CHECK-CVT-NEXT: cmp w8, #1 ; CHECK-CVT-NEXT: cmp w8, #1
; CHECK-CVT-NEXT: fcvtzu w12, s2
; CHECK-CVT-NEXT: csinc w8, w8, wzr, lo ; CHECK-CVT-NEXT: csinc w8, w8, wzr, lo
; CHECK-CVT-NEXT: cmp w9, #1 ; CHECK-CVT-NEXT: cmp w9, #1
; CHECK-CVT-NEXT: csinc w9, w9, wzr, lo ; CHECK-CVT-NEXT: csinc w9, w9, wzr, lo
; CHECK-CVT-NEXT: cmp w10, #1
; CHECK-CVT-NEXT: csinc w10, w10, wzr, lo
; CHECK-CVT-NEXT: cmp w11, #1 ; CHECK-CVT-NEXT: cmp w11, #1
; CHECK-CVT-NEXT: fmov s1, w9
; CHECK-CVT-NEXT: csinc w11, w11, wzr, lo ; CHECK-CVT-NEXT: csinc w11, w11, wzr, lo
; CHECK-CVT-NEXT: cmp w12, #1 ; CHECK-CVT-NEXT: cmp w12, #1
; CHECK-CVT-NEXT: csinc w12, w12, wzr, lo ; CHECK-CVT-NEXT: csinc w12, w12, wzr, lo
; CHECK-CVT-NEXT: cmp w13, #1 ; CHECK-CVT-NEXT: cmp w13, #1
; CHECK-CVT-NEXT: csinc w13, w13, wzr, lo ; CHECK-CVT-NEXT: csinc w13, w13, wzr, lo
; CHECK-CVT-NEXT: cmp w10, #1 ; CHECK-CVT-NEXT: mov v1.s[1], w8
; CHECK-CVT-NEXT: csinc w10, w10, wzr, lo ; CHECK-CVT-NEXT: cmp w14, #1
; CHECK-CVT-NEXT: fmov s2, w9 ; CHECK-CVT-NEXT: fmov s2, w13
; CHECK-CVT-NEXT: fcvtzu w9, s1 ; CHECK-CVT-NEXT: fcvtzu w8, s0
; CHECK-CVT-NEXT: fmov s3, w10 ; CHECK-CVT-NEXT: csinc w9, w14, wzr, lo
; CHECK-CVT-NEXT: mov v2.s[1], w8 ; CHECK-CVT-NEXT: mov v2.s[1], w12
; CHECK-CVT-NEXT: cmp w9, #1 ; CHECK-CVT-NEXT: mov v1.s[2], w10
; CHECK-CVT-NEXT: csinc w8, w9, wzr, lo ; CHECK-CVT-NEXT: cmp w8, #1
; CHECK-CVT-NEXT: fcvtzu w9, s0 ; CHECK-CVT-NEXT: csinc w8, w8, wzr, lo
; CHECK-CVT-NEXT: mov v3.s[1], w13 ; CHECK-CVT-NEXT: mov v2.s[2], w9
; CHECK-CVT-NEXT: mov v2.s[2], w11 ; CHECK-CVT-NEXT: mov v1.s[3], w11
; CHECK-CVT-NEXT: cmp w9, #1 ; CHECK-CVT-NEXT: mov v2.s[3], w8
; CHECK-CVT-NEXT: mov v3.s[2], w8 ; CHECK-CVT-NEXT: uzp1 v0.8h, v2.8h, v1.8h
; CHECK-CVT-NEXT: csinc w8, w9, wzr, lo
; CHECK-CVT-NEXT: mov v2.s[3], w12
; CHECK-CVT-NEXT: mov v3.s[3], w8
; CHECK-CVT-NEXT: uzp1 v0.8h, v3.8h, v2.8h
; CHECK-CVT-NEXT: xtn v0.8b, v0.8h ; CHECK-CVT-NEXT: xtn v0.8b, v0.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
Context not available.
; CHECK-CVT-NEXT: mov s2, v1.s[1] ; CHECK-CVT-NEXT: mov s2, v1.s[1]
; CHECK-CVT-NEXT: mov s3, v1.s[2] ; CHECK-CVT-NEXT: mov s3, v1.s[2]
; CHECK-CVT-NEXT: mov s4, v1.s[3] ; CHECK-CVT-NEXT: mov s4, v1.s[3]
; CHECK-CVT-NEXT: mov s5, v0.s[1]
; CHECK-CVT-NEXT: fcvtzu w10, s1 ; CHECK-CVT-NEXT: fcvtzu w10, s1
; CHECK-CVT-NEXT: fcvtzu w11, s0 ; CHECK-CVT-NEXT: fcvtzu w14, s0
; CHECK-CVT-NEXT: mov s1, v0.s[2] ; CHECK-CVT-NEXT: mov s1, v0.s[2]
; CHECK-CVT-NEXT: mov s0, v0.s[3]
; CHECK-CVT-NEXT: fcvtzu w9, s2 ; CHECK-CVT-NEXT: fcvtzu w9, s2
; CHECK-CVT-NEXT: fcvtzu w12, s3 ; CHECK-CVT-NEXT: mov s2, v0.s[1]
; CHECK-CVT-NEXT: fcvtzu w13, s4 ; CHECK-CVT-NEXT: fcvtzu w11, s3
; CHECK-CVT-NEXT: fcvtzu w14, s5 ; CHECK-CVT-NEXT: fcvtzu w12, s4
; CHECK-CVT-NEXT: fcvtzu w15, s1
; CHECK-CVT-NEXT: mov s0, v0.s[3]
; CHECK-CVT-NEXT: cmp w9, #255 ; CHECK-CVT-NEXT: cmp w9, #255
; CHECK-CVT-NEXT: fcvtzu w13, s2
; CHECK-CVT-NEXT: csel w9, w9, w8, lo ; CHECK-CVT-NEXT: csel w9, w9, w8, lo
; CHECK-CVT-NEXT: cmp w10, #255 ; CHECK-CVT-NEXT: cmp w10, #255
; CHECK-CVT-NEXT: csel w10, w10, w8, lo ; CHECK-CVT-NEXT: csel w10, w10, w8, lo
; CHECK-CVT-NEXT: cmp w11, #255
; CHECK-CVT-NEXT: csel w11, w11, w8, lo
; CHECK-CVT-NEXT: cmp w12, #255 ; CHECK-CVT-NEXT: cmp w12, #255
; CHECK-CVT-NEXT: fmov s1, w10
; CHECK-CVT-NEXT: csel w12, w12, w8, lo ; CHECK-CVT-NEXT: csel w12, w12, w8, lo
; CHECK-CVT-NEXT: cmp w13, #255 ; CHECK-CVT-NEXT: cmp w13, #255
; CHECK-CVT-NEXT: csel w13, w13, w8, lo ; CHECK-CVT-NEXT: csel w13, w13, w8, lo
; CHECK-CVT-NEXT: cmp w14, #255 ; CHECK-CVT-NEXT: cmp w14, #255
; CHECK-CVT-NEXT: csel w14, w14, w8, lo ; CHECK-CVT-NEXT: csel w14, w14, w8, lo
; CHECK-CVT-NEXT: cmp w11, #255 ; CHECK-CVT-NEXT: mov v1.s[1], w9
; CHECK-CVT-NEXT: csel w11, w11, w8, lo ; CHECK-CVT-NEXT: cmp w15, #255
; CHECK-CVT-NEXT: fmov s2, w10 ; CHECK-CVT-NEXT: fmov s2, w14
; CHECK-CVT-NEXT: fcvtzu w10, s1 ; CHECK-CVT-NEXT: fcvtzu w9, s0
; CHECK-CVT-NEXT: fmov s3, w11 ; CHECK-CVT-NEXT: csel w10, w15, w8, lo
; CHECK-CVT-NEXT: mov v2.s[1], w9 ; CHECK-CVT-NEXT: mov v2.s[1], w13
; CHECK-CVT-NEXT: cmp w10, #255 ; CHECK-CVT-NEXT: mov v1.s[2], w11
; CHECK-CVT-NEXT: csel w9, w10, w8, lo ; CHECK-CVT-NEXT: cmp w9, #255
; CHECK-CVT-NEXT: fcvtzu w10, s0 ; CHECK-CVT-NEXT: csel w8, w9, w8, lo
; CHECK-CVT-NEXT: mov v3.s[1], w14 ; CHECK-CVT-NEXT: mov v2.s[2], w10
; CHECK-CVT-NEXT: mov v2.s[2], w12 ; CHECK-CVT-NEXT: mov v1.s[3], w12
; CHECK-CVT-NEXT: cmp w10, #255 ; CHECK-CVT-NEXT: mov v2.s[3], w8
; CHECK-CVT-NEXT: csel w8, w10, w8, lo ; CHECK-CVT-NEXT: uzp1 v0.8h, v2.8h, v1.8h
; CHECK-CVT-NEXT: mov v3.s[2], w9
; CHECK-CVT-NEXT: mov v2.s[3], w13
; CHECK-CVT-NEXT: mov v3.s[3], w8
; CHECK-CVT-NEXT: uzp1 v0.8h, v3.8h, v2.8h
; CHECK-CVT-NEXT: xtn v0.8b, v0.8h ; CHECK-CVT-NEXT: xtn v0.8b, v0.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
Context not available.
; CHECK-CVT-NEXT: mov s2, v1.s[1] ; CHECK-CVT-NEXT: mov s2, v1.s[1]
; CHECK-CVT-NEXT: mov s3, v1.s[2] ; CHECK-CVT-NEXT: mov s3, v1.s[2]
; CHECK-CVT-NEXT: mov s4, v1.s[3] ; CHECK-CVT-NEXT: mov s4, v1.s[3]
; CHECK-CVT-NEXT: mov s5, v0.s[1]
; CHECK-CVT-NEXT: fcvtzu w10, s1 ; CHECK-CVT-NEXT: fcvtzu w10, s1
; CHECK-CVT-NEXT: fcvtzu w11, s0 ; CHECK-CVT-NEXT: fcvtzu w14, s0
; CHECK-CVT-NEXT: mov s1, v0.s[2] ; CHECK-CVT-NEXT: mov s1, v0.s[2]
; CHECK-CVT-NEXT: mov s0, v0.s[3]
; CHECK-CVT-NEXT: fcvtzu w9, s2 ; CHECK-CVT-NEXT: fcvtzu w9, s2
; CHECK-CVT-NEXT: fcvtzu w12, s3 ; CHECK-CVT-NEXT: mov s2, v0.s[1]
; CHECK-CVT-NEXT: fcvtzu w13, s4 ; CHECK-CVT-NEXT: fcvtzu w11, s3
; CHECK-CVT-NEXT: fcvtzu w14, s5 ; CHECK-CVT-NEXT: fcvtzu w12, s4
; CHECK-CVT-NEXT: fcvtzu w15, s1
; CHECK-CVT-NEXT: mov s0, v0.s[3]
; CHECK-CVT-NEXT: cmp w9, w8 ; CHECK-CVT-NEXT: cmp w9, w8
; CHECK-CVT-NEXT: fcvtzu w13, s2
; CHECK-CVT-NEXT: csel w9, w9, w8, lo ; CHECK-CVT-NEXT: csel w9, w9, w8, lo
; CHECK-CVT-NEXT: cmp w10, w8 ; CHECK-CVT-NEXT: cmp w10, w8
; CHECK-CVT-NEXT: csel w10, w10, w8, lo ; CHECK-CVT-NEXT: csel w10, w10, w8, lo
; CHECK-CVT-NEXT: cmp w11, w8
; CHECK-CVT-NEXT: csel w11, w11, w8, lo
; CHECK-CVT-NEXT: cmp w12, w8 ; CHECK-CVT-NEXT: cmp w12, w8
; CHECK-CVT-NEXT: fmov s1, w10
; CHECK-CVT-NEXT: csel w12, w12, w8, lo ; CHECK-CVT-NEXT: csel w12, w12, w8, lo
; CHECK-CVT-NEXT: cmp w13, w8 ; CHECK-CVT-NEXT: cmp w13, w8
; CHECK-CVT-NEXT: csel w13, w13, w8, lo ; CHECK-CVT-NEXT: csel w13, w13, w8, lo
; CHECK-CVT-NEXT: cmp w14, w8 ; CHECK-CVT-NEXT: cmp w14, w8
; CHECK-CVT-NEXT: csel w14, w14, w8, lo ; CHECK-CVT-NEXT: csel w14, w14, w8, lo
; CHECK-CVT-NEXT: cmp w11, w8 ; CHECK-CVT-NEXT: mov v1.s[1], w9
; CHECK-CVT-NEXT: csel w11, w11, w8, lo ; CHECK-CVT-NEXT: cmp w15, w8
; CHECK-CVT-NEXT: fmov s2, w10 ; CHECK-CVT-NEXT: fmov s2, w14
; CHECK-CVT-NEXT: fcvtzu w10, s1 ; CHECK-CVT-NEXT: fcvtzu w9, s0
; CHECK-CVT-NEXT: fmov s3, w11 ; CHECK-CVT-NEXT: csel w10, w15, w8, lo
; CHECK-CVT-NEXT: mov v2.s[1], w9 ; CHECK-CVT-NEXT: mov v2.s[1], w13
; CHECK-CVT-NEXT: cmp w10, w8 ; CHECK-CVT-NEXT: mov v1.s[2], w11
; CHECK-CVT-NEXT: csel w9, w10, w8, lo ; CHECK-CVT-NEXT: cmp w9, w8
; CHECK-CVT-NEXT: fcvtzu w10, s0 ; CHECK-CVT-NEXT: csel w8, w9, w8, lo
; CHECK-CVT-NEXT: mov v3.s[1], w14 ; CHECK-CVT-NEXT: mov v2.s[2], w10
; CHECK-CVT-NEXT: mov v2.s[2], w12 ; CHECK-CVT-NEXT: mov v1.s[3], w12
; CHECK-CVT-NEXT: cmp w10, w8 ; CHECK-CVT-NEXT: mov v2.s[3], w8
; CHECK-CVT-NEXT: csel w8, w10, w8, lo ; CHECK-CVT-NEXT: uzp1 v0.8h, v2.8h, v1.8h
; CHECK-CVT-NEXT: mov v3.s[2], w9
; CHECK-CVT-NEXT: mov v2.s[3], w13
; CHECK-CVT-NEXT: mov v3.s[3], w8
; CHECK-CVT-NEXT: uzp1 v0.8h, v3.8h, v2.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i13: ; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i13:
Context not available.
; CHECK-CVT-NEXT: mov s2, v1.s[1] ; CHECK-CVT-NEXT: mov s2, v1.s[1]
; CHECK-CVT-NEXT: mov s3, v1.s[2] ; CHECK-CVT-NEXT: mov s3, v1.s[2]
; CHECK-CVT-NEXT: mov s4, v1.s[3] ; CHECK-CVT-NEXT: mov s4, v1.s[3]
; CHECK-CVT-NEXT: mov s5, v0.s[1]
; CHECK-CVT-NEXT: fcvtzu w10, s1 ; CHECK-CVT-NEXT: fcvtzu w10, s1
; CHECK-CVT-NEXT: fcvtzu w11, s0 ; CHECK-CVT-NEXT: fcvtzu w14, s0
; CHECK-CVT-NEXT: mov s1, v0.s[2] ; CHECK-CVT-NEXT: mov s1, v0.s[2]
; CHECK-CVT-NEXT: mov s0, v0.s[3]
; CHECK-CVT-NEXT: fcvtzu w9, s2 ; CHECK-CVT-NEXT: fcvtzu w9, s2
; CHECK-CVT-NEXT: fcvtzu w12, s3 ; CHECK-CVT-NEXT: mov s2, v0.s[1]
; CHECK-CVT-NEXT: fcvtzu w13, s4 ; CHECK-CVT-NEXT: fcvtzu w11, s3
; CHECK-CVT-NEXT: fcvtzu w14, s5 ; CHECK-CVT-NEXT: fcvtzu w12, s4
; CHECK-CVT-NEXT: fcvtzu w15, s1
; CHECK-CVT-NEXT: mov s0, v0.s[3]
; CHECK-CVT-NEXT: cmp w9, w8 ; CHECK-CVT-NEXT: cmp w9, w8
; CHECK-CVT-NEXT: fcvtzu w13, s2
; CHECK-CVT-NEXT: csel w9, w9, w8, lo ; CHECK-CVT-NEXT: csel w9, w9, w8, lo
; CHECK-CVT-NEXT: cmp w10, w8 ; CHECK-CVT-NEXT: cmp w10, w8
; CHECK-CVT-NEXT: csel w10, w10, w8, lo ; CHECK-CVT-NEXT: csel w10, w10, w8, lo
; CHECK-CVT-NEXT: cmp w11, w8
; CHECK-CVT-NEXT: csel w11, w11, w8, lo
; CHECK-CVT-NEXT: cmp w12, w8 ; CHECK-CVT-NEXT: cmp w12, w8
; CHECK-CVT-NEXT: fmov s1, w10
; CHECK-CVT-NEXT: csel w12, w12, w8, lo ; CHECK-CVT-NEXT: csel w12, w12, w8, lo
; CHECK-CVT-NEXT: cmp w13, w8 ; CHECK-CVT-NEXT: cmp w13, w8
; CHECK-CVT-NEXT: csel w13, w13, w8, lo ; CHECK-CVT-NEXT: csel w13, w13, w8, lo
; CHECK-CVT-NEXT: cmp w14, w8 ; CHECK-CVT-NEXT: cmp w14, w8
; CHECK-CVT-NEXT: csel w14, w14, w8, lo ; CHECK-CVT-NEXT: csel w14, w14, w8, lo
; CHECK-CVT-NEXT: cmp w11, w8 ; CHECK-CVT-NEXT: mov v1.s[1], w9
; CHECK-CVT-NEXT: csel w11, w11, w8, lo ; CHECK-CVT-NEXT: cmp w15, w8
; CHECK-CVT-NEXT: fmov s2, w10 ; CHECK-CVT-NEXT: fmov s2, w14
; CHECK-CVT-NEXT: fcvtzu w10, s1 ; CHECK-CVT-NEXT: fcvtzu w9, s0
; CHECK-CVT-NEXT: fmov s3, w11 ; CHECK-CVT-NEXT: csel w10, w15, w8, lo
; CHECK-CVT-NEXT: mov v2.s[1], w9 ; CHECK-CVT-NEXT: mov v2.s[1], w13
; CHECK-CVT-NEXT: cmp w10, w8 ; CHECK-CVT-NEXT: mov v1.s[2], w11
; CHECK-CVT-NEXT: csel w9, w10, w8, lo ; CHECK-CVT-NEXT: cmp w9, w8
; CHECK-CVT-NEXT: fcvtzu w10, s0 ; CHECK-CVT-NEXT: csel w8, w9, w8, lo
; CHECK-CVT-NEXT: mov v3.s[1], w14 ; CHECK-CVT-NEXT: mov v2.s[2], w10
; CHECK-CVT-NEXT: mov v2.s[2], w12 ; CHECK-CVT-NEXT: mov v1.s[3], w12
; CHECK-CVT-NEXT: cmp w10, w8 ; CHECK-CVT-NEXT: mov v2.s[3], w8
; CHECK-CVT-NEXT: csel w8, w10, w8, lo ; CHECK-CVT-NEXT: uzp1 v0.8h, v2.8h, v1.8h
; CHECK-CVT-NEXT: mov v3.s[2], w9
; CHECK-CVT-NEXT: mov v2.s[3], w13
; CHECK-CVT-NEXT: mov v3.s[3], w8
; CHECK-CVT-NEXT: uzp1 v0.8h, v3.8h, v2.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i16: ; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i16:
Context not available.
; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s ; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
; CHECK-NEXT: mov w1, v2.s[1] ; CHECK-NEXT: mov w1, v2.s[1]
; CHECK-NEXT: mov w2, v2.s[2] ; CHECK-NEXT: mov w2, v2.s[2]
; CHECK-NEXT: mov w5, v0.s[1]
; CHECK-NEXT: mov w3, v2.s[3] ; CHECK-NEXT: mov w3, v2.s[3]
; CHECK-NEXT: mov w5, v0.s[1]
; CHECK-NEXT: mov w6, v0.s[2] ; CHECK-NEXT: mov w6, v0.s[2]
; CHECK-NEXT: mov w7, v0.s[3] ; CHECK-NEXT: mov w7, v0.s[3]
; CHECK-NEXT: fmov w4, s0 ; CHECK-NEXT: fmov w4, s0
Context not available.
; CHECK-CVT-LABEL: test_unsigned_v8f16_v8i50: ; CHECK-CVT-LABEL: test_unsigned_v8f16_v8i50:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-CVT-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-CVT-NEXT: mov h5, v0.h[1]
; CHECK-CVT-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff ; CHECK-CVT-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
; CHECK-CVT-NEXT: mov h2, v0.h[1] ; CHECK-CVT-NEXT: mov h6, v0.h[2]
; CHECK-CVT-NEXT: mov h3, v0.h[2] ; CHECK-CVT-NEXT: mov h7, v0.h[3]
; CHECK-CVT-NEXT: mov h5, v0.h[3]
; CHECK-CVT-NEXT: fcvt s0, h0 ; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov h4, v1.h[1] ; CHECK-CVT-NEXT: mov h2, v1.h[1]
; CHECK-CVT-NEXT: mov h6, v1.h[2] ; CHECK-CVT-NEXT: mov h3, v1.h[2]
; CHECK-CVT-NEXT: mov h7, v1.h[3] ; CHECK-CVT-NEXT: mov h4, v1.h[3]
; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: fcvtzu x13, s0
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvt s3, h3 ; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcvtzu x9, s0
; CHECK-CVT-NEXT: fcvt s5, h5
; CHECK-CVT-NEXT: fcvt s4, h4 ; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: fcvt s6, h6 ; CHECK-CVT-NEXT: fcvtzu x9, s1
; CHECK-CVT-NEXT: fcvt s0, h7 ; CHECK-CVT-NEXT: fcvt s1, h5
; CHECK-CVT-NEXT: fcvtzu x10, s1 ; CHECK-CVT-NEXT: fcvtzu x10, s2
; CHECK-CVT-NEXT: fcvtzu x11, s2 ; CHECK-CVT-NEXT: fcvtzu x11, s3
; CHECK-CVT-NEXT: fcvtzu x12, s3 ; CHECK-CVT-NEXT: fcvt s2, h6
; CHECK-CVT-NEXT: fcvtzu x14, s5 ; CHECK-CVT-NEXT: fcvtzu x12, s4
; CHECK-CVT-NEXT: fcvtzu x13, s4 ; CHECK-CVT-NEXT: fcvt s3, h7
; CHECK-CVT-NEXT: fcvtzu x15, s6
; CHECK-CVT-NEXT: cmp x10, x8
; CHECK-CVT-NEXT: fcvtzu x16, s0
; CHECK-CVT-NEXT: csel x4, x10, x8, lo
; CHECK-CVT-NEXT: cmp x13, x8
; CHECK-CVT-NEXT: csel x5, x13, x8, lo
; CHECK-CVT-NEXT: cmp x15, x8
; CHECK-CVT-NEXT: csel x6, x15, x8, lo
; CHECK-CVT-NEXT: cmp x16, x8
; CHECK-CVT-NEXT: csel x7, x16, x8, lo
; CHECK-CVT-NEXT: cmp x9, x8 ; CHECK-CVT-NEXT: cmp x9, x8
; CHECK-CVT-NEXT: csel x0, x9, x8, lo ; CHECK-CVT-NEXT: fcvtzu x14, s1
; CHECK-CVT-NEXT: csel x4, x9, x8, lo
; CHECK-CVT-NEXT: cmp x10, x8
; CHECK-CVT-NEXT: fcvtzu x9, s2
; CHECK-CVT-NEXT: csel x5, x10, x8, lo
; CHECK-CVT-NEXT: cmp x11, x8 ; CHECK-CVT-NEXT: cmp x11, x8
; CHECK-CVT-NEXT: csel x1, x11, x8, lo ; CHECK-CVT-NEXT: fcvtzu x10, s3
; CHECK-CVT-NEXT: csel x6, x11, x8, lo
; CHECK-CVT-NEXT: cmp x12, x8 ; CHECK-CVT-NEXT: cmp x12, x8
; CHECK-CVT-NEXT: csel x2, x12, x8, lo ; CHECK-CVT-NEXT: csel x7, x12, x8, lo
; CHECK-CVT-NEXT: cmp x13, x8
; CHECK-CVT-NEXT: csel x0, x13, x8, lo
; CHECK-CVT-NEXT: cmp x14, x8 ; CHECK-CVT-NEXT: cmp x14, x8
; CHECK-CVT-NEXT: csel x3, x14, x8, lo ; CHECK-CVT-NEXT: csel x1, x14, x8, lo
; CHECK-CVT-NEXT: cmp x9, x8
; CHECK-CVT-NEXT: csel x2, x9, x8, lo
; CHECK-CVT-NEXT: cmp x10, x8
; CHECK-CVT-NEXT: csel x3, x10, x8, lo
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i50: ; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i50:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-FP16-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff ; CHECK-FP16-NEXT: mov x8, #1125899906842623 // =0x3ffffffffffff
; CHECK-FP16-NEXT: mov h2, v0.h[1] ; CHECK-FP16-NEXT: fcvtzu x13, h0
; CHECK-FP16-NEXT: mov h3, v0.h[2] ; CHECK-FP16-NEXT: mov h2, v1.h[1]
; CHECK-FP16-NEXT: mov h5, v0.h[3] ; CHECK-FP16-NEXT: mov h3, v1.h[2]
; CHECK-FP16-NEXT: fcvtzu x9, h0 ; CHECK-FP16-NEXT: mov h4, v1.h[3]
; CHECK-FP16-NEXT: mov h4, v1.h[1] ; CHECK-FP16-NEXT: fcvtzu x9, h1
; CHECK-FP16-NEXT: mov h6, v1.h[2] ; CHECK-FP16-NEXT: mov h1, v0.h[1]
; CHECK-FP16-NEXT: mov h0, v1.h[3] ; CHECK-FP16-NEXT: fcvtzu x10, h2
; CHECK-FP16-NEXT: fcvtzu x10, h1 ; CHECK-FP16-NEXT: fcvtzu x11, h3
; CHECK-FP16-NEXT: fcvtzu x11, h2 ; CHECK-FP16-NEXT: mov h2, v0.h[2]
; CHECK-FP16-NEXT: fcvtzu x12, h3 ; CHECK-FP16-NEXT: fcvtzu x12, h4
; CHECK-FP16-NEXT: fcvtzu x14, h5 ; CHECK-FP16-NEXT: mov h3, v0.h[3]
; CHECK-FP16-NEXT: fcvtzu x13, h4
; CHECK-FP16-NEXT: fcvtzu x15, h6
; CHECK-FP16-NEXT: cmp x10, x8
; CHECK-FP16-NEXT: fcvtzu x16, h0
; CHECK-FP16-NEXT: csel x4, x10, x8, lo
; CHECK-FP16-NEXT: cmp x13, x8
; CHECK-FP16-NEXT: csel x5, x13, x8, lo
; CHECK-FP16-NEXT: cmp x15, x8
; CHECK-FP16-NEXT: csel x6, x15, x8, lo
; CHECK-FP16-NEXT: cmp x16, x8
; CHECK-FP16-NEXT: csel x7, x16, x8, lo
; CHECK-FP16-NEXT: cmp x9, x8 ; CHECK-FP16-NEXT: cmp x9, x8
; CHECK-FP16-NEXT: csel x0, x9, x8, lo ; CHECK-FP16-NEXT: fcvtzu x14, h1
; CHECK-FP16-NEXT: csel x4, x9, x8, lo
; CHECK-FP16-NEXT: cmp x10, x8
; CHECK-FP16-NEXT: fcvtzu x9, h2
; CHECK-FP16-NEXT: csel x5, x10, x8, lo
; CHECK-FP16-NEXT: cmp x11, x8 ; CHECK-FP16-NEXT: cmp x11, x8
; CHECK-FP16-NEXT: csel x1, x11, x8, lo ; CHECK-FP16-NEXT: fcvtzu x10, h3
; CHECK-FP16-NEXT: csel x6, x11, x8, lo
; CHECK-FP16-NEXT: cmp x12, x8 ; CHECK-FP16-NEXT: cmp x12, x8
; CHECK-FP16-NEXT: csel x2, x12, x8, lo ; CHECK-FP16-NEXT: csel x7, x12, x8, lo
; CHECK-FP16-NEXT: cmp x13, x8
; CHECK-FP16-NEXT: csel x0, x13, x8, lo
; CHECK-FP16-NEXT: cmp x14, x8 ; CHECK-FP16-NEXT: cmp x14, x8
; CHECK-FP16-NEXT: csel x3, x14, x8, lo ; CHECK-FP16-NEXT: csel x1, x14, x8, lo
; CHECK-FP16-NEXT: cmp x9, x8
; CHECK-FP16-NEXT: csel x2, x9, x8, lo
; CHECK-FP16-NEXT: cmp x10, x8
; CHECK-FP16-NEXT: csel x3, x10, x8, lo
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%x = call <8 x i50> @llvm.fptoui.sat.v8f16.v8i50(<8 x half> %f) %x = call <8 x i50> @llvm.fptoui.sat.v8f16.v8i50(<8 x half> %f)
ret <8 x i50> %x ret <8 x i50> %x
Context not available.
; CHECK-CVT-LABEL: test_unsigned_v8f16_v8i64: ; CHECK-CVT-LABEL: test_unsigned_v8f16_v8i64:
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-CVT-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-CVT-NEXT: mov h2, v0.h[2] ; CHECK-CVT-NEXT: mov h4, v0.h[2]
; CHECK-CVT-NEXT: fcvt s3, h0 ; CHECK-CVT-NEXT: mov h3, v0.h[1]
; CHECK-CVT-NEXT: mov h7, v0.h[1] ; CHECK-CVT-NEXT: mov h7, v0.h[3]
; CHECK-CVT-NEXT: mov h0, v0.h[3] ; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov h4, v1.h[1] ; CHECK-CVT-NEXT: mov h2, v1.h[2]
; CHECK-CVT-NEXT: mov h6, v1.h[2] ; CHECK-CVT-NEXT: mov h5, v1.h[1]
; CHECK-CVT-NEXT: fcvt s5, h1 ; CHECK-CVT-NEXT: mov h6, v1.h[3]
; CHECK-CVT-NEXT: mov h1, v1.h[3] ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: fcvt s4, h4
; CHECK-CVT-NEXT: fcvt s3, h3
; CHECK-CVT-NEXT: fcvt s7, h7
; CHECK-CVT-NEXT: fcvtzu x9, s0
; CHECK-CVT-NEXT: fcvt s2, h2 ; CHECK-CVT-NEXT: fcvt s2, h2
; CHECK-CVT-NEXT: fcvtzu x8, s3 ; CHECK-CVT-NEXT: fcvt s5, h5
; CHECK-CVT-NEXT: fcvt s3, h4 ; CHECK-CVT-NEXT: fcvt s6, h6
; CHECK-CVT-NEXT: fcvt s4, h6 ; CHECK-CVT-NEXT: fcvtzu x8, s1
; CHECK-CVT-NEXT: fcvtzu x9, s5 ; CHECK-CVT-NEXT: fcvtzu x12, s4
; CHECK-CVT-NEXT: fcvt s5, h7
; CHECK-CVT-NEXT: fcvt s6, h0
; CHECK-CVT-NEXT: fcvt s7, h1
; CHECK-CVT-NEXT: fcvtzu x10, s2
; CHECK-CVT-NEXT: fmov d0, x8
; CHECK-CVT-NEXT: fmov d2, x9
; CHECK-CVT-NEXT: fcvtzu x9, s4
; CHECK-CVT-NEXT: fcvtzu x11, s3 ; CHECK-CVT-NEXT: fcvtzu x11, s3
; CHECK-CVT-NEXT: fcvtzu x8, s5 ; CHECK-CVT-NEXT: fcvtzu x15, s7
; CHECK-CVT-NEXT: fmov d1, x10 ; CHECK-CVT-NEXT: fmov d0, x9
; CHECK-CVT-NEXT: fcvtzu x10, s6 ; CHECK-CVT-NEXT: fcvtzu x10, s2
; CHECK-CVT-NEXT: fmov d3, x9 ; CHECK-CVT-NEXT: fcvtzu x13, s5
; CHECK-CVT-NEXT: fcvtzu x9, s7 ; CHECK-CVT-NEXT: fcvtzu x14, s6
; CHECK-CVT-NEXT: mov v2.d[1], x11 ; CHECK-CVT-NEXT: fmov d2, x8
; CHECK-CVT-NEXT: mov v0.d[1], x8 ; CHECK-CVT-NEXT: fmov d1, x12
; CHECK-CVT-NEXT: mov v1.d[1], x10 ; CHECK-CVT-NEXT: mov v0.d[1], x11
; CHECK-CVT-NEXT: mov v3.d[1], x9 ; CHECK-CVT-NEXT: fmov d3, x10
; CHECK-CVT-NEXT: mov v2.d[1], x13
; CHECK-CVT-NEXT: mov v1.d[1], x15
; CHECK-CVT-NEXT: mov v3.d[1], x14
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i64: ; CHECK-FP16-LABEL: test_unsigned_v8f16_v8i64:
; CHECK-FP16: // %bb.0: ; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-FP16-NEXT: mov h2, v0.h[2] ; CHECK-FP16-NEXT: mov h4, v0.h[2]
; CHECK-FP16-NEXT: mov h5, v0.h[1] ; CHECK-FP16-NEXT: mov h3, v0.h[1]
; CHECK-FP16-NEXT: mov h6, v0.h[3] ; CHECK-FP16-NEXT: mov h7, v0.h[3]
; CHECK-FP16-NEXT: fcvtzu x8, h0 ; CHECK-FP16-NEXT: fcvtzu x9, h0
; CHECK-FP16-NEXT: mov h4, v1.h[2] ; CHECK-FP16-NEXT: mov h2, v1.h[2]
; CHECK-FP16-NEXT: fcvtzu x9, h1 ; CHECK-FP16-NEXT: mov h5, v1.h[1]
; CHECK-FP16-NEXT: mov h3, v1.h[1] ; CHECK-FP16-NEXT: mov h6, v1.h[3]
; CHECK-FP16-NEXT: mov h7, v1.h[3] ; CHECK-FP16-NEXT: fcvtzu x8, h1
; CHECK-FP16-NEXT: fcvtzu x10, h2 ; CHECK-FP16-NEXT: fcvtzu x12, h4
; CHECK-FP16-NEXT: fmov d0, x8
; CHECK-FP16-NEXT: fmov d2, x9
; CHECK-FP16-NEXT: fcvtzu x8, h5
; CHECK-FP16-NEXT: fcvtzu x9, h4
; CHECK-FP16-NEXT: fcvtzu x11, h3 ; CHECK-FP16-NEXT: fcvtzu x11, h3
; CHECK-FP16-NEXT: fmov d1, x10 ; CHECK-FP16-NEXT: fcvtzu x15, h7
; CHECK-FP16-NEXT: fcvtzu x10, h6 ; CHECK-FP16-NEXT: fmov d0, x9
; CHECK-FP16-NEXT: fmov d3, x9 ; CHECK-FP16-NEXT: fcvtzu x10, h2
; CHECK-FP16-NEXT: fcvtzu x9, h7 ; CHECK-FP16-NEXT: fcvtzu x13, h5
; CHECK-FP16-NEXT: mov v2.d[1], x11 ; CHECK-FP16-NEXT: fcvtzu x14, h6
; CHECK-FP16-NEXT: mov v0.d[1], x8 ; CHECK-FP16-NEXT: fmov d2, x8
; CHECK-FP16-NEXT: mov v1.d[1], x10 ; CHECK-FP16-NEXT: fmov d1, x12
; CHECK-FP16-NEXT: mov v3.d[1], x9 ; CHECK-FP16-NEXT: mov v0.d[1], x11
; CHECK-FP16-NEXT: fmov d3, x10
; CHECK-FP16-NEXT: mov v2.d[1], x13
; CHECK-FP16-NEXT: mov v1.d[1], x15
; CHECK-FP16-NEXT: mov v3.d[1], x14
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
%x = call <8 x i64> @llvm.fptoui.sat.v8f16.v8i64(<8 x half> %f) %x = call <8 x i64> @llvm.fptoui.sat.v8f16.v8i64(<8 x half> %f)
ret <8 x i64> %x ret <8 x i64> %x
Context not available.
; CHECK-NEXT: .cfi_offset b8, -104 ; CHECK-NEXT: .cfi_offset b8, -104
; CHECK-NEXT: .cfi_offset b9, -112 ; CHECK-NEXT: .cfi_offset b9, -112
; CHECK-NEXT: str q0, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: mov x19, x8
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: mov x19, x8
; CHECK-NEXT: str q0, [sp, #32] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #32] // 16-byte Folded Spill
; CHECK-NEXT: mov h0, v0.h[1] ; CHECK-NEXT: mov h0, v0.h[1]
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
Context not available.
; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: mov w8, #1904214015 // =0x717fffff ; CHECK-NEXT: mov w8, #1904214015 // =0x717fffff
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
; CHECK-NEXT: mov x23, #68719476735 // =0xfffffffff
; CHECK-NEXT: mov h0, v0.h[3]
; CHECK-NEXT: fmov s9, w8 ; CHECK-NEXT: fmov s9, w8
; CHECK-NEXT: csel x8, xzr, x0, lt ; CHECK-NEXT: mov x22, #68719476735 // =0xfffffffff
; CHECK-NEXT: csel x9, xzr, x1, lt ; CHECK-NEXT: mov h0, v0.h[3]
; CHECK-NEXT: csel x9, xzr, x0, lt
; CHECK-NEXT: csel x8, xzr, x1, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
; CHECK-NEXT: csel x9, x23, x9, gt ; CHECK-NEXT: csel x10, x22, x8, gt
; CHECK-NEXT: csinv x8, x8, xzr, le ; CHECK-NEXT: csinv x8, x9, xzr, le
; CHECK-NEXT: stp x8, x10, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: stp x8, x9, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
Context not available.
; CHECK-NEXT: csel x9, xzr, x1, lt ; CHECK-NEXT: csel x9, xzr, x1, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
; CHECK-NEXT: csel x9, x23, x9, gt ; CHECK-NEXT: csel x9, x22, x9, gt
; CHECK-NEXT: csinv x24, x8, xzr, le ; CHECK-NEXT: csinv x24, x8, xzr, le
; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: str x9, [sp, #8] // 8-byte Folded Spill ; CHECK-NEXT: str x9, [sp, #8] // 8-byte Folded Spill
; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
Context not available.
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
; CHECK-NEXT: csinv x8, x8, xzr, le ; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: csel x25, x23, x9, gt ; CHECK-NEXT: csel x25, x22, x9, gt
; CHECK-NEXT: str x8, [sp, #32] // 8-byte Folded Spill ; CHECK-NEXT: str x8, [sp, #32] // 8-byte Folded Spill
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
Context not available.
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
; CHECK-NEXT: csinv x8, x8, xzr, le ; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: csel x27, x23, x9, gt ; CHECK-NEXT: csel x26, x22, x9, gt
; CHECK-NEXT: str x8, [sp] // 8-byte Folded Spill ; CHECK-NEXT: str x8, [sp] // 8-byte Folded Spill
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
Context not available.
; CHECK-NEXT: csel x9, xzr, x1, lt ; CHECK-NEXT: csel x9, xzr, x1, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
; CHECK-NEXT: csel x29, x23, x9, gt ; CHECK-NEXT: csel x29, x22, x9, gt
; CHECK-NEXT: csinv x26, x8, xzr, le ; CHECK-NEXT: csinv x27, x8, xzr, le
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
Context not available.
; CHECK-NEXT: csel x9, xzr, x1, lt ; CHECK-NEXT: csel x9, xzr, x1, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
; CHECK-NEXT: csel x28, x23, x9, gt ; CHECK-NEXT: csel x20, x22, x9, gt
; CHECK-NEXT: csinv x20, x8, xzr, le ; CHECK-NEXT: csinv x21, x8, xzr, le
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Folded Reload
Context not available.
; CHECK-NEXT: csel x9, xzr, x1, lt ; CHECK-NEXT: csel x9, xzr, x1, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
; CHECK-NEXT: csel x21, x23, x9, gt ; CHECK-NEXT: csel x28, x22, x9, gt
; CHECK-NEXT: csinv x22, x8, xzr, le ; CHECK-NEXT: csinv x23, x8, xzr, le
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: ldr x9, [sp] // 8-byte Folded Reload
dmgreenUnsubmitted
Done
ReplyInline Actions

There is an extra spill here, but that kind of things is expected given enough code.

dmgreen: There is an extra spill here, but that kind of things is expected given enough code.
; CHECK-NEXT: extr x8, x20, x21, #28
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
; CHECK-NEXT: extr x8, x28, x20, #28 ; CHECK-NEXT: bfi x28, x27, #36, #28
; CHECK-NEXT: bfi x21, x26, #36, #28
; CHECK-NEXT: extr x9, x29, x26, #28
; CHECK-NEXT: lsr x11, x29, #28 ; CHECK-NEXT: lsr x11, x29, #28
; CHECK-NEXT: str x22, [x19] ; CHECK-NEXT: bfi x26, x24, #36, #28
; CHECK-NEXT: stur x9, [x19, #75]
; CHECK-NEXT: extr x9, x29, x27, #28
; CHECK-NEXT: stur x8, [x19, #41] ; CHECK-NEXT: stur x8, [x19, #41]
; CHECK-NEXT: csel x8, xzr, x0, lt ; CHECK-NEXT: csel x8, xzr, x0, lt
; CHECK-NEXT: csel x10, xzr, x1, lt ; CHECK-NEXT: str x9, [x19, #16]
; CHECK-NEXT: csel x9, xzr, x1, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: stp x21, x9, [x19, #8] ; CHECK-NEXT: ldr x10, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: lsr x9, x28, #28 ; CHECK-NEXT: stp x23, x28, [x19]
; CHECK-NEXT: strb w11, [x19, #24] ; CHECK-NEXT: strb w11, [x19, #24]
; CHECK-NEXT: bfi x27, x24, #36, #28 ; CHECK-NEXT: stur x10, [x19, #50]
; CHECK-NEXT: csel x10, x23, x10, gt ; CHECK-NEXT: lsr x10, x20, #28
; CHECK-NEXT: csel x9, x22, x9, gt
; CHECK-NEXT: bfi x9, x21, #36, #28
; CHECK-NEXT: csinv x8, x8, xzr, le ; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: bfi x10, x20, #36, #28 ; CHECK-NEXT: strb w10, [x19, #49]
; CHECK-NEXT: strb w9, [x19, #49] ; CHECK-NEXT: ldr x11, [sp, #8] // 8-byte Folded Reload
; CHECK-NEXT: stur x8, [x19, #25] ; CHECK-NEXT: stur x8, [x19, #25]
; CHECK-NEXT: stur x10, [x19, #33] ; CHECK-NEXT: stur x9, [x19, #33]
; CHECK-NEXT: ldp x9, x12, [sp] // 16-byte Folded Reload ; CHECK-NEXT: extr x10, x11, x24, #28
; CHECK-NEXT: stur x9, [x19, #75] ; CHECK-NEXT: stur x10, [x19, #91]
; CHECK-NEXT: extr x8, x12, x24, #28 ; CHECK-NEXT: ldp x10, x9, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: ldr x9, [sp, #32] // 8-byte Folded Reload ; CHECK-NEXT: stur x26, [x19, #83]
; CHECK-NEXT: stur x9, [x19, #50] ; CHECK-NEXT: extr x8, x9, x10, #28
; CHECK-NEXT: ldp x11, x10, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: bfi x25, x10, #36, #28
; CHECK-NEXT: stur x8, [x19, #91] ; CHECK-NEXT: lsr x9, x9, #28
; CHECK-NEXT: lsr x8, x12, #28 ; CHECK-NEXT: stur x8, [x19, #66]
; CHECK-NEXT: stur x27, [x19, #83] ; CHECK-NEXT: lsr x8, x11, #28
; CHECK-NEXT: extr x9, x10, x11, #28
; CHECK-NEXT: bfi x25, x11, #36, #28
; CHECK-NEXT: strb w8, [x19, #99]
; CHECK-NEXT: stur x9, [x19, #66]
; CHECK-NEXT: lsr x9, x10, #28
; CHECK-NEXT: stur x25, [x19, #58] ; CHECK-NEXT: stur x25, [x19, #58]
; CHECK-NEXT: strb w8, [x19, #99]
; CHECK-NEXT: strb w9, [x19, #74] ; CHECK-NEXT: strb w9, [x19, #74]
; CHECK-NEXT: ldp x20, x19, [sp, #160] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #160] // 16-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #144] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #144] // 16-byte Folded Reload
Context not available.
; CHECK-NEXT: .cfi_offset b8, -104 ; CHECK-NEXT: .cfi_offset b8, -104
; CHECK-NEXT: .cfi_offset b9, -112 ; CHECK-NEXT: .cfi_offset b9, -112
; CHECK-NEXT: str q0, [sp, #48] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #48] // 16-byte Folded Spill
; CHECK-NEXT: mov x19, x8
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: mov x19, x8
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
; CHECK-NEXT: str q0, [sp, #32] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp, #32] // 16-byte Folded Spill
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
Context not available.
; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: mov w8, #2139095039 // =0x7f7fffff ; CHECK-NEXT: mov w8, #2139095039 // =0x7f7fffff
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
; CHECK-NEXT: mov h0, v0.h[1]
; CHECK-NEXT: fmov s9, w8 ; CHECK-NEXT: fmov s9, w8
; CHECK-NEXT: csel x8, xzr, x1, lt ; CHECK-NEXT: mov h0, v0.h[1]
; CHECK-NEXT: csel x9, xzr, x0, lt ; CHECK-NEXT: csel x9, xzr, x1, lt
; CHECK-NEXT: csel x8, xzr, x0, lt
; CHECK-NEXT: fcmp s8, s9 ; CHECK-NEXT: fcmp s8, s9
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
; CHECK-NEXT: csinv x9, x9, xzr, le ; CHECK-NEXT: csinv x10, x8, xzr, le
; CHECK-NEXT: csinv x8, x8, xzr, le ; CHECK-NEXT: csinv x8, x9, xzr, le
; CHECK-NEXT: stp x8, x10, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: fmov s0, s8 ; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: stp x8, x9, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
Context not available.
; CHECK-NEXT: fcvt s8, h0 ; CHECK-NEXT: fcvt s8, h0
; CHECK-NEXT: csinv x9, x9, xzr, le ; CHECK-NEXT: csinv x9, x9, xzr, le
; CHECK-NEXT: csinv x8, x8, xzr, le ; CHECK-NEXT: csinv x8, x8, xzr, le
; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: stp x8, x9, [sp] // 16-byte Folded Spill ; CHECK-NEXT: stp x8, x9, [sp] // 16-byte Folded Spill
; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: fcmp s8, #0.0 ; CHECK-NEXT: fcmp s8, #0.0
Context not available.
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: fcvtl2 v2.4s, v1.8h ; CHECK-CVT-NEXT: fcvtl2 v2.4s, v1.8h
; CHECK-CVT-NEXT: fcvtl v1.4s, v1.4h ; CHECK-CVT-NEXT: fcvtl v1.4s, v1.4h
; CHECK-CVT-NEXT: fcvtl2 v5.4s, v0.8h
; CHECK-CVT-NEXT: mov w8, #255 // =0xff ; CHECK-CVT-NEXT: mov w8, #255 // =0xff
; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h
; CHECK-CVT-NEXT: mov s3, v2.s[1] ; CHECK-CVT-NEXT: mov s3, v2.s[1]
; CHECK-CVT-NEXT: mov s4, v2.s[2] ; CHECK-CVT-NEXT: mov s4, v2.s[2]
; CHECK-CVT-NEXT: fcvtzu w9, s2 ; CHECK-CVT-NEXT: mov s5, v2.s[3]
; CHECK-CVT-NEXT: mov s2, v2.s[3] ; CHECK-CVT-NEXT: fcvtzu w10, s2
; CHECK-CVT-NEXT: fcvtzu w12, s1 ; CHECK-CVT-NEXT: fcvtl2 v2.4s, v0.8h
; CHECK-CVT-NEXT: fcvtzu w16, s5 ; CHECK-CVT-NEXT: fcvtzu w13, s1
; CHECK-CVT-NEXT: fcvtzu w2, s0 ; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h
; CHECK-CVT-NEXT: fcvtzu w10, s3 ; CHECK-CVT-NEXT: fcvtzu w9, s3
; CHECK-CVT-NEXT: mov s3, v1.s[1] ; CHECK-CVT-NEXT: mov s3, v1.s[1]
; CHECK-CVT-NEXT: fcvtzu w11, s4 ; CHECK-CVT-NEXT: fcvtzu w11, s4
; CHECK-CVT-NEXT: mov s4, v1.s[2] ; CHECK-CVT-NEXT: mov s4, v1.s[2]
; CHECK-CVT-NEXT: fcvtzu w12, s5
; CHECK-CVT-NEXT: mov s1, v1.s[3] ; CHECK-CVT-NEXT: mov s1, v1.s[3]
; CHECK-CVT-NEXT: fcvtzu w13, s2 ; CHECK-CVT-NEXT: fcvtzu w18, s2
; CHECK-CVT-NEXT: cmp w10, #255 ; CHECK-CVT-NEXT: fcvtzu w3, s0
; CHECK-CVT-NEXT: mov s2, v5.s[1]
; CHECK-CVT-NEXT: fcvtzu w14, s3 ; CHECK-CVT-NEXT: fcvtzu w14, s3
; CHECK-CVT-NEXT: csel w10, w10, w8, lo
; CHECK-CVT-NEXT: cmp w9, #255 ; CHECK-CVT-NEXT: cmp w9, #255
; CHECK-CVT-NEXT: fcvtzu w15, s4 ; CHECK-CVT-NEXT: mov s3, v2.s[1]
; CHECK-CVT-NEXT: csel w9, w9, w8, lo ; CHECK-CVT-NEXT: csel w9, w9, w8, lo
; CHECK-CVT-NEXT: cmp w10, #255
; CHECK-CVT-NEXT: fcvtzu w15, s4
; CHECK-CVT-NEXT: csel w10, w10, w8, lo
; CHECK-CVT-NEXT: cmp w11, #255 ; CHECK-CVT-NEXT: cmp w11, #255
; CHECK-CVT-NEXT: mov s4, v2.s[2]
; CHECK-CVT-NEXT: csel w11, w11, w8, lo ; CHECK-CVT-NEXT: csel w11, w11, w8, lo
; CHECK-CVT-NEXT: cmp w13, #255
; CHECK-CVT-NEXT: mov s3, v5.s[2]
; CHECK-CVT-NEXT: fcvtzu w17, s1
; CHECK-CVT-NEXT: csel w13, w13, w8, lo
; CHECK-CVT-NEXT: cmp w14, #255
; CHECK-CVT-NEXT: mov s4, v5.s[3]
; CHECK-CVT-NEXT: fcvtzu w18, s2
; CHECK-CVT-NEXT: csel w14, w14, w8, lo
; CHECK-CVT-NEXT: cmp w12, #255 ; CHECK-CVT-NEXT: cmp w12, #255
; CHECK-CVT-NEXT: mov s1, v0.s[1] ; CHECK-CVT-NEXT: fcvtzu w16, s1
; CHECK-CVT-NEXT: mov s1, v2.s[3]
; CHECK-CVT-NEXT: csel w12, w12, w8, lo ; CHECK-CVT-NEXT: csel w12, w12, w8, lo
; CHECK-CVT-NEXT: cmp w14, #255
; CHECK-CVT-NEXT: fcvtzu w17, s3
; CHECK-CVT-NEXT: mov s3, v0.s[1]
; CHECK-CVT-NEXT: csel w14, w14, w8, lo
; CHECK-CVT-NEXT: cmp w13, #255
; CHECK-CVT-NEXT: fcvtzu w0, s4
; CHECK-CVT-NEXT: fmov s2, w10
; CHECK-CVT-NEXT: csel w13, w13, w8, lo
; CHECK-CVT-NEXT: cmp w15, #255 ; CHECK-CVT-NEXT: cmp w15, #255
; CHECK-CVT-NEXT: fcvtzu w0, s3
; CHECK-CVT-NEXT: csel w15, w15, w8, lo ; CHECK-CVT-NEXT: csel w15, w15, w8, lo
; CHECK-CVT-NEXT: cmp w17, #255
; CHECK-CVT-NEXT: csel w17, w17, w8, lo
; CHECK-CVT-NEXT: cmp w18, #255
; CHECK-CVT-NEXT: fmov s2, w9
; CHECK-CVT-NEXT: csel w9, w18, w8, lo
; CHECK-CVT-NEXT: fcvtzu w18, s4
; CHECK-CVT-NEXT: cmp w16, #255 ; CHECK-CVT-NEXT: cmp w16, #255
; CHECK-CVT-NEXT: fcvtzu w1, s1 ; CHECK-CVT-NEXT: fcvtzu w1, s1
; CHECK-CVT-NEXT: csel w16, w16, w8, lo ; CHECK-CVT-NEXT: csel w16, w16, w8, lo
; CHECK-CVT-NEXT: cmp w0, #255 ; CHECK-CVT-NEXT: cmp w17, #255
; CHECK-CVT-NEXT: fcvtzu w2, s3
; CHECK-CVT-NEXT: csel w17, w17, w8, lo
; CHECK-CVT-NEXT: cmp w18, #255
; CHECK-CVT-NEXT: mov s1, v0.s[2] ; CHECK-CVT-NEXT: mov s1, v0.s[2]
; CHECK-CVT-NEXT: csel w18, w18, w8, lo
; CHECK-CVT-NEXT: cmp w0, #255
; CHECK-CVT-NEXT: mov v2.s[1], w9
; CHECK-CVT-NEXT: csel w0, w0, w8, lo ; CHECK-CVT-NEXT: csel w0, w0, w8, lo
; CHECK-CVT-NEXT: cmp w18, #255
; CHECK-CVT-NEXT: mov v2.s[1], w10
; CHECK-CVT-NEXT: csel w10, w18, w8, lo
; CHECK-CVT-NEXT: cmp w1, #255 ; CHECK-CVT-NEXT: cmp w1, #255
; CHECK-CVT-NEXT: fmov s3, w12 ; CHECK-CVT-NEXT: fmov s3, w18
; CHECK-CVT-NEXT: csel w18, w1, w8, lo ; CHECK-CVT-NEXT: csel w10, w1, w8, lo
; CHECK-CVT-NEXT: cmp w2, #255 ; CHECK-CVT-NEXT: cmp w2, #255
; CHECK-CVT-NEXT: csel w1, w2, w8, lo
; CHECK-CVT-NEXT: fmov s4, w16
; CHECK-CVT-NEXT: mov v2.s[2], w11
; CHECK-CVT-NEXT: fcvtzu w11, s1
; CHECK-CVT-NEXT: mov s0, v0.s[3] ; CHECK-CVT-NEXT: mov s0, v0.s[3]
; CHECK-CVT-NEXT: fmov s1, w1 ; CHECK-CVT-NEXT: csel w9, w2, w8, lo
; CHECK-CVT-NEXT: mov v3.s[1], w14 ; CHECK-CVT-NEXT: cmp w3, #255
; CHECK-CVT-NEXT: cmp w11, #255 ; CHECK-CVT-NEXT: fcvtzu w2, s1
; CHECK-CVT-NEXT: csel w1, w3, w8, lo
; CHECK-CVT-NEXT: fmov s1, w13
; CHECK-CVT-NEXT: mov v3.s[1], w17
; CHECK-CVT-NEXT: fmov s4, w1
; CHECK-CVT-NEXT: mov v2.s[2], w11
; CHECK-CVT-NEXT: mov v1.s[1], w14
; CHECK-CVT-NEXT: cmp w2, #255
; CHECK-CVT-NEXT: mov v4.s[1], w9 ; CHECK-CVT-NEXT: mov v4.s[1], w9
; CHECK-CVT-NEXT: csel w9, w11, w8, lo ; CHECK-CVT-NEXT: fcvtzu w9, s0
; CHECK-CVT-NEXT: mov v1.s[1], w18 ; CHECK-CVT-NEXT: csel w11, w2, w8, lo
; CHECK-CVT-NEXT: fcvtzu w11, s0 ; CHECK-CVT-NEXT: mov v3.s[2], w0
; CHECK-CVT-NEXT: mov v3.s[2], w15 ; CHECK-CVT-NEXT: mov v2.s[3], w12
; CHECK-CVT-NEXT: mov v4.s[2], w0 ; CHECK-CVT-NEXT: mov v1.s[2], w15
; CHECK-CVT-NEXT: mov v1.s[2], w9 ; CHECK-CVT-NEXT: mov v4.s[2], w11
; CHECK-CVT-NEXT: cmp w11, #255 ; CHECK-CVT-NEXT: cmp w9, #255
; CHECK-CVT-NEXT: csel w8, w11, w8, lo ; CHECK-CVT-NEXT: csel w8, w9, w8, lo
; CHECK-CVT-NEXT: mov v2.s[3], w13 ; CHECK-CVT-NEXT: mov v3.s[3], w10
; CHECK-CVT-NEXT: mov v3.s[3], w17 ; CHECK-CVT-NEXT: mov v1.s[3], w16
; CHECK-CVT-NEXT: mov v4.s[3], w10 ; CHECK-CVT-NEXT: mov v4.s[3], w8
; CHECK-CVT-NEXT: mov v1.s[3], w8 ; CHECK-CVT-NEXT: uzp1 v0.8h, v1.8h, v2.8h
; CHECK-CVT-NEXT: uzp1 v0.8h, v3.8h, v2.8h ; CHECK-CVT-NEXT: uzp1 v1.8h, v4.8h, v3.8h
; CHECK-CVT-NEXT: uzp1 v1.8h, v1.8h, v4.8h
; CHECK-CVT-NEXT: uzp1 v0.16b, v1.16b, v0.16b ; CHECK-CVT-NEXT: uzp1 v0.16b, v1.16b, v0.16b
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
Context not available.
; CHECK-CVT: // %bb.0: ; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: fcvtl2 v2.4s, v0.8h ; CHECK-CVT-NEXT: fcvtl2 v2.4s, v0.8h
; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h ; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h
; CHECK-CVT-NEXT: fcvtl2 v5.4s, v1.8h
; CHECK-CVT-NEXT: mov w8, #65535 // =0xffff ; CHECK-CVT-NEXT: mov w8, #65535 // =0xffff
; CHECK-CVT-NEXT: fcvtl v1.4s, v1.4h
; CHECK-CVT-NEXT: mov s3, v2.s[1] ; CHECK-CVT-NEXT: mov s3, v2.s[1]
; CHECK-CVT-NEXT: mov s4, v2.s[2] ; CHECK-CVT-NEXT: mov s4, v2.s[2]
; CHECK-CVT-NEXT: fcvtzu w9, s2 ; CHECK-CVT-NEXT: mov s5, v2.s[3]
; CHECK-CVT-NEXT: mov s2, v2.s[3] ; CHECK-CVT-NEXT: fcvtzu w10, s2
; CHECK-CVT-NEXT: fcvtzu w12, s0 ; CHECK-CVT-NEXT: fcvtl2 v2.4s, v1.8h
; CHECK-CVT-NEXT: fcvtzu w16, s5 ; CHECK-CVT-NEXT: fcvtzu w13, s0
; CHECK-CVT-NEXT: fcvtzu w2, s1 ; CHECK-CVT-NEXT: fcvtl v1.4s, v1.4h
; CHECK-CVT-NEXT: fcvtzu w10, s3 ; CHECK-CVT-NEXT: fcvtzu w9, s3
; CHECK-CVT-NEXT: mov s3, v0.s[1] ; CHECK-CVT-NEXT: mov s3, v0.s[1]
; CHECK-CVT-NEXT: fcvtzu w11, s4 ; CHECK-CVT-NEXT: fcvtzu w11, s4
; CHECK-CVT-NEXT: mov s4, v0.s[2] ; CHECK-CVT-NEXT: mov s4, v0.s[2]
; CHECK-CVT-NEXT: fcvtzu w12, s5
; CHECK-CVT-NEXT: mov s0, v0.s[3] ; CHECK-CVT-NEXT: mov s0, v0.s[3]
; CHECK-CVT-NEXT: fcvtzu w13, s2 ; CHECK-CVT-NEXT: fcvtzu w18, s2
; CHECK-CVT-NEXT: cmp w10, w8 ; CHECK-CVT-NEXT: fcvtzu w3, s1
; CHECK-CVT-NEXT: mov s2, v5.s[1]
; CHECK-CVT-NEXT: fcvtzu w14, s3 ; CHECK-CVT-NEXT: fcvtzu w14, s3
; CHECK-CVT-NEXT: csel w10, w10, w8, lo
; CHECK-CVT-NEXT: cmp w9, w8 ; CHECK-CVT-NEXT: cmp w9, w8
; CHECK-CVT-NEXT: fcvtzu w15, s4 ; CHECK-CVT-NEXT: mov s3, v2.s[1]
; CHECK-CVT-NEXT: csel w9, w9, w8, lo ; CHECK-CVT-NEXT: csel w9, w9, w8, lo
; CHECK-CVT-NEXT: cmp w10, w8
; CHECK-CVT-NEXT: fcvtzu w15, s4
; CHECK-CVT-NEXT: csel w10, w10, w8, lo
; CHECK-CVT-NEXT: cmp w11, w8 ; CHECK-CVT-NEXT: cmp w11, w8
; CHECK-CVT-NEXT: mov s4, v2.s[2]
; CHECK-CVT-NEXT: csel w11, w11, w8, lo ; CHECK-CVT-NEXT: csel w11, w11, w8, lo
; CHECK-CVT-NEXT: cmp w13, w8
; CHECK-CVT-NEXT: mov s3, v5.s[2]
; CHECK-CVT-NEXT: fcvtzu w17, s0
; CHECK-CVT-NEXT: csel w13, w13, w8, lo
; CHECK-CVT-NEXT: cmp w14, w8
; CHECK-CVT-NEXT: mov s4, v5.s[3]
; CHECK-CVT-NEXT: fcvtzu w18, s2
; CHECK-CVT-NEXT: csel w14, w14, w8, lo
; CHECK-CVT-NEXT: cmp w12, w8 ; CHECK-CVT-NEXT: cmp w12, w8
; CHECK-CVT-NEXT: mov s0, v1.s[1] ; CHECK-CVT-NEXT: fcvtzu w16, s0
; CHECK-CVT-NEXT: mov s0, v2.s[3]
; CHECK-CVT-NEXT: csel w12, w12, w8, lo ; CHECK-CVT-NEXT: csel w12, w12, w8, lo
; CHECK-CVT-NEXT: cmp w14, w8
; CHECK-CVT-NEXT: fcvtzu w17, s3
; CHECK-CVT-NEXT: mov s3, v1.s[1]
; CHECK-CVT-NEXT: csel w14, w14, w8, lo
; CHECK-CVT-NEXT: cmp w13, w8
; CHECK-CVT-NEXT: fcvtzu w0, s4
; CHECK-CVT-NEXT: fmov s2, w10
; CHECK-CVT-NEXT: csel w13, w13, w8, lo
; CHECK-CVT-NEXT: cmp w15, w8 ; CHECK-CVT-NEXT: cmp w15, w8
; CHECK-CVT-NEXT: fcvtzu w0, s3
; CHECK-CVT-NEXT: csel w15, w15, w8, lo ; CHECK-CVT-NEXT: csel w15, w15, w8, lo
; CHECK-CVT-NEXT: cmp w17, w8
; CHECK-CVT-NEXT: csel w17, w17, w8, lo
; CHECK-CVT-NEXT: cmp w18, w8
; CHECK-CVT-NEXT: fmov s2, w9
; CHECK-CVT-NEXT: csel w9, w18, w8, lo
; CHECK-CVT-NEXT: fcvtzu w18, s4
; CHECK-CVT-NEXT: cmp w16, w8 ; CHECK-CVT-NEXT: cmp w16, w8
; CHECK-CVT-NEXT: fcvtzu w1, s0 ; CHECK-CVT-NEXT: fcvtzu w1, s0
; CHECK-CVT-NEXT: csel w16, w16, w8, lo ; CHECK-CVT-NEXT: csel w16, w16, w8, lo
; CHECK-CVT-NEXT: cmp w0, w8 ; CHECK-CVT-NEXT: cmp w17, w8
; CHECK-CVT-NEXT: fcvtzu w2, s3
; CHECK-CVT-NEXT: csel w17, w17, w8, lo
; CHECK-CVT-NEXT: cmp w18, w8
; CHECK-CVT-NEXT: mov s0, v1.s[2] ; CHECK-CVT-NEXT: mov s0, v1.s[2]
; CHECK-CVT-NEXT: csel w18, w18, w8, lo
; CHECK-CVT-NEXT: cmp w0, w8
; CHECK-CVT-NEXT: mov v2.s[1], w9
; CHECK-CVT-NEXT: csel w0, w0, w8, lo ; CHECK-CVT-NEXT: csel w0, w0, w8, lo
; CHECK-CVT-NEXT: cmp w18, w8
; CHECK-CVT-NEXT: mov v2.s[1], w10
; CHECK-CVT-NEXT: csel w10, w18, w8, lo
; CHECK-CVT-NEXT: cmp w1, w8 ; CHECK-CVT-NEXT: cmp w1, w8
; CHECK-CVT-NEXT: fmov s3, w12 ; CHECK-CVT-NEXT: fmov s3, w18
; CHECK-CVT-NEXT: csel w18, w1, w8, lo ; CHECK-CVT-NEXT: csel w10, w1, w8, lo
; CHECK-CVT-NEXT: cmp w2, w8 ; CHECK-CVT-NEXT: cmp w2, w8
; CHECK-CVT-NEXT: csel w1, w2, w8, lo ; CHECK-CVT-NEXT: csel w9, w2, w8, lo
; CHECK-CVT-NEXT: fmov s4, w16 ; CHECK-CVT-NEXT: cmp w3, w8
; CHECK-CVT-NEXT: mov v2.s[2], w11 ; CHECK-CVT-NEXT: fcvtzu w2, s0
; CHECK-CVT-NEXT: fcvtzu w11, s0 ; CHECK-CVT-NEXT: csel w1, w3, w8, lo
; CHECK-CVT-NEXT: mov s0, v1.s[3] ; CHECK-CVT-NEXT: mov s0, v1.s[3]
; CHECK-CVT-NEXT: fmov s5, w1 ; CHECK-CVT-NEXT: fmov s1, w13
; CHECK-CVT-NEXT: mov v3.s[1], w14 ; CHECK-CVT-NEXT: fmov s4, w1
; CHECK-CVT-NEXT: cmp w11, w8 ; CHECK-CVT-NEXT: mov v3.s[1], w17
; CHECK-CVT-NEXT: mov v2.s[2], w11
; CHECK-CVT-NEXT: mov v1.s[1], w14
; CHECK-CVT-NEXT: cmp w2, w8
; CHECK-CVT-NEXT: mov v4.s[1], w9 ; CHECK-CVT-NEXT: mov v4.s[1], w9
; CHECK-CVT-NEXT: csel w9, w11, w8, lo ; CHECK-CVT-NEXT: fcvtzu w9, s0
; CHECK-CVT-NEXT: mov v5.s[1], w18 ; CHECK-CVT-NEXT: csel w11, w2, w8, lo
; CHECK-CVT-NEXT: fcvtzu w11, s0 ; CHECK-CVT-NEXT: mov v3.s[2], w0
; CHECK-CVT-NEXT: mov v3.s[2], w15 ; CHECK-CVT-NEXT: mov v2.s[3], w12
; CHECK-CVT-NEXT: mov v4.s[2], w0 ; CHECK-CVT-NEXT: mov v1.s[2], w15
; CHECK-CVT-NEXT: mov v5.s[2], w9 ; CHECK-CVT-NEXT: mov v4.s[2], w11
; CHECK-CVT-NEXT: cmp w11, w8 ; CHECK-CVT-NEXT: cmp w9, w8
; CHECK-CVT-NEXT: csel w8, w11, w8, lo ; CHECK-CVT-NEXT: csel w8, w9, w8, lo
; CHECK-CVT-NEXT: mov v2.s[3], w13 ; CHECK-CVT-NEXT: mov v3.s[3], w10
; CHECK-CVT-NEXT: mov v3.s[3], w17 ; CHECK-CVT-NEXT: mov v1.s[3], w16
; CHECK-CVT-NEXT: mov v4.s[3], w10 ; CHECK-CVT-NEXT: mov v4.s[3], w8
; CHECK-CVT-NEXT: mov v5.s[3], w8 ; CHECK-CVT-NEXT: uzp1 v0.8h, v1.8h, v2.8h
; CHECK-CVT-NEXT: uzp1 v0.8h, v3.8h, v2.8h ; CHECK-CVT-NEXT: uzp1 v1.8h, v4.8h, v3.8h
; CHECK-CVT-NEXT: uzp1 v1.8h, v5.8h, v4.8h
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; ;
; CHECK-FP16-LABEL: test_unsigned_v16f16_v16i16: ; CHECK-FP16-LABEL: test_unsigned_v16f16_v16i16:
Context not available.
; CHECK-LABEL: test_unsigned_v8f64_v8i8: ; CHECK-LABEL: test_unsigned_v8f64_v8i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov d4, v3.d[1] ; CHECK-NEXT: mov d4, v3.d[1]
; CHECK-NEXT: fcvtzu w10, d3 ; CHECK-NEXT: mov d5, v2.d[1]
; CHECK-NEXT: mov d3, v2.d[1] ; CHECK-NEXT: mov w11, #255 // =0xff
; CHECK-NEXT: mov w8, #255 // =0xff ; CHECK-NEXT: fcvtzu w9, d3
; CHECK-NEXT: mov d3, v1.d[1]
; CHECK-NEXT: fcvtzu w12, d2 ; CHECK-NEXT: fcvtzu w12, d2
; CHECK-NEXT: fcvtzu w13, d1 ; CHECK-NEXT: fcvtzu w14, d1
; CHECK-NEXT: fcvtzu w9, d4 ; CHECK-NEXT: fcvtzu w8, d4
; CHECK-NEXT: mov d4, v1.d[1] ; CHECK-NEXT: mov d4, v0.d[1]
; CHECK-NEXT: fcvtzu w11, d3 ; CHECK-NEXT: fcvtzu w10, d5
; CHECK-NEXT: mov d1, v0.d[1] ; CHECK-NEXT: fcvtzu w13, d3
; CHECK-NEXT: cmp w8, #255
; CHECK-NEXT: fcvtzu w15, d4
; CHECK-NEXT: csel w8, w8, w11, lo
; CHECK-NEXT: cmp w9, #255 ; CHECK-NEXT: cmp w9, #255
; CHECK-NEXT: csel w9, w9, w8, lo ; CHECK-NEXT: csel w9, w9, w11, lo
; CHECK-NEXT: cmp w10, #255 ; CHECK-NEXT: cmp w10, #255
; CHECK-NEXT: csel w10, w10, w8, lo ; CHECK-NEXT: fmov s4, w9
; CHECK-NEXT: cmp w11, #255 ; CHECK-NEXT: csel w9, w10, w11, lo
; CHECK-NEXT: csel w11, w11, w8, lo
; CHECK-NEXT: cmp w12, #255 ; CHECK-NEXT: cmp w12, #255
; CHECK-NEXT: csel w12, w12, w8, lo ; CHECK-NEXT: fcvtzu w10, d0
; CHECK-NEXT: fmov s19, w10 ; CHECK-NEXT: mov v4.s[1], w8
; CHECK-NEXT: fcvtzu w10, d4 ; CHECK-NEXT: csel w8, w12, w11, lo
; CHECK-NEXT: cmp w10, #255
; CHECK-NEXT: mov v19.s[1], w9
; CHECK-NEXT: csel w10, w10, w8, lo
; CHECK-NEXT: cmp w13, #255
; CHECK-NEXT: fmov s18, w12
; CHECK-NEXT: fcvtzu w9, d1
; CHECK-NEXT: csel w12, w13, w8, lo
; CHECK-NEXT: fcvtzu w13, d0
; CHECK-NEXT: mov v18.s[1], w11
; CHECK-NEXT: cmp w9, #255
; CHECK-NEXT: fmov s17, w12
; CHECK-NEXT: csel w9, w9, w8, lo
; CHECK-NEXT: cmp w13, #255 ; CHECK-NEXT: cmp w13, #255
; CHECK-NEXT: csel w8, w13, w8, lo ; CHECK-NEXT: fmov s3, w8
; CHECK-NEXT: mov v17.s[1], w10 ; CHECK-NEXT: csel w8, w13, w11, lo
; CHECK-NEXT: fmov s16, w8 ; CHECK-NEXT: cmp w14, #255
; CHECK-NEXT: mov v3.s[1], w9
; CHECK-NEXT: csel w9, w14, w11, lo
; CHECK-NEXT: cmp w15, #255
; CHECK-NEXT: fmov s2, w9
; CHECK-NEXT: csel w9, w15, w11, lo
; CHECK-NEXT: cmp w10, #255
; CHECK-NEXT: mov v2.s[1], w8
; CHECK-NEXT: csel w8, w10, w11, lo
; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: adrp x8, .LCPI82_0 ; CHECK-NEXT: adrp x8, .LCPI82_0
; CHECK-NEXT: mov v16.s[1], w9
; CHECK-NEXT: ldr d0, [x8, :lo12:.LCPI82_0] ; CHECK-NEXT: ldr d0, [x8, :lo12:.LCPI82_0]
; CHECK-NEXT: tbl v0.8b, { v16.16b, v17.16b, v18.16b, v19.16b }, v0.8b ; CHECK-NEXT: mov v1.s[1], w9
; CHECK-NEXT: tbl v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v0.8b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <8 x i8> @llvm.fptoui.sat.v8f64.v8i8(<8 x double> %f) %x = call <8 x i8> @llvm.fptoui.sat.v8f64.v8i8(<8 x double> %f)
ret <8 x i8> %x ret <8 x i8> %x
Context not available.
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov d16, v0.d[1] ; CHECK-NEXT: mov d16, v0.d[1]
; CHECK-NEXT: fcvtzu w10, d0 ; CHECK-NEXT: fcvtzu w10, d0
; CHECK-NEXT: mov d0, v1.d[1]
; CHECK-NEXT: mov w8, #255 // =0xff ; CHECK-NEXT: mov w8, #255 // =0xff
; CHECK-NEXT: fcvtzu w12, d1
; CHECK-NEXT: mov d1, v2.d[1]
; CHECK-NEXT: fcvtzu w9, d16 ; CHECK-NEXT: fcvtzu w9, d16
; CHECK-NEXT: fcvtzu w11, d0 ; CHECK-NEXT: mov d16, v1.d[1]
; CHECK-NEXT: cmp w9, #255 ; CHECK-NEXT: cmp w9, #255
; CHECK-NEXT: csel w9, w9, w8, lo ; CHECK-NEXT: csel w9, w9, w8, lo
; CHECK-NEXT: cmp w10, #255 ; CHECK-NEXT: cmp w10, #255
; CHECK-NEXT: csel w10, w10, w8, lo ; CHECK-NEXT: csel w10, w10, w8, lo
; CHECK-NEXT: cmp w11, #255
; CHECK-NEXT: fmov s0, w10 ; CHECK-NEXT: fmov s0, w10
; CHECK-NEXT: csel w10, w11, w8, lo ; CHECK-NEXT: fcvtzu w10, d16
; CHECK-NEXT: cmp w12, #255 ; CHECK-NEXT: mov d16, v2.d[1]
; CHECK-NEXT: csel w11, w12, w8, lo
; CHECK-NEXT: fcvtzu w12, d2
; CHECK-NEXT: mov v0.s[1], w9 ; CHECK-NEXT: mov v0.s[1], w9
; CHECK-NEXT: fcvtzu w9, d1 ; CHECK-NEXT: fcvtzu w9, d1
; CHECK-NEXT: mov d2, v3.d[1] ; CHECK-NEXT: cmp w10, #255
; CHECK-NEXT: fmov s1, w11 ; CHECK-NEXT: csel w10, w10, w8, lo
; CHECK-NEXT: cmp w9, #255 ; CHECK-NEXT: cmp w9, #255
; CHECK-NEXT: mov w11, v0.s[1] ; CHECK-NEXT: mov w11, v0.s[1]
; CHECK-NEXT: csel w9, w9, w8, lo ; CHECK-NEXT: csel w9, w9, w8, lo
; CHECK-NEXT: cmp w12, #255 ; CHECK-NEXT: fmov s1, w9
; CHECK-NEXT: fcvtzu w9, d16
; CHECK-NEXT: mov d16, v3.d[1]
; CHECK-NEXT: mov v0.b[1], w11
; CHECK-NEXT: mov v1.s[1], w10 ; CHECK-NEXT: mov v1.s[1], w10
; CHECK-NEXT: csel w12, w12, w8, lo
; CHECK-NEXT: fcvtzu w10, d2 ; CHECK-NEXT: fcvtzu w10, d2
; CHECK-NEXT: mov v0.b[1], w11 ; CHECK-NEXT: cmp w9, #255
; CHECK-NEXT: fcvtzu w11, d3 ; CHECK-NEXT: csel w9, w9, w8, lo
; CHECK-NEXT: fmov s2, w12
; CHECK-NEXT: mov w12, v1.s[1]
; CHECK-NEXT: cmp w10, #255 ; CHECK-NEXT: cmp w10, #255
; CHECK-NEXT: mov d3, v4.d[1] ; CHECK-NEXT: mov w11, v1.s[1]
; CHECK-NEXT: csel w10, w10, w8, lo
; CHECK-NEXT: mov v0.b[2], v1.b[0] ; CHECK-NEXT: mov v0.b[2], v1.b[0]
; CHECK-NEXT: cmp w11, #255 ; CHECK-NEXT: csel w10, w10, w8, lo
; CHECK-NEXT: fmov s2, w10
; CHECK-NEXT: fcvtzu w10, d16
; CHECK-NEXT: mov d16, v4.d[1]
; CHECK-NEXT: mov v0.b[3], w11
; CHECK-NEXT: mov v2.s[1], w9 ; CHECK-NEXT: mov v2.s[1], w9
; CHECK-NEXT: csel w11, w11, w8, lo
; CHECK-NEXT: fcvtzu w9, d3 ; CHECK-NEXT: fcvtzu w9, d3
; CHECK-NEXT: mov d3, v5.d[1] ; CHECK-NEXT: cmp w10, #255
; CHECK-NEXT: mov v0.b[3], w12 ; CHECK-NEXT: csel w10, w10, w8, lo
; CHECK-NEXT: fcvtzu w12, d4
; CHECK-NEXT: fmov s4, w11
; CHECK-NEXT: mov w11, v2.s[1]
; CHECK-NEXT: cmp w9, #255 ; CHECK-NEXT: cmp w9, #255
; CHECK-NEXT: csel w9, w9, w8, lo ; CHECK-NEXT: mov w11, v2.s[1]
; CHECK-NEXT: cmp w12, #255
; CHECK-NEXT: mov v0.b[4], v2.b[0] ; CHECK-NEXT: mov v0.b[4], v2.b[0]
; CHECK-NEXT: csel w12, w12, w8, lo ; CHECK-NEXT: csel w9, w9, w8, lo
; CHECK-NEXT: mov v4.s[1], w10 ; CHECK-NEXT: fmov s3, w9
; CHECK-NEXT: fcvtzu w10, d3 ; CHECK-NEXT: fcvtzu w9, d16
; CHECK-NEXT: fmov s3, w12
; CHECK-NEXT: mov v0.b[5], w11 ; CHECK-NEXT: mov v0.b[5], w11
; CHECK-NEXT: fcvtzu w11, d5 ; CHECK-NEXT: mov v3.s[1], w10
; CHECK-NEXT: mov w12, v4.s[1] ; CHECK-NEXT: fcvtzu w10, d4
; CHECK-NEXT: mov d4, v5.d[1]
; CHECK-NEXT: cmp w9, #255
; CHECK-NEXT: csel w9, w9, w8, lo
; CHECK-NEXT: cmp w10, #255 ; CHECK-NEXT: cmp w10, #255
; CHECK-NEXT: csel w10, w10, w8, lo
; CHECK-NEXT: mov d5, v6.d[1]
; CHECK-NEXT: cmp w11, #255
; CHECK-NEXT: mov v0.b[6], v4.b[0]
; CHECK-NEXT: csel w11, w11, w8, lo
; CHECK-NEXT: mov v3.s[1], w9
; CHECK-NEXT: fcvtzu w9, d6
; CHECK-NEXT: mov d6, v7.d[1]
; CHECK-NEXT: mov v0.b[7], w12
; CHECK-NEXT: fcvtzu w12, d5
; CHECK-NEXT: fmov s5, w11
; CHECK-NEXT: mov w11, v3.s[1] ; CHECK-NEXT: mov w11, v3.s[1]
; CHECK-NEXT: cmp w12, #255 ; CHECK-NEXT: mov v0.b[6], v3.b[0]
; CHECK-NEXT: mov v0.b[8], v3.b[0] ; CHECK-NEXT: csel w10, w10, w8, lo
; CHECK-NEXT: csel w12, w12, w8, lo ; CHECK-NEXT: fmov s16, w10
; CHECK-NEXT: fcvtzu w10, d4
; CHECK-NEXT: mov d4, v6.d[1]
; CHECK-NEXT: mov v0.b[7], w11
; CHECK-NEXT: mov v16.s[1], w9
; CHECK-NEXT: fcvtzu w9, d5
; CHECK-NEXT: cmp w10, #255
; CHECK-NEXT: csel w10, w10, w8, lo
; CHECK-NEXT: cmp w9, #255 ; CHECK-NEXT: cmp w9, #255
; CHECK-NEXT: mov v5.s[1], w10 ; CHECK-NEXT: mov w11, v16.s[1]
; CHECK-NEXT: mov v0.b[8], v16.b[0]
; CHECK-NEXT: csel w9, w9, w8, lo ; CHECK-NEXT: csel w9, w9, w8, lo
; CHECK-NEXT: fcvtzu w10, d6 ; CHECK-NEXT: fmov s5, w9
; CHECK-NEXT: fcvtzu w9, d4
; CHECK-NEXT: mov d4, v7.d[1]
; CHECK-NEXT: mov v0.b[9], w11 ; CHECK-NEXT: mov v0.b[9], w11
; CHECK-NEXT: fcvtzu w11, d7 ; CHECK-NEXT: mov v5.s[1], w10
; CHECK-NEXT: fmov s16, w9 ; CHECK-NEXT: fcvtzu w10, d6
; CHECK-NEXT: mov w9, v5.s[1] ; CHECK-NEXT: cmp w9, #255
; CHECK-NEXT: csel w9, w9, w8, lo
; CHECK-NEXT: cmp w10, #255 ; CHECK-NEXT: cmp w10, #255
; CHECK-NEXT: mov v0.b[10], v5.b[0] ; CHECK-NEXT: mov v0.b[10], v5.b[0]
; CHECK-NEXT: mov v16.s[1], w12 ; CHECK-NEXT: mov w11, v5.s[1]
; CHECK-NEXT: mov v0.b[11], w9 ; CHECK-NEXT: csel w10, w10, w8, lo
; CHECK-NEXT: csel w9, w10, w8, lo ; CHECK-NEXT: fmov s6, w10
; CHECK-NEXT: cmp w11, #255 ; CHECK-NEXT: fcvtzu w10, d7
; CHECK-NEXT: mov w10, v16.s[1] ; CHECK-NEXT: mov v0.b[11], w11
; CHECK-NEXT: csel w8, w11, w8, lo
; CHECK-NEXT: mov v0.b[12], v16.b[0]
; CHECK-NEXT: fmov s6, w8
; CHECK-NEXT: mov v0.b[13], w10
; CHECK-NEXT: mov v6.s[1], w9 ; CHECK-NEXT: mov v6.s[1], w9
; CHECK-NEXT: mov v0.b[14], v6.b[0] ; CHECK-NEXT: fcvtzu w9, d4
; CHECK-NEXT: mov w8, v6.s[1] ; CHECK-NEXT: cmp w9, #255
; CHECK-NEXT: mov v0.b[12], v6.b[0]
; CHECK-NEXT: mov w11, v6.s[1]
; CHECK-NEXT: csel w9, w9, w8, lo
; CHECK-NEXT: cmp w10, #255
; CHECK-NEXT: csel w8, w10, w8, lo
; CHECK-NEXT: fmov s4, w8
; CHECK-NEXT: mov v0.b[13], w11
; CHECK-NEXT: mov v4.s[1], w9
; CHECK-NEXT: mov v0.b[14], v4.b[0]
; CHECK-NEXT: mov w8, v4.s[1]
; CHECK-NEXT: mov v0.b[15], w8 ; CHECK-NEXT: mov v0.b[15], w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <16 x i8> @llvm.fptoui.sat.v16f64.v16i8(<16 x double> %f) %x = call <16 x i8> @llvm.fptoui.sat.v16f64.v16i8(<16 x double> %f)
Context not available.
; CHECK-LABEL: test_unsigned_v8f64_v8i16: ; CHECK-LABEL: test_unsigned_v8f64_v8i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov d4, v3.d[1] ; CHECK-NEXT: mov d4, v3.d[1]
; CHECK-NEXT: fcvtzu w10, d3 ; CHECK-NEXT: mov d5, v2.d[1]
; CHECK-NEXT: mov d3, v2.d[1] ; CHECK-NEXT: mov w10, #65535 // =0xffff
; CHECK-NEXT: mov w8, #65535 // =0xffff ; CHECK-NEXT: fcvtzu w9, d3
; CHECK-NEXT: mov d3, v1.d[1]
; CHECK-NEXT: fcvtzu w12, d2 ; CHECK-NEXT: fcvtzu w12, d2
; CHECK-NEXT: fcvtzu w13, d1 ; CHECK-NEXT: fcvtzu w14, d1
; CHECK-NEXT: fcvtzu w9, d4 ; CHECK-NEXT: fcvtzu w8, d4
; CHECK-NEXT: mov d4, v1.d[1] ; CHECK-NEXT: mov d4, v0.d[1]
; CHECK-NEXT: fcvtzu w11, d3 ; CHECK-NEXT: fcvtzu w11, d5
; CHECK-NEXT: mov d1, v0.d[1] ; CHECK-NEXT: fcvtzu w13, d3
; CHECK-NEXT: cmp w9, w8 ; CHECK-NEXT: cmp w8, w10
; CHECK-NEXT: csel w9, w9, w8, lo ; CHECK-NEXT: fcvtzu w15, d4
; CHECK-NEXT: cmp w10, w8 ; CHECK-NEXT: csel w8, w8, w10, lo
; CHECK-NEXT: csel w10, w10, w8, lo ; CHECK-NEXT: cmp w9, w10
; CHECK-NEXT: cmp w11, w8 ; CHECK-NEXT: csel w9, w9, w10, lo
; CHECK-NEXT: csel w11, w11, w8, lo ; CHECK-NEXT: cmp w11, w10
; CHECK-NEXT: cmp w12, w8 ; CHECK-NEXT: fmov s4, w9
; CHECK-NEXT: csel w12, w12, w8, lo ; CHECK-NEXT: csel w9, w11, w10, lo
; CHECK-NEXT: fmov s19, w10 ; CHECK-NEXT: cmp w12, w10
; CHECK-NEXT: fcvtzu w10, d4 ; CHECK-NEXT: fcvtzu w11, d0
; CHECK-NEXT: cmp w10, w8 ; CHECK-NEXT: mov v4.s[1], w8
; CHECK-NEXT: mov v19.s[1], w9 ; CHECK-NEXT: csel w8, w12, w10, lo
; CHECK-NEXT: csel w10, w10, w8, lo ; CHECK-NEXT: cmp w13, w10
; CHECK-NEXT: cmp w13, w8 ; CHECK-NEXT: fmov s3, w8
; CHECK-NEXT: fmov s18, w12 ; CHECK-NEXT: csel w8, w13, w10, lo
; CHECK-NEXT: fcvtzu w9, d1 ; CHECK-NEXT: cmp w14, w10
; CHECK-NEXT: csel w12, w13, w8, lo ; CHECK-NEXT: mov v3.s[1], w9
; CHECK-NEXT: fcvtzu w13, d0 ; CHECK-NEXT: csel w9, w14, w10, lo
; CHECK-NEXT: mov v18.s[1], w11 ; CHECK-NEXT: cmp w15, w10
; CHECK-NEXT: cmp w9, w8 ; CHECK-NEXT: fmov s2, w9
; CHECK-NEXT: fmov s17, w12 ; CHECK-NEXT: csel w9, w15, w10, lo
; CHECK-NEXT: csel w9, w9, w8, lo ; CHECK-NEXT: cmp w11, w10
; CHECK-NEXT: cmp w13, w8 ; CHECK-NEXT: mov v2.s[1], w8
; CHECK-NEXT: csel w8, w13, w8, lo ; CHECK-NEXT: csel w8, w11, w10, lo
; CHECK-NEXT: mov v17.s[1], w10 ; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: fmov s16, w8
; CHECK-NEXT: adrp x8, .LCPI84_0 ; CHECK-NEXT: adrp x8, .LCPI84_0
; CHECK-NEXT: mov v16.s[1], w9
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI84_0] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI84_0]
; CHECK-NEXT: tbl v0.16b, { v16.16b, v17.16b, v18.16b, v19.16b }, v0.16b ; CHECK-NEXT: mov v1.s[1], w9
; CHECK-NEXT: tbl v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <8 x i16> @llvm.fptoui.sat.v8f64.v8i16(<8 x double> %f) %x = call <8 x i16> @llvm.fptoui.sat.v8f64.v8i16(<8 x double> %f)
ret <8 x i16> %x ret <8 x i16> %x
Context not available.
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov d16, v3.d[1] ; CHECK-NEXT: mov d16, v3.d[1]
; CHECK-NEXT: mov d17, v2.d[1] ; CHECK-NEXT: mov d17, v2.d[1]
; CHECK-NEXT: mov w8, #65535 // =0xffff
; CHECK-NEXT: fcvtzu w9, d3 ; CHECK-NEXT: fcvtzu w9, d3
; CHECK-NEXT: mov d3, v1.d[1] ; CHECK-NEXT: mov d3, v1.d[1]
; CHECK-NEXT: mov w8, #65535 // =0xffff ; CHECK-NEXT: fcvtzu w11, d1
; CHECK-NEXT: fcvtzu w10, d2
; CHECK-NEXT: fcvtzu w12, d1
; CHECK-NEXT: mov d1, v0.d[1] ; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: fcvtzu w11, d16 ; CHECK-NEXT: fcvtzu w10, d2
; CHECK-NEXT: fcvtzu w13, d17 ; CHECK-NEXT: fcvtzu w13, d0
; CHECK-NEXT: fcvtzu w14, d3 ; CHECK-NEXT: mov d0, v7.d[1]
; CHECK-NEXT: mov d2, v7.d[1] ; CHECK-NEXT: mov d2, v6.d[1]
; CHECK-NEXT: fcvtzu w17, d6 ; CHECK-NEXT: fcvtzu w15, d7
; CHECK-NEXT: cmp w11, w8 ; CHECK-NEXT: fcvtzu w12, d16
; CHECK-NEXT: fcvtzu w15, d1 ; CHECK-NEXT: fcvtzu w14, d17
; CHECK-NEXT: csel w11, w11, w8, lo ; CHECK-NEXT: fcvtzu w16, d6
; CHECK-NEXT: fcvtzu w17, d3
; CHECK-NEXT: mov d6, v5.d[1]
; CHECK-NEXT: mov d3, v4.d[1]
; CHECK-NEXT: fcvtzu w18, d1
; CHECK-NEXT: cmp w12, w8
; CHECK-NEXT: csel w12, w12, w8, lo
; CHECK-NEXT: cmp w9, w8 ; CHECK-NEXT: cmp w9, w8
; CHECK-NEXT: csel w9, w9, w8, lo ; CHECK-NEXT: csel w9, w9, w8, lo
; CHECK-NEXT: cmp w13, w8
; CHECK-NEXT: csel w13, w13, w8, lo
; CHECK-NEXT: cmp w10, w8
; CHECK-NEXT: csel w10, w10, w8, lo
; CHECK-NEXT: cmp w14, w8 ; CHECK-NEXT: cmp w14, w8
; CHECK-NEXT: fmov s19, w9 ; CHECK-NEXT: fmov s19, w9
; CHECK-NEXT: csel w9, w14, w8, lo ; CHECK-NEXT: csel w9, w14, w8, lo
; CHECK-NEXT: cmp w10, w8
; CHECK-NEXT: fcvtzu w14, d0 ; CHECK-NEXT: fcvtzu w14, d0
; CHECK-NEXT: cmp w12, w8 ; CHECK-NEXT: csel w10, w10, w8, lo
; CHECK-NEXT: fcvtzu w16, d2 ; CHECK-NEXT: cmp w17, w8
; CHECK-NEXT: mov d0, v6.d[1] ; CHECK-NEXT: mov v19.s[1], w12
; CHECK-NEXT: csel w12, w12, w8, lo ; CHECK-NEXT: csel w12, w17, w8, lo
; CHECK-NEXT: cmp w15, w8
; CHECK-NEXT: mov v19.s[1], w11
; CHECK-NEXT: fcvtzu w11, d7
; CHECK-NEXT: fmov s18, w10
; CHECK-NEXT: csel w10, w15, w8, lo
; CHECK-NEXT: cmp w14, w8
; CHECK-NEXT: csel w14, w14, w8, lo
; CHECK-NEXT: cmp w16, w8
; CHECK-NEXT: csel w15, w16, w8, lo
; CHECK-NEXT: cmp w11, w8 ; CHECK-NEXT: cmp w11, w8
; CHECK-NEXT: fcvtzu w16, d0
; CHECK-NEXT: mov d0, v5.d[1]
; CHECK-NEXT: csel w11, w11, w8, lo ; CHECK-NEXT: csel w11, w11, w8, lo
; CHECK-NEXT: mov v18.s[1], w13 ; CHECK-NEXT: cmp w18, w8
; CHECK-NEXT: cmp w16, w8 ; CHECK-NEXT: fmov s18, w10
; CHECK-NEXT: fmov s17, w12 ; CHECK-NEXT: csel w10, w18, w8, lo
; CHECK-NEXT: cmp w13, w8
; CHECK-NEXT: fcvtzu w17, d2
; CHECK-NEXT: csel w13, w13, w8, lo
; CHECK-NEXT: cmp w14, w8
; CHECK-NEXT: fcvtzu w18, d6
; CHECK-NEXT: mov v18.s[1], w9
; CHECK-NEXT: csel w9, w14, w8, lo
; CHECK-NEXT: cmp w15, w8
; CHECK-NEXT: fmov s17, w11
; CHECK-NEXT: csel w11, w15, w8, lo
; CHECK-NEXT: fcvtzu w14, d5
; CHECK-NEXT: fmov s23, w11 ; CHECK-NEXT: fmov s23, w11
; CHECK-NEXT: csel w11, w16, w8, lo
; CHECK-NEXT: cmp w17, w8 ; CHECK-NEXT: cmp w17, w8
; CHECK-NEXT: fcvtzu w16, d0 ; CHECK-NEXT: fcvtzu w15, d3
; CHECK-NEXT: mov d0, v4.d[1] ; CHECK-NEXT: csel w11, w17, w8, lo
; CHECK-NEXT: csel w13, w17, w8, lo
; CHECK-NEXT: fcvtzu w17, d5
; CHECK-NEXT: fcvtzu w12, d4
; CHECK-NEXT: mov v23.s[1], w15
; CHECK-NEXT: cmp w16, w8 ; CHECK-NEXT: cmp w16, w8
; CHECK-NEXT: fmov s22, w13 ; CHECK-NEXT: fcvtzu w17, d4
; CHECK-NEXT: csel w13, w16, w8, lo ; CHECK-NEXT: mov v17.s[1], w12
; CHECK-NEXT: cmp w17, w8 ; CHECK-NEXT: mov v23.s[1], w9
; CHECK-NEXT: fcvtzu w16, d0 ; CHECK-NEXT: csel w9, w16, w8, lo
; CHECK-NEXT: csel w15, w17, w8, lo ; CHECK-NEXT: cmp w18, w8
; CHECK-NEXT: fmov s22, w9
; CHECK-NEXT: csel w9, w18, w8, lo
; CHECK-NEXT: cmp w14, w8
; CHECK-NEXT: fmov s16, w13
; CHECK-NEXT: mov v22.s[1], w11 ; CHECK-NEXT: mov v22.s[1], w11
; CHECK-NEXT: cmp w16, w8 ; CHECK-NEXT: csel w11, w14, w8, lo
; CHECK-NEXT: fmov s21, w15 ; CHECK-NEXT: cmp w15, w8
; CHECK-NEXT: csel w11, w16, w8, lo ; CHECK-NEXT: fmov s21, w11
; CHECK-NEXT: cmp w12, w8 ; CHECK-NEXT: csel w11, w15, w8, lo
; CHECK-NEXT: csel w8, w12, w8, lo ; CHECK-NEXT: cmp w17, w8
; CHECK-NEXT: mov v17.s[1], w9 ; CHECK-NEXT: csel w8, w17, w8, lo
; CHECK-NEXT: adrp x9, .LCPI85_0
; CHECK-NEXT: mov v21.s[1], w13
; CHECK-NEXT: fmov s16, w14
; CHECK-NEXT: fmov s20, w8
; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI85_0]
; CHECK-NEXT: mov v16.s[1], w10 ; CHECK-NEXT: mov v16.s[1], w10
; CHECK-NEXT: mov v21.s[1], w9
; CHECK-NEXT: fmov s20, w8
; CHECK-NEXT: adrp x8, .LCPI85_0
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI85_0]
; CHECK-NEXT: mov v20.s[1], w11 ; CHECK-NEXT: mov v20.s[1], w11
; CHECK-NEXT: tbl v0.16b, { v16.16b, v17.16b, v18.16b, v19.16b }, v1.16b ; CHECK-NEXT: tbl v0.16b, { v16.16b, v17.16b, v18.16b, v19.16b }, v1.16b
; CHECK-NEXT: tbl v1.16b, { v20.16b, v21.16b, v22.16b, v23.16b }, v1.16b ; CHECK-NEXT: tbl v1.16b, { v20.16b, v21.16b, v22.16b, v23.16b }, v1.16b
Context not available.

llvm/test/CodeGen/AArch64/fptrunc.ll

llvm/test/CodeGen/AArch64/fsqrt.ll

llvm/test/CodeGen/AArch64/funnel-shift-rot.ll

llvm/test/CodeGen/AArch64/funnel-shift.ll

llvm/test/CodeGen/AArch64/global-merge-3.ll

llvm/test/CodeGen/AArch64/gpr_cttz.ll

llvm/test/CodeGen/AArch64/half.ll

llvm/test/CodeGen/AArch64/highextractbitcast.ll

llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll

llvm/test/CodeGen/AArch64/i128-math.ll

llvm/test/CodeGen/AArch64/i128_volatile_load_store.ll

llvm/test/CodeGen/AArch64/illegal-floating-point-vector-compares.ll

llvm/test/CodeGen/AArch64/insert-extend.ll

llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll

llvm/test/CodeGen/AArch64/insert-subvector.ll

llvm/test/CodeGen/AArch64/insertshuffleload.ll

llvm/test/CodeGen/AArch64/isinf.ll

llvm/test/CodeGen/AArch64/known-never-nan.ll

llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll

llvm/test/CodeGen/AArch64/load-insert-zero.ll

llvm/test/CodeGen/AArch64/logic-reassociate.ll

llvm/test/CodeGen/AArch64/logic-shift.ll

llvm/test/CodeGen/AArch64/logical_shifted_reg.ll

Context not available.
; CHECK-NEXT: ldr w9, [x9] ; CHECK-NEXT: ldr w9, [x9]
; CHECK-NEXT: and w11, w10, w9 ; CHECK-NEXT: and w11, w10, w9
; CHECK-NEXT: bic w12, w10, w9 ; CHECK-NEXT: bic w12, w10, w9
; CHECK-NEXT: orr w13, w10, w9
; CHECK-NEXT: str w11, [x8] ; CHECK-NEXT: str w11, [x8]
; CHECK-NEXT: orn w11, w10, w9 ; CHECK-NEXT: orr w11, w10, w9
; CHECK-NEXT: str w12, [x8] ; CHECK-NEXT: str w12, [x8]
; CHECK-NEXT: eor w12, w10, w9 ; CHECK-NEXT: orn w12, w10, w9
; CHECK-NEXT: str w13, [x8] ; CHECK-NEXT: str w11, [x8]
; CHECK-NEXT: eon w13, w9, w10 ; CHECK-NEXT: eor w11, w10, w9
; CHECK-NEXT: str w12, [x8]
; CHECK-NEXT: eon w12, w9, w10
; CHECK-NEXT: str w11, [x8] ; CHECK-NEXT: str w11, [x8]
; CHECK-NEXT: and w11, w10, w9, lsl #31 ; CHECK-NEXT: and w11, w10, w9, lsl #31
; CHECK-NEXT: str w12, [x8] ; CHECK-NEXT: str w12, [x8]
; CHECK-NEXT: bic w12, w10, w9, lsl #31 ; CHECK-NEXT: bic w12, w10, w9, lsl #31
; CHECK-NEXT: str w13, [x8]
; CHECK-NEXT: orr w13, w10, w9, lsl #31
; CHECK-NEXT: str w11, [x8] ; CHECK-NEXT: str w11, [x8]
; CHECK-NEXT: orn w11, w10, w9, lsl #31 ; CHECK-NEXT: orr w11, w10, w9, lsl #31
; CHECK-NEXT: str w12, [x8]
; CHECK-NEXT: orn w12, w10, w9, lsl #31
; CHECK-NEXT: str w11, [x8]
; CHECK-NEXT: eor w11, w10, w9, lsl #31
; CHECK-NEXT: str w12, [x8] ; CHECK-NEXT: str w12, [x8]
; CHECK-NEXT: eor w12, w10, w9, lsl #31 ; CHECK-NEXT: eon w12, w10, w9, lsl #31
; CHECK-NEXT: str w13, [x8]
; CHECK-NEXT: eon w13, w10, w9, lsl #31
; CHECK-NEXT: str w11, [x8] ; CHECK-NEXT: str w11, [x8]
; CHECK-NEXT: bic w11, w10, w9, asr #10 ; CHECK-NEXT: bic w11, w10, w9, asr #10
; CHECK-NEXT: str w12, [x8] ; CHECK-NEXT: str w12, [x8]
; CHECK-NEXT: eor w12, w10, w9, asr #10 ; CHECK-NEXT: eor w12, w10, w9, asr #10
; CHECK-NEXT: str w13, [x8]
; CHECK-NEXT: orn w13, w10, w9, lsr #1
; CHECK-NEXT: str w11, [x8] ; CHECK-NEXT: str w11, [x8]
; CHECK-NEXT: eor w11, w10, w9, lsr #1 ; CHECK-NEXT: orn w11, w10, w9, lsr #1
; CHECK-NEXT: str w12, [x8] ; CHECK-NEXT: str w12, [x8]
; CHECK-NEXT: eon w12, w10, w9, ror #20 ; CHECK-NEXT: eor w12, w10, w9, lsr #1
; CHECK-NEXT: and w9, w10, w9, ror #20
; CHECK-NEXT: str w13, [x8]
; CHECK-NEXT: str w11, [x8] ; CHECK-NEXT: str w11, [x8]
; CHECK-NEXT: eon w11, w10, w9, ror #20
; CHECK-NEXT: and w9, w10, w9, ror #20
; CHECK-NEXT: str w12, [x8] ; CHECK-NEXT: str w12, [x8]
; CHECK-NEXT: str w11, [x8]
; CHECK-NEXT: str w9, [x8] ; CHECK-NEXT: str w9, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%val1 = load i32, ptr @var1_32 %val1 = load i32, ptr @var1_32
Context not available.
; CHECK-NEXT: ldr x9, [x9] ; CHECK-NEXT: ldr x9, [x9]
; CHECK-NEXT: and x11, x10, x9 ; CHECK-NEXT: and x11, x10, x9
; CHECK-NEXT: bic x12, x10, x9 ; CHECK-NEXT: bic x12, x10, x9
; CHECK-NEXT: orr x13, x10, x9
; CHECK-NEXT: str x11, [x8] ; CHECK-NEXT: str x11, [x8]
; CHECK-NEXT: orn x11, x10, x9 ; CHECK-NEXT: orr x11, x10, x9
; CHECK-NEXT: str x12, [x8] ; CHECK-NEXT: str x12, [x8]
; CHECK-NEXT: eor x12, x10, x9 ; CHECK-NEXT: orn x12, x10, x9
; CHECK-NEXT: str x13, [x8] ; CHECK-NEXT: str x11, [x8]
; CHECK-NEXT: eon x13, x9, x10 ; CHECK-NEXT: eor x11, x10, x9
; CHECK-NEXT: str x12, [x8]
; CHECK-NEXT: eon x12, x9, x10
; CHECK-NEXT: str x11, [x8] ; CHECK-NEXT: str x11, [x8]
; CHECK-NEXT: and x11, x10, x9, lsl #63 ; CHECK-NEXT: and x11, x10, x9, lsl #63
; CHECK-NEXT: str x12, [x8] ; CHECK-NEXT: str x12, [x8]
; CHECK-NEXT: bic x12, x10, x9, lsl #63 ; CHECK-NEXT: bic x12, x10, x9, lsl #63
; CHECK-NEXT: str x13, [x8]
; CHECK-NEXT: orr x13, x10, x9, lsl #63
; CHECK-NEXT: str x11, [x8] ; CHECK-NEXT: str x11, [x8]
; CHECK-NEXT: orn x11, x10, x9, lsl #63 ; CHECK-NEXT: orr x11, x10, x9, lsl #63
; CHECK-NEXT: str x12, [x8]
; CHECK-NEXT: orn x12, x10, x9, lsl #63
; CHECK-NEXT: str x11, [x8]
; CHECK-NEXT: eor x11, x10, x9, lsl #63
; CHECK-NEXT: str x12, [x8] ; CHECK-NEXT: str x12, [x8]
; CHECK-NEXT: eor x12, x10, x9, lsl #63 ; CHECK-NEXT: eon x12, x10, x9, lsl #63
; CHECK-NEXT: str x13, [x8]
; CHECK-NEXT: eon x13, x10, x9, lsl #63
; CHECK-NEXT: str x11, [x8] ; CHECK-NEXT: str x11, [x8]
; CHECK-NEXT: bic x11, x10, x9, asr #10 ; CHECK-NEXT: bic x11, x10, x9, asr #10
; CHECK-NEXT: str x12, [x8] ; CHECK-NEXT: str x12, [x8]
; CHECK-NEXT: eor x12, x10, x9, asr #10 ; CHECK-NEXT: eor x12, x10, x9, asr #10
; CHECK-NEXT: str x13, [x8]
; CHECK-NEXT: orn x13, x10, x9, lsr #1
; CHECK-NEXT: str x11, [x8] ; CHECK-NEXT: str x11, [x8]
; CHECK-NEXT: eor x11, x10, x9, lsr #1 ; CHECK-NEXT: orn x11, x10, x9, lsr #1
; CHECK-NEXT: str x12, [x8] ; CHECK-NEXT: str x12, [x8]
; CHECK-NEXT: eon x12, x10, x9, ror #20 ; CHECK-NEXT: eor x12, x10, x9, lsr #1
; CHECK-NEXT: and x9, x10, x9, ror #20
; CHECK-NEXT: str x13, [x8]
; CHECK-NEXT: str x11, [x8] ; CHECK-NEXT: str x11, [x8]
; CHECK-NEXT: eon x11, x10, x9, ror #20
; CHECK-NEXT: and x9, x10, x9, ror #20
; CHECK-NEXT: str x12, [x8] ; CHECK-NEXT: str x12, [x8]
; CHECK-NEXT: str x11, [x8]
; CHECK-NEXT: str x9, [x8] ; CHECK-NEXT: str x9, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%val1 = load i64, ptr @var1_64 %val1 = load i64, ptr @var1_64
Context not available.
; CHECK-NEXT: ldr x9, [x8] ; CHECK-NEXT: ldr x9, [x8]
; CHECK-NEXT: ldr x10, [x10] ; CHECK-NEXT: ldr x10, [x10]
; CHECK-NEXT: tst x9, x10 ; CHECK-NEXT: tst x9, x10
; CHECK-NEXT: b.gt .LBB2_2 ; CHECK-NEXT: b.gt .LBB2_4
; CHECK-NEXT: // %bb.1: // %test2 ; CHECK-NEXT: // %bb.1: // %test2
; CHECK-NEXT: tst x9, x10, lsl #63 ; CHECK-NEXT: tst x9, x10, lsl #63
; CHECK-NEXT: b.lt .LBB2_4
; CHECK-NEXT: // %bb.2: // %test3
; CHECK-NEXT: and x10, x9, x10, asr #12 ; CHECK-NEXT: and x10, x9, x10, asr #12
; CHECK-NEXT: ccmp x10, #1, #0, ge ; CHECK-NEXT: cmp x10, #1
; CHECK-NEXT: b.lt .LBB2_3 ; CHECK-NEXT: b.ge .LBB2_4
; CHECK-NEXT: .LBB2_2: // %common.ret ; CHECK-NEXT: // %bb.3: // %other_exit
dmgreenUnsubmitted
Done
ReplyInline Actions

This looks like it no longer decides to ifcvt. Given the test that sound fine I think.

dmgreen: This looks like it no longer decides to ifcvt. Given the test that sound fine I think.
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB2_3: // %other_exit
; CHECK-NEXT: str x9, [x8] ; CHECK-NEXT: str x9, [x8]
; CHECK-NEXT: .LBB2_4: // %common.ret
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%val1 = load i64, ptr @var1_64 %val1 = load i64, ptr @var1_64
%val2 = load i64, ptr @var2_64 %val2 = load i64, ptr @var2_64
Context not available.

llvm/test/CodeGen/AArch64/lowerMUL-newload.ll

llvm/test/CodeGen/AArch64/machine-combiner-copy.ll

llvm/test/CodeGen/AArch64/machine-combiner-subadd.ll

llvm/test/CodeGen/AArch64/machine-combiner-transient.ll

llvm/test/CodeGen/AArch64/machine-licm-sink-instr.ll

llvm/test/CodeGen/AArch64/machine-licm-sub-loop.ll

llvm/test/CodeGen/AArch64/machine_cse_impdef_killflags.ll

llvm/test/CodeGen/AArch64/madd-combiner.ll

llvm/test/CodeGen/AArch64/memcpy-scoped-aa.ll

Context not available.
; CHECK-LABEL: test_memcpy: ; CHECK-LABEL: test_memcpy:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldp w9, w10, [x1] ; CHECK-NEXT: ldp w9, w10, [x1]
; CHECK-NEXT: ldr q0, [x0, #16]
; CHECK-NEXT: mov x8, x0 ; CHECK-NEXT: mov x8, x0
; CHECK-NEXT: add w0, w9, w10 ; CHECK-NEXT: add w0, w9, w10
; CHECK-NEXT: ldr q0, [x8, #16]
; CHECK-NEXT: str q0, [x8] ; CHECK-NEXT: str q0, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%p0 = bitcast i32* %p to i8* %p0 = bitcast i32* %p to i8*
Context not available.
; CHECK-LABEL: test_memcpy_inline: ; CHECK-LABEL: test_memcpy_inline:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldp w9, w10, [x1] ; CHECK-NEXT: ldp w9, w10, [x1]
; CHECK-NEXT: ldr q0, [x0, #16]
; CHECK-NEXT: mov x8, x0 ; CHECK-NEXT: mov x8, x0
; CHECK-NEXT: add w0, w9, w10 ; CHECK-NEXT: add w0, w9, w10
; CHECK-NEXT: ldr q0, [x8, #16]
; CHECK-NEXT: str q0, [x8] ; CHECK-NEXT: str q0, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%p0 = bitcast i32* %p to i8* %p0 = bitcast i32* %p to i8*
Context not available.
; CHECK-LABEL: test_memmove: ; CHECK-LABEL: test_memmove:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldp w9, w10, [x1] ; CHECK-NEXT: ldp w9, w10, [x1]
; CHECK-NEXT: ldr q0, [x0, #16]
; CHECK-NEXT: mov x8, x0 ; CHECK-NEXT: mov x8, x0
; CHECK-NEXT: add w0, w9, w10 ; CHECK-NEXT: add w0, w9, w10
; CHECK-NEXT: ldr q0, [x8, #16]
; CHECK-NEXT: str q0, [x8] ; CHECK-NEXT: str q0, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%p0 = bitcast i32* %p to i8* %p0 = bitcast i32* %p to i8*
Context not available.
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldp w10, w11, [x1] ; CHECK-NEXT: ldp w10, w11, [x1]
; CHECK-NEXT: mov x8, x0 ; CHECK-NEXT: mov x8, x0
; CHECK-NEXT: mov x9, #-6148914691236517206 ; CHECK-NEXT: mov x9, #-6148914691236517206 // =0xaaaaaaaaaaaaaaaa
; CHECK-NEXT: add w0, w10, w11
; CHECK-NEXT: stp x9, x9, [x8] ; CHECK-NEXT: stp x9, x9, [x8]
; CHECK-NEXT: add w0, w10, w11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%p0 = bitcast i32* %p to i8* %p0 = bitcast i32* %p to i8*
tail call void @llvm.memset.p0i8.i64(i8* noundef nonnull align 4 dereferenceable(16) %p0, i8 170, i64 16, i1 false), !alias.scope !2, !noalias !4 tail call void @llvm.memset.p0i8.i64(i8* noundef nonnull align 4 dereferenceable(16) %p0, i8 170, i64 16, i1 false), !alias.scope !2, !noalias !4
Context not available.
; CHECK-LABEL: test_mempcpy: ; CHECK-LABEL: test_mempcpy:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldp w9, w10, [x1] ; CHECK-NEXT: ldp w9, w10, [x1]
; CHECK-NEXT: ldr q0, [x0, #16]
; CHECK-NEXT: mov x8, x0 ; CHECK-NEXT: mov x8, x0
; CHECK-NEXT: add w0, w9, w10 ; CHECK-NEXT: add w0, w9, w10
; CHECK-NEXT: ldr q0, [x8, #16]
; CHECK-NEXT: str q0, [x8] ; CHECK-NEXT: str q0, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%p0 = bitcast i32* %p to i8* %p0 = bitcast i32* %p to i8*
Context not available.
dmgreenUnsubmitted
Done
ReplyInline Actions

Things like this can be removed too, so long as there are check lines elsewhere.

dmgreen: Things like this can be removed too, so long as there are check lines elsewhere.

llvm/test/CodeGen/AArch64/merge-trunc-store.ll

llvm/test/CodeGen/AArch64/midpoint-int.ll

llvm/test/CodeGen/AArch64/minmax-of-minmax.ll

llvm/test/CodeGen/AArch64/minmax.ll

llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir

# RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon %s -o - 2>&1 \ # RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -mcpu=cortex-a55 %s -o - 2>&1 \
dmgreenUnsubmitted
Done
ReplyInline Actions

This doesn't look right. Should it be using -mcpu=cortex-a55 instead?

dmgreen: This doesn't look right. Should it be using -mcpu=cortex-a55 instead?
harviniriawanAuthorUnsubmitted
Done
ReplyInline Actions

shouldn't it be a510 as it's the default scheduling policy now?

harviniriawan: shouldn't it be a510 as it's the default scheduling policy now?
dmgreenUnsubmitted
Done
ReplyInline Actions

Sorry I forgot to reply to the old comment. AFAIU this is testing some of the info in the scheduling model, not which model is being used. So pinning it to the A55 makes sense for keeping the old testing in place.

dmgreen: Sorry I forgot to reply to the old comment. AFAIU this is testing some of the info in the…
# RUN: -misched-dump-reserved-cycles=true \ # RUN: -misched-dump-reserved-cycles=true \
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler \ # RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler \
# RUN: -misched-bottomup=true -sched-print-cycles=true \ # RUN: -misched-bottomup=true -sched-print-cycles=true \
Context not available.
source_filename = "../llvm-project/llvm/test/CodeGen/AArch64/aarch64-smull.failing.ll" source_filename = "../llvm-project/llvm/test/CodeGen/AArch64/aarch64-smull.failing.ll"
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-none-linux-gnu" target triple = "aarch64-none-linux-gnu"
define <8 x i32> @umull_and_v8i32(<8 x i16> %src1, <8 x i32> %src2) #0 { define <8 x i32> @umull_and_v8i32(<8 x i16> %src1, <8 x i32> %src2) #0 {
entry: entry:
%in1 = zext <8 x i16> %src1 to <8 x i32> %in1 = zext <8 x i16> %src1 to <8 x i32>
Context not available.
%out = mul nsw <8 x i32> %in1, %in2 %out = mul nsw <8 x i32> %in1, %in2
ret <8 x i32> %out ret <8 x i32> %out
} }
attributes #0 = { "target-features"="+neon" } attributes #0 = { "target-features"="+neon" }
... ...
dmgreenUnsubmitted
Done
ReplyInline Actions

This file can specify -mcpu=cortex-a55 to keep the test as it was before.

dmgreen: This file can specify -mcpu=cortex-a55 to keep the test as it was before.
Context not available.
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2 liveins: $q0, $q1, $q2
%2:fpr128 = COPY $q2 %2:fpr128 = COPY $q2
%1:fpr128 = COPY $q1 %1:fpr128 = COPY $q1
%0:fpr128 = COPY $q0 %0:fpr128 = COPY $q0
Context not available.
# CHECK-LABEL: Before MISched: # CHECK-LABEL: Before MISched:
# CHECK-NEXT: # Machine code for function umull_and_v8i32: IsSSA, NoPHIs, TracksLiveness # CHECK-NEXT: # Machine code for function umull_and_v8i32: IsSSA, NoPHIs, TracksLiveness
# CHECK-NEXT: Function Live Ins: $q0 in %0, $q1 in %1, $q2 in %2 # CHECK-NEXT: Function Live Ins: $q0 in %0, $q1 in %1, $q2 in %2
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: bb.0.entry: # CHECK-NEXT: bb.0.entry:
# CHECK-NEXT: liveins: $q0, $q1, $q2 # CHECK-NEXT: liveins: $q0, $q1, $q2
# CHECK-NEXT: %2:fpr128 = COPY $q2 # CHECK-NEXT: %2:fpr128 = COPY $q2
Context not available.
# CHECK-NEXT: $q0 = COPY %10:fpr128 # CHECK-NEXT: $q0 = COPY %10:fpr128
# CHECK-NEXT: $q1 = COPY %12:fpr128 # CHECK-NEXT: $q1 = COPY %12:fpr128
# CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1 # CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: # End machine code for function umull_and_v8i32. # CHECK-NEXT: # End machine code for function umull_and_v8i32.
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: ********** MI Scheduling ********** # CHECK-NEXT: ********** MI Scheduling **********
# CHECK-NEXT: umull_and_v8i32:%bb.0 entry # CHECK-NEXT: umull_and_v8i32:%bb.0 entry
# CHECK-NEXT: From: %2:fpr128 = COPY $q2 # CHECK-NEXT: From: %2:fpr128 = COPY $q2
Context not available.
# CHECK-NEXT: Predecessors: # CHECK-NEXT: Predecessors:
# CHECK-NEXT: SU(12): Ord Latency=3 Artificial # CHECK-NEXT: SU(12): Ord Latency=3 Artificial
# CHECK-NEXT: SU(11): Ord Latency=3 Artificial # CHECK-NEXT: SU(11): Ord Latency=3 Artificial
# CHECK-NEXT: Resource booking (@0c): # CHECK-NEXT: Resource booking (@0c):
# CHECK-NEXT: CortexA55UnitALU(0) = 4294967295 # CHECK-NEXT: CortexA55UnitALU(0) = 4294967295
# CHECK-NEXT: CortexA55UnitALU(1) = 4294967295 # CHECK-NEXT: CortexA55UnitALU(1) = 4294967295
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@0c): # CHECK-NEXT: getNextResourceCycle (@0c):
# CHECK-NEXT: Instance 0 available @0c # CHECK-NEXT: Instance 0 available @0c
# CHECK-NEXT: Instance 1 available @0c # CHECK-NEXT: Instance 1 available @0c
# CHECK-NEXT: selecting CortexA55UnitALU[0] available @0c # CHECK-NEXT: selecting CortexA55UnitALU[0] available @0c
# CHECK-NEXT: Resource booking (@0c): # CHECK-NEXT: Resource booking (@0c):
# CHECK-NEXT: CortexA55UnitALU(0) = 4294967295 # CHECK-NEXT: CortexA55UnitALU(0) = 4294967295
# CHECK-NEXT: CortexA55UnitALU(1) = 4294967295 # CHECK-NEXT: CortexA55UnitALU(1) = 4294967295
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@0c): # CHECK-NEXT: getNextResourceCycle (@0c):
# CHECK-NEXT: Instance 0 available @0c # CHECK-NEXT: Instance 0 available @0c
# CHECK-NEXT: Instance 1 available @0c # CHECK-NEXT: Instance 1 available @0c
# CHECK-NEXT: selecting CortexA55UnitALU[0] available @0c # CHECK-NEXT: selecting CortexA55UnitALU[0] available @0c
# CHECK-NEXT: Resource booking (@0c): # CHECK-NEXT: Resource booking (@0c):
# CHECK-NEXT: CortexA55UnitALU(0) = 4294967295 # CHECK-NEXT: CortexA55UnitALU(0) = 4294967295
# CHECK-NEXT: CortexA55UnitALU(1) = 4294967295 # CHECK-NEXT: CortexA55UnitALU(1) = 4294967295
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@0c): # CHECK-NEXT: getNextResourceCycle (@0c):
# CHECK-NEXT: Instance 0 available @0c # CHECK-NEXT: Instance 0 available @0c
# CHECK-NEXT: Instance 1 available @0c # CHECK-NEXT: Instance 1 available @0c
# CHECK-NEXT: selecting CortexA55UnitALU[0] available @0c # CHECK-NEXT: selecting CortexA55UnitALU[0] available @0c
# CHECK-NEXT: Resource booking (@0c): # CHECK-NEXT: Resource booking (@0c):
# CHECK-NEXT: CortexA55UnitALU(0) = 4294967295 # CHECK-NEXT: CortexA55UnitALU(0) = 4294967295
# CHECK-NEXT: CortexA55UnitALU(1) = 4294967295 # CHECK-NEXT: CortexA55UnitALU(1) = 4294967295
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@0c): # CHECK-NEXT: getNextResourceCycle (@0c):
# CHECK-NEXT: Instance 0 available @0c # CHECK-NEXT: Instance 0 available @0c
# CHECK-NEXT: Instance 1 available @0c # CHECK-NEXT: Instance 1 available @0c
# CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @0c # CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @0c
# CHECK-NEXT: Critical Path(GS-RR ): 14 # CHECK-NEXT: Critical Path(GS-RR ): 14
# CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node # CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node
# CHECK-NEXT: Cycle: 3 BotQ.A # CHECK-NEXT: Cycle: 3 BotQ.A
# CHECK-NEXT: Resource booking (@3c): # CHECK-NEXT: Resource booking (@3c):
# CHECK-NEXT: CortexA55UnitALU(0) = 4294967295 # CHECK-NEXT: CortexA55UnitALU(0) = 4294967295
# CHECK-NEXT: CortexA55UnitALU(1) = 4294967295 # CHECK-NEXT: CortexA55UnitALU(1) = 4294967295
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@3c): # CHECK-NEXT: getNextResourceCycle (@3c):
# CHECK-NEXT: Instance 0 available @3c # CHECK-NEXT: Instance 0 available @3c
# CHECK-NEXT: Instance 1 available @3c # CHECK-NEXT: Instance 1 available @3c
# CHECK-NEXT: selecting CortexA55UnitALU[0] available @3c # CHECK-NEXT: selecting CortexA55UnitALU[0] available @3c
# CHECK-NEXT: Resource booking (@3c): # CHECK-NEXT: Resource booking (@3c):
# CHECK-NEXT: CortexA55UnitALU(0) = 4294967295 # CHECK-NEXT: CortexA55UnitALU(0) = 4294967295
# CHECK-NEXT: CortexA55UnitALU(1) = 4294967295 # CHECK-NEXT: CortexA55UnitALU(1) = 4294967295
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@3c): # CHECK-NEXT: getNextResourceCycle (@3c):
# CHECK-NEXT: Instance 0 available @3c # CHECK-NEXT: Instance 0 available @3c
# CHECK-NEXT: Instance 1 available @3c # CHECK-NEXT: Instance 1 available @3c
# CHECK-NEXT: selecting CortexA55UnitALU[0] available @3c # CHECK-NEXT: selecting CortexA55UnitALU[0] available @3c
# CHECK-NEXT: Queue BotQ.P: # CHECK-NEXT: Queue BotQ.P:
# CHECK-NEXT: Queue BotQ.A: 12 11 # CHECK-NEXT: Queue BotQ.A: 12 11
# CHECK-NEXT: Cand SU(12) ORDER # CHECK-NEXT: Cand SU(12) ORDER
# CHECK-NEXT: Pick Bot ORDER # CHECK-NEXT: Pick Bot ORDER
# CHECK-NEXT: Scheduling SU(12) $q1 = COPY %12:fpr128 # CHECK-NEXT: Scheduling SU(12) $q1 = COPY %12:fpr128
# CHECK-NEXT: Ready @3c # CHECK-NEXT: Ready @3c
# CHECK-NEXT: CortexA55UnitALU +1x1u # CHECK-NEXT: CortexA55UnitALU +1x1u
# CHECK-NEXT: Resource booking (@3c): # CHECK-NEXT: Resource booking (@3c):
# CHECK-NEXT: CortexA55UnitALU(0) = 4294967295 # CHECK-NEXT: CortexA55UnitALU(0) = 4294967295
# CHECK-NEXT: CortexA55UnitALU(1) = 4294967295 # CHECK-NEXT: CortexA55UnitALU(1) = 4294967295
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@3c): # CHECK-NEXT: getNextResourceCycle (@3c):
# CHECK-NEXT: Instance 0 available @3c # CHECK-NEXT: Instance 0 available @3c
# CHECK-NEXT: Instance 1 available @3c # CHECK-NEXT: Instance 1 available @3c
# CHECK-NEXT: selecting CortexA55UnitALU[0] available @3c # CHECK-NEXT: selecting CortexA55UnitALU[0] available @3c
# CHECK-NEXT: Resource booking (@3c): # CHECK-NEXT: Resource booking (@3c):
# CHECK-NEXT: CortexA55UnitALU(0) = 4294967295 # CHECK-NEXT: CortexA55UnitALU(0) = 4294967295
# CHECK-NEXT: CortexA55UnitALU(1) = 4294967295 # CHECK-NEXT: CortexA55UnitALU(1) = 4294967295
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@3c): # CHECK-NEXT: getNextResourceCycle (@3c):
# CHECK-NEXT: Instance 0 available @3c # CHECK-NEXT: Instance 0 available @3c
# CHECK-NEXT: Instance 1 available @3c # CHECK-NEXT: Instance 1 available @3c
# CHECK-NEXT: selecting CortexA55UnitALU[0] available @3c # CHECK-NEXT: selecting CortexA55UnitALU[0] available @3c
Context not available.
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node # CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node
# CHECK-NEXT: Resource booking (@3c): # CHECK-NEXT: Resource booking (@3c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 4294967295 # CHECK-NEXT: CortexA55UnitALU(1) = 4294967295
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@3c): # CHECK-NEXT: getNextResourceCycle (@3c):
# CHECK-NEXT: Instance 0 available @4c # CHECK-NEXT: Instance 0 available @4c
# CHECK-NEXT: Instance 1 available @3c # CHECK-NEXT: Instance 1 available @3c
# CHECK-NEXT: selecting CortexA55UnitALU[1] available @3c # CHECK-NEXT: selecting CortexA55UnitALU[1] available @3c
# CHECK-NEXT: Queue BotQ.P: 10 # CHECK-NEXT: Queue BotQ.P: 10
# CHECK-NEXT: Queue BotQ.A: 11 # CHECK-NEXT: Queue BotQ.A: 11
# CHECK-NEXT: Scheduling SU(11) $q0 = COPY %10:fpr128 # CHECK-NEXT: Scheduling SU(11) $q0 = COPY %10:fpr128
# CHECK-NEXT: Ready @3c # CHECK-NEXT: Ready @3c
# CHECK-NEXT: CortexA55UnitALU +1x1u # CHECK-NEXT: CortexA55UnitALU +1x1u
# CHECK-NEXT: Resource booking (@3c): # CHECK-NEXT: Resource booking (@3c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 4294967295 # CHECK-NEXT: CortexA55UnitALU(1) = 4294967295
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@3c): # CHECK-NEXT: getNextResourceCycle (@3c):
# CHECK-NEXT: Instance 0 available @4c # CHECK-NEXT: Instance 0 available @4c
# CHECK-NEXT: Instance 1 available @3c # CHECK-NEXT: Instance 1 available @3c
# CHECK-NEXT: selecting CortexA55UnitALU[1] available @3c # CHECK-NEXT: selecting CortexA55UnitALU[1] available @3c
# CHECK-NEXT: Resource booking (@3c): # CHECK-NEXT: Resource booking (@3c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 4294967295 # CHECK-NEXT: CortexA55UnitALU(1) = 4294967295
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@3c): # CHECK-NEXT: getNextResourceCycle (@3c):
# CHECK-NEXT: Instance 0 available @4c # CHECK-NEXT: Instance 0 available @4c
# CHECK-NEXT: Instance 1 available @3c # CHECK-NEXT: Instance 1 available @3c
# CHECK-NEXT: selecting CortexA55UnitALU[1] available @3c # CHECK-NEXT: selecting CortexA55UnitALU[1] available @3c
Context not available.
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node # CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node
# CHECK-NEXT: Cycle: 7 BotQ.A # CHECK-NEXT: Cycle: 7 BotQ.A
# CHECK-NEXT: Resource booking (@7c): # CHECK-NEXT: Resource booking (@7c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@7c): # CHECK-NEXT: getNextResourceCycle (@7c):
# CHECK-NEXT: Instance 0 available @7c # CHECK-NEXT: Instance 0 available @7c
# CHECK-NEXT: Instance 1 available @7c # CHECK-NEXT: Instance 1 available @7c
# CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @7c # CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @7c
# CHECK-NEXT: Resource booking (@7c): # CHECK-NEXT: Resource booking (@7c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@7c): # CHECK-NEXT: getNextResourceCycle (@7c):
# CHECK-NEXT: Instance 0 available @7c # CHECK-NEXT: Instance 0 available @7c
# CHECK-NEXT: Instance 1 available @7c # CHECK-NEXT: Instance 1 available @7c
# CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @7c # CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @7c
# CHECK-NEXT: Queue BotQ.P: # CHECK-NEXT: Queue BotQ.P:
# CHECK-NEXT: Queue BotQ.A: 10 8 # CHECK-NEXT: Queue BotQ.A: 10 8
# CHECK-NEXT: Cand SU(10) ORDER # CHECK-NEXT: Cand SU(10) ORDER
# CHECK-NEXT: Pick Bot ORDER # CHECK-NEXT: Pick Bot ORDER
# CHECK-NEXT: Scheduling SU(10) %12:fpr128 = UMULLv4i16_v4i32 %3.dsub:fpr128, %11:fpr64 # CHECK-NEXT: Scheduling SU(10) %12:fpr128 = UMULLv4i16_v4i32 %3.dsub:fpr128, %11:fpr64
# CHECK-NEXT: Ready @7c # CHECK-NEXT: Ready @7c
# CHECK-NEXT: CortexA55UnitFPALU +2x1u # CHECK-NEXT: CortexA55UnitFPALU +2x1u
# CHECK-NEXT: Resource booking (@7c): # CHECK-NEXT: Resource booking (@7c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@7c): # CHECK-NEXT: getNextResourceCycle (@7c):
# CHECK-NEXT: Instance 0 available @7c # CHECK-NEXT: Instance 0 available @7c
# CHECK-NEXT: Instance 1 available @7c # CHECK-NEXT: Instance 1 available @7c
# CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @7c # CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @7c
# CHECK-NEXT: Resource booking (@7c): # CHECK-NEXT: Resource booking (@7c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@7c): # CHECK-NEXT: getNextResourceCycle (@7c):
# CHECK-NEXT: Instance 0 available @7c # CHECK-NEXT: Instance 0 available @7c
# CHECK-NEXT: Instance 1 available @7c # CHECK-NEXT: Instance 1 available @7c
# CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @7c # CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @7c
Context not available.
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node # CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node
# CHECK-NEXT: Resource booking (@8c): # CHECK-NEXT: Resource booking (@8c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@8c): # CHECK-NEXT: getNextResourceCycle (@8c):
# CHECK-NEXT: Instance 0 available @9c # CHECK-NEXT: Instance 0 available @9c
# CHECK-NEXT: Instance 1 available @8c # CHECK-NEXT: Instance 1 available @8c
# CHECK-NEXT: selecting CortexA55UnitFPALU[1] available @8c # CHECK-NEXT: selecting CortexA55UnitFPALU[1] available @8c
# CHECK-NEXT: Queue BotQ.P: 9 3 # CHECK-NEXT: Queue BotQ.P: 9 3
# CHECK-NEXT: Queue BotQ.A: 8 # CHECK-NEXT: Queue BotQ.A: 8
# CHECK-NEXT: Scheduling SU(8) %10:fpr128 = UMULLv4i16_v4i32 %0.dsub:fpr128, %9:fpr64 # CHECK-NEXT: Scheduling SU(8) %10:fpr128 = UMULLv4i16_v4i32 %0.dsub:fpr128, %9:fpr64
# CHECK-NEXT: Ready @8c # CHECK-NEXT: Ready @8c
# CHECK-NEXT: CortexA55UnitFPALU +2x1u # CHECK-NEXT: CortexA55UnitFPALU +2x1u
# CHECK-NEXT: Resource booking (@8c): # CHECK-NEXT: Resource booking (@8c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@8c): # CHECK-NEXT: getNextResourceCycle (@8c):
# CHECK-NEXT: Instance 0 available @9c # CHECK-NEXT: Instance 0 available @9c
# CHECK-NEXT: Instance 1 available @8c # CHECK-NEXT: Instance 1 available @8c
# CHECK-NEXT: selecting CortexA55UnitFPALU[1] available @8c # CHECK-NEXT: selecting CortexA55UnitFPALU[1] available @8c
# CHECK-NEXT: Resource booking (@8c): # CHECK-NEXT: Resource booking (@8c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@8c): # CHECK-NEXT: getNextResourceCycle (@8c):
# CHECK-NEXT: Instance 0 available @9c # CHECK-NEXT: Instance 0 available @9c
# CHECK-NEXT: Instance 1 available @8c # CHECK-NEXT: Instance 1 available @8c
# CHECK-NEXT: selecting CortexA55UnitFPALU[1] available @8c # CHECK-NEXT: selecting CortexA55UnitFPALU[1] available @8c
Context not available.
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node # CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node
# CHECK-NEXT: Resource booking (@9c): # CHECK-NEXT: Resource booking (@9c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@9c): # CHECK-NEXT: getNextResourceCycle (@9c):
# CHECK-NEXT: Instance 0 available @9c # CHECK-NEXT: Instance 0 available @9c
# CHECK-NEXT: Instance 1 available @9c # CHECK-NEXT: Instance 1 available @9c
# CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @9c # CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @9c
# CHECK-NEXT: Resource booking (@9c): # CHECK-NEXT: Resource booking (@9c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@9c): # CHECK-NEXT: getNextResourceCycle (@9c):
# CHECK-NEXT: Instance 0 available @9c # CHECK-NEXT: Instance 0 available @9c
# CHECK-NEXT: Instance 1 available @9c # CHECK-NEXT: Instance 1 available @9c
# CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @9c # CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @9c
# CHECK-NEXT: Queue BotQ.P: 7 3 # CHECK-NEXT: Queue BotQ.P: 7 3
# CHECK-NEXT: Queue BotQ.A: 9 # CHECK-NEXT: Queue BotQ.A: 9
# CHECK-NEXT: Scheduling SU(9) %11:fpr64 = XTNv4i16 %7:fpr128 # CHECK-NEXT: Scheduling SU(9) %11:fpr64 = XTNv4i16 %7:fpr128
# CHECK-NEXT: Ready @9c # CHECK-NEXT: Ready @9c
# CHECK-NEXT: CortexA55UnitFPALU +1x1u # CHECK-NEXT: CortexA55UnitFPALU +1x1u
# CHECK-NEXT: Resource booking (@9c): # CHECK-NEXT: Resource booking (@9c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@9c): # CHECK-NEXT: getNextResourceCycle (@9c):
# CHECK-NEXT: Instance 0 available @9c # CHECK-NEXT: Instance 0 available @9c
# CHECK-NEXT: Instance 1 available @9c # CHECK-NEXT: Instance 1 available @9c
# CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @9c # CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @9c
# CHECK-NEXT: Resource booking (@9c): # CHECK-NEXT: Resource booking (@9c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@9c): # CHECK-NEXT: getNextResourceCycle (@9c):
# CHECK-NEXT: Instance 0 available @9c # CHECK-NEXT: Instance 0 available @9c
# CHECK-NEXT: Instance 1 available @9c # CHECK-NEXT: Instance 1 available @9c
# CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @9c # CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @9c
Context not available.
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node # CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node
# CHECK-NEXT: Cycle: 10 BotQ.A # CHECK-NEXT: Cycle: 10 BotQ.A
# CHECK-NEXT: Resource booking (@10c): # CHECK-NEXT: Resource booking (@10c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@10c): # CHECK-NEXT: getNextResourceCycle (@10c):
# CHECK-NEXT: Instance 0 available @10c # CHECK-NEXT: Instance 0 available @10c
# CHECK-NEXT: Instance 1 available @10c # CHECK-NEXT: Instance 1 available @10c
# CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @10c # CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @10c
# CHECK-NEXT: Resource booking (@10c): # CHECK-NEXT: Resource booking (@10c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@10c): # CHECK-NEXT: getNextResourceCycle (@10c):
# CHECK-NEXT: Instance 0 available @11c # CHECK-NEXT: Instance 0 available @11c
# CHECK-NEXT: Instance 1 available @10c # CHECK-NEXT: Instance 1 available @10c
# CHECK-NEXT: selecting CortexA55UnitFPALU[1] available @10c # CHECK-NEXT: selecting CortexA55UnitFPALU[1] available @10c
# CHECK-NEXT: Queue BotQ.P: 3 # CHECK-NEXT: Queue BotQ.P: 3
# CHECK-NEXT: Queue BotQ.A: 7 5 # CHECK-NEXT: Queue BotQ.A: 7 5
# CHECK-NEXT: Cand SU(7) ORDER # CHECK-NEXT: Cand SU(7) ORDER
# CHECK-NEXT: Pick Bot ORDER # CHECK-NEXT: Pick Bot ORDER
# CHECK-NEXT: Scheduling SU(7) %9:fpr64 = XTNv4i16 %8:fpr128 # CHECK-NEXT: Scheduling SU(7) %9:fpr64 = XTNv4i16 %8:fpr128
# CHECK-NEXT: Ready @10c # CHECK-NEXT: Ready @10c
# CHECK-NEXT: CortexA55UnitFPALU +1x1u # CHECK-NEXT: CortexA55UnitFPALU +1x1u
# CHECK-NEXT: Resource booking (@10c): # CHECK-NEXT: Resource booking (@10c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@10c): # CHECK-NEXT: getNextResourceCycle (@10c):
# CHECK-NEXT: Instance 0 available @10c # CHECK-NEXT: Instance 0 available @10c
# CHECK-NEXT: Instance 1 available @10c # CHECK-NEXT: Instance 1 available @10c
# CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @10c # CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @10c
# CHECK-NEXT: Resource booking (@10c): # CHECK-NEXT: Resource booking (@10c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@10c): # CHECK-NEXT: getNextResourceCycle (@10c):
# CHECK-NEXT: Instance 0 available @10c # CHECK-NEXT: Instance 0 available @10c
# CHECK-NEXT: Instance 1 available @10c # CHECK-NEXT: Instance 1 available @10c
# CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @10c # CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @10c
Context not available.
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node # CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node
# CHECK-NEXT: Resource booking (@10c): # CHECK-NEXT: Resource booking (@10c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@10c): # CHECK-NEXT: getNextResourceCycle (@10c):
# CHECK-NEXT: Instance 0 available @12c # CHECK-NEXT: Instance 0 available @12c
# CHECK-NEXT: Instance 1 available @10c # CHECK-NEXT: Instance 1 available @10c
# CHECK-NEXT: selecting CortexA55UnitFPALU[1] available @10c # CHECK-NEXT: selecting CortexA55UnitFPALU[1] available @10c
# CHECK-NEXT: Queue BotQ.P: 3 6 # CHECK-NEXT: Queue BotQ.P: 3 6
# CHECK-NEXT: Queue BotQ.A: 5 # CHECK-NEXT: Queue BotQ.A: 5
# CHECK-NEXT: Scheduling SU(5) %7:fpr128 = ANDv16i8 %2:fpr128, %6:fpr128 # CHECK-NEXT: Scheduling SU(5) %7:fpr128 = ANDv16i8 %2:fpr128, %6:fpr128
# CHECK-NEXT: Ready @10c # CHECK-NEXT: Ready @10c
# CHECK-NEXT: CortexA55UnitFPALU +2x1u # CHECK-NEXT: CortexA55UnitFPALU +2x1u
# CHECK-NEXT: *** Critical resource CortexA55UnitFPALU: 4c # CHECK-NEXT: *** Critical resource CortexA55UnitFPALU: 4c
# CHECK-NEXT: Resource booking (@10c): # CHECK-NEXT: Resource booking (@10c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@10c): # CHECK-NEXT: getNextResourceCycle (@10c):
# CHECK-NEXT: Instance 0 available @12c # CHECK-NEXT: Instance 0 available @12c
# CHECK-NEXT: Instance 1 available @10c # CHECK-NEXT: Instance 1 available @10c
# CHECK-NEXT: selecting CortexA55UnitFPALU[1] available @10c # CHECK-NEXT: selecting CortexA55UnitFPALU[1] available @10c
# CHECK-NEXT: Resource booking (@10c): # CHECK-NEXT: Resource booking (@10c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@10c): # CHECK-NEXT: getNextResourceCycle (@10c):
# CHECK-NEXT: Instance 0 available @12c # CHECK-NEXT: Instance 0 available @12c
# CHECK-NEXT: Instance 1 available @10c # CHECK-NEXT: Instance 1 available @10c
# CHECK-NEXT: selecting CortexA55UnitFPALU[1] available @10c # CHECK-NEXT: selecting CortexA55UnitFPALU[1] available @10c
Context not available.
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node # CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node
# CHECK-NEXT: Resource booking (@11c): # CHECK-NEXT: Resource booking (@11c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@11c): # CHECK-NEXT: getNextResourceCycle (@11c):
# CHECK-NEXT: Instance 0 available @12c # CHECK-NEXT: Instance 0 available @12c
# CHECK-NEXT: Instance 1 available @12c # CHECK-NEXT: Instance 1 available @12c
# CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @12c # CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @12c
# CHECK-NEXT: SU(3) CortexA55UnitFPALU[0]=12c # CHECK-NEXT: SU(3) CortexA55UnitFPALU[0]=12c
# CHECK-NEXT: Resource booking (@11c): # CHECK-NEXT: Resource booking (@11c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@11c): # CHECK-NEXT: getNextResourceCycle (@11c):
# CHECK-NEXT: Instance 0 available @12c # CHECK-NEXT: Instance 0 available @12c
# CHECK-NEXT: Instance 1 available @12c # CHECK-NEXT: Instance 1 available @12c
# CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @12c # CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @12c
# CHECK-NEXT: SU(6) CortexA55UnitFPALU[0]=12c # CHECK-NEXT: SU(6) CortexA55UnitFPALU[0]=12c
# CHECK-NEXT: Cycle: 12 BotQ.A # CHECK-NEXT: Cycle: 12 BotQ.A
# CHECK-NEXT: Resource booking (@12c): # CHECK-NEXT: Resource booking (@12c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@12c): # CHECK-NEXT: getNextResourceCycle (@12c):
# CHECK-NEXT: Instance 0 available @12c # CHECK-NEXT: Instance 0 available @12c
# CHECK-NEXT: Instance 1 available @12c # CHECK-NEXT: Instance 1 available @12c
# CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @12c # CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @12c
# CHECK-NEXT: Resource booking (@12c): # CHECK-NEXT: Resource booking (@12c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@12c): # CHECK-NEXT: getNextResourceCycle (@12c):
# CHECK-NEXT: Instance 0 available @12c # CHECK-NEXT: Instance 0 available @12c
# CHECK-NEXT: Instance 1 available @12c # CHECK-NEXT: Instance 1 available @12c
# CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @12c # CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @12c
# CHECK-NEXT: Queue BotQ.P: 0 # CHECK-NEXT: Queue BotQ.P: 0
# CHECK-NEXT: Queue BotQ.A: 3 6 # CHECK-NEXT: Queue BotQ.A: 3 6
# CHECK-NEXT: Cand SU(3) ORDER # CHECK-NEXT: Cand SU(3) ORDER
# CHECK-NEXT: Cand SU(6) ORDER # CHECK-NEXT: Cand SU(6) ORDER
# CHECK-NEXT: Pick Bot ORDER # CHECK-NEXT: Pick Bot ORDER
# CHECK-NEXT: Scheduling SU(6) %8:fpr128 = ANDv16i8 %1:fpr128, %6:fpr128 # CHECK-NEXT: Scheduling SU(6) %8:fpr128 = ANDv16i8 %1:fpr128, %6:fpr128
# CHECK-NEXT: Ready @12c # CHECK-NEXT: Ready @12c
# CHECK-NEXT: CortexA55UnitFPALU +2x1u # CHECK-NEXT: CortexA55UnitFPALU +2x1u
# CHECK-NEXT: Resource booking (@12c): # CHECK-NEXT: Resource booking (@12c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@12c): # CHECK-NEXT: getNextResourceCycle (@12c):
# CHECK-NEXT: Instance 0 available @12c # CHECK-NEXT: Instance 0 available @12c
# CHECK-NEXT: Instance 1 available @12c # CHECK-NEXT: Instance 1 available @12c
# CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @12c # CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @12c
# CHECK-NEXT: Resource booking (@12c): # CHECK-NEXT: Resource booking (@12c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@12c): # CHECK-NEXT: getNextResourceCycle (@12c):
# CHECK-NEXT: Instance 0 available @12c # CHECK-NEXT: Instance 0 available @12c
# CHECK-NEXT: Instance 1 available @12c # CHECK-NEXT: Instance 1 available @12c
# CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @12c # CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @12c
Context not available.
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node # CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node
# CHECK-NEXT: Resource booking (@13c): # CHECK-NEXT: Resource booking (@13c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@13c): # CHECK-NEXT: getNextResourceCycle (@13c):
# CHECK-NEXT: Instance 0 available @13c # CHECK-NEXT: Instance 0 available @13c
# CHECK-NEXT: Instance 1 available @13c # CHECK-NEXT: Instance 1 available @13c
# CHECK-NEXT: selecting CortexA55UnitALU[0] available @13c # CHECK-NEXT: selecting CortexA55UnitALU[0] available @13c
# CHECK-NEXT: Resource booking (@13c): # CHECK-NEXT: Resource booking (@13c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@13c): # CHECK-NEXT: getNextResourceCycle (@13c):
# CHECK-NEXT: Instance 0 available @14c # CHECK-NEXT: Instance 0 available @14c
# CHECK-NEXT: Instance 1 available @13c # CHECK-NEXT: Instance 1 available @13c
# CHECK-NEXT: selecting CortexA55UnitFPALU[1] available @13c # CHECK-NEXT: selecting CortexA55UnitFPALU[1] available @13c
# CHECK-NEXT: Resource booking (@13c): # CHECK-NEXT: Resource booking (@13c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@13c): # CHECK-NEXT: getNextResourceCycle (@13c):
# CHECK-NEXT: Instance 0 available @13c # CHECK-NEXT: Instance 0 available @13c
# CHECK-NEXT: Instance 1 available @13c # CHECK-NEXT: Instance 1 available @13c
# CHECK-NEXT: selecting CortexA55UnitALU[0] available @13c # CHECK-NEXT: selecting CortexA55UnitALU[0] available @13c
# CHECK-NEXT: Queue BotQ.P: 1 4 # CHECK-NEXT: Queue BotQ.P: 1 4
# CHECK-NEXT: Queue BotQ.A: 3 0 # CHECK-NEXT: Queue BotQ.A: 3 0
# CHECK-NEXT: Cand SU(3) ORDER # CHECK-NEXT: Cand SU(3) ORDER
# CHECK-NEXT: Pick Bot PHYS-REG # CHECK-NEXT: Pick Bot PHYS-REG
# CHECK-NEXT: Scheduling SU(3) %3:fpr128 = EXTv16i8 %0:fpr128, %0:fpr128, 8 # CHECK-NEXT: Scheduling SU(3) %3:fpr128 = EXTv16i8 %0:fpr128, %0:fpr128, 8
# CHECK-NEXT: Ready @13c # CHECK-NEXT: Ready @13c
# CHECK-NEXT: CortexA55UnitFPALU +2x1u # CHECK-NEXT: CortexA55UnitFPALU +2x1u
# CHECK-NEXT: Resource booking (@13c): # CHECK-NEXT: Resource booking (@13c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@13c): # CHECK-NEXT: getNextResourceCycle (@13c):
# CHECK-NEXT: Instance 0 available @14c # CHECK-NEXT: Instance 0 available @14c
# CHECK-NEXT: Instance 1 available @13c # CHECK-NEXT: Instance 1 available @13c
# CHECK-NEXT: selecting CortexA55UnitFPALU[1] available @13c # CHECK-NEXT: selecting CortexA55UnitFPALU[1] available @13c
# CHECK-NEXT: Resource booking (@13c): # CHECK-NEXT: Resource booking (@13c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@13c): # CHECK-NEXT: getNextResourceCycle (@13c):
# CHECK-NEXT: Instance 0 available @14c # CHECK-NEXT: Instance 0 available @14c
# CHECK-NEXT: Instance 1 available @13c # CHECK-NEXT: Instance 1 available @13c
# CHECK-NEXT: selecting CortexA55UnitFPALU[1] available @13c # CHECK-NEXT: selecting CortexA55UnitFPALU[1] available @13c
Context not available.
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node # CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node
# CHECK-NEXT: Resource booking (@14c): # CHECK-NEXT: Resource booking (@14c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@14c): # CHECK-NEXT: getNextResourceCycle (@14c):
# CHECK-NEXT: Instance 0 available @14c # CHECK-NEXT: Instance 0 available @14c
# CHECK-NEXT: Instance 1 available @14c # CHECK-NEXT: Instance 1 available @14c
# CHECK-NEXT: selecting CortexA55UnitALU[0] available @14c # CHECK-NEXT: selecting CortexA55UnitALU[0] available @14c
# CHECK-NEXT: Queue BotQ.P: 1 4 2 # CHECK-NEXT: Queue BotQ.P: 1 4 2
# CHECK-NEXT: Queue BotQ.A: 0 # CHECK-NEXT: Queue BotQ.A: 0
# CHECK-NEXT: Scheduling SU(0) %2:fpr128 = COPY $q2 # CHECK-NEXT: Scheduling SU(0) %2:fpr128 = COPY $q2
# CHECK-NEXT: Ready @14c # CHECK-NEXT: Ready @14c
# CHECK-NEXT: CortexA55UnitALU +1x1u # CHECK-NEXT: CortexA55UnitALU +1x1u
# CHECK-NEXT: Resource booking (@14c): # CHECK-NEXT: Resource booking (@14c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@14c): # CHECK-NEXT: getNextResourceCycle (@14c):
# CHECK-NEXT: Instance 0 available @14c # CHECK-NEXT: Instance 0 available @14c
# CHECK-NEXT: Instance 1 available @14c # CHECK-NEXT: Instance 1 available @14c
# CHECK-NEXT: selecting CortexA55UnitALU[0] available @14c # CHECK-NEXT: selecting CortexA55UnitALU[0] available @14c
# CHECK-NEXT: Resource booking (@14c): # CHECK-NEXT: Resource booking (@14c):
# CHECK-NEXT: CortexA55UnitALU(0) = 3 # CHECK-NEXT: CortexA55UnitALU(0) = 3
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@14c): # CHECK-NEXT: getNextResourceCycle (@14c):
# CHECK-NEXT: Instance 0 available @14c # CHECK-NEXT: Instance 0 available @14c
# CHECK-NEXT: Instance 1 available @14c # CHECK-NEXT: Instance 1 available @14c
# CHECK-NEXT: selecting CortexA55UnitALU[0] available @14c # CHECK-NEXT: selecting CortexA55UnitALU[0] available @14c
Context not available.
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node # CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node
# CHECK-NEXT: Cycle: 15 BotQ.A # CHECK-NEXT: Cycle: 15 BotQ.A
# CHECK-NEXT: Resource booking (@15c): # CHECK-NEXT: Resource booking (@15c):
# CHECK-NEXT: CortexA55UnitALU(0) = 14 # CHECK-NEXT: CortexA55UnitALU(0) = 14
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@15c): # CHECK-NEXT: getNextResourceCycle (@15c):
# CHECK-NEXT: Instance 0 available @15c # CHECK-NEXT: Instance 0 available @15c
# CHECK-NEXT: Instance 1 available @15c # CHECK-NEXT: Instance 1 available @15c
# CHECK-NEXT: selecting CortexA55UnitALU[0] available @15c # CHECK-NEXT: selecting CortexA55UnitALU[0] available @15c
# CHECK-NEXT: Queue BotQ.P: 2 4 # CHECK-NEXT: Queue BotQ.P: 2 4
# CHECK-NEXT: Queue BotQ.A: 1 # CHECK-NEXT: Queue BotQ.A: 1
# CHECK-NEXT: Scheduling SU(1) %1:fpr128 = COPY $q1 # CHECK-NEXT: Scheduling SU(1) %1:fpr128 = COPY $q1
# CHECK-NEXT: Ready @15c # CHECK-NEXT: Ready @15c
# CHECK-NEXT: CortexA55UnitALU +1x1u # CHECK-NEXT: CortexA55UnitALU +1x1u
# CHECK-NEXT: Resource booking (@15c): # CHECK-NEXT: Resource booking (@15c):
# CHECK-NEXT: CortexA55UnitALU(0) = 14 # CHECK-NEXT: CortexA55UnitALU(0) = 14
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@15c): # CHECK-NEXT: getNextResourceCycle (@15c):
# CHECK-NEXT: Instance 0 available @15c # CHECK-NEXT: Instance 0 available @15c
# CHECK-NEXT: Instance 1 available @15c # CHECK-NEXT: Instance 1 available @15c
# CHECK-NEXT: selecting CortexA55UnitALU[0] available @15c # CHECK-NEXT: selecting CortexA55UnitALU[0] available @15c
# CHECK-NEXT: Resource booking (@15c): # CHECK-NEXT: Resource booking (@15c):
# CHECK-NEXT: CortexA55UnitALU(0) = 14 # CHECK-NEXT: CortexA55UnitALU(0) = 14
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@15c): # CHECK-NEXT: getNextResourceCycle (@15c):
# CHECK-NEXT: Instance 0 available @15c # CHECK-NEXT: Instance 0 available @15c
# CHECK-NEXT: Instance 1 available @15c # CHECK-NEXT: Instance 1 available @15c
# CHECK-NEXT: selecting CortexA55UnitALU[0] available @15c # CHECK-NEXT: selecting CortexA55UnitALU[0] available @15c
Context not available.
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node # CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node
# CHECK-NEXT: Cycle: 16 BotQ.A # CHECK-NEXT: Cycle: 16 BotQ.A
# CHECK-NEXT: Resource booking (@16c): # CHECK-NEXT: Resource booking (@16c):
# CHECK-NEXT: CortexA55UnitALU(0) = 15 # CHECK-NEXT: CortexA55UnitALU(0) = 15
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@16c): # CHECK-NEXT: getNextResourceCycle (@16c):
# CHECK-NEXT: Instance 0 available @16c # CHECK-NEXT: Instance 0 available @16c
# CHECK-NEXT: Instance 1 available @16c # CHECK-NEXT: Instance 1 available @16c
# CHECK-NEXT: selecting CortexA55UnitALU[0] available @16c # CHECK-NEXT: selecting CortexA55UnitALU[0] available @16c
# CHECK-NEXT: Resource booking (@16c): # CHECK-NEXT: Resource booking (@16c):
# CHECK-NEXT: CortexA55UnitALU(0) = 15 # CHECK-NEXT: CortexA55UnitALU(0) = 15
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@16c): # CHECK-NEXT: getNextResourceCycle (@16c):
# CHECK-NEXT: Instance 0 available @16c # CHECK-NEXT: Instance 0 available @16c
# CHECK-NEXT: Instance 1 available @16c # CHECK-NEXT: Instance 1 available @16c
# CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @16c # CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @16c
# CHECK-NEXT: Queue BotQ.P: # CHECK-NEXT: Queue BotQ.P:
# CHECK-NEXT: Queue BotQ.A: 2 4 # CHECK-NEXT: Queue BotQ.A: 2 4
# CHECK-NEXT: Cand SU(2) ORDER # CHECK-NEXT: Cand SU(2) ORDER
# CHECK-NEXT: Cand SU(4) PHYS-REG # CHECK-NEXT: Cand SU(4) PHYS-REG
# CHECK-NEXT: Pick Bot PHYS-REG # CHECK-NEXT: Pick Bot PHYS-REG
# CHECK-NEXT: Scheduling SU(4) %6:fpr128 = MOVIv2d_ns 17 # CHECK-NEXT: Scheduling SU(4) %6:fpr128 = MOVIv2d_ns 17
# CHECK-NEXT: Ready @16c # CHECK-NEXT: Ready @16c
# CHECK-NEXT: CortexA55UnitFPALU +2x1u # CHECK-NEXT: CortexA55UnitFPALU +2x1u
# CHECK-NEXT: Resource booking (@16c): # CHECK-NEXT: Resource booking (@16c):
# CHECK-NEXT: CortexA55UnitALU(0) = 15 # CHECK-NEXT: CortexA55UnitALU(0) = 15
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@16c): # CHECK-NEXT: getNextResourceCycle (@16c):
# CHECK-NEXT: Instance 0 available @16c # CHECK-NEXT: Instance 0 available @16c
# CHECK-NEXT: Instance 1 available @16c # CHECK-NEXT: Instance 1 available @16c
# CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @16c # CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @16c
# CHECK-NEXT: Resource booking (@16c): # CHECK-NEXT: Resource booking (@16c):
# CHECK-NEXT: CortexA55UnitALU(0) = 15 # CHECK-NEXT: CortexA55UnitALU(0) = 15
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@16c): # CHECK-NEXT: getNextResourceCycle (@16c):
# CHECK-NEXT: Instance 0 available @16c # CHECK-NEXT: Instance 0 available @16c
# CHECK-NEXT: Instance 1 available @16c # CHECK-NEXT: Instance 1 available @16c
# CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @16c # CHECK-NEXT: selecting CortexA55UnitFPALU[0] available @16c
Context not available.
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node # CHECK-NEXT: ** ScheduleDAGMILive::schedule picking next node
# CHECK-NEXT: Resource booking (@17c): # CHECK-NEXT: Resource booking (@17c):
# CHECK-NEXT: CortexA55UnitALU(0) = 15 # CHECK-NEXT: CortexA55UnitALU(0) = 15
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@17c): # CHECK-NEXT: getNextResourceCycle (@17c):
# CHECK-NEXT: Instance 0 available @17c # CHECK-NEXT: Instance 0 available @17c
# CHECK-NEXT: Instance 1 available @17c # CHECK-NEXT: Instance 1 available @17c
# CHECK-NEXT: selecting CortexA55UnitALU[0] available @17c # CHECK-NEXT: selecting CortexA55UnitALU[0] available @17c
# CHECK-NEXT: Queue BotQ.P: # CHECK-NEXT: Queue BotQ.P:
# CHECK-NEXT: Queue BotQ.A: 2 # CHECK-NEXT: Queue BotQ.A: 2
# CHECK-NEXT: Scheduling SU(2) %0:fpr128 = COPY $q0 # CHECK-NEXT: Scheduling SU(2) %0:fpr128 = COPY $q0
# CHECK-NEXT: Ready @17c # CHECK-NEXT: Ready @17c
# CHECK-NEXT: CortexA55UnitALU +1x1u # CHECK-NEXT: CortexA55UnitALU +1x1u
# CHECK-NEXT: Resource booking (@17c): # CHECK-NEXT: Resource booking (@17c):
# CHECK-NEXT: CortexA55UnitALU(0) = 15 # CHECK-NEXT: CortexA55UnitALU(0) = 15
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@17c): # CHECK-NEXT: getNextResourceCycle (@17c):
# CHECK-NEXT: Instance 0 available @17c # CHECK-NEXT: Instance 0 available @17c
# CHECK-NEXT: Instance 1 available @17c # CHECK-NEXT: Instance 1 available @17c
# CHECK-NEXT: selecting CortexA55UnitALU[0] available @17c # CHECK-NEXT: selecting CortexA55UnitALU[0] available @17c
# CHECK-NEXT: Resource booking (@17c): # CHECK-NEXT: Resource booking (@17c):
# CHECK-NEXT: CortexA55UnitALU(0) = 15 # CHECK-NEXT: CortexA55UnitALU(0) = 15
# CHECK-NEXT: CortexA55UnitALU(1) = 3 # CHECK-NEXT: CortexA55UnitALU(1) = 3
# CHECK-NEXT: CortexA55UnitB(0) = 4294967295 # CHECK-NEXT: CortexA55UnitB(0) = 4294967295
Context not available.
# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295 # CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295 # CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
# CHECK-NEXT: CortexA55UnitSt(0) = 4294967295 # CHECK-NEXT: CortexA55UnitSt(0) = 4294967295
# CHECK-NEXT: getNextResourceCycle (@17c): # CHECK-NEXT: getNextResourceCycle (@17c):
# CHECK-NEXT: Instance 0 available @17c # CHECK-NEXT: Instance 0 available @17c
# CHECK-NEXT: Instance 1 available @17c # CHECK-NEXT: Instance 1 available @17c
# CHECK-NEXT: selecting CortexA55UnitALU[0] available @17c # CHECK-NEXT: selecting CortexA55UnitALU[0] available @17c
Context not available.
# CHECK-NEXT: x: resource booked # CHECK-NEXT: x: resource booked
# CHECK-NEXT: Cycle | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | # CHECK-NEXT: Cycle | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 |
# CHECK-NEXT: SU(2) | i | | | | | | | | | | | | | | | # CHECK-NEXT: SU(2) | i | | | | | | | | | | | | | | |
# CHECK-NEXT: CortexA55UnitALU | x | | | | | | | | | | | | | | | # CHECK-NEXT: CortexA55UnitALU | x | | | | | | | | | | | | | | |
# CHECK-NEXT: SU(4) | | i | | | | | | | | | | | | | | # CHECK-NEXT: SU(4) | | i | | | | | | | | | | | | | |
# CHECK-NEXT: CortexA55UnitFPALU | | x | x | | | | | | | | | | | | | # CHECK-NEXT: CortexA55UnitFPALU | | x | x | | | | | | | | | | | | |
# CHECK-NEXT: SU(1) | | | i | | | | | | | | | | | | | # CHECK-NEXT: SU(1) | | | i | | | | | | | | | | | | |
# CHECK-NEXT: CortexA55UnitALU | | | x | | | | | | | | | | | | | # CHECK-NEXT: CortexA55UnitALU | | | x | | | | | | | | | | | | |
# CHECK-NEXT: SU(0) | | | | i | | | | | | | | | | | | # CHECK-NEXT: SU(0) | | | | i | | | | | | | | | | | |
# CHECK-NEXT: CortexA55UnitALU | | | | x | | | | | | | | | | | | # CHECK-NEXT: CortexA55UnitALU | | | | x | | | | | | | | | | | |
# CHECK-NEXT: SU(3) | | | | | i | | | | | | | | | | | # CHECK-NEXT: SU(3) | | | | | i | | | | | | | | | | |
# CHECK-NEXT: CortexA55UnitFPALU | | | | | x | x | | | | | | | | | | # CHECK-NEXT: CortexA55UnitFPALU | | | | | x | x | | | | | | | | | |
# CHECK-NEXT: SU(6) | | | | | | i | | | | | | | | | | # CHECK-NEXT: SU(6) | | | | | | i | | | | | | | | | |
# CHECK-NEXT: CortexA55UnitFPALU | | | | | | x | x | | | | | | | | | # CHECK-NEXT: CortexA55UnitFPALU | | | | | | x | x | | | | | | | | |
# CHECK-NEXT: SU(5) | | | | | | | | i | | | | | | | | # CHECK-NEXT: SU(5) | | | | | | | | i | | | | | | | |
# CHECK-NEXT: CortexA55UnitFPALU | | | | | | | | x | x | | | | | | | # CHECK-NEXT: CortexA55UnitFPALU | | | | | | | | x | x | | | | | | |
# CHECK-NEXT: SU(7) | | | | | | | | i | | | | | | | | # CHECK-NEXT: SU(7) | | | | | | | | i | | | | | | | |
# CHECK-NEXT: CortexA55UnitFPALU | | | | | | | | x | | | | | | | | # CHECK-NEXT: CortexA55UnitFPALU | | | | | | | | x | | | | | | | |
# CHECK-NEXT: SU(9) | | | | | | | | | i | | | | | | | # CHECK-NEXT: SU(9) | | | | | | | | | i | | | | | | |
# CHECK-NEXT: CortexA55UnitFPALU | | | | | | | | | x | | | | | | | # CHECK-NEXT: CortexA55UnitFPALU | | | | | | | | | x | | | | | | |
# CHECK-NEXT: SU(8) | | | | | | | | | | i | | | | | | # CHECK-NEXT: SU(8) | | | | | | | | | | i | | | | | |
# CHECK-NEXT: CortexA55UnitFPALU | | | | | | | | | | x | x | | | | | # CHECK-NEXT: CortexA55UnitFPALU | | | | | | | | | | x | x | | | | |
# CHECK-NEXT: SU(10) | | | | | | | | | | | i | | | | | # CHECK-NEXT: SU(10) | | | | | | | | | | | i | | | | |
# CHECK-NEXT: CortexA55UnitFPALU | | | | | | | | | | | x | x | | | | # CHECK-NEXT: CortexA55UnitFPALU | | | | | | | | | | | x | x | | | |
# CHECK-NEXT: SU(11) | | | | | | | | | | | | | | | i | # CHECK-NEXT: SU(11) | | | | | | | | | | | | | | | i |
# CHECK-NEXT: CortexA55UnitALU | | | | | | | | | | | | | | | x | # CHECK-NEXT: CortexA55UnitALU | | | | | | | | | | | | | | | x |
# CHECK-NEXT: SU(12) | | | | | | | | | | | | | | | i | # CHECK-NEXT: SU(12) | | | | | | | | | | | | | | | i |
# CHECK-NEXT: CortexA55UnitALU | | | | | | | | | | | | | | | x | # CHECK-NEXT: CortexA55UnitALU | | | | | | | | | | | | | | | x |
# CHECK-NEXT: SU(2) [TopReadyCycle = 0, BottomReadyCycle = 17]: %0:fpr128 = COPY $q0 # CHECK-NEXT: SU(2) [TopReadyCycle = 0, BottomReadyCycle = 17]: %0:fpr128 = COPY $q0
# CHECK-NEXT: SU(4) [TopReadyCycle = 0, BottomReadyCycle = 16]: %6:fpr128 = MOVIv2d_ns 17 # CHECK-NEXT: SU(4) [TopReadyCycle = 0, BottomReadyCycle = 16]: %6:fpr128 = MOVIv2d_ns 17
# CHECK-NEXT: SU(1) [TopReadyCycle = 0, BottomReadyCycle = 15]: %1:fpr128 = COPY $q1 # CHECK-NEXT: SU(1) [TopReadyCycle = 0, BottomReadyCycle = 15]: %1:fpr128 = COPY $q1
Context not available.
# CHECK-NEXT: SU(10) [TopReadyCycle = 0, BottomReadyCycle = 7]: %12:fpr128 = UMULLv4i16_v4i32 %3.dsub:fpr128, %11:fpr64 # CHECK-NEXT: SU(10) [TopReadyCycle = 0, BottomReadyCycle = 7]: %12:fpr128 = UMULLv4i16_v4i32 %3.dsub:fpr128, %11:fpr64
# CHECK-NEXT: SU(11) [TopReadyCycle = 0, BottomReadyCycle = 3]: $q0 = COPY %10:fpr128 # CHECK-NEXT: SU(11) [TopReadyCycle = 0, BottomReadyCycle = 3]: $q0 = COPY %10:fpr128
# CHECK-NEXT: SU(12) [TopReadyCycle = 0, BottomReadyCycle = 3]: $q1 = COPY %12:fpr128 # CHECK-NEXT: SU(12) [TopReadyCycle = 0, BottomReadyCycle = 3]: $q1 = COPY %12:fpr128
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: ********** INTERVALS ********** # CHECK-NEXT: ********** INTERVALS **********
# CHECK-NEXT: B0 [0B,48r:0)[192r,224r:1) 0@0B-phi 1@192r # CHECK-NEXT: B0 [0B,48r:0)[192r,224r:1) 0@0B-phi 1@192r
# CHECK-NEXT: B1 [0B,88r:0)[208r,224r:1) 0@0B-phi 1@208r # CHECK-NEXT: B1 [0B,88r:0)[208r,224r:1) 0@0B-phi 1@208r
Context not available.
# CHECK-NEXT: ********** MACHINEINSTRS ********** # CHECK-NEXT: ********** MACHINEINSTRS **********
# CHECK-NEXT: # Machine code for function umull_and_v8i32: IsSSA, NoPHIs, TracksLiveness # CHECK-NEXT: # Machine code for function umull_and_v8i32: IsSSA, NoPHIs, TracksLiveness
# CHECK-NEXT: Function Live Ins: $q0 in %0, $q1 in %1, $q2 in %2 # CHECK-NEXT: Function Live Ins: $q0 in %0, $q1 in %1, $q2 in %2
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: 0B bb.0.entry: # CHECK-NEXT: 0B bb.0.entry:
# CHECK-NEXT: liveins: $q0, $q1, $q2 # CHECK-NEXT: liveins: $q0, $q1, $q2
# CHECK-NEXT: 48B %0:fpr128 = COPY $q0 # CHECK-NEXT: 48B %0:fpr128 = COPY $q0
Context not available.
# CHECK-NEXT: 192B $q0 = COPY %10:fpr128 # CHECK-NEXT: 192B $q0 = COPY %10:fpr128
# CHECK-NEXT: 208B $q1 = COPY %12:fpr128 # CHECK-NEXT: 208B $q1 = COPY %12:fpr128
# CHECK-NEXT: 224B RET_ReallyLR implicit $q0, implicit $q1 # CHECK-NEXT: 224B RET_ReallyLR implicit $q0, implicit $q1
# CHECK-EMPTY: # CHECK-EMPTY:
# CHECK-NEXT: # End machine code for function umull_and_v8i32. # CHECK-NEXT: # End machine code for function umull_and_v8i32.
Context not available.

llvm/test/CodeGen/AArch64/misched-fusion-lit.ll

Context not available.
; CHECK-LABEL: litp_tune_generic: ; CHECK-LABEL: litp_tune_generic:
; CHECK: adrp [[R:x[0-9]+]], litp_tune_generic ; CHECK: adrp [[R:x[0-9]+]], litp_tune_generic
; CHECKDONT: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
; CHECK-NEXT: add {{x[0-9]+}}, [[R]], :lo12:litp_tune_generic ; CHECK-NEXT: add {{x[0-9]+}}, [[R]], :lo12:litp_tune_generic
} }
Context not available.

llvm/test/CodeGen/AArch64/mul_pow2.ll

llvm/test/CodeGen/AArch64/mulcmle.ll

llvm/test/CodeGen/AArch64/named-vector-shuffles-neon.ll

Context not available.
define <8 x i32> @splice_v8i32_idx(<8 x i32> %a, <8 x i32> %b) #0 { define <8 x i32> @splice_v8i32_idx(<8 x i32> %a, <8 x i32> %b) #0 {
; CHECK-LABEL: splice_v8i32_idx: ; CHECK-LABEL: splice_v8i32_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v3.16b, v2.16b, v3.16b, #4
; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #4 ; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #4
; CHECK-NEXT: mov v1.16b, v3.16b ; CHECK-NEXT: ext v1.16b, v2.16b, v3.16b, #4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <8 x i32> @llvm.experimental.vector.splice.v8i32(<8 x i32> %a, <8 x i32> %b, i32 5) %res = call <8 x i32> @llvm.experimental.vector.splice.v8i32(<8 x i32> %a, <8 x i32> %b, i32 5)
ret <8 x i32> %res ret <8 x i32> %res
Context not available.
define <16 x float> @splice_v16f32_idx(<16 x float> %a, <16 x float> %b) #0 { define <16 x float> @splice_v16f32_idx(<16 x float> %a, <16 x float> %b) #0 {
; CHECK-LABEL: splice_v16f32_idx: ; CHECK-LABEL: splice_v16f32_idx:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v5.16b, v4.16b, v5.16b, #12 ; CHECK-NEXT: ext v6.16b, v3.16b, v4.16b, #12
; CHECK-NEXT: ext v6.16b, v2.16b, v3.16b, #12
; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #12 ; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #12
; CHECK-NEXT: ext v2.16b, v3.16b, v4.16b, #12 ; CHECK-NEXT: ext v1.16b, v2.16b, v3.16b, #12
; CHECK-NEXT: mov v3.16b, v5.16b ; CHECK-NEXT: ext v3.16b, v4.16b, v5.16b, #12
; CHECK-NEXT: mov v1.16b, v6.16b ; CHECK-NEXT: mov v2.16b, v6.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <16 x float> @llvm.experimental.vector.splice.v16f32(<16 x float> %a, <16 x float> %b, i32 7) %res = call <16 x float> @llvm.experimental.vector.splice.v16f32(<16 x float> %a, <16 x float> %b, i32 7)
ret <16 x float> %res ret <16 x float> %res
Context not available.
define <8 x i32> @splice_v8i32(<8 x i32> %a, <8 x i32> %b) #0 { define <8 x i32> @splice_v8i32(<8 x i32> %a, <8 x i32> %b) #0 {
; CHECK-LABEL: splice_v8i32: ; CHECK-LABEL: splice_v8i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v3.16b, v2.16b, v3.16b, #4
; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #4 ; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #4
; CHECK-NEXT: mov v1.16b, v3.16b ; CHECK-NEXT: ext v1.16b, v2.16b, v3.16b, #4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <8 x i32> @llvm.experimental.vector.splice.v8i32(<8 x i32> %a, <8 x i32> %b, i32 -3) %res = call <8 x i32> @llvm.experimental.vector.splice.v8i32(<8 x i32> %a, <8 x i32> %b, i32 -3)
ret <8 x i32> %res ret <8 x i32> %res
Context not available.
define <16 x float> @splice_v16f32(<16 x float> %a, <16 x float> %b) #0 { define <16 x float> @splice_v16f32(<16 x float> %a, <16 x float> %b) #0 {
; CHECK-LABEL: splice_v16f32: ; CHECK-LABEL: splice_v16f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ext v5.16b, v4.16b, v5.16b, #12 ; CHECK-NEXT: ext v6.16b, v3.16b, v4.16b, #12
; CHECK-NEXT: ext v6.16b, v2.16b, v3.16b, #12
; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #12 ; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #12
; CHECK-NEXT: ext v2.16b, v3.16b, v4.16b, #12 ; CHECK-NEXT: ext v1.16b, v2.16b, v3.16b, #12
; CHECK-NEXT: mov v3.16b, v5.16b ; CHECK-NEXT: ext v3.16b, v4.16b, v5.16b, #12
; CHECK-NEXT: mov v1.16b, v6.16b ; CHECK-NEXT: mov v2.16b, v6.16b
dmgreenUnsubmitted
Done
ReplyInline Actions

Some of these have less movs thanks to the lower latencies, which is nice.

dmgreen: Some of these have less movs thanks to the lower latencies, which is nice.
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <16 x float> @llvm.experimental.vector.splice.v16f32(<16 x float> %a, <16 x float> %b, i32 -9) %res = call <16 x float> @llvm.experimental.vector.splice.v16f32(<16 x float> %a, <16 x float> %b, i32 -9)
ret <16 x float> %res ret <16 x float> %res
Context not available.

llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll

llvm/test/CodeGen/AArch64/neg-imm.ll

llvm/test/CodeGen/AArch64/neon-abd.ll

llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll

llvm/test/CodeGen/AArch64/neon-compare-instructions.ll

llvm/test/CodeGen/AArch64/neon-dotpattern.ll

llvm/test/CodeGen/AArch64/neon-dotreduce.ll

llvm/test/CodeGen/AArch64/neon-extadd.ll

llvm/test/CodeGen/AArch64/neon-extracttruncate.ll

llvm/test/CodeGen/AArch64/neon-mov.ll

llvm/test/CodeGen/AArch64/neon-reverseshuffle.ll

llvm/test/CodeGen/AArch64/neon-rshrn.ll

llvm/test/CodeGen/AArch64/neon-shift-neg.ll

llvm/test/CodeGen/AArch64/neon-truncstore.ll

llvm/test/CodeGen/AArch64/neon-wide-splat.ll

llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll

llvm/test/CodeGen/AArch64/no-sve-no-neon.ll

llvm/test/CodeGen/AArch64/nontemporal-load.ll

Context not available.
; CHECK-LABEL: test_ldnp_v17f32: ; CHECK-LABEL: test_ldnp_v17f32:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: ldnp q0, q1, [x0, #32] ; CHECK-NEXT: ldnp q0, q1, [x0, #32]
; CHECK-NEXT: ldnp q2, q3, [x0] ; CHECK-NEXT: ldr s2, [x0, #64]
; CHECK-NEXT: ldr s4, [x0, #64] ; CHECK-NEXT: ldnp q3, q4, [x0]
; CHECK-NEXT: stp q0, q1, [x8, #32] ; CHECK-NEXT: stp q0, q1, [x8, #32]
; CHECK-NEXT: stp q2, q3, [x8] ; CHECK-NEXT: stp q3, q4, [x8]
; CHECK-NEXT: str s4, [x8, #64] ; CHECK-NEXT: str s2, [x8, #64]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; CHECK-BE-LABEL: test_ldnp_v17f32: ; CHECK-BE-LABEL: test_ldnp_v17f32:
; CHECK-BE: // %bb.0: ; CHECK-BE: // %bb.0:
; CHECK-BE-NEXT: add x9, x0, #32
; CHECK-BE-NEXT: ld1 { v1.4s }, [x0]
; CHECK-BE-NEXT: add x10, x0, #16
; CHECK-BE-NEXT: ldr s2, [x0, #64]
; CHECK-BE-NEXT: ld1 { v0.4s }, [x9]
; CHECK-BE-NEXT: add x9, x0, #48 ; CHECK-BE-NEXT: add x9, x0, #48
; CHECK-BE-NEXT: ld1 { v4.4s }, [x10] ; CHECK-BE-NEXT: ld1 { v0.4s }, [x0]
; CHECK-BE-NEXT: add x10, x8, #32 ; CHECK-BE-NEXT: add x10, x0, #32
; CHECK-BE-NEXT: ld1 { v2.4s }, [x9]
; CHECK-BE-NEXT: add x9, x0, #16
; CHECK-BE-NEXT: ldr s1, [x0, #64]
; CHECK-BE-NEXT: ld1 { v3.4s }, [x9] ; CHECK-BE-NEXT: ld1 { v3.4s }, [x9]
; CHECK-BE-NEXT: ld1 { v4.4s }, [x10]
; CHECK-BE-NEXT: add x9, x8, #48 ; CHECK-BE-NEXT: add x9, x8, #48
; CHECK-BE-NEXT: str s2, [x8, #64] ; CHECK-BE-NEXT: str s1, [x8, #64]
; CHECK-BE-NEXT: st1 { v1.4s }, [x8] ; CHECK-BE-NEXT: add x10, x8, #32
; CHECK-BE-NEXT: st1 { v0.4s }, [x8]
; CHECK-BE-NEXT: add x8, x8, #16 ; CHECK-BE-NEXT: add x8, x8, #16
; CHECK-BE-NEXT: st1 { v3.4s }, [x9] ; CHECK-BE-NEXT: st1 { v2.4s }, [x9]
; CHECK-BE-NEXT: st1 { v0.4s }, [x10] ; CHECK-BE-NEXT: st1 { v4.4s }, [x10]
; CHECK-BE-NEXT: st1 { v4.4s }, [x8] ; CHECK-BE-NEXT: st1 { v3.4s }, [x8]
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
%lv = load <17 x float>, ptr %A, align 8, !nontemporal !0 %lv = load <17 x float>, ptr %A, align 8, !nontemporal !0
ret <17 x float> %lv ret <17 x float> %lv
Context not available.
; CHECK-LABEL: test_ldnp_v33f64: ; CHECK-LABEL: test_ldnp_v33f64:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: ldnp q0, q1, [x0] ; CHECK-NEXT: ldnp q0, q1, [x0]
; CHECK-NEXT: ldr d20, [x0, #256]
; CHECK-NEXT: ldnp q2, q3, [x0, #32] ; CHECK-NEXT: ldnp q2, q3, [x0, #32]
; CHECK-NEXT: ldnp q4, q5, [x0, #64] ; CHECK-NEXT: ldnp q4, q5, [x0, #64]
; CHECK-NEXT: ldnp q6, q7, [x0, #96] ; CHECK-NEXT: ldnp q6, q7, [x0, #96]
; CHECK-NEXT: ldnp q16, q17, [x0, #128] ; CHECK-NEXT: ldnp q16, q17, [x0, #128]
; CHECK-NEXT: ldnp q18, q19, [x0, #224] ; CHECK-NEXT: ldnp q18, q19, [x0, #224]
; CHECK-NEXT: ldnp q20, q21, [x0, #192] ; CHECK-NEXT: ldnp q21, q22, [x0, #160]
; CHECK-NEXT: ldnp q22, q23, [x0, #160] ; CHECK-NEXT: ldnp q23, q24, [x0, #192]
; CHECK-NEXT: ldr d24, [x0, #256]
; CHECK-NEXT: stp q0, q1, [x8] ; CHECK-NEXT: stp q0, q1, [x8]
; CHECK-NEXT: stp q2, q3, [x8, #32] ; CHECK-NEXT: stp q2, q3, [x8, #32]
; CHECK-NEXT: stp q4, q5, [x8, #64] ; CHECK-NEXT: stp q4, q5, [x8, #64]
; CHECK-NEXT: stp q6, q7, [x8, #96] ; CHECK-NEXT: stp q6, q7, [x8, #96]
; CHECK-NEXT: stp q16, q17, [x8, #128] ; CHECK-NEXT: stp q16, q17, [x8, #128]
; CHECK-NEXT: stp q22, q23, [x8, #160] ; CHECK-NEXT: stp q21, q22, [x8, #160]
; CHECK-NEXT: stp q20, q21, [x8, #192] ; CHECK-NEXT: stp q23, q24, [x8, #192]
; CHECK-NEXT: stp q18, q19, [x8, #224] ; CHECK-NEXT: stp q18, q19, [x8, #224]
; CHECK-NEXT: str d24, [x8, #256] ; CHECK-NEXT: str d20, [x8, #256]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; CHECK-BE-LABEL: test_ldnp_v33f64: ; CHECK-BE-LABEL: test_ldnp_v33f64:
; CHECK-BE: // %bb.0: ; CHECK-BE: // %bb.0:
; CHECK-BE-NEXT: add x9, x0, #16 ; CHECK-BE-NEXT: add x9, x0, #16
; CHECK-BE-NEXT: add x10, x0, #32 ; CHECK-BE-NEXT: add x10, x0, #32
; CHECK-BE-NEXT: ld1 { v21.2d }, [x0] ; CHECK-BE-NEXT: add x11, x0, #48
; CHECK-BE-NEXT: add x11, x8, #208
; CHECK-BE-NEXT: ld1 { v0.2d }, [x9] ; CHECK-BE-NEXT: ld1 { v0.2d }, [x9]
; CHECK-BE-NEXT: add x9, x0, #48 ; CHECK-BE-NEXT: add x9, x0, #64
; CHECK-BE-NEXT: ld1 { v1.2d }, [x10] ; CHECK-BE-NEXT: ld1 { v1.2d }, [x10]
; CHECK-BE-NEXT: add x10, x0, #64 ; CHECK-BE-NEXT: add x10, x0, #80
; CHECK-BE-NEXT: ld1 { v2.2d }, [x9] ; CHECK-BE-NEXT: ld1 { v3.2d }, [x9]
; CHECK-BE-NEXT: add x9, x0, #80
; CHECK-BE-NEXT: ld1 { v3.2d }, [x10]
; CHECK-BE-NEXT: add x10, x0, #96
; CHECK-BE-NEXT: ld1 { v4.2d }, [x9]
; CHECK-BE-NEXT: add x9, x0, #112 ; CHECK-BE-NEXT: add x9, x0, #112
; CHECK-BE-NEXT: ld1 { v5.2d }, [x10] ; CHECK-BE-NEXT: ld1 { v4.2d }, [x10]
; CHECK-BE-NEXT: add x10, x0, #128 ; CHECK-BE-NEXT: add x10, x0, #128
; CHECK-BE-NEXT: ld1 { v6.2d }, [x9] ; CHECK-BE-NEXT: ld1 { v6.2d }, [x9]
; CHECK-BE-NEXT: add x9, x0, #144 ; CHECK-BE-NEXT: add x9, x0, #160
; CHECK-BE-NEXT: ld1 { v7.2d }, [x10] ; CHECK-BE-NEXT: ld1 { v7.2d }, [x10]
; CHECK-BE-NEXT: add x10, x0, #160 ; CHECK-BE-NEXT: add x10, x0, #176
; CHECK-BE-NEXT: ld1 { v16.2d }, [x9] ; CHECK-BE-NEXT: ld1 { v17.2d }, [x9]
; CHECK-BE-NEXT: add x9, x0, #176
; CHECK-BE-NEXT: ld1 { v17.2d }, [x10]
; CHECK-BE-NEXT: add x10, x0, #192
; CHECK-BE-NEXT: ld1 { v18.2d }, [x9]
; CHECK-BE-NEXT: add x9, x0, #224
; CHECK-BE-NEXT: ld1 { v19.2d }, [x10]
; CHECK-BE-NEXT: add x10, x0, #208
; CHECK-BE-NEXT: ld1 { v20.2d }, [x9]
; CHECK-BE-NEXT: add x9, x0, #240 ; CHECK-BE-NEXT: add x9, x0, #240
; CHECK-BE-NEXT: ldr d22, [x0, #256] ; CHECK-BE-NEXT: ld1 { v2.2d }, [x11]
; CHECK-BE-NEXT: add x11, x0, #96
; CHECK-BE-NEXT: ld1 { v18.2d }, [x10]
; CHECK-BE-NEXT: ld1 { v20.2d }, [x0]
; CHECK-BE-NEXT: ld1 { v22.2d }, [x9]
; CHECK-BE-NEXT: add x10, x0, #224
; CHECK-BE-NEXT: ld1 { v5.2d }, [x11]
; CHECK-BE-NEXT: add x11, x0, #144
; CHECK-BE-NEXT: ldr d21, [x0, #256]
; CHECK-BE-NEXT: add x9, x0, #208
; CHECK-BE-NEXT: ld1 { v24.2d }, [x10]
; CHECK-BE-NEXT: ld1 { v16.2d }, [x11]
; CHECK-BE-NEXT: add x11, x0, #192
; CHECK-BE-NEXT: ld1 { v23.2d }, [x9] ; CHECK-BE-NEXT: ld1 { v23.2d }, [x9]
; CHECK-BE-NEXT: add x9, x8, #240 ; CHECK-BE-NEXT: add x9, x8, #240
; CHECK-BE-NEXT: ld1 { v24.2d }, [x10] ; CHECK-BE-NEXT: ld1 { v19.2d }, [x11]
; CHECK-BE-NEXT: add x10, x8, #224 ; CHECK-BE-NEXT: str d21, [x8, #256]
; CHECK-BE-NEXT: str d22, [x8, #256] ; CHECK-BE-NEXT: st1 { v20.2d }, [x8]
; CHECK-BE-NEXT: st1 { v21.2d }, [x8] ; CHECK-BE-NEXT: st1 { v22.2d }, [x9]
; CHECK-BE-NEXT: add x9, x8, #224
; CHECK-BE-NEXT: st1 { v24.2d }, [x9]
; CHECK-BE-NEXT: add x9, x8, #208
; CHECK-BE-NEXT: st1 { v23.2d }, [x9] ; CHECK-BE-NEXT: st1 { v23.2d }, [x9]
; CHECK-BE-NEXT: add x9, x8, #192 ; CHECK-BE-NEXT: add x9, x8, #192
; CHECK-BE-NEXT: st1 { v20.2d }, [x10]
; CHECK-BE-NEXT: add x10, x8, #176
; CHECK-BE-NEXT: st1 { v24.2d }, [x11]
; CHECK-BE-NEXT: add x11, x8, #160
; CHECK-BE-NEXT: st1 { v19.2d }, [x9] ; CHECK-BE-NEXT: st1 { v19.2d }, [x9]
; CHECK-BE-NEXT: add x9, x8, #176
; CHECK-BE-NEXT: st1 { v18.2d }, [x9]
; CHECK-BE-NEXT: add x9, x8, #160
; CHECK-BE-NEXT: st1 { v17.2d }, [x9]
; CHECK-BE-NEXT: add x9, x8, #144 ; CHECK-BE-NEXT: add x9, x8, #144
; CHECK-BE-NEXT: st1 { v18.2d }, [x10]
; CHECK-BE-NEXT: add x10, x8, #128
; CHECK-BE-NEXT: st1 { v17.2d }, [x11]
; CHECK-BE-NEXT: add x11, x8, #112
; CHECK-BE-NEXT: st1 { v16.2d }, [x9] ; CHECK-BE-NEXT: st1 { v16.2d }, [x9]
; CHECK-BE-NEXT: add x9, x8, #128
; CHECK-BE-NEXT: st1 { v7.2d }, [x9]
; CHECK-BE-NEXT: add x9, x8, #112
; CHECK-BE-NEXT: st1 { v6.2d }, [x9]
; CHECK-BE-NEXT: add x9, x8, #96 ; CHECK-BE-NEXT: add x9, x8, #96
; CHECK-BE-NEXT: st1 { v7.2d }, [x10]
; CHECK-BE-NEXT: add x10, x8, #80
; CHECK-BE-NEXT: st1 { v6.2d }, [x11]
; CHECK-BE-NEXT: add x11, x8, #64
; CHECK-BE-NEXT: st1 { v5.2d }, [x9] ; CHECK-BE-NEXT: st1 { v5.2d }, [x9]
; CHECK-BE-NEXT: add x9, x8, #80
; CHECK-BE-NEXT: st1 { v4.2d }, [x9]
; CHECK-BE-NEXT: add x9, x8, #64
; CHECK-BE-NEXT: st1 { v3.2d }, [x9]
; CHECK-BE-NEXT: add x9, x8, #48 ; CHECK-BE-NEXT: add x9, x8, #48
; CHECK-BE-NEXT: st1 { v4.2d }, [x10]
; CHECK-BE-NEXT: add x10, x8, #32
; CHECK-BE-NEXT: add x8, x8, #16
; CHECK-BE-NEXT: st1 { v3.2d }, [x11]
; CHECK-BE-NEXT: st1 { v2.2d }, [x9] ; CHECK-BE-NEXT: st1 { v2.2d }, [x9]
; CHECK-BE-NEXT: st1 { v1.2d }, [x10] ; CHECK-BE-NEXT: add x9, x8, #32
; CHECK-BE-NEXT: add x8, x8, #16
; CHECK-BE-NEXT: st1 { v1.2d }, [x9]
; CHECK-BE-NEXT: st1 { v0.2d }, [x8] ; CHECK-BE-NEXT: st1 { v0.2d }, [x8]
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
%lv = load <33 x double>, ptr %A, align 8, !nontemporal !0 %lv = load <33 x double>, ptr %A, align 8, !nontemporal !0
Context not available.
; CHECK-BE: // %bb.0: ; CHECK-BE: // %bb.0:
; CHECK-BE-NEXT: add x9, x0, #16 ; CHECK-BE-NEXT: add x9, x0, #16
; CHECK-BE-NEXT: ld1 { v0.16b }, [x0] ; CHECK-BE-NEXT: ld1 { v0.16b }, [x0]
; CHECK-BE-NEXT: add x10, x8, #16 ; CHECK-BE-NEXT: ldrb w10, [x0, #32]
; CHECK-BE-NEXT: ld1 { v1.16b }, [x9] ; CHECK-BE-NEXT: ld1 { v1.16b }, [x9]
; CHECK-BE-NEXT: ldrb w9, [x0, #32] ; CHECK-BE-NEXT: strb w10, [x8, #32]
; CHECK-BE-NEXT: strb w9, [x8, #32]
; CHECK-BE-NEXT: st1 { v0.16b }, [x8] ; CHECK-BE-NEXT: st1 { v0.16b }, [x8]
; CHECK-BE-NEXT: st1 { v1.16b }, [x10] ; CHECK-BE-NEXT: add x8, x8, #16
; CHECK-BE-NEXT: st1 { v1.16b }, [x8]
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
%lv = load<33 x i8>, ptr %A, align 8, !nontemporal !0 %lv = load<33 x i8>, ptr %A, align 8, !nontemporal !0
ret <33 x i8> %lv ret <33 x i8> %lv
Context not available.
; CHECK-NEXT: ldp x8, x9, [x0, #8] ; CHECK-NEXT: ldp x8, x9, [x0, #8]
; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ldr x10, [x0, #24] ; CHECK-NEXT: ldr x10, [x0, #24]
; CHECK-NEXT: and x1, x8, #0x1
; CHECK-NEXT: ldrb w11, [x0, #32] ; CHECK-NEXT: ldrb w11, [x0, #32]
; CHECK-NEXT: and x1, x8, #0x1
; CHECK-NEXT: extr x2, x9, x8, #1 ; CHECK-NEXT: extr x2, x9, x8, #1
; CHECK-NEXT: extr x4, x10, x9, #2 ; CHECK-NEXT: extr x4, x10, x9, #2
; CHECK-NEXT: mov.d v0[1], x1
; CHECK-NEXT: extr x6, x11, x10, #3 ; CHECK-NEXT: extr x6, x11, x10, #3
; CHECK-NEXT: ubfx x3, x9, #1, #1 ; CHECK-NEXT: ubfx x3, x9, #1, #1
; CHECK-NEXT: mov.d v0[1], x1
; CHECK-NEXT: ubfx x5, x10, #2, #1 ; CHECK-NEXT: ubfx x5, x10, #2, #1
; CHECK-NEXT: ubfx x7, x11, #3, #1 ; CHECK-NEXT: ubfx x7, x11, #3, #1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
Context not available.
; ;
; CHECK-BE-LABEL: test_ldnp_v4i65: ; CHECK-BE-LABEL: test_ldnp_v4i65:
; CHECK-BE: // %bb.0: ; CHECK-BE: // %bb.0:
; CHECK-BE-NEXT: ldp x10, x9, [x0, #16] ; CHECK-BE-NEXT: ldp x10, x9, [x0]
; CHECK-BE-NEXT: ldp x12, x11, [x0]
; CHECK-BE-NEXT: ldrb w8, [x0, #32] ; CHECK-BE-NEXT: ldrb w8, [x0, #32]
; CHECK-BE-NEXT: ldp x12, x11, [x0, #16]
; CHECK-BE-NEXT: lsr x13, x10, #56 ; CHECK-BE-NEXT: lsr x13, x10, #56
; CHECK-BE-NEXT: lsr x14, x12, #56 ; CHECK-BE-NEXT: orr x7, x8, x11, lsl #8
; CHECK-BE-NEXT: extr x15, x11, x10, #56
; CHECK-BE-NEXT: orr x7, x8, x9, lsl #8
; CHECK-BE-NEXT: extr x8, x10, x9, #56 ; CHECK-BE-NEXT: extr x8, x10, x9, #56
; CHECK-BE-NEXT: extr x9, x12, x11, #56 ; CHECK-BE-NEXT: extr x11, x12, x11, #56
; CHECK-BE-NEXT: lsr x12, x12, #59 ; CHECK-BE-NEXT: lsr x14, x12, #56
; CHECK-BE-NEXT: ubfx x10, x10, #57, #1 ; CHECK-BE-NEXT: extr x15, x9, x12, #56
; CHECK-BE-NEXT: extr x5, x13, x8, #1 ; CHECK-BE-NEXT: lsr x10, x10, #59
; CHECK-BE-NEXT: extr x1, x14, x9, #3 ; CHECK-BE-NEXT: extr x1, x13, x8, #3
; CHECK-BE-NEXT: ubfx x9, x11, #58, #1 ; CHECK-BE-NEXT: lsr x8, x9, #56
; CHECK-BE-NEXT: fmov d0, x12 ; CHECK-BE-NEXT: ubfx x12, x12, #57, #1
; CHECK-BE-NEXT: and x12, x8, #0x1 ; CHECK-BE-NEXT: ubfx x9, x9, #58, #1
; CHECK-BE-NEXT: lsr x11, x11, #56 ; CHECK-BE-NEXT: extr x5, x14, x11, #1
; CHECK-BE-NEXT: fmov d2, x10 ; CHECK-BE-NEXT: and x11, x11, #0x1
; CHECK-BE-NEXT: fmov d0, x10
; CHECK-BE-NEXT: fmov d2, x12
; CHECK-BE-NEXT: fmov d3, x11
; CHECK-BE-NEXT: fmov d1, x9 ; CHECK-BE-NEXT: fmov d1, x9
; CHECK-BE-NEXT: extr x3, x11, x15, #2 ; CHECK-BE-NEXT: extr x3, x8, x15, #2
; CHECK-BE-NEXT: fmov d3, x12
; CHECK-BE-NEXT: mov v0.d[1], x1 ; CHECK-BE-NEXT: mov v0.d[1], x1
; CHECK-BE-NEXT: mov v2.d[1], x5 ; CHECK-BE-NEXT: mov v2.d[1], x5
; CHECK-BE-NEXT: mov v1.d[1], x3
; CHECK-BE-NEXT: mov v3.d[1], x7 ; CHECK-BE-NEXT: mov v3.d[1], x7
; CHECK-BE-NEXT: mov v1.d[1], x3
; CHECK-BE-NEXT: fmov x0, d0 ; CHECK-BE-NEXT: fmov x0, d0
; CHECK-BE-NEXT: fmov x4, d2 ; CHECK-BE-NEXT: fmov x4, d2
; CHECK-BE-NEXT: fmov x2, d1
; CHECK-BE-NEXT: fmov x6, d3 ; CHECK-BE-NEXT: fmov x6, d3
; CHECK-BE-NEXT: fmov x2, d1
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
%lv = load <4 x i65>, ptr %A, align 8, !nontemporal !0 %lv = load <4 x i65>, ptr %A, align 8, !nontemporal !0
ret <4 x i65> %lv ret <4 x i65> %lv
Context not available.
; CHECK-LABEL: test_ldnp_v4i63: ; CHECK-LABEL: test_ldnp_v4i63:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: ldp x8, x9, [x0] ; CHECK-NEXT: ldp x8, x9, [x0]
; CHECK-NEXT: ldp x10, x12, [x0, #16] ; CHECK-NEXT: ldp x10, x11, [x0, #16]
; CHECK-NEXT: extr x11, x9, x8, #63 ; CHECK-NEXT: extr x12, x9, x8, #63
; CHECK-NEXT: and x0, x8, #0x7fffffffffffffff ; CHECK-NEXT: and x0, x8, #0x7fffffffffffffff
; CHECK-NEXT: extr x9, x10, x9, #62 ; CHECK-NEXT: extr x9, x10, x9, #62
; CHECK-NEXT: extr x3, x12, x10, #61 ; CHECK-NEXT: extr x3, x11, x10, #61
; CHECK-NEXT: and x1, x11, #0x7fffffffffffffff ; CHECK-NEXT: and x1, x12, #0x7fffffffffffffff
; CHECK-NEXT: and x2, x9, #0x7fffffffffffffff ; CHECK-NEXT: and x2, x9, #0x7fffffffffffffff
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; CHECK-BE-LABEL: test_ldnp_v4i63: ; CHECK-BE-LABEL: test_ldnp_v4i63:
; CHECK-BE: // %bb.0: ; CHECK-BE: // %bb.0:
; CHECK-BE-NEXT: ldp x8, x9, [x0, #16] ; CHECK-BE-NEXT: ldp x9, x8, [x0, #8]
; CHECK-BE-NEXT: ldp x11, x10, [x0] ; CHECK-BE-NEXT: ldr x11, [x0, #24]
; CHECK-BE-NEXT: and x3, x9, #0x7fffffffffffffff ; CHECK-BE-NEXT: ldr x10, [x0]
; CHECK-BE-NEXT: extr x12, x10, x8, #62 ; CHECK-BE-NEXT: and x3, x11, #0x7fffffffffffffff
; CHECK-BE-NEXT: extr x8, x8, x9, #63 ; CHECK-BE-NEXT: extr x12, x9, x8, #62
; CHECK-BE-NEXT: extr x0, x11, x10, #61 ; CHECK-BE-NEXT: extr x8, x8, x11, #63
; CHECK-BE-NEXT: extr x0, x10, x9, #61
; CHECK-BE-NEXT: and x1, x12, #0x7fffffffffffffff ; CHECK-BE-NEXT: and x1, x12, #0x7fffffffffffffff
; CHECK-BE-NEXT: and x2, x8, #0x7fffffffffffffff ; CHECK-BE-NEXT: and x2, x8, #0x7fffffffffffffff
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
Context not available.
; CHECK-NEXT: ldnp q0, q2, [x0] ; CHECK-NEXT: ldnp q0, q2, [x0]
; CHECK-NEXT: ldr d4, [x0, #32] ; CHECK-NEXT: ldr d4, [x0, #32]
; CHECK-NEXT: ext.16b v1, v0, v0, #8 ; CHECK-NEXT: ext.16b v1, v0, v0, #8
; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ; kill: def $d1 killed $d1 killed $q1
; CHECK-NEXT: ext.16b v3, v2, v2, #8 ; CHECK-NEXT: ext.16b v3, v2, v2, #8
; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ; kill: def $d2 killed $d2 killed $q2 ; CHECK-NEXT: ; kill: def $d2 killed $d2 killed $q2
; CHECK-NEXT: ; kill: def $d1 killed $d1 killed $q1
; CHECK-NEXT: ; kill: def $d3 killed $d3 killed $q3 ; CHECK-NEXT: ; kill: def $d3 killed $d3 killed $q3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
Context not available.
; CHECK-BE-NEXT: // kill: def $d4 killed $d4 killed $q4 ; CHECK-BE-NEXT: // kill: def $d4 killed $d4 killed $q4
; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8 ; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-BE-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-BE-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-BE-NEXT: ext v3.16b, v2.16b, v2.16b, #8 ; CHECK-BE-NEXT: ext v3.16b, v2.16b, v2.16b, #8
; CHECK-BE-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-BE-NEXT: // kill: def $d2 killed $d2 killed $q2 ; CHECK-BE-NEXT: // kill: def $d2 killed $d2 killed $q2
; CHECK-BE-NEXT: // kill: def $d3 killed $d3 killed $q3 ; CHECK-BE-NEXT: // kill: def $d3 killed $d3 killed $q3
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
Context not available.

llvm/test/CodeGen/AArch64/nontemporal.ll

llvm/test/CodeGen/AArch64/nzcv-save.ll

llvm/test/CodeGen/AArch64/overeager_mla_fusing.ll

llvm/test/CodeGen/AArch64/peephole-and-tst.ll

llvm/test/CodeGen/AArch64/pmull-ldr-merge.ll

llvm/test/CodeGen/AArch64/pr-cf624b2.ll

llvm/test/CodeGen/AArch64/pr58350.ll

llvm/test/CodeGen/AArch64/pr58516.ll

llvm/test/CodeGen/AArch64/pr61549.ll

llvm/test/CodeGen/AArch64/predicated-add-sub.ll

llvm/test/CodeGen/AArch64/pull-negations-after-concat-of-truncates.ll

llvm/test/CodeGen/AArch64/ragreedy-csr.ll

llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll

llvm/test/CodeGen/AArch64/rand.ll

llvm/test/CodeGen/AArch64/rcpc3-sve.ll

llvm/test/CodeGen/AArch64/reduce-and.ll

llvm/test/CodeGen/AArch64/reduce-or.ll

llvm/test/CodeGen/AArch64/reduce-shuffle.ll

llvm/test/CodeGen/AArch64/reduce-xor.ll

llvm/test/CodeGen/AArch64/regress-tblgen-chains.ll

llvm/test/CodeGen/AArch64/rotate-extract.ll

llvm/test/CodeGen/AArch64/sadd_sat.ll

llvm/test/CodeGen/AArch64/sadd_sat_plus.ll

llvm/test/CodeGen/AArch64/sadd_sat_vec.ll

llvm/test/CodeGen/AArch64/sat-add.ll

llvm/test/CodeGen/AArch64/select-constant-xor.ll

llvm/test/CodeGen/AArch64/select_const.ll

llvm/test/CodeGen/AArch64/select_fmf.ll

llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll

llvm/test/CodeGen/AArch64/setcc-type-mismatch.ll

llvm/test/CodeGen/AArch64/settag-merge-order.ll

llvm/test/CodeGen/AArch64/settag-merge.ll

llvm/test/CodeGen/AArch64/settag.ll

llvm/test/CodeGen/AArch64/sext.ll

llvm/test/CodeGen/AArch64/shift-amount-mod.ll

llvm/test/CodeGen/AArch64/shift-by-signext.ll

llvm/test/CodeGen/AArch64/shift_minsize.ll

llvm/test/CodeGen/AArch64/shrink-wrap-byval-inalloca-preallocated.ll

llvm/test/CodeGen/AArch64/shrink-wrapping-vla.ll

Context not available.
; VLA allocation ; VLA allocation
; CHECK: ubfiz x8, x0, #2, #32 ; CHECK: ubfiz x8, x0, #2, #32
; CHECK: mov x9, sp ; CHECK: mov x9, sp
; CHECK: add x8, x8, #15
; CHECK: mov [[SAVE:x[0-9]+]], sp ; CHECK: mov [[SAVE:x[0-9]+]], sp
; CHECK: add x8, x8, #15
; CHECK: and [[X1:x[0-9]+]], [[X1]], #0x7fffffff0 ; CHECK: and [[X1:x[0-9]+]], [[X1]], #0x7fffffff0
; Saving the SP via llvm.stacksave() ; Saving the SP via llvm.stacksave()
; CHECK: sub [[X1]], [[X2:x[0-9]+]], [[X1]] ; CHECK: sub [[X1]], [[X2:x[0-9]+]], [[X1]]
Context not available.

llvm/test/CodeGen/AArch64/shuffle-tbl34.ll

llvm/test/CodeGen/AArch64/shuffles.ll

llvm/test/CodeGen/AArch64/sink-addsub-of-const.ll

llvm/test/CodeGen/AArch64/sinksplat.ll

llvm/test/CodeGen/AArch64/sitofp-fixed-legal.ll

llvm/test/CodeGen/AArch64/sme-aarch64-svcount.ll

llvm/test/CodeGen/AArch64/sme-disable-gisel-fisel.ll

llvm/test/CodeGen/AArch64/sme-intrinsics-loads.ll

llvm/test/CodeGen/AArch64/sme-intrinsics-mova-extract.ll

llvm/test/CodeGen/AArch64/sme-intrinsics-mova-insert.ll

llvm/test/CodeGen/AArch64/sme-intrinsics-stores.ll

llvm/test/CodeGen/AArch64/sme-lazy-save-call.ll

llvm/test/CodeGen/AArch64/sme-shared-za-interface.ll

llvm/test/CodeGen/AArch64/sme-streaming-body.ll

llvm/test/CodeGen/AArch64/sme-streaming-compatible-interface.ll

llvm/test/CodeGen/AArch64/sme-streaming-interface.ll

llvm/test/CodeGen/AArch64/sme2-intrinsics-add.ll

llvm/test/CodeGen/AArch64/sme2-intrinsics-fmlas.ll

llvm/test/CodeGen/AArch64/sme2-intrinsics-fp-dots.ll

llvm/test/CodeGen/AArch64/sme2-intrinsics-insert-mova.ll

llvm/test/CodeGen/AArch64/sme2-intrinsics-int-dots.ll

llvm/test/CodeGen/AArch64/sme2-intrinsics-ld1.ll

llvm/test/CodeGen/AArch64/sme2-intrinsics-ldnt1.ll

llvm/test/CodeGen/AArch64/sme2-intrinsics-max.ll

llvm/test/CodeGen/AArch64/sme2-intrinsics-min.ll

Context not available.
<vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4) { <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4) {
; CHECK-LABEL: multi_vec_min_multi_x4_s8: ; CHECK-LABEL: multi_vec_min_multi_x4_s8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.b ; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: ld1b { z31.b }, p0/z, [x0] ; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d ; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d ; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1b { z31.b }, p0/z, [x0]
; CHECK-NEXT: smin { z24.b - z27.b }, { z24.b - z27.b }, { z28.b - z31.b } ; CHECK-NEXT: smin { z24.b - z27.b }, { z24.b - z27.b }, { z28.b - z31.b }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
<vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4) { <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4) {
; CHECK-LABEL: multi_vec_min_multi_x4_s16: ; CHECK-LABEL: multi_vec_min_multi_x4_s16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: ld1h { z31.h }, p0/z, [x0] ; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d ; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d ; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1h { z31.h }, p0/z, [x0]
; CHECK-NEXT: smin { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h } ; CHECK-NEXT: smin { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
<vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4) { <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4) {
; CHECK-LABEL: multi_vec_min_multi_x4_s32: ; CHECK-LABEL: multi_vec_min_multi_x4_s32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: ld1w { z31.s }, p0/z, [x0] ; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d ; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d ; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1w { z31.s }, p0/z, [x0]
; CHECK-NEXT: smin { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s } ; CHECK-NEXT: smin { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
<vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4) { <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4) {
; CHECK-LABEL: multi_vec_min_multi_x4_s64: ; CHECK-LABEL: multi_vec_min_multi_x4_s64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: ld1d { z31.d }, p0/z, [x0] ; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d ; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d ; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1d { z31.d }, p0/z, [x0]
; CHECK-NEXT: smin { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d } ; CHECK-NEXT: smin { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
<vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4) { <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4) {
; CHECK-LABEL: multi_vec_min_multi_x4_u8: ; CHECK-LABEL: multi_vec_min_multi_x4_u8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.b ; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: ld1b { z31.b }, p0/z, [x0] ; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d ; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d ; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1b { z31.b }, p0/z, [x0]
; CHECK-NEXT: umin { z24.b - z27.b }, { z24.b - z27.b }, { z28.b - z31.b } ; CHECK-NEXT: umin { z24.b - z27.b }, { z24.b - z27.b }, { z28.b - z31.b }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
<vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4) { <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4) {
; CHECK-LABEL: multi_vec_min_multi_x4_u16: ; CHECK-LABEL: multi_vec_min_multi_x4_u16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: ld1h { z31.h }, p0/z, [x0] ; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d ; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d ; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1h { z31.h }, p0/z, [x0]
; CHECK-NEXT: umin { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h } ; CHECK-NEXT: umin { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
<vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4) { <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4) {
; CHECK-LABEL: multi_vec_min_multi_x4_u32: ; CHECK-LABEL: multi_vec_min_multi_x4_u32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: ld1w { z31.s }, p0/z, [x0] ; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d ; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d ; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1w { z31.s }, p0/z, [x0]
; CHECK-NEXT: umin { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s } ; CHECK-NEXT: umin { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
<vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4) { <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4) {
; CHECK-LABEL: multi_vec_min_multi_x4_u64: ; CHECK-LABEL: multi_vec_min_multi_x4_u64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: ld1d { z31.d }, p0/z, [x0] ; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d ; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d ; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1d { z31.d }, p0/z, [x0]
; CHECK-NEXT: umin { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d } ; CHECK-NEXT: umin { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
<vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2, <vscale x 8 x half> %zm3, <vscale x 8 x half> %zm4) { <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2, <vscale x 8 x half> %zm3, <vscale x 8 x half> %zm4) {
; CHECK-LABEL: multi_vec_min_multi_x4_f16: ; CHECK-LABEL: multi_vec_min_multi_x4_f16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: ld1h { z31.h }, p0/z, [x0] ; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d ; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d ; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1h { z31.h }, p0/z, [x0]
; CHECK-NEXT: fmin { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h } ; CHECK-NEXT: fmin { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
<vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2, <vscale x 4 x float> %zm3, <vscale x 4 x float> %zm4) { <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2, <vscale x 4 x float> %zm3, <vscale x 4 x float> %zm4) {
; CHECK-LABEL: multi_vec_min_multi_x4_f32: ; CHECK-LABEL: multi_vec_min_multi_x4_f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: ld1w { z31.s }, p0/z, [x0] ; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d ; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d ; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1w { z31.s }, p0/z, [x0]
; CHECK-NEXT: fmin { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s } ; CHECK-NEXT: fmin { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
<vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4) { <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4) {
; CHECK-LABEL: multi_vec_min_multi_x4_f64: ; CHECK-LABEL: multi_vec_min_multi_x4_f64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: ld1d { z31.d }, p0/z, [x0] ; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d ; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d ; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1d { z31.d }, p0/z, [x0]
; CHECK-NEXT: fmin { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d } ; CHECK-NEXT: fmin { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
@multi_vec_minnm_x4_f16(<vscale x 8 x half> %dummy, <vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zdn3, <vscale x 8 x half> %zdn4, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2, <vscale x 8 x half> %zm3, <vscale x 8 x half> %zm4) { @multi_vec_minnm_x4_f16(<vscale x 8 x half> %dummy, <vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zdn3, <vscale x 8 x half> %zdn4, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2, <vscale x 8 x half> %zm3, <vscale x 8 x half> %zm4) {
; CHECK-LABEL: multi_vec_minnm_x4_f16: ; CHECK-LABEL: multi_vec_minnm_x4_f16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: ld1h { z31.h }, p0/z, [x0] ; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d ; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d ; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1h { z31.h }, p0/z, [x0]
; CHECK-NEXT: fminnm { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h } ; CHECK-NEXT: fminnm { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
@multi_vec_minnm_x4_f32(<vscale x 8 x half> %dummy, <vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zdn3, <vscale x 4 x float> %zdn4, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2, <vscale x 4 x float> %zm3, <vscale x 4 x float> %zm4) { @multi_vec_minnm_x4_f32(<vscale x 8 x half> %dummy, <vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zdn3, <vscale x 4 x float> %zdn4, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2, <vscale x 4 x float> %zm3, <vscale x 4 x float> %zm4) {
; CHECK-LABEL: multi_vec_minnm_x4_f32: ; CHECK-LABEL: multi_vec_minnm_x4_f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: ld1w { z31.s }, p0/z, [x0] ; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d ; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d ; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1w { z31.s }, p0/z, [x0]
; CHECK-NEXT: fminnm { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s } ; CHECK-NEXT: fminnm { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
@multi_vec_minnm_x4_f64(<vscale x 8 x half> %dummy, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4) { @multi_vec_minnm_x4_f64(<vscale x 8 x half> %dummy, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4) {
; CHECK-LABEL: multi_vec_minnm_x4_f64: ; CHECK-LABEL: multi_vec_minnm_x4_f64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: ld1d { z31.d }, p0/z, [x0] ; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d ; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d ; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1d { z31.d }, p0/z, [x0]
; CHECK-NEXT: fminnm { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d } ; CHECK-NEXT: fminnm { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.

llvm/test/CodeGen/AArch64/sme2-intrinsics-mlall.ll

llvm/test/CodeGen/AArch64/sme2-intrinsics-mlals.ll

llvm/test/CodeGen/AArch64/sme2-intrinsics-rshl.ll

Context not available.
@multi_vec_rounding_shl_x4_s8(<vscale x 16 x i8> %dummy, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4) { @multi_vec_rounding_shl_x4_s8(<vscale x 16 x i8> %dummy, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4) {
; CHECK-LABEL: multi_vec_rounding_shl_x4_s8: ; CHECK-LABEL: multi_vec_rounding_shl_x4_s8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.b ; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1b { z31.b }, p0/z, [x0] ; CHECK-NEXT: ld1b { z31.b }, p0/z, [x0]
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: srshl { z24.b - z27.b }, { z24.b - z27.b }, { z28.b - z31.b } ; CHECK-NEXT: srshl { z24.b - z27.b }, { z24.b - z27.b }, { z28.b - z31.b }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
@multi_vec_rounding_shl_x4_s16(<vscale x 8 x i16> %dummy, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4) { @multi_vec_rounding_shl_x4_s16(<vscale x 8 x i16> %dummy, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4) {
; CHECK-LABEL: multi_vec_rounding_shl_x4_s16: ; CHECK-LABEL: multi_vec_rounding_shl_x4_s16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1h { z31.h }, p0/z, [x0] ; CHECK-NEXT: ld1h { z31.h }, p0/z, [x0]
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: srshl { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h } ; CHECK-NEXT: srshl { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
@multi_vec_rounding_shl_x4_s32(<vscale x 4 x i32> %dummy, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4, <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4) { @multi_vec_rounding_shl_x4_s32(<vscale x 4 x i32> %dummy, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4, <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4) {
; CHECK-LABEL: multi_vec_rounding_shl_x4_s32: ; CHECK-LABEL: multi_vec_rounding_shl_x4_s32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1w { z31.s }, p0/z, [x0] ; CHECK-NEXT: ld1w { z31.s }, p0/z, [x0]
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: srshl { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s } ; CHECK-NEXT: srshl { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
@multi_vec_rounding_shl_x4_s64(<vscale x 2 x i64> %dummy, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4) { @multi_vec_rounding_shl_x4_s64(<vscale x 2 x i64> %dummy, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4) {
; CHECK-LABEL: multi_vec_rounding_shl_x4_s64: ; CHECK-LABEL: multi_vec_rounding_shl_x4_s64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1d { z31.d }, p0/z, [x0] ; CHECK-NEXT: ld1d { z31.d }, p0/z, [x0]
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: srshl { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d } ; CHECK-NEXT: srshl { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
@multi_vec_rounding_shl_x4_u8(<vscale x 16 x i8> %dummy, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4) { @multi_vec_rounding_shl_x4_u8(<vscale x 16 x i8> %dummy, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4) {
; CHECK-LABEL: multi_vec_rounding_shl_x4_u8: ; CHECK-LABEL: multi_vec_rounding_shl_x4_u8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.b ; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1b { z31.b }, p0/z, [x0] ; CHECK-NEXT: ld1b { z31.b }, p0/z, [x0]
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: urshl { z24.b - z27.b }, { z24.b - z27.b }, { z28.b - z31.b } ; CHECK-NEXT: urshl { z24.b - z27.b }, { z24.b - z27.b }, { z28.b - z31.b }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
@multi_vec_rounding_shl_x4_u16(<vscale x 8 x i16> %dummy, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4) { @multi_vec_rounding_shl_x4_u16(<vscale x 8 x i16> %dummy, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4) {
; CHECK-LABEL: multi_vec_rounding_shl_x4_u16: ; CHECK-LABEL: multi_vec_rounding_shl_x4_u16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1h { z31.h }, p0/z, [x0] ; CHECK-NEXT: ld1h { z31.h }, p0/z, [x0]
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: urshl { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h } ; CHECK-NEXT: urshl { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
@multi_vec_rounding_shl_x4_u32(<vscale x 4 x i32> %dummy, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4, <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4) { @multi_vec_rounding_shl_x4_u32(<vscale x 4 x i32> %dummy, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4, <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4) {
; CHECK-LABEL: multi_vec_rounding_shl_x4_u32: ; CHECK-LABEL: multi_vec_rounding_shl_x4_u32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1w { z31.s }, p0/z, [x0] ; CHECK-NEXT: ld1w { z31.s }, p0/z, [x0]
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: urshl { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s } ; CHECK-NEXT: urshl { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
@multi_vec_rounding_shl_x4_u64(<vscale x 2 x i64> %dummy, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4) { @multi_vec_rounding_shl_x4_u64(<vscale x 2 x i64> %dummy, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4) {
; CHECK-LABEL: multi_vec_rounding_shl_x4_u64: ; CHECK-LABEL: multi_vec_rounding_shl_x4_u64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1d { z31.d }, p0/z, [x0] ; CHECK-NEXT: ld1d { z31.d }, p0/z, [x0]
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: urshl { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d } ; CHECK-NEXT: urshl { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.

llvm/test/CodeGen/AArch64/sme2-intrinsics-sqdmulh.ll

Context not available.
<vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4) { <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4) {
; CHECK-LABEL: multi_vec_sat_double_mulh_multi_x4_s8: ; CHECK-LABEL: multi_vec_sat_double_mulh_multi_x4_s8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.b ; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1b { z31.b }, p0/z, [x0] ; CHECK-NEXT: ld1b { z31.b }, p0/z, [x0]
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: sqdmulh { z24.b - z27.b }, { z24.b - z27.b }, { z28.b - z31.b } ; CHECK-NEXT: sqdmulh { z24.b - z27.b }, { z24.b - z27.b }, { z28.b - z31.b }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
<vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4) { <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4) {
; CHECK-LABEL: multi_vec_sat_double_mulh_multi_x4_s16: ; CHECK-LABEL: multi_vec_sat_double_mulh_multi_x4_s16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1h { z31.h }, p0/z, [x0] ; CHECK-NEXT: ld1h { z31.h }, p0/z, [x0]
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: sqdmulh { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h } ; CHECK-NEXT: sqdmulh { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
<vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4) { <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4) {
; CHECK-LABEL: multi_vec_sat_double_mulh_multi_x4_s32: ; CHECK-LABEL: multi_vec_sat_double_mulh_multi_x4_s32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1w { z31.s }, p0/z, [x0] ; CHECK-NEXT: ld1w { z31.s }, p0/z, [x0]
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: sqdmulh { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s } ; CHECK-NEXT: sqdmulh { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.
<vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4) { <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4) {
; CHECK-LABEL: multi_vec_sat_double_mulh_multi_x4_s64: ; CHECK-LABEL: multi_vec_sat_double_mulh_multi_x4_s64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: mov z29.d, z6.d ; CHECK-NEXT: mov z30.d, z7.d
; CHECK-NEXT: mov z27.d, z4.d ; CHECK-NEXT: mov z27.d, z4.d
; CHECK-NEXT: mov z28.d, z5.d ; CHECK-NEXT: mov z29.d, z6.d
; CHECK-NEXT: mov z26.d, z3.d ; CHECK-NEXT: mov z26.d, z3.d
; CHECK-NEXT: mov z28.d, z5.d
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: ld1d { z31.d }, p0/z, [x0] ; CHECK-NEXT: ld1d { z31.d }, p0/z, [x0]
; CHECK-NEXT: mov z25.d, z2.d
; CHECK-NEXT: mov z24.d, z1.d
; CHECK-NEXT: sqdmulh { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d } ; CHECK-NEXT: sqdmulh { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }
; CHECK-NEXT: mov z0.d, z24.d ; CHECK-NEXT: mov z0.d, z24.d
; CHECK-NEXT: mov z1.d, z25.d ; CHECK-NEXT: mov z1.d, z25.d
Context not available.

llvm/test/CodeGen/AArch64/sme2-intrinsics-sub.ll

llvm/test/CodeGen/AArch64/sme2-intrinsics-vdot.ll

llvm/test/CodeGen/AArch64/speculation-hardening-loads.ll

Context not available.
ret i32 %ret ret i32 %ret
; Checking that the address laoded from is masked for a floating point load. ; Checking that the address laoded from is masked for a floating point load.
; CHECK-LABEL: csdb_emitted_for_subreg_use ; CHECK-LABEL: csdb_emitted_for_subreg_use
; CHECK: ldr x8, [x0] ; CHECK: cmp sp, #0
; CHECK-NEXT: cmp sp, #0 ; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: csetm x16, ne ; CHECK-NEXT: csetm x16, ne
; CHECK-NEXT: and x8, x8, x16 ; CHECK-NEXT: and x8, x8, x16
; csdb instruction must occur before the add instruction with w8 as operand. ; csdb instruction must occur before the add instruction with w8 as operand.
Context not available.
ret i64 %ret ret i64 %ret
; Checking that the address laoded from is masked for a floating point load. ; Checking that the address laoded from is masked for a floating point load.
; CHECK-LABEL: csdb_emitted_for_superreg_use ; CHECK-LABEL: csdb_emitted_for_superreg_use
; CHECK: ldr w8, [x0] ; CHECK: cmp sp, #0
; CHECK-NEXT: cmp sp, #0 ; CHECK-NEXT: ldr w8, [x0]
; CHECK-NEXT: csetm x16, ne ; CHECK-NEXT: csetm x16, ne
; CHECK-NEXT: and w8, w8, w16 ; CHECK-NEXT: and w8, w8, w16
; csdb instruction must occur before the add instruction with x8 as operand. ; csdb instruction must occur before the add instruction with x8 as operand.
Context not available.

llvm/test/CodeGen/AArch64/split-vector-insert.ll

Context not available.
; CHECK-LABEL: test_nxv2i64_v8i64: ; CHECK-LABEL: test_nxv2i64_v8i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: addvl sp, sp, #-3 ; CHECK-NEXT: addvl sp, sp, #-3
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 24 * VG ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 24 * VG
; CHECK-NEXT: cntd x8 ; CHECK-NEXT: ptrue p1.d, vl2
; CHECK-NEXT: mov w9, #2 ; CHECK-NEXT: cntd x8
; CHECK-NEXT: sub x8, x8, #2 ; CHECK-NEXT: mov w9, #2 // =0x2
; CHECK-NEXT: ptrue p0.d, vl2 ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: cmp x8, #2 ; CHECK-NEXT: sub x8, x8, #2
; CHECK-NEXT: mov x10, sp ; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT: csel x9, x8, x9, lo ; CHECK-NEXT: mov x10, sp
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 ; CHECK-NEXT: cmp x8, #2
; CHECK-NEXT: mov z0.d, p0/m, z1.d ; CHECK-NEXT: csel x9, x8, x9, lo
; CHECK-NEXT: lsl x9, x9, #3 ; CHECK-NEXT: cmp x8, #4
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: lsl x9, x9, #3
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: mov z0.d, p1/m, z1.d
; CHECK-NEXT: cmp x8, #4 ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: str q2, [x10, x9] ; CHECK-NEXT: str q2, [x10, x9]
; CHECK-NEXT: mov w9, #4 ; CHECK-NEXT: mov w9, #4 // =0x4
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] ; CHECK-NEXT: addvl x10, sp, #1
; CHECK-NEXT: csel x9, x8, x9, lo ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
; CHECK-NEXT: lsl x9, x9, #3 ; CHECK-NEXT: csel x9, x8, x9, lo
; CHECK-NEXT: addvl x10, sp, #1 ; CHECK-NEXT: cmp x8, #6
; CHECK-NEXT: cmp x8, #6 ; CHECK-NEXT: lsl x9, x9, #3
; CHECK-NEXT: st1d { z0.d }, p0, [sp, #1, mul vl] ; CHECK-NEXT: st1d { z0.d }, p0, [sp, #1, mul vl]
; CHECK-NEXT: str q3, [x10, x9] ; CHECK-NEXT: str q3, [x10, x9]
; CHECK-NEXT: mov w9, #6 ; CHECK-NEXT: mov w9, #6 // =0x6
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #1, mul vl] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: csel x8, x8, x9, lo ; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: addvl x9, sp, #2 ; CHECK-NEXT: addvl x9, sp, #2
; CHECK-NEXT: lsl x8, x8, #3 ; CHECK-NEXT: lsl x8, x8, #3
; CHECK-NEXT: st1d { z0.d }, p0, [sp, #2, mul vl] ; CHECK-NEXT: st1d { z0.d }, p0, [sp, #2, mul vl]
; CHECK-NEXT: str q4, [x9, x8] ; CHECK-NEXT: str q4, [x9, x8]
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #2, mul vl] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #2, mul vl]
; CHECK-NEXT: addvl sp, sp, #3 ; CHECK-NEXT: addvl sp, sp, #3
; CHECK-NEXT: .cfi_def_cfa wsp, 16 ; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w29 ; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret ; CHECK-NEXT: ret
Context not available.
; CHECK-LABEL: test_nxv2f64_v8f64: ; CHECK-LABEL: test_nxv2f64_v8f64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: addvl sp, sp, #-3 ; CHECK-NEXT: addvl sp, sp, #-3
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 24 * VG ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 24 * VG
; CHECK-NEXT: cntd x8 ; CHECK-NEXT: ptrue p1.d, vl2
; CHECK-NEXT: mov w9, #2 ; CHECK-NEXT: cntd x8
; CHECK-NEXT: sub x8, x8, #2 ; CHECK-NEXT: mov w9, #2 // =0x2
; CHECK-NEXT: ptrue p0.d, vl2 ; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: cmp x8, #2 ; CHECK-NEXT: sub x8, x8, #2
; CHECK-NEXT: mov x10, sp ; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT: csel x9, x8, x9, lo ; CHECK-NEXT: mov x10, sp
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 ; CHECK-NEXT: cmp x8, #2
; CHECK-NEXT: mov z0.d, p0/m, z1.d ; CHECK-NEXT: csel x9, x8, x9, lo
; CHECK-NEXT: lsl x9, x9, #3 ; CHECK-NEXT: cmp x8, #4
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: lsl x9, x9, #3
; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: mov z0.d, p1/m, z1.d
; CHECK-NEXT: cmp x8, #4 ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
; CHECK-NEXT: str q2, [x10, x9] ; CHECK-NEXT: str q2, [x10, x9]
; CHECK-NEXT: mov w9, #4 ; CHECK-NEXT: mov w9, #4 // =0x4
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] ; CHECK-NEXT: addvl x10, sp, #1
; CHECK-NEXT: csel x9, x8, x9, lo ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
; CHECK-NEXT: lsl x9, x9, #3 ; CHECK-NEXT: csel x9, x8, x9, lo
; CHECK-NEXT: addvl x10, sp, #1 ; CHECK-NEXT: cmp x8, #6
; CHECK-NEXT: cmp x8, #6 ; CHECK-NEXT: lsl x9, x9, #3
; CHECK-NEXT: st1d { z0.d }, p0, [sp, #1, mul vl] ; CHECK-NEXT: st1d { z0.d }, p0, [sp, #1, mul vl]
; CHECK-NEXT: str q3, [x10, x9] ; CHECK-NEXT: str q3, [x10, x9]
; CHECK-NEXT: mov w9, #6 ; CHECK-NEXT: mov w9, #6 // =0x6
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #1, mul vl] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: csel x8, x8, x9, lo ; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: addvl x9, sp, #2 ; CHECK-NEXT: addvl x9, sp, #2
; CHECK-NEXT: lsl x8, x8, #3 ; CHECK-NEXT: lsl x8, x8, #3
; CHECK-NEXT: st1d { z0.d }, p0, [sp, #2, mul vl] ; CHECK-NEXT: st1d { z0.d }, p0, [sp, #2, mul vl]
; CHECK-NEXT: str q4, [x9, x8] ; CHECK-NEXT: str q4, [x9, x8]
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #2, mul vl] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #2, mul vl]
; CHECK-NEXT: addvl sp, sp, #3 ; CHECK-NEXT: addvl sp, sp, #3
; CHECK-NEXT: .cfi_def_cfa wsp, 16 ; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w29 ; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret ; CHECK-NEXT: ret
Context not available.

llvm/test/CodeGen/AArch64/sqrt-fastmath.ll

llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll

llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll

llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll

llvm/test/CodeGen/AArch64/srem-vector-lkk.ll

llvm/test/CodeGen/AArch64/sshl_sat.ll

llvm/test/CodeGen/AArch64/ssub_sat.ll

llvm/test/CodeGen/AArch64/ssub_sat_plus.ll

llvm/test/CodeGen/AArch64/ssub_sat_vec.ll

llvm/test/CodeGen/AArch64/stack-guard-sysreg.ll

; RUN: split-file %s %t
; RUN: cat %t/main.ll %t/a.ll > %t/a2.ll ; RUN: cat %t/main.ll %t/a.ll > %t/a2.ll
dmgreenUnsubmitted
Done
ReplyInline Actions

Can you explain this one? Are the two versions now too different to keep the same?

dmgreen: Can you explain this one? Are the two versions now too different to keep the same?
harviniriawanAuthorUnsubmitted
Done
ReplyInline Actions

Yes indeed. the ones with CHECK-ADD annoyingly is scheduled slightly differently due to it being ADD instead of LDR

harviniriawan: Yes indeed. the ones with CHECK-ADD annoyingly is scheduled slightly differently due to it…
aeubanksUnsubmitted
Not Done
ReplyInline Actions

this test is broken, without the split-file the other files won't exist in a clean build, please fix or revert if it takes time to fix

aeubanks: this test is broken, without the `split-file` the other files won't exist in a clean build…
; RUN: cat %t/main.ll %t/b.ll > %t/b2.ll ; RUN: cat %t/main.ll %t/b.ll > %t/b2.ll
; RUN: cat %t/main.ll %t/c.ll > %t/c2.ll ; RUN: cat %t/main.ll %t/c.ll > %t/c2.ll
Context not available.
; RUN: llc %t/e2.ll -verify-machineinstrs -o - | \ ; RUN: llc %t/e2.ll -verify-machineinstrs -o - | \
; RUN: FileCheck --check-prefix=CHECK --check-prefix=CHECK-NPOT-NEG-OFFSET %s ; RUN: FileCheck --check-prefix=CHECK --check-prefix=CHECK-NPOT-NEG-OFFSET %s
; RUN: llc %t/f2.ll -verify-machineinstrs -o - | \ ; RUN: llc %t/f2.ll -verify-machineinstrs -o - | \
; RUN: FileCheck --check-prefix=CHECK --check-prefix=CHECK-257-OFFSET %s ; RUN: FileCheck --check-prefix=CHECK-ADD --check-prefix=CHECK-257-OFFSET %s
; RUN: llc %t/g2.ll -verify-machineinstrs -o - | \ ; RUN: llc %t/g2.ll -verify-machineinstrs -o - | \
; RUN: FileCheck --check-prefix=CHECK --check-prefix=CHECK-MINUS-257-OFFSET %s ; RUN: FileCheck --check-prefix=CHECK-ADD --check-prefix=CHECK-MINUS-257-OFFSET %s
; XFAIL ; XFAIL
; RUN: not --crash llc %t/h2.ll -o - 2>&1 | \ ; RUN: not --crash llc %t/h2.ll -o - 2>&1 | \
Context not available.
; Verify that we `mrs` from `SP_EL0` twice, rather than load from ; Verify that we `mrs` from `SP_EL0` twice, rather than load from
; __stack_chk_guard. ; __stack_chk_guard.
define dso_local void @foo(i64 %t) local_unnamed_addr #0 { define dso_local void @foo(i64 %t) local_unnamed_addr #0 {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo: // @foo
; CHECK: // %bb.0: // %entry ; CHECK: .cfi_startproc
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: mov x29, sp ; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: .cfi_def_cfa w29, 16 ; CHECK-NEXT: .cfi_def_cfa w29, 16
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: .cfi_remember_state ; CHECK-NEXT: .cfi_remember_state
; CHECK-NEXT: sub sp, sp, #16 ; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: mrs x8, SP_EL0 ; CHECK-NEXT: mrs x8, SP_EL0
; CHECK-NEXT: lsl x9, x0, #2 ; CHECK-NEXT: lsl x9, x0, #2
; CHECK-NO-OFFSET: ldr x8, [x8] ; CHECK-NO-OFFSET: ldr x8, [x8]
; CHECK-POSITIVE-OFFSET: ldr x8, [x8, #8] ; CHECK-POSITIVE-OFFSET: ldr x8, [x8, #8]
; CHECK-NEGATIVE-OFFSET: ldur x8, [x8, #-8] ; CHECK-NEGATIVE-OFFSET: ldur x8, [x8, #-8]
; CHECK-NPOT-OFFSET: ldur x8, [x8, #1] ; CHECK-NPOT-OFFSET: ldur x8, [x8, #1]
; CHECK-NPOT-NEG-OFFSET: ldur x8, [x8, #-1] ; CHECK-NPOT-NEG-OFFSET: ldur x8, [x8, #-1]
; CHECK-257-OFFSET: add x8, x8, #257 ; CHECK-NEXT: add x9, x9, #15
; CHECK-MINUS-257-OFFSET: sub x8, x8, #257 ; CHECK-NEXT: stur x8, [x29, #-8]
; CHECK-NEXT: add x9, x9, #15 ; CHECK-NEXT mov x8, sp
; CHECK-NEXT: and x9, x9, #0xfffffffffffffff0 ; CHECK-NEXT and x9, x9, #0xfffffffffffffff0
; CHECK-257-OFFSET-NEXT: ldr x8, [x8] ; CHECK-NEXT sub x0, x8, x9
; CHECK-MINUS-257-OFFSET-NEXT: ldr x8, [x8] ; CHECK-NEXT mov sp, x0
; CHECK-NEXT: stur x8, [x29, #-8] ; CHECK-NEXT bl baz
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT mrs x8, SP_EL0
; CHECK-NEXT: sub x0, x8, x9
; CHECK-NEXT: mov sp, x0
; CHECK-NEXT: bl baz
; CHECK-NEXT: mrs x8, SP_EL0
; CHECK-NO-OFFSET: ldr x8, [x8] ; CHECK-NO-OFFSET: ldr x8, [x8]
; CHECK-POSITIVE-OFFSET: ldr x8, [x8, #8] ; CHECK-POSITIVE-OFFSET: ldr x8, [x8, #8]
; CHECK-NEGATIVE-OFFSET: ldur x8, [x8, #-8] ; CHECK-NEGATIVE-OFFSET: ldur x8, [x8, #-8]
; CHECK-NPOT-OFFSET: ldur x8, [x8, #1] ; CHECK-NPOT-OFFSET: ldur x8, [x8, #1]
; CHECK-NPOT-NEG-OFFSET: ldur x8, [x8, #-1] ; CHECK-NPOT-NEG-OFFSET: ldur x8, [x8, #-1]
; CHECK-257-OFFSET: add x8, x8, #257 ; CHECK-NEXT: ldur x9, [x29, #-8]
; CHECK-257-OFFSET-NEXT: ldr x8, [x8] ; CHECK-NEXT: cmp x8, x9
; CHECK-MINUS-257-OFFSET: sub x8, x8, #257 ; CHECK-NEXT: b.ne .LBB0_2
; CHECK-MINUS-257-OFFSET-NEXT: ldr x8, [x8] ; CHECK-NEXT: // %bb.1: // %entry
; CHECK-NEXT: ldur x9, [x29, #-8] ; CHECK-NEXT: mov sp, x29
; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: b.ne .LBB0_2 ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: // %bb.1: // %entry ; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: mov sp, x29 ; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: .cfi_def_cfa wsp, 16 ; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ret
; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: .LBB0_2: // %entry
; CHECK-NEXT: .cfi_restore w30 ; CHECK-NEXT: .cfi_restore_state
; CHECK-NEXT: .cfi_restore w29 ; CHECK-NEXT: bl __stack_chk_fail
; CHECK-NEXT: ret ; CHECK-NEXT: .Lfunc_end0:
; CHECK-NEXT: .LBB0_2: // %entry ; CHECK-NEXT: .size foo, .Lfunc_end0-foo
; CHECK-NEXT: .cfi_restore_state ; CHECK-NEXT: .cfi_endproc
; CHECK-NEXT: bl __stack_chk_fail ; CHECK-NEXT: // -- End function
; CHECK-NOT: __stack_chk_guard ; CHECK-NEXT: .section ".note.GNU-stack","",@progbits
; CHECK-ADD: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-ADD-NEXT: .cfi_def_cfa_offset 16
; CHECK-ADD-NEXT: mov x29, sp
; CHECK-ADD-NEXT: .cfi_def_cfa w29, 16
; CHECK-ADD-NEXT: .cfi_offset w30, -8
; CHECK-ADD-NEXT: .cfi_offset w29, -16
; CHECK-ADD-NEXT: .cfi_remember_state
; CHECK-ADD-NEXT: sub sp, sp, #16
; CHECK-ADD-NEXT: mrs x8, SP_EL0
; CHECK-ADD-NEXT: lsl x9, x0, #2
; CHECK-MINUS-257-OFFSET: sub x8, x8, #257
; CHECK-257-OFFSET: add x8, x8, #257
; CHECK-ADD-NEXT: ldr x8, [x8]
; CHECK-ADD-NEXT: add x9, x9, #15
; CHECK-ADD-NEXT: and x9, x9, #0xfffffffffffffff0
; CHECK-ADD-NEXT: stur x8, [x29, #-8]
; CHECK-ADD-NEXT: mov x8, sp
; CHECK-ADD-NEXT: sub x0, x8, x9
; CHECK-ADD-NEXT: mov sp, x0
; CHECK-ADD-NEXT: bl baz
; CHECK-ADD-NEXT: mrs x8, SP_EL0
; CHECK-257-OFFSET: add x8, x8, #257
; CHECK-MINUS-257-OFFSET: sub x8, x8, #257
; CHECK-ADD-NEXT: ldr x8, [x8]
; CHECK-ADD-NEXT: ldur x9, [x29, #-8]
; CHECK-ADD-NEXT: cmp x8, x9
; CHECK-ADD-NEXT: b.ne .LBB0_2
; CHECK-ADD-NEXT: // %bb.1: // %entry
; CHECK-ADD-NEXT: mov sp, x29
; CHECK-ADD-NEXT: .cfi_def_cfa wsp, 16
; CHECK-ADD-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-ADD-NEXT: .cfi_def_cfa_offset 0
; CHECK-ADD-NEXT: .cfi_restore w30
; CHECK-ADD-NEXT: .cfi_restore w29
; CHECK-ADD-NEXT: ret
; CHECK-ADD-NEXT: .LBB0_2: // %entry
; CHECK-ADD-NEXT: .cfi_restore_state
; CHECK-ADD-NEXT: bl __stack_chk_fail
; CHECK-ADD-NEXT: .Lfunc_end0:
; CHECK-ADD-NEXT: .size foo, .Lfunc_end0-foo
; CHECK-ADD-NEXT: .cfi_endproc
; CHECK-ADD-NEXT: // -- End function
; CHECK-ADD-NEXT: .section ".note.GNU-stack","",@progbits
entry: entry:
%vla = alloca i32, i64 %t, align 4 %vla = alloca i32, i64 %t, align 4
call void @baz(ptr nonnull %vla) call void @baz(ptr nonnull %vla)
Context not available.

llvm/test/CodeGen/AArch64/statepoint-call-lowering.ll

llvm/test/CodeGen/AArch64/sve-abd.ll

llvm/test/CodeGen/AArch64/sve-alloca.ll

llvm/test/CodeGen/AArch64/sve-bitcast.ll

llvm/test/CodeGen/AArch64/sve-breakdown-scalable-vectortype.ll

llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll

llvm/test/CodeGen/AArch64/sve-doublereduct.ll

llvm/test/CodeGen/AArch64/sve-expand-div.ll

llvm/test/CodeGen/AArch64/sve-extract-element.ll

llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll

llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll

llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll

llvm/test/CodeGen/AArch64/sve-fcmp.ll

llvm/test/CodeGen/AArch64/sve-fcopysign.ll

llvm/test/CodeGen/AArch64/sve-fix-length-and-combine-512.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-addressing-modes.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-bitcast.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-build-vector.ll

Context not available.
define void @build_vector_minus2_dec32_v4i64(ptr %a) #0 { define void @build_vector_minus2_dec32_v4i64(ptr %a) #0 {
; VBITS_GE_256-LABEL: build_vector_minus2_dec32_v4i64: ; VBITS_GE_256-LABEL: build_vector_minus2_dec32_v4i64:
; VBITS_GE_256: // %bb.0: ; VBITS_GE_256: // %bb.0:
; VBITS_GE_256-NEXT: mov x8, #-32
; VBITS_GE_256-NEXT: ptrue p0.d, vl4 ; VBITS_GE_256-NEXT: ptrue p0.d, vl4
; VBITS_GE_256-NEXT: mov x8, #-32
; VBITS_GE_256-NEXT: index z0.d, #-2, x8 ; VBITS_GE_256-NEXT: index z0.d, #-2, x8
; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0]
; VBITS_GE_256-NEXT: ret ; VBITS_GE_256-NEXT: ret
dmgreenUnsubmitted
Done
ReplyInline Actions

Keep this

dmgreen: Keep this
Context not available.
; VBITS_GE_256-NEXT: .xword 8 ; VBITS_GE_256-NEXT: .xword 8
; VBITS_GE_256-LABEL: build_vector_no_stride_v4i64: ; VBITS_GE_256-LABEL: build_vector_no_stride_v4i64:
; VBITS_GE_256: // %bb.0: ; VBITS_GE_256: // %bb.0:
; VBITS_GE_256-NEXT: ptrue p0.d, vl4
; VBITS_GE_256-NEXT: adrp x8, .LCPI4_0 ; VBITS_GE_256-NEXT: adrp x8, .LCPI4_0
; VBITS_GE_256-NEXT: add x8, x8, :lo12:.LCPI4_0 ; VBITS_GE_256-NEXT: add x8, x8, :lo12:.LCPI4_0
; VBITS_GE_256-NEXT: ptrue p0.d, vl4
; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x8] ; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x8]
; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0] ; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0]
; VBITS_GE_256-NEXT: ret ; VBITS_GE_256-NEXT: ret
Context not available.

llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fcopysign.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-compares.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-fma.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-rounding.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-vselect.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-fp128.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests-crash.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-insert-vector-elt.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-compares.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-log.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-shifts.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-int-vselect.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-limit-duplane.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-loads.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-mask-opt.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-no-vscale-range.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-ptest.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-stores.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-trunc.ll

llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll

llvm/test/CodeGen/AArch64/sve-fold-vscale.ll

llvm/test/CodeGen/AArch64/sve-forward-st-to-ld.ll

llvm/test/CodeGen/AArch64/sve-fp-combine.ll

llvm/test/CodeGen/AArch64/sve-fp-int-min-max.ll

llvm/test/CodeGen/AArch64/sve-fp-reduce-fadda.ll

llvm/test/CodeGen/AArch64/sve-fpext-load.ll

llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll

llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll

llvm/test/CodeGen/AArch64/sve-fptrunc-store.ll

llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll

llvm/test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll

llvm/test/CodeGen/AArch64/sve-gep.ll

llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll

llvm/test/CodeGen/AArch64/sve-insert-element.ll

llvm/test/CodeGen/AArch64/sve-insert-vector.ll

llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll

llvm/test/CodeGen/AArch64/sve-int-arith.ll

llvm/test/CodeGen/AArch64/sve-int-reduce.ll

llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll

llvm/test/CodeGen/AArch64/sve-intrinsics-index.ll

llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll

llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.ll

llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll

llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-imm-addr-mode.ll

llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll

llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll

llvm/test/CodeGen/AArch64/sve-ld1r.ll

llvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll

llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll

llvm/test/CodeGen/AArch64/sve-masked-ldst-sext.ll

llvm/test/CodeGen/AArch64/sve-masked-ldst-zext.ll

llvm/test/CodeGen/AArch64/sve-masked-scatter-legalize.ll

llvm/test/CodeGen/AArch64/sve-masked-scatter.ll

llvm/test/CodeGen/AArch64/sve-pr62151.ll

llvm/test/CodeGen/AArch64/sve-pred-arith.ll

llvm/test/CodeGen/AArch64/sve-pred-selectop.ll

llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll

llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll

llvm/test/CodeGen/AArch64/sve-ptest-removal-sink.ll

llvm/test/CodeGen/AArch64/sve-redundant-store.ll

llvm/test/CodeGen/AArch64/sve-select.ll

llvm/test/CodeGen/AArch64/sve-sext-zext.ll

llvm/test/CodeGen/AArch64/sve-smulo-sdnode.ll

llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll

llvm/test/CodeGen/AArch64/sve-split-fcvt.ll

llvm/test/CodeGen/AArch64/sve-split-fp-reduce.ll

llvm/test/CodeGen/AArch64/sve-split-insert-elt.ll

llvm/test/CodeGen/AArch64/sve-split-int-pred-reduce.ll

Context not available.
define i1 @andv_nxv64i1(<vscale x 64 x i1> %a) { define i1 @andv_nxv64i1(<vscale x 64 x i1> %a) {
; CHECK-LABEL: andv_nxv64i1: ; CHECK-LABEL: andv_nxv64i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: and p1.b, p1/z, p1.b, p3.b ; CHECK-NEXT: and p1.b, p1/z, p1.b, p3.b
; CHECK-NEXT: and p0.b, p0/z, p0.b, p2.b ; CHECK-NEXT: and p0.b, p0/z, p0.b, p2.b
; CHECK-NEXT: ptrue p4.b
; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b ; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: nots p0.b, p4/z, p0.b ; CHECK-NEXT: ptrue p1.b
; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: nots p0.b, p1/z, p0.b
dmgreenUnsubmitted
Done
ReplyInline Actions

This is nice :)

dmgreen: This is nice :)
; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call i1 @llvm.vector.reduce.and.nxv64i1(<vscale x 64 x i1> %a) %res = call i1 @llvm.vector.reduce.and.nxv64i1(<vscale x 64 x i1> %a)
ret i1 %res ret i1 %res
Context not available.

llvm/test/CodeGen/AArch64/sve-split-load.ll

llvm/test/CodeGen/AArch64/sve-split-store.ll

llvm/test/CodeGen/AArch64/sve-srem-combine-loop.ll

llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll

llvm/test/CodeGen/AArch64/sve-stepvector.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitcast.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-subvector.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-convert.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-log.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-log-reduce.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reshuffle.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll

llvm/test/CodeGen/AArch64/sve-tailcall.ll

llvm/test/CodeGen/AArch64/sve-trunc.ll

llvm/test/CodeGen/AArch64/sve-umulo-sdnode.ll

llvm/test/CodeGen/AArch64/sve-vecreduce-fold.ll

llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll

llvm/test/CodeGen/AArch64/sve-vector-interleave.ll

llvm/test/CodeGen/AArch64/sve-vector-splat.ll

llvm/test/CodeGen/AArch64/sve-vscale-attr.ll

llvm/test/CodeGen/AArch64/sve-vselect-imm.ll

llvm/test/CodeGen/AArch64/sve2-fcopysign.ll

llvm/test/CodeGen/AArch64/sve2-fixed-length-fcopysign.ll

llvm/test/CodeGen/AArch64/sve2-intrinsics-combine-rshrnb.ll

llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx2.ll

llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx4.ll

llvm/test/CodeGen/AArch64/sve2p1-intrinsics-stores.ll

llvm/test/CodeGen/AArch64/swift-return.ll

Context not available.
; CHECK-LABEL: _gen10 ; CHECK-LABEL: _gen10
; CHECK: fmov d1, d0 ; CHECK: fmov d1, d0
; CHECK: fmov d2, d0 ; CHECK: fmov d2, d0
; CHECK: fmov d3, d0
; CHECK: mov w1, w0 ; CHECK: mov w1, w0
; CHECK: fmov d3, d0
; CHECK: mov w2, w0 ; CHECK: mov w2, w0
; CHECK: mov w3, w0 ; CHECK: mov w3, w0
; CHECK: ret ; CHECK: ret
Context not available.

llvm/test/CodeGen/AArch64/swifterror.ll

llvm/test/CodeGen/AArch64/tbl-loops.ll

llvm/test/CodeGen/AArch64/trunc-to-tbl.ll

llvm/test/CodeGen/AArch64/typepromotion-overflow.ll

llvm/test/CodeGen/AArch64/typepromotion-phisret.ll

llvm/test/CodeGen/AArch64/typepromotion-signed.ll

llvm/test/CodeGen/AArch64/uadd_sat.ll

llvm/test/CodeGen/AArch64/uadd_sat_plus.ll

llvm/test/CodeGen/AArch64/uadd_sat_vec.ll

llvm/test/CodeGen/AArch64/umulo-128-legalisation-lowering.ll

llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-innerouter.ll

llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-interleavedbits.ll

llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll

llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-lowhigh.ll

llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-variablemask.ll

llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll

llvm/test/CodeGen/AArch64/urem-lkk.ll

llvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll

llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll

llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll

llvm/test/CodeGen/AArch64/urem-seteq-vec-tautological.ll

llvm/test/CodeGen/AArch64/urem-vector-lkk.ll

llvm/test/CodeGen/AArch64/usub_sat_vec.ll

llvm/test/CodeGen/AArch64/vcvt-oversize.ll

llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+neon -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+neon -verify-machineinstrs < %s | FileCheck %s
; Basic tests from input vector to bitmask ; Basic tests from input vector to bitmask
Context not available.
define i16 @convert_to_bitmask16(<16 x i8> %vec) { define i16 @convert_to_bitmask16(<16 x i8> %vec) {
; Bits used in mask ; Bits used in mask
; CHECK-LABEL: lCPI0_0 ; CHECK-LABEL: convert_to_bitmask16:
dmgreenUnsubmitted
Done
ReplyInline Actions

These need to keep checking the constant pools

dmgreen: These need to keep checking the constant pools
; CHECK-NEXT: .byte 1 ; CHECK: ; %bb.0:
; CHECK-NEXT: .byte 2 ; CHECK-NEXT: Lloh0:
; CHECK-NEXT: .byte 4 ; CHECK-NEXT: adrp x8, lCPI0_0@PAGE
; CHECK-NEXT: .byte 8 ; CHECK-NEXT: cmeq.16b v0, v0, #0
; CHECK-NEXT: .byte 16 ; CHECK-NEXT: Lloh1:
; CHECK-NEXT: .byte 32 ; CHECK-NEXT: ldr q1, [x8, lCPI0_0@PAGEOFF]
; CHECK-NEXT: .byte 64 ; CHECK-NEXT: bic.16b v0, v1, v0
; CHECK-NEXT: .byte 128 ; CHECK-NEXT: ext.16b v1, v0, v0, #8
; CHECK-NEXT: .byte 1 ; CHECK-NEXT: zip1.16b v0, v0, v1
; CHECK-NEXT: .byte 2 ; CHECK-NEXT: addv.8h h0, v0
; CHECK-NEXT: .byte 4 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: .byte 8 ; CHECK-NEXT: ret
; CHECK-NEXT: .byte 16 ; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh1
; CHECK-NEXT: .byte 32
; CHECK-NEXT: .byte 64
; CHECK-NEXT: .byte 128
; Actual conversion ; Actual conversion
; CHECK-LABEL: convert_to_bitmask16
; CHECK: ; %bb.0:
; CHECK-NEXT: Lloh0:
; CHECK-NEXT: adrp x8, lCPI0_0@PAGE
; CHECK-NEXT: cmeq.16b v0, v0, #0
; CHECK-NEXT: Lloh1:
; CHECK-NEXT: ldr q1, [x8, lCPI0_0@PAGEOFF]
; CHECK-NEXT: bic.16b v0, v1, v0
; CHECK-NEXT: ext.16b v1, v0, v0, #8
; CHECK-NEXT: zip1.16b v0, v0, v1
; CHECK-NEXT: addv.8h h0, v0
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
%cmp_result = icmp ne <16 x i8> %vec, zeroinitializer %cmp_result = icmp ne <16 x i8> %vec, zeroinitializer
%bitmask = bitcast <16 x i1> %cmp_result to i16 %bitmask = bitcast <16 x i1> %cmp_result to i16
Context not available.
} }
define i16 @convert_to_bitmask8(<8 x i16> %vec) { define i16 @convert_to_bitmask8(<8 x i16> %vec) {
; CHECK-LABEL: lCPI1_0: ; CHECK-LABEL: convert_to_bitmask8:
; CHECK-NEXT: .short 1
; CHECK-NEXT: .short 2
; CHECK-NEXT: .short 4
; CHECK-NEXT: .short 8
; CHECK-NEXT: .short 16
; CHECK-NEXT: .short 32
; CHECK-NEXT: .short 64
; CHECK-NEXT: .short 128
; CHECK-LABEL: convert_to_bitmask8
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: Lloh2: ; CHECK-NEXT: Lloh2:
; CHECK-NEXT: adrp x8, lCPI1_0@PAGE ; CHECK-NEXT: adrp x8, lCPI1_0@PAGE
; CHECK-NEXT: cmeq.8h v0, v0, #0 ; CHECK-NEXT: cmeq.8h v0, v0, #0
; CHECK-NEXT: Lloh3: ; CHECK-NEXT: Lloh3:
; CHECK-NEXT: ldr q1, [x8, lCPI1_0@PAGEOFF] ; CHECK-NEXT: ldr q1, [x8, lCPI1_0@PAGEOFF]
; CHECK-NEXT: bic.16b v0, v1, v0 ; CHECK-NEXT: bic.16b v0, v1, v0
; CHECK-NEXT: addv.8h h0, v0 ; CHECK-NEXT: addv.8h h0, v0
; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: and w0, w8, #0xff ; CHECK-NEXT: and w0, w8, #0xff
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh2, Lloh3
%cmp_result = icmp ne <8 x i16> %vec, zeroinitializer %cmp_result = icmp ne <8 x i16> %vec, zeroinitializer
%bitmask = bitcast <8 x i1> %cmp_result to i8 %bitmask = bitcast <8 x i1> %cmp_result to i8
Context not available.
} }
define i4 @convert_to_bitmask4(<4 x i32> %vec) { define i4 @convert_to_bitmask4(<4 x i32> %vec) {
; CHECK-LABEL: lCPI2_0: ; CHECK-LABEL: convert_to_bitmask4:
; CHECK-NEXT: .long 1
; CHECK-NEXT: .long 2
; CHECK-NEXT: .long 4
; CHECK-NEXT: .long 8
; CHECK-LABEL: convert_to_bitmask4
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: Lloh4: ; CHECK-NEXT: Lloh4:
; CHECK-NEXT: adrp x8, lCPI2_0@PAGE ; CHECK-NEXT: adrp x8, lCPI2_0@PAGE
; CHECK-NEXT: cmeq.4s v0, v0, #0 ; CHECK-NEXT: cmeq.4s v0, v0, #0
; CHECK-NEXT: Lloh5: ; CHECK-NEXT: Lloh5:
; CHECK-NEXT: ldr q1, [x8, lCPI2_0@PAGEOFF] ; CHECK-NEXT: ldr q1, [x8, lCPI2_0@PAGEOFF]
; CHECK-NEXT: bic.16b v0, v1, v0 ; CHECK-NEXT: bic.16b v0, v1, v0
; CHECK-NEXT: addv.4s s0, v0 ; CHECK-NEXT: addv.4s s0, v0
; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh4, Lloh5
%cmp_result = icmp ne <4 x i32> %vec, zeroinitializer %cmp_result = icmp ne <4 x i32> %vec, zeroinitializer
%bitmask = bitcast <4 x i1> %cmp_result to i4 %bitmask = bitcast <4 x i1> %cmp_result to i4
Context not available.
} }
define i8 @convert_to_bitmask2(<2 x i64> %vec) { define i8 @convert_to_bitmask2(<2 x i64> %vec) {
; CHECK-LABEL: lCPI3_0: ; CHECK-LABEL: convert_to_bitmask2:
; CHECK-NEXT: .quad 1
; CHECK-NEXT: .quad 2
; CHECK-LABEL: convert_to_bitmask2
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: Lloh6: ; CHECK-NEXT: Lloh6:
; CHECK-NEXT: adrp x8, lCPI3_0@PAGE ; CHECK-NEXT: adrp x8, lCPI3_0@PAGE
; CHECK-NEXT: cmeq.2d v0, v0, #0 ; CHECK-NEXT: cmeq.2d v0, v0, #0
; CHECK-NEXT: Lloh7: ; CHECK-NEXT: Lloh7:
; CHECK-NEXT: ldr q1, [x8, lCPI3_0@PAGEOFF] ; CHECK-NEXT: ldr q1, [x8, lCPI3_0@PAGEOFF]
; CHECK-NEXT: bic.16b v0, v1, v0 ; CHECK-NEXT: bic.16b v0, v1, v0
; CHECK-NEXT: addp.2d d0, v0 ; CHECK-NEXT: addp.2d d0, v0
; CHECK-NEXT: fmov x8, d0 ; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: and w0, w8, #0x3 ; CHECK-NEXT: and w0, w8, #0x3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh6, Lloh7
%cmp_result = icmp ne <2 x i64> %vec, zeroinitializer %cmp_result = icmp ne <2 x i64> %vec, zeroinitializer
%bitmask = bitcast <2 x i1> %cmp_result to i2 %bitmask = bitcast <2 x i1> %cmp_result to i2
Context not available.
; Clang's __builtin_convertvector adds an undef vector concat for vectors with <8 elements. ; Clang's __builtin_convertvector adds an undef vector concat for vectors with <8 elements.
define i8 @clang_builtins_undef_concat_convert_to_bitmask4(<4 x i32> %vec) { define i8 @clang_builtins_undef_concat_convert_to_bitmask4(<4 x i32> %vec) {
; CHECK-LABEL: lCPI4_0: ; CHECK-LABEL: clang_builtins_undef_concat_convert_to_bitmask4:
; CHECK-NEXT: .long 1
; CHECK-NEXT: .long 2
; CHECK-NEXT: .long 4
; CHECK-NEXT: .long 8
; CHECK-LABEL: clang_builtins_undef_concat_convert_to_bitmask4
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: Lloh8: ; CHECK-NEXT: Lloh8:
; CHECK-NEXT: adrp x8, lCPI4_0@PAGE ; CHECK-NEXT: adrp x8, lCPI4_0@PAGE
; CHECK-NEXT: cmeq.4s v0, v0, #0 ; CHECK-NEXT: cmeq.4s v0, v0, #0
; CHECK-NEXT: Lloh9: ; CHECK-NEXT: Lloh9:
; CHECK-NEXT: ldr q1, [x8, lCPI4_0@PAGEOFF] ; CHECK-NEXT: ldr q1, [x8, lCPI4_0@PAGEOFF]
; CHECK-NEXT: bic.16b v0, v1, v0 ; CHECK-NEXT: bic.16b v0, v1, v0
; CHECK-NEXT: addv.4s s0, v0 ; CHECK-NEXT: addv.4s s0, v0
; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh8, Lloh9
%cmp_result = icmp ne <4 x i32> %vec, zeroinitializer %cmp_result = icmp ne <4 x i32> %vec, zeroinitializer
%vector_pad = shufflevector <4 x i1> %cmp_result, <4 x i1> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> %vector_pad = shufflevector <4 x i1> %cmp_result, <4 x i1> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
Context not available.
define i4 @convert_to_bitmask_no_compare(<4 x i32> %vec1, <4 x i32> %vec2) { define i4 @convert_to_bitmask_no_compare(<4 x i32> %vec1, <4 x i32> %vec2) {
; CHECK-LABEL: lCPI5_0: ; CHECK-LABEL: convert_to_bitmask_no_compare:
; CHECK-NEXT: .long 1
; CHECK-NEXT: .long 2
; CHECK-NEXT: .long 4
; CHECK-NEXT: .long 8
; CHECK-LABEL: convert_to_bitmask_no_compare
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: Lloh10: ; CHECK-NEXT: and.16b v0, v0, v1
; CHECK-NEXT: adrp x8, lCPI5_0@PAGE ; CHECK-NEXT: Lloh10:
; CHECK-NEXT: and.16b v0, v0, v1 ; CHECK-NEXT: adrp x8, lCPI5_0@PAGE
; CHECK-NEXT: shl.4s v0, v0, #31 ; CHECK-NEXT: Lloh11:
; CHECK-NEXT: Lloh11: ; CHECK-NEXT: ldr q1, [x8, lCPI5_0@PAGEOFF]
; CHECK-NEXT: ldr q1, [x8, lCPI5_0@PAGEOFF] ; CHECK-NEXT: shl.4s v0, v0, #31
; CHECK-NEXT: cmlt.4s v0, v0, #0 ; CHECK-NEXT: cmlt.4s v0, v0, #0
; CHECK-NEXT: and.16b v0, v0, v1 ; CHECK-NEXT: and.16b v0, v0, v1
; CHECK-NEXT: addv.4s s0, v0 ; CHECK-NEXT: addv.4s s0, v0
; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh10, Lloh11
%cmp = and <4 x i32> %vec1, %vec2 %cmp = and <4 x i32> %vec1, %vec2
%trunc = trunc <4 x i32> %cmp to <4 x i1> %trunc = trunc <4 x i32> %cmp to <4 x i1>
Context not available.
} }
define i4 @convert_to_bitmask_with_compare_chain(<4 x i32> %vec1, <4 x i32> %vec2) { define i4 @convert_to_bitmask_with_compare_chain(<4 x i32> %vec1, <4 x i32> %vec2) {
; CHECK-LABEL: lCPI6_0: ; CHECK-LABEL: convert_to_bitmask_with_compare_chain:
; CHECK-NEXT: .long 1
; CHECK-NEXT: .long 2
; CHECK-NEXT: .long 4
; CHECK-NEXT: .long 8
; CHECK-LABEL: convert_to_bitmask_with_compare_chain
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: Lloh12: ; CHECK-NEXT: cmeq.4s v2, v0, #0
; CHECK-NEXT: adrp x8, lCPI6_0@PAGE ; CHECK-NEXT: cmeq.4s v0, v0, v1
; CHECK-NEXT: cmeq.4s v2, v0, #0 ; CHECK-NEXT: Lloh12:
; CHECK-NEXT: cmeq.4s v0, v0, v1 ; CHECK-NEXT: adrp x8, lCPI6_0@PAGE
; CHECK-NEXT: Lloh13: ; CHECK-NEXT: Lloh13:
; CHECK-NEXT: ldr q1, [x8, lCPI6_0@PAGEOFF] ; CHECK-NEXT: ldr q1, [x8, lCPI6_0@PAGEOFF]
; CHECK-NEXT: bic.16b v0, v0, v2 ; CHECK-NEXT: bic.16b v0, v0, v2
; CHECK-NEXT: and.16b v0, v0, v1 ; CHECK-NEXT: and.16b v0, v0, v1
; CHECK-NEXT: addv.4s s0, v0 ; CHECK-NEXT: addv.4s s0, v0
; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh12, Lloh13
%cmp1 = icmp ne <4 x i32> %vec1, zeroinitializer %cmp1 = icmp ne <4 x i32> %vec1, zeroinitializer
%cmp2 = icmp eq <4 x i32> %vec1, %vec2 %cmp2 = icmp eq <4 x i32> %vec1, %vec2
Context not available.
} }
define i4 @convert_to_bitmask_with_trunc_in_chain(<4 x i32> %vec1, <4 x i32> %vec2) { define i4 @convert_to_bitmask_with_trunc_in_chain(<4 x i32> %vec1, <4 x i32> %vec2) {
; CHECK-LABEL: lCPI7_0: ; CHECK-LABEL: convert_to_bitmask_with_trunc_in_chain:
; CHECK-NEXT: .long 1
; CHECK-NEXT: .long 2
; CHECK-NEXT: .long 4
; CHECK-NEXT: .long 8
; CHECK-LABEL: convert_to_bitmask_with_trunc_in_chain
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: cmeq.4s v0, v0, #0 ; CHECK-NEXT: cmeq.4s v0, v0, #0
; CHECK-NEXT: Lloh14: ; CHECK-NEXT: Lloh14:
; CHECK-NEXT: adrp x8, lCPI7_0@PAGE ; CHECK-NEXT: adrp x8, lCPI7_0@PAGE
; CHECK-NEXT: bic.16b v0, v1, v0 ; CHECK-NEXT: bic.16b v0, v1, v0
; CHECK-NEXT: shl.4s v0, v0, #31 ; CHECK-NEXT: Lloh15:
; CHECK-NEXT: Lloh15: ; CHECK-NEXT: ldr q1, [x8, lCPI7_0@PAGEOFF]
; CHECK-NEXT: ldr q1, [x8, lCPI7_0@PAGEOFF] ; CHECK-NEXT: shl.4s v0, v0, #31
; CHECK-NEXT: cmlt.4s v0, v0, #0 ; CHECK-NEXT: cmlt.4s v0, v0, #0
; CHECK-NEXT: and.16b v0, v0, v1 ; CHECK-NEXT: and.16b v0, v0, v1
; CHECK-NEXT: addv.4s s0, v0 ; CHECK-NEXT: addv.4s s0, v0
; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh14, Lloh15
%cmp1 = icmp ne <4 x i32> %vec1, zeroinitializer %cmp1 = icmp ne <4 x i32> %vec1, zeroinitializer
%trunc_vec = trunc <4 x i32> %vec2 to <4 x i1> %trunc_vec = trunc <4 x i32> %vec2 to <4 x i1>
Context not available.
} }
define i4 @convert_to_bitmask_with_unknown_type_in_long_chain(<4 x i32> %vec1, <4 x i32> %vec2) { define i4 @convert_to_bitmask_with_unknown_type_in_long_chain(<4 x i32> %vec1, <4 x i32> %vec2) {
; CHECK-LABEL: lCPI8_0: ; CHECK-LABEL: convert_to_bitmask_with_unknown_type_in_long_chain:
; CHECK-NEXT: .short 1 ; CHECK: ; %bb.0:
; CHECK-NEXT: .short 2 ; CHECK-NEXT: cmeq.4s v0, v0, #0
; CHECK-NEXT: .short 4 ; CHECK-NEXT: cmeq.4s v1, v1, #0
; CHECK-NEXT: .short 8 ; CHECK-NEXT: Lloh16:
; CHECK-NEXT: adrp x8, lCPI8_0@PAGE
; CHECK-LABEL: convert_to_bitmask_with_unknown_type_in_long_chain ; CHECK-NEXT: movi d2, #0x000000ffffffff
; CHECK: ; %bb.0: ; CHECK-NEXT: movi d3, #0x00ffffffffffff
; CHECK-NEXT: cmeq.4s v0, v0, #0 ; CHECK-NEXT: bic.16b v0, v1, v0
; CHECK-NEXT: Lloh16: ; CHECK-NEXT: movi d1, #0xffff0000ffff0000
; CHECK-NEXT: adrp x8, lCPI8_0@PAGE ; CHECK-NEXT: xtn.4h v0, v0
; CHECK-NEXT: cmeq.4s v1, v1, #0 ; CHECK-NEXT: orr.8b v0, v0, v2
; CHECK-NEXT: movi d2, #0x000000ffffffff ; CHECK-NEXT: movi d2, #0x00ffffffff0000
; CHECK-NEXT: bic.16b v0, v1, v0 ; CHECK-NEXT: eor.8b v1, v0, v1
; CHECK-NEXT: movi d1, #0xffff0000ffff0000 ; CHECK-NEXT: eor.8b v0, v0, v2
; CHECK-NEXT: xtn.4h v0, v0 ; CHECK-NEXT: mov.h v1[2], wzr
; CHECK-NEXT: movi d3, #0x00ffffffffffff ; CHECK-NEXT: orr.8b v0, v0, v3
; CHECK-NEXT: orr.8b v0, v0, v2 ; CHECK-NEXT: orr.8b v0, v1, v0
; CHECK-NEXT: movi d2, #0x00ffffffff0000 ; CHECK-NEXT: Lloh17:
; CHECK-NEXT: eor.8b v1, v0, v1 ; CHECK-NEXT: ldr d1, [x8, lCPI8_0@PAGEOFF]
; CHECK-NEXT: mov.h v1[2], wzr ; CHECK-NEXT: shl.4h v0, v0, #15
; CHECK-NEXT: eor.8b v0, v0, v2 ; CHECK-NEXT: cmlt.4h v0, v0, #0
; CHECK-NEXT: orr.8b v0, v0, v3 ; CHECK-NEXT: and.8b v0, v0, v1
; CHECK-NEXT: orr.8b v0, v1, v0 ; CHECK-NEXT: addv.4h h0, v0
; CHECK-NEXT: Lloh17: ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ldr d1, [x8, lCPI8_0@PAGEOFF] ; CHECK-NEXT: ret
; CHECK-NEXT: shl.4h v0, v0, #15 ; CHECK-NEXT: .loh AdrpLdr Lloh16, Lloh17
; CHECK-NEXT: cmlt.4h v0, v0, #0
; CHECK-NEXT: and.8b v0, v0, v1
; CHECK-NEXT: addv.4h h0, v0
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
%cmp1 = icmp ne <4 x i32> %vec1, zeroinitializer %cmp1 = icmp ne <4 x i32> %vec1, zeroinitializer
%cmp2 = icmp eq <4 x i32> %vec2, zeroinitializer %cmp2 = icmp eq <4 x i32> %vec2, zeroinitializer
Context not available.
} }
define i4 @convert_to_bitmask_with_different_types_in_chain(<4 x i16> %vec1, <4 x i32> %vec2) { define i4 @convert_to_bitmask_with_different_types_in_chain(<4 x i16> %vec1, <4 x i32> %vec2) {
; CHECK-LABEL: lCPI9_0: ; CHECK-LABEL: convert_to_bitmask_with_different_types_in_chain:
; CHECK-NEXT: .short 1 ; CHECK: ; %bb.0:
; CHECK-NEXT: .short 2 ; CHECK-NEXT: cmeq.4s v1, v1, #0
; CHECK-NEXT: .short 4 ; CHECK-NEXT: cmeq.4h v0, v0, #0
; CHECK-NEXT: .short 8 ; CHECK-NEXT: Lloh18:
; CHECK-NEXT: adrp x8, lCPI9_0@PAGE
; CHECK-LABEL: convert_to_bitmask_with_different_types_in_chain ; CHECK-NEXT: xtn.4h v1, v1
; CHECK: ; %bb.0: ; CHECK-NEXT: orn.8b v0, v1, v0
; CHECK-NEXT: Lloh18: ; CHECK-NEXT: Lloh19:
; CHECK-NEXT: adrp x8, lCPI9_0@PAGE ; CHECK-NEXT: ldr d1, [x8, lCPI9_0@PAGEOFF]
; CHECK-NEXT: cmeq.4h v0, v0, #0 ; CHECK-NEXT: and.8b v0, v0, v1
; CHECK-NEXT: cmeq.4s v1, v1, #0 ; CHECK-NEXT: addv.4h h0, v0
; CHECK-NEXT: xtn.4h v1, v1 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: Lloh19: ; CHECK-NEXT: ret
; CHECK-NEXT: ldr d2, [x8, lCPI9_0@PAGEOFF] ; CHECK-NEXT: .loh AdrpLdr Lloh18, Lloh19
; CHECK-NEXT: orn.8b v0, v1, v0
; CHECK-NEXT: and.8b v0, v0, v2
; CHECK-NEXT: addv.4h h0, v0
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
%cmp1 = icmp ne <4 x i16> %vec1, zeroinitializer %cmp1 = icmp ne <4 x i16> %vec1, zeroinitializer
%cmp2 = icmp eq <4 x i32> %vec2, zeroinitializer %cmp2 = icmp eq <4 x i32> %vec2, zeroinitializer
Context not available.
define i16 @convert_to_bitmask_without_knowing_type(<16 x i1> %vec) { define i16 @convert_to_bitmask_without_knowing_type(<16 x i1> %vec) {
; CHECK-LABEL: convert_to_bitmask_without_knowing_type: ; CHECK-LABEL: convert_to_bitmask_without_knowing_type:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: shl.16b v0, v0, #7
; CHECK-NEXT: Lloh20: ; CHECK-NEXT: Lloh20:
; CHECK-NEXT: adrp x8, lCPI10_0@PAGE ; CHECK-NEXT: adrp x8, lCPI10_0@PAGE
; CHECK-NEXT: shl.16b v0, v0, #7
; CHECK-NEXT: cmlt.16b v0, v0, #0
; CHECK-NEXT: Lloh21: ; CHECK-NEXT: Lloh21:
; CHECK-NEXT: ldr q1, [x8, lCPI10_0@PAGEOFF] ; CHECK-NEXT: ldr q1, [x8, lCPI10_0@PAGEOFF]
; CHECK-NEXT: cmlt.16b v0, v0, #0
; CHECK-NEXT: and.16b v0, v0, v1 ; CHECK-NEXT: and.16b v0, v0, v1
; CHECK-NEXT: ext.16b v1, v0, v0, #8 ; CHECK-NEXT: ext.16b v1, v0, v0, #8
; CHECK-NEXT: zip1.16b v0, v0, v1 ; CHECK-NEXT: zip1.16b v0, v0, v1
; CHECK-NEXT: addv.8h h0, v0 ; CHECK-NEXT: addv.8h h0, v0
; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh20, Lloh21
%bitmask = bitcast <16 x i1> %vec to i16 %bitmask = bitcast <16 x i1> %vec to i16
ret i16 %bitmask ret i16 %bitmask
} }
define i2 @convert_to_bitmask_2xi32(<2 x i32> %vec) { define i2 @convert_to_bitmask_2xi32(<2 x i32> %vec) {
; CHECK-LABEL: convert_to_bitmask_2xi32 ; CHECK-LABEL: convert_to_bitmask_2xi32:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: Lloh22: ; CHECK-NEXT: Lloh22:
; CHECK-NEXT: adrp x8, lCPI11_0@PAGE ; CHECK-NEXT: adrp x8, lCPI11_0@PAGE
; CHECK-NEXT: cmeq.2s v0, v0, #0 ; CHECK-NEXT: cmeq.2s v0, v0, #0
; CHECK-NEXT: Lloh23: ; CHECK-NEXT: Lloh23:
; CHECK-NEXT: ldr d1, [x8, lCPI11_0@PAGEOFF] ; CHECK-NEXT: ldr d1, [x8, lCPI11_0@PAGEOFF]
; CHECK-NEXT: bic.8b v0, v1, v0 ; CHECK-NEXT: bic.8b v0, v1, v0
; CHECK-NEXT: addp.2s v0, v0, v0 ; CHECK-NEXT: addp.2s v0, v0, v0
; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh22, Lloh23
%cmp_result = icmp ne <2 x i32> %vec, zeroinitializer %cmp_result = icmp ne <2 x i32> %vec, zeroinitializer
%bitmask = bitcast <2 x i1> %cmp_result to i2 %bitmask = bitcast <2 x i1> %cmp_result to i2
Context not available.
} }
define i4 @convert_to_bitmask_4xi8(<4 x i8> %vec) { define i4 @convert_to_bitmask_4xi8(<4 x i8> %vec) {
; CHECK-LABEL: convert_to_bitmask_4xi8 ; CHECK-LABEL: convert_to_bitmask_4xi8:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: bic.4h v0, #255, lsl #8
; CHECK-NEXT: Lloh24: ; CHECK-NEXT: Lloh24:
; CHECK-NEXT: adrp x8, lCPI12_0@PAGE ; CHECK-NEXT: adrp x8, lCPI12_0@PAGE
; CHECK-NEXT: bic.4h v0, #255, lsl #8
; CHECK-NEXT: cmeq.4h v0, v0, #0
; CHECK-NEXT: Lloh25: ; CHECK-NEXT: Lloh25:
; CHECK-NEXT: ldr d1, [x8, lCPI12_0@PAGEOFF] ; CHECK-NEXT: ldr d1, [x8, lCPI12_0@PAGEOFF]
; CHECK-NEXT: bic.8b v0, v1, v0 ; CHECK-NEXT: cmeq.4h v0, v0, #0
; CHECK-NEXT: addv.4h h0, v0 ; CHECK-NEXT: bic.8b v0, v1, v0
; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: addv.4h h0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh24, Lloh25
%cmp_result = icmp ne <4 x i8> %vec, zeroinitializer %cmp_result = icmp ne <4 x i8> %vec, zeroinitializer
%bitmask = bitcast <4 x i1> %cmp_result to i4 %bitmask = bitcast <4 x i1> %cmp_result to i4
Context not available.
} }
define i8 @convert_to_bitmask_8xi2(<8 x i2> %vec) { define i8 @convert_to_bitmask_8xi2(<8 x i2> %vec) {
; CHECK-LABEL: convert_to_bitmask_8xi2 ; CHECK-LABEL: convert_to_bitmask_8xi2:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: movi.8b v1, #3 ; CHECK-NEXT: movi.8b v1, #3
; CHECK-NEXT: Lloh26: ; CHECK-NEXT: Lloh26:
; CHECK-NEXT: adrp x8, lCPI13_0@PAGE ; CHECK-NEXT: adrp x8, lCPI13_0@PAGE
; CHECK-NEXT: and.8b v0, v0, v1 ; CHECK-NEXT: and.8b v0, v0, v1
; CHECK-NEXT: Lloh27: ; CHECK-NEXT: Lloh27:
; CHECK-NEXT: ldr d1, [x8, lCPI13_0@PAGEOFF] ; CHECK-NEXT: ldr d1, [x8, lCPI13_0@PAGEOFF]
; CHECK-NEXT: cmeq.8b v0, v0, #0 ; CHECK-NEXT: cmeq.8b v0, v0, #0
; CHECK-NEXT: bic.8b v0, v1, v0 ; CHECK-NEXT: bic.8b v0, v1, v0
; CHECK-NEXT: addv.8b b0, v0 ; CHECK-NEXT: addv.8b b0, v0
; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh26, Lloh27
%cmp_result = icmp ne <8 x i2> %vec, zeroinitializer %cmp_result = icmp ne <8 x i2> %vec, zeroinitializer
%bitmask = bitcast <8 x i1> %cmp_result to i8 %bitmask = bitcast <8 x i1> %cmp_result to i8
Context not available.
} }
define i4 @convert_to_bitmask_float(<4 x float> %vec) { define i4 @convert_to_bitmask_float(<4 x float> %vec) {
; CHECK-LABEL: lCPI14_0: ; CHECK-LABEL: convert_to_bitmask_float:
; CHECK-NEXT: .long 1
; CHECK-NEXT: .long 2
; CHECK-NEXT: .long 4
; CHECK-NEXT: .long 8
; CHECK-LABEL: convert_to_bitmask_float
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: Lloh28: ; CHECK-NEXT: fcmgt.4s v1, v0, #0.0
; CHECK-NEXT: adrp x8, lCPI14_0@PAGE ; CHECK-NEXT: fcmlt.4s v0, v0, #0.0
; CHECK-NEXT: fcmgt.4s v1, v0, #0.0 ; CHECK-NEXT: Lloh28:
; CHECK-NEXT: fcmlt.4s v0, v0, #0.0 ; CHECK-NEXT: adrp x8, lCPI14_0@PAGE
; CHECK-NEXT: Lloh29: ; CHECK-NEXT: orr.16b v0, v0, v1
; CHECK-NEXT: ldr q2, [x8, lCPI14_0@PAGEOFF] ; CHECK-NEXT: Lloh29:
; CHECK-NEXT: orr.16b v0, v0, v1 ; CHECK-NEXT: ldr q1, [x8, lCPI14_0@PAGEOFF]
; CHECK-NEXT: and.16b v0, v0, v2 ; CHECK-NEXT: and.16b v0, v0, v1
; CHECK-NEXT: addv.4s s0, v0 ; CHECK-NEXT: addv.4s s0, v0
; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh28, Lloh29
%cmp_result = fcmp one <4 x float> %vec, zeroinitializer %cmp_result = fcmp one <4 x float> %vec, zeroinitializer
%bitmask = bitcast <4 x i1> %cmp_result to i4 %bitmask = bitcast <4 x i1> %cmp_result to i4
Context not available.
; Larger vector types don't map directly, but the can be split/truncated and then converted. ; Larger vector types don't map directly, but the can be split/truncated and then converted.
; After the comparison against 0, this is truncated to <8 x i16>, which is valid again. ; After the comparison against 0, this is truncated to <8 x i16>, which is valid again.
define i8 @convert_large_vector(<8 x i32> %vec) { define i8 @convert_large_vector(<8 x i32> %vec) {
; CHECK-LABEL: lCPI15_0:
; CHECK-NEXT: .short 1
; CHECK-NEXT: .short 2
; CHECK-NEXT: .short 4
; CHECK-NEXT: .short 8
; CHECK-NEXT: .short 16
; CHECK-NEXT: .short 32
; CHECK-NEXT: .short 64
; CHECK-NEXT: .short 128
; CHECK-LABEL: convert_large_vector: ; CHECK-LABEL: convert_large_vector:
; CHECK: Lloh30: ; CHECK: ; %bb.0:
; CHECK-NEXT: adrp x8, lCPI15_0@PAGE ; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: cmeq.4s v1, v1, #0 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: cmeq.4s v0, v0, #0 ; CHECK-NEXT: cmeq.4s v1, v1, #0
; CHECK-NEXT: uzp1.8h v0, v0, v1 ; CHECK-NEXT: cmeq.4s v0, v0, #0
; CHECK-NEXT: Lloh31: ; CHECK-NEXT: Lloh30:
; CHECK-NEXT: ldr q1, [x8, lCPI15_0@PAGEOFF] ; CHECK-NEXT: adrp x8, lCPI15_0@PAGE
; CHECK-NEXT: bic.16b v0, v1, v0 ; CHECK-NEXT: uzp1.8h v0, v0, v1
; CHECK-NEXT: addv.8h h0, v0 ; CHECK-NEXT: Lloh31:
; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: ldr q1, [x8, lCPI15_0@PAGEOFF]
; CHECK-NEXT: and w0, w8, #0xff ; CHECK-NEXT: bic.16b v0, v1, v0
; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: addv.8h h0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: and w0, w8, #0xff
; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh30, Lloh31
%cmp_result = icmp ne <8 x i32> %vec, zeroinitializer %cmp_result = icmp ne <8 x i32> %vec, zeroinitializer
%bitmask = bitcast <8 x i1> %cmp_result to i8 %bitmask = bitcast <8 x i1> %cmp_result to i8
Context not available.
} }
define i4 @convert_legalized_illegal_element_size(<4 x i22> %vec) { define i4 @convert_legalized_illegal_element_size(<4 x i22> %vec) {
; CHECK-LABEL: convert_legalized_illegal_element_size ; CHECK-LABEL: convert_legalized_illegal_element_size:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: movi.4s v1, #63, msl #16 ; CHECK-NEXT: movi.4s v1, #63, msl #16
; CHECK-NEXT: Lloh32: ; CHECK-NEXT: Lloh32:
; CHECK-NEXT: adrp x8, lCPI16_0@PAGE ; CHECK-NEXT: adrp x8, lCPI16_0@PAGE
; CHECK-NEXT: cmtst.4s v0, v0, v1 ; CHECK-NEXT: cmtst.4s v0, v0, v1
; CHECK-NEXT: Lloh33: ; CHECK-NEXT: Lloh33:
; CHECK-NEXT: ldr d1, [x8, lCPI16_0@PAGEOFF] ; CHECK-NEXT: ldr d1, [x8, lCPI16_0@PAGEOFF]
; CHECK-NEXT: xtn.4h v0, v0 ; CHECK-NEXT: xtn.4h v0, v0
; CHECK-NEXT: and.8b v0, v0, v1 ; CHECK-NEXT: and.8b v0, v0, v1
; CHECK-NEXT: addv.4h h0, v0 ; CHECK-NEXT: addv.4h h0, v0
; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh32, Lloh33
%cmp_result = icmp ne <4 x i22> %vec, zeroinitializer %cmp_result = icmp ne <4 x i22> %vec, zeroinitializer
%bitmask = bitcast <4 x i1> %cmp_result to i4 %bitmask = bitcast <4 x i1> %cmp_result to i4
Context not available.
; This may still be converted as a v8i8 after the vector concat (but not as v4iX). ; This may still be converted as a v8i8 after the vector concat (but not as v4iX).
define i8 @no_direct_convert_for_bad_concat(<4 x i32> %vec) { define i8 @no_direct_convert_for_bad_concat(<4 x i32> %vec) {
; CHECK-LABEL: no_direct_convert_for_bad_concat: ; CHECK-LABEL: no_direct_convert_for_bad_concat:
; CHECK: cmtst.4s v0, v0, v0 ; CHECK: ; %bb.0:
; CHECK-NOT: addv.4 ; CHECK-NEXT: cmtst.4s v0, v0, v0
; CHECK-NEXT: Lloh34:
; CHECK-NEXT: adrp x8, lCPI17_0@PAGE
; CHECK-NEXT: xtn.4h v0, v0
; CHECK-NEXT: umov.h w9, v0[0]
; CHECK-NEXT: mov.b v1[4], w9
; CHECK-NEXT: umov.h w9, v0[1]
; CHECK-NEXT: mov.b v1[5], w9
; CHECK-NEXT: umov.h w9, v0[2]
; CHECK-NEXT: mov.b v1[6], w9
; CHECK-NEXT: umov.h w9, v0[3]
; CHECK-NEXT: mov.b v1[7], w9
; CHECK-NEXT: shl.8b v0, v1, #7
; CHECK-NEXT: Lloh35:
; CHECK-NEXT: ldr d1, [x8, lCPI17_0@PAGEOFF]
; CHECK-NEXT: cmlt.8b v0, v0, #0
; CHECK-NEXT: and.8b v0, v0, v1
; CHECK-NEXT: addv.8b b0, v0
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh34, Lloh35
%cmp_result = icmp ne <4 x i32> %vec, zeroinitializer %cmp_result = icmp ne <4 x i32> %vec, zeroinitializer
%vector_pad = shufflevector <4 x i1> poison, <4 x i1> %cmp_result, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 4, i32 5, i32 6, i32 7> %vector_pad = shufflevector <4 x i1> poison, <4 x i1> %cmp_result, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 4, i32 5, i32 6, i32 7>
Context not available.
define <8 x i1> @no_convert_without_direct_bitcast(<8 x i16> %vec) { define <8 x i1> @no_convert_without_direct_bitcast(<8 x i16> %vec) {
; CHECK-LABEL: no_convert_without_direct_bitcast: ; CHECK-LABEL: no_convert_without_direct_bitcast:
; CHECK: cmtst.8h v0, v0, v0 ; CHECK: ; %bb.0:
; CHECK-NOT: addv.4s s0, v0 ; CHECK-NEXT: cmtst.8h v0, v0, v0
; CHECK-NEXT: xtn.8b v0, v0
; CHECK-NEXT: ret
%cmp_result = icmp ne <8 x i16> %vec, zeroinitializer %cmp_result = icmp ne <8 x i16> %vec, zeroinitializer
ret <8 x i1> %cmp_result ret <8 x i1> %cmp_result
} }
define i6 @no_combine_illegal_num_elements(<6 x i32> %vec) { define i6 @no_combine_illegal_num_elements(<6 x i32> %vec) {
; CHECK-LABEL: no_combine_illegal_num_elements ; CHECK-LABEL: no_combine_illegal_num_elements:
; CHECK-NOT: addv ; CHECK: ; %bb.0:
; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: fmov s1, w4
; CHECK-NEXT: mov.s v0[1], w1
; CHECK-NEXT: mov.s v1[1], w5
; CHECK-NEXT: mov.s v0[2], w2
; CHECK-NEXT: cmeq.4s v1, v1, #0
; CHECK-NEXT: mov.s v0[3], w3
; CHECK-NEXT: cmeq.4s v0, v0, #0
; CHECK-NEXT: uzp1.8h v0, v0, v1
; CHECK-NEXT: mvn.16b v0, v0
; CHECK-NEXT: xtn.8b v0, v0
; CHECK-NEXT: umov.b w8, v0[0]
; CHECK-NEXT: umov.b w9, v0[1]
; CHECK-NEXT: umov.b w10, v0[2]
; CHECK-NEXT: and w8, w8, #0x1
; CHECK-NEXT: bfi w8, w9, #1, #1
; CHECK-NEXT: umov.b w9, v0[3]
; CHECK-NEXT: bfi w8, w10, #2, #1
; CHECK-NEXT: umov.b w10, v0[4]
; CHECK-NEXT: bfi w8, w9, #3, #1
; CHECK-NEXT: umov.b w9, v0[5]
; CHECK-NEXT: bfi w8, w10, #4, #1
; CHECK-NEXT: orr w8, w8, w9, lsl #5
; CHECK-NEXT: and w0, w8, #0x3f
; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: ret
%cmp_result = icmp ne <6 x i32> %vec, zeroinitializer %cmp_result = icmp ne <6 x i32> %vec, zeroinitializer
%bitmask = bitcast <6 x i1> %cmp_result to i6 %bitmask = bitcast <6 x i1> %cmp_result to i6
Context not available.

llvm/test/CodeGen/AArch64/vec-combine-compare-truncate-store.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+neon -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+neon -verify-machineinstrs < %s | FileCheck %s
define void @store_16_elements(<16 x i8> %vec, ptr %out) { define void @store_16_elements(<16 x i8> %vec, ptr %out) {
; Bits used in mask ; Bits used in mask
dmgreenUnsubmitted
Done
ReplyInline Actions

These too.

dmgreen: These too.
; CHECK-LABEL: lCPI0_0 ; CHECK-LABEL: store_16_elements:
; CHECK-NEXT: .byte 1
; CHECK-NEXT: .byte 2
; CHECK-NEXT: .byte 4
; CHECK-NEXT: .byte 8
; CHECK-NEXT: .byte 16
; CHECK-NEXT: .byte 32
; CHECK-NEXT: .byte 64
; CHECK-NEXT: .byte 128
; CHECK-NEXT: .byte 1
; CHECK-NEXT: .byte 2
; CHECK-NEXT: .byte 4
; CHECK-NEXT: .byte 8
; CHECK-NEXT: .byte 16
; CHECK-NEXT: .byte 32
; CHECK-NEXT: .byte 64
; CHECK-NEXT: .byte 128
; Actual conversion
; CHECK-LABEL: store_16_elements
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: Lloh0: ; CHECK-NEXT: Lloh0:
; CHECK-NEXT: adrp x8, lCPI0_0@PAGE ; CHECK-NEXT: adrp x8, lCPI0_0@PAGE
; CHECK-NEXT: cmeq.16b v0, v0, #0 ; CHECK-NEXT: cmeq.16b v0, v0, #0
; CHECK-NEXT: Lloh1: ; CHECK-NEXT: Lloh1:
; CHECK-NEXT: ldr q1, [x8, lCPI0_0@PAGEOFF] ; CHECK-NEXT: ldr q1, [x8, lCPI0_0@PAGEOFF]
; CHECK-NEXT: bic.16b v0, v1, v0 ; CHECK-NEXT: bic.16b v0, v1, v0
; CHECK-NEXT: ext.16b v1, v0, v0, #8 ; CHECK-NEXT: ext.16b v1, v0, v0, #8
; CHECK-NEXT: zip1.16b v0, v0, v1 ; CHECK-NEXT: zip1.16b v0, v0, v1
; CHECK-NEXT: addv.8h h0, v0 ; CHECK-NEXT: addv.8h h0, v0
; CHECK-NEXT: str h0, [x0] ; CHECK-NEXT: str h0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh1
; Actual conversion
%cmp_result = icmp ne <16 x i8> %vec, zeroinitializer %cmp_result = icmp ne <16 x i8> %vec, zeroinitializer
store <16 x i1> %cmp_result, ptr %out store <16 x i1> %cmp_result, ptr %out
Context not available.
} }
define void @store_8_elements(<8 x i16> %vec, ptr %out) { define void @store_8_elements(<8 x i16> %vec, ptr %out) {
; CHECK-LABEL: lCPI1_0: ; CHECK-LABEL: store_8_elements:
; CHECK-NEXT: .short 1
; CHECK-NEXT: .short 2
; CHECK-NEXT: .short 4
; CHECK-NEXT: .short 8
; CHECK-NEXT: .short 16
; CHECK-NEXT: .short 32
; CHECK-NEXT: .short 64
; CHECK-NEXT: .short 128
; CHECK-LABEL: store_8_elements
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: Lloh2: ; CHECK-NEXT: Lloh2:
; CHECK-NEXT: adrp x8, lCPI1_0@PAGE ; CHECK-NEXT: adrp x8, lCPI1_0@PAGE
; CHECK-NEXT: cmeq.8h v0, v0, #0 ; CHECK-NEXT: cmeq.8h v0, v0, #0
; CHECK-NEXT: Lloh3: ; CHECK-NEXT: Lloh3:
; CHECK-NEXT: ldr q1, [x8, lCPI1_0@PAGEOFF] ; CHECK-NEXT: ldr q1, [x8, lCPI1_0@PAGEOFF]
; CHECK-NEXT: bic.16b v0, v1, v0 ; CHECK-NEXT: bic.16b v0, v1, v0
; CHECK-NEXT: addv.8h h0, v0 ; CHECK-NEXT: addv.8h h0, v0
; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: strb w8, [x0] ; CHECK-NEXT: strb w8, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh2, Lloh3
%cmp_result = icmp ne <8 x i16> %vec, zeroinitializer %cmp_result = icmp ne <8 x i16> %vec, zeroinitializer
store <8 x i1> %cmp_result, ptr %out store <8 x i1> %cmp_result, ptr %out
Context not available.
} }
define void @store_4_elements(<4 x i32> %vec, ptr %out) { define void @store_4_elements(<4 x i32> %vec, ptr %out) {
; CHECK-LABEL: lCPI2_0: ; CHECK-LABEL: store_4_elements:
; CHECK-NEXT: .long 1
; CHECK-NEXT: .long 2
; CHECK-NEXT: .long 4
; CHECK-NEXT: .long 8
; CHECK-LABEL: store_4_elements
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: Lloh4: ; CHECK-NEXT: Lloh4:
; CHECK-NEXT: adrp x8, lCPI2_0@PAGE ; CHECK-NEXT: adrp x8, lCPI2_0@PAGE
; CHECK-NEXT: cmeq.4s v0, v0, #0 ; CHECK-NEXT: cmeq.4s v0, v0, #0
; CHECK-NEXT: Lloh5: ; CHECK-NEXT: Lloh5:
; CHECK-NEXT: ldr q1, [x8, lCPI2_0@PAGEOFF] ; CHECK-NEXT: ldr q1, [x8, lCPI2_0@PAGEOFF]
; CHECK-NEXT: bic.16b v0, v1, v0 ; CHECK-NEXT: bic.16b v0, v1, v0
; CHECK-NEXT: addv.4s s0, v0 ; CHECK-NEXT: addv.4s s0, v0
; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: strb w8, [x0] ; CHECK-NEXT: strb w8, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh4, Lloh5
%cmp_result = icmp ne <4 x i32> %vec, zeroinitializer %cmp_result = icmp ne <4 x i32> %vec, zeroinitializer
store <4 x i1> %cmp_result, ptr %out store <4 x i1> %cmp_result, ptr %out
Context not available.
} }
define void @store_2_elements(<2 x i64> %vec, ptr %out) { define void @store_2_elements(<2 x i64> %vec, ptr %out) {
; CHECK-LABEL: lCPI3_0: ; CHECK-LABEL: store_2_elements:
; CHECK-NEXT: .quad 1
; CHECK-NEXT: .quad 2
; CHECK-LABEL: store_2_elements
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: Lloh6: ; CHECK-NEXT: Lloh6:
; CHECK-NEXT: adrp x8, lCPI3_0@PAGE ; CHECK-NEXT: adrp x8, lCPI3_0@PAGE
; CHECK-NEXT: cmeq.2d v0, v0, #0 ; CHECK-NEXT: cmeq.2d v0, v0, #0
; CHECK-NEXT: Lloh7: ; CHECK-NEXT: Lloh7:
; CHECK-NEXT: ldr q1, [x8, lCPI3_0@PAGEOFF] ; CHECK-NEXT: ldr q1, [x8, lCPI3_0@PAGEOFF]
; CHECK-NEXT: bic.16b v0, v1, v0 ; CHECK-NEXT: bic.16b v0, v1, v0
; CHECK-NEXT: addp.2d d0, v0 ; CHECK-NEXT: addp.2d d0, v0
; CHECK-NEXT: fmov x8, d0 ; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: strb w8, [x0] ; CHECK-NEXT: strb w8, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh6, Lloh7
%cmp_result = icmp ne <2 x i64> %vec, zeroinitializer %cmp_result = icmp ne <2 x i64> %vec, zeroinitializer
store <2 x i1> %cmp_result, ptr %out store <2 x i1> %cmp_result, ptr %out
Context not available.
} }
define void @add_trunc_compare_before_store(<4 x i32> %vec, ptr %out) { define void @add_trunc_compare_before_store(<4 x i32> %vec, ptr %out) {
; CHECK-LABEL: lCPI4_0: ; CHECK-LABEL: add_trunc_compare_before_store:
; CHECK-NEXT: .long 1
; CHECK-NEXT: .long 2
; CHECK-NEXT: .long 4
; CHECK-NEXT: .long 8
; CHECK-LABEL: add_trunc_compare_before_store
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: shl.4s v0, v0, #31
; CHECK-NEXT: Lloh8: ; CHECK-NEXT: Lloh8:
; CHECK-NEXT: adrp x8, lCPI4_0@PAGE ; CHECK-NEXT: adrp x8, lCPI4_0@PAGE
; CHECK-NEXT: shl.4s v0, v0, #31
; CHECK-NEXT: cmlt.4s v0, v0, #0
; CHECK-NEXT: Lloh9: ; CHECK-NEXT: Lloh9:
; CHECK-NEXT: ldr q1, [x8, lCPI4_0@PAGEOFF] ; CHECK-NEXT: ldr q1, [x8, lCPI4_0@PAGEOFF]
; CHECK-NEXT: and.16b v0, v0, v1 ; CHECK-NEXT: cmlt.4s v0, v0, #0
; CHECK-NEXT: addv.4s s0, v0 ; CHECK-NEXT: and.16b v0, v0, v1
; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: addv.4s s0, v0
; CHECK-NEXT: strb w8, [x0] ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: ret ; CHECK-NEXT: strb w8, [x0]
; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh8, Lloh9
%trunc = trunc <4 x i32> %vec to <4 x i1> %trunc = trunc <4 x i32> %vec to <4 x i1>
store <4 x i1> %trunc, ptr %out store <4 x i1> %trunc, ptr %out
Context not available.
} }
define void @add_trunc_mask_unknown_vector_type(<4 x i1> %vec, ptr %out) { define void @add_trunc_mask_unknown_vector_type(<4 x i1> %vec, ptr %out) {
; CHECK-LABEL: lCPI5_0: ; CHECK-LABEL: add_trunc_mask_unknown_vector_type:
; CHECK: .short 1
; CHECK: .short 2
; CHECK: .short 4
; CHECK: .short 8
; CHECK-LABEL: add_trunc_mask_unknown_vector_type
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: Lloh10: ; CHECK-NEXT: shl.4h v0, v0, #15
; CHECK-NEXT: adrp x8, lCPI5_0@PAGE ; CHECK-NEXT: Lloh10:
; CHECK-NEXT: shl.4h v0, v0, #15 ; CHECK-NEXT: adrp x8, lCPI5_0@PAGE
; CHECK-NEXT: cmlt.4h v0, v0, #0 ; CHECK-NEXT: Lloh11:
; CHECK-NEXT: Lloh11: ; CHECK-NEXT: ldr d1, [x8, lCPI5_0@PAGEOFF]
; CHECK-NEXT: ldr d1, [x8, lCPI5_0@PAGEOFF] ; CHECK-NEXT: cmlt.4h v0, v0, #0
; CHECK-NEXT: and.8b v0, v0, v1 ; CHECK-NEXT: and.8b v0, v0, v1
; CHECK-NEXT: addv.4h h0, v0 ; CHECK-NEXT: addv.4h h0, v0
; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: strb w8, [x0] ; CHECK-NEXT: strb w8, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh10, Lloh11
store <4 x i1> %vec, ptr %out store <4 x i1> %vec, ptr %out
ret void ret void
} }
define void @store_8_elements_64_bit_vector(<8 x i8> %vec, ptr %out) { define void @store_8_elements_64_bit_vector(<8 x i8> %vec, ptr %out) {
; CHECK-LABEL: lCPI6_0: ; CHECK-LABEL: store_8_elements_64_bit_vector:
; CHECK-NEXT: .byte 1
; CHECK-NEXT: .byte 2
; CHECK-NEXT: .byte 4
; CHECK-NEXT: .byte 8
; CHECK-NEXT: .byte 16
; CHECK-NEXT: .byte 32
; CHECK-NEXT: .byte 64
; CHECK-NEXT: .byte 128
; CHECK-LABEL: store_8_elements_64_bit_vector
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: Lloh12: ; CHECK-NEXT: Lloh12:
; CHECK-NEXT: adrp x8, lCPI6_0@PAGE ; CHECK-NEXT: adrp x8, lCPI6_0@PAGE
; CHECK-NEXT: cmeq.8b v0, v0, #0 ; CHECK-NEXT: cmeq.8b v0, v0, #0
; CHECK-NEXT: Lloh13: ; CHECK-NEXT: Lloh13:
; CHECK-NEXT: ldr d1, [x8, lCPI6_0@PAGEOFF] ; CHECK-NEXT: ldr d1, [x8, lCPI6_0@PAGEOFF]
; CHECK-NEXT: bic.8b v0, v1, v0 ; CHECK-NEXT: bic.8b v0, v1, v0
; CHECK-NEXT: addv.8b b0, v0 ; CHECK-NEXT: addv.8b b0, v0
; CHECK-NEXT: st1.b { v0 }[0], [x0] ; CHECK-NEXT: st1.b { v0 }[0], [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh12, Lloh13
%cmp_result = icmp ne <8 x i8> %vec, zeroinitializer %cmp_result = icmp ne <8 x i8> %vec, zeroinitializer
store <8 x i1> %cmp_result, ptr %out store <8 x i1> %cmp_result, ptr %out
Context not available.
} }
define void @store_4_elements_64_bit_vector(<4 x i16> %vec, ptr %out) { define void @store_4_elements_64_bit_vector(<4 x i16> %vec, ptr %out) {
; CHECK-LABEL: lCPI7_0: ; CHECK-LABEL: store_4_elements_64_bit_vector:
; CHECK-NEXT: .short 1
; CHECK-NEXT: .short 2
; CHECK-NEXT: .short 4
; CHECK-NEXT: .short 8
; CHECK-LABEL: store_4_elements_64_bit_vector
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: Lloh14: ; CHECK-NEXT: Lloh14:
; CHECK-NEXT: adrp x8, lCPI7_0@PAGE ; CHECK-NEXT: adrp x8, lCPI7_0@PAGE
; CHECK-NEXT: cmeq.4h v0, v0, #0 ; CHECK-NEXT: cmeq.4h v0, v0, #0
; CHECK-NEXT: Lloh15: ; CHECK-NEXT: Lloh15:
; CHECK-NEXT: ldr d1, [x8, lCPI7_0@PAGEOFF] ; CHECK-NEXT: ldr d1, [x8, lCPI7_0@PAGEOFF]
; CHECK-NEXT: bic.8b v0, v1, v0 ; CHECK-NEXT: bic.8b v0, v1, v0
; CHECK-NEXT: addv.4h h0, v0 ; CHECK-NEXT: addv.4h h0, v0
; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: strb w8, [x0] ; CHECK-NEXT: strb w8, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh14, Lloh15
%cmp_result = icmp ne <4 x i16> %vec, zeroinitializer %cmp_result = icmp ne <4 x i16> %vec, zeroinitializer
store <4 x i1> %cmp_result, ptr %out store <4 x i1> %cmp_result, ptr %out
Context not available.
} }
define void @store_2_elements_64_bit_vector(<2 x i32> %vec, ptr %out) { define void @store_2_elements_64_bit_vector(<2 x i32> %vec, ptr %out) {
; CHECK-LABEL: lCPI8_0: ; CHECK-LABEL: store_2_elements_64_bit_vector:
; CHECK-NEXT: .long 1
; CHECK-NEXT: .long 2
; CHECK-LABEL: store_2_elements_64_bit_vector
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: Lloh16: ; CHECK-NEXT: Lloh16:
; CHECK-NEXT: adrp x8, lCPI8_0@PAGE ; CHECK-NEXT: adrp x8, lCPI8_0@PAGE
; CHECK-NEXT: cmeq.2s v0, v0, #0 ; CHECK-NEXT: cmeq.2s v0, v0, #0
; CHECK-NEXT: Lloh17: ; CHECK-NEXT: Lloh17:
; CHECK-NEXT: ldr d1, [x8, lCPI8_0@PAGEOFF] ; CHECK-NEXT: ldr d1, [x8, lCPI8_0@PAGEOFF]
; CHECK-NEXT: bic.8b v0, v1, v0 ; CHECK-NEXT: bic.8b v0, v1, v0
; CHECK-NEXT: addp.2s v0, v0, v0 ; CHECK-NEXT: addp.2s v0, v0, v0
; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: strb w8, [x0] ; CHECK-NEXT: strb w8, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh16, Lloh17
%cmp_result = icmp ne <2 x i32> %vec, zeroinitializer %cmp_result = icmp ne <2 x i32> %vec, zeroinitializer
store <2 x i1> %cmp_result, ptr %out store <2 x i1> %cmp_result, ptr %out
Context not available.
} }
define void @no_combine_without_truncate(<16 x i8> %vec, ptr %out) { define void @no_combine_without_truncate(<16 x i8> %vec, ptr %out) {
; CHECK-LABEL: no_combine_without_truncate ; CHECK-LABEL: no_combine_without_truncate:
; CHECK: cmtst.16b v0, v0, v0 ; CHECK: ; %bb.0:
; CHECK-NOT: addv.8b b0, v0 ; CHECK-NEXT: cmtst.16b v0, v0, v0
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
%cmp_result = icmp ne <16 x i8> %vec, zeroinitializer %cmp_result = icmp ne <16 x i8> %vec, zeroinitializer
%extended_result = sext <16 x i1> %cmp_result to <16 x i8> %extended_result = sext <16 x i1> %cmp_result to <16 x i8>
Context not available.
} }
define void @no_combine_for_non_bool_truncate(<4 x i32> %vec, ptr %out) { define void @no_combine_for_non_bool_truncate(<4 x i32> %vec, ptr %out) {
; CHECK-LABEL: no_combine_for_non_bool_truncate ; CHECK-LABEL: no_combine_for_non_bool_truncate:
; CHECK: xtn.4h v0, v0 ; CHECK: ; %bb.0:
; CHECK-NOT: addv.4s s0, v0 ; CHECK-NEXT: xtn.4h v0, v0
; CHECK-NEXT: xtn.8b v0, v0
; CHECK-NEXT: str s0, [x0]
; CHECK-NEXT: ret
%trunc = trunc <4 x i32> %vec to <4 x i8> %trunc = trunc <4 x i32> %vec to <4 x i8>
store <4 x i8> %trunc, ptr %out store <4 x i8> %trunc, ptr %out
Context not available.
} }
define void @no_combine_for_build_vector(i1 %a, i1 %b, i1 %c, i1 %d, ptr %out) { define void @no_combine_for_build_vector(i1 %a, i1 %b, i1 %c, i1 %d, ptr %out) {
; CHECK-LABEL: no_combine_for_build_vector ; CHECK-LABEL: no_combine_for_build_vector:
; CHECK-NOT: addv ; CHECK: ; %bb.0:
; CHECK-NEXT: orr w8, w0, w1, lsl #1
; CHECK-NEXT: orr w8, w8, w2, lsl #2
; CHECK-NEXT: orr w8, w8, w3, lsl #3
; CHECK-NEXT: strb w8, [x4]
; CHECK-NEXT: ret
%1 = insertelement <4 x i1> undef, i1 %a, i64 0 %1 = insertelement <4 x i1> undef, i1 %a, i64 0
%2 = insertelement <4 x i1> %1, i1 %b, i64 1 %2 = insertelement <4 x i1> %1, i1 %b, i64 1
Context not available.

llvm/test/CodeGen/AArch64/vec-libcalls.ll

llvm/test/CodeGen/AArch64/vec_cttz.ll

llvm/test/CodeGen/AArch64/vec_uaddo.ll

llvm/test/CodeGen/AArch64/vec_umulo.ll

llvm/test/CodeGen/AArch64/vecreduce-add.ll

llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll

llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll

llvm/test/CodeGen/AArch64/vecreduce-fadd.ll

llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll

llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll

llvm/test/CodeGen/AArch64/vecreduce-fmaximum.ll

llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll

llvm/test/CodeGen/AArch64/vecreduce-fminimum.ll

llvm/test/CodeGen/AArch64/vector-fcopysign.ll

llvm/test/CodeGen/AArch64/vector-fcvt.ll

llvm/test/CodeGen/AArch64/vector-gep.ll

llvm/test/CodeGen/AArch64/vldn_shuffle.ll

llvm/test/CodeGen/AArch64/vselect-constants.ll

llvm/test/CodeGen/AArch64/vselect-ext.ll

llvm/test/CodeGen/AArch64/wide-scalar-shift-by-byte-multiple-legalization.ll

llvm/test/CodeGen/AArch64/wide-scalar-shift-legalization.ll

llvm/test/CodeGen/AArch64/win64_vararg.ll

llvm/test/CodeGen/AArch64/win64_vararg2.ll

llvm/test/CodeGen/AArch64/win64_vararg_float.ll

llvm/test/CodeGen/AArch64/win64_vararg_float_cc.ll

llvm/test/CodeGen/AArch64/wineh-bti.ll

Context not available.
; CHECK: .LBB0_2: ; CHECK: .LBB0_2:
; CHECK-NEXT: hint #36 ; CHECK-NEXT: hint #36
; CHECK-NEXT: mov w0, #1 ; CHECK: mov w0, #1
; CHECK: .LBB0_3: ; CHECK: .LBB0_3:
; CHECK-NEXT: hint #36 ; CHECK-NEXT: hint #36
Context not available.

llvm/test/CodeGen/AArch64/zero-call-used-regs.ll

llvm/test/CodeGen/AArch64/zext-to-tbl.ll

Context not available.
; CHECK-LABEL: zext_v16i8_to_v16i32_in_loop: ; CHECK-LABEL: zext_v16i8_to_v16i32_in_loop:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: Lloh0: ; CHECK-NEXT: Lloh0:
; CHECK-NEXT: adrp x9, lCPI0_0@PAGE ; CHECK-NEXT: adrp x8, lCPI0_0@PAGE
; CHECK-NEXT: Lloh1: ; CHECK-NEXT: Lloh1:
; CHECK-NEXT: adrp x10, lCPI0_1@PAGE ; CHECK-NEXT: adrp x9, lCPI0_1@PAGE
; CHECK-NEXT: Lloh2: ; CHECK-NEXT: Lloh2:
; CHECK-NEXT: adrp x11, lCPI0_2@PAGE ; CHECK-NEXT: adrp x10, lCPI0_2@PAGE
; CHECK-NEXT: Lloh3: ; CHECK-NEXT: Lloh3:
; CHECK-NEXT: adrp x12, lCPI0_3@PAGE ; CHECK-NEXT: ldr q0, [x8, lCPI0_0@PAGEOFF]
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: Lloh4: ; CHECK-NEXT: Lloh4:
; CHECK-NEXT: ldr q0, [x9, lCPI0_0@PAGEOFF] ; CHECK-NEXT: adrp x8, lCPI0_3@PAGE
; CHECK-NEXT: Lloh5: ; CHECK-NEXT: Lloh5:
; CHECK-NEXT: ldr q1, [x10, lCPI0_1@PAGEOFF] ; CHECK-NEXT: ldr q1, [x9, lCPI0_1@PAGEOFF]
; CHECK-NEXT: Lloh6: ; CHECK-NEXT: Lloh6:
; CHECK-NEXT: ldr q2, [x11, lCPI0_2@PAGEOFF] ; CHECK-NEXT: ldr q2, [x10, lCPI0_2@PAGEOFF]
; CHECK-NEXT: Lloh7: ; CHECK-NEXT: Lloh7:
; CHECK-NEXT: ldr q3, [x12, lCPI0_3@PAGEOFF] ; CHECK-NEXT: ldr q3, [x8, lCPI0_3@PAGEOFF]
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: LBB0_1: ; %loop ; CHECK-NEXT: LBB0_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr q4, [x0, x8] ; CHECK-NEXT: ldr q4, [x0, x8]
Context not available.
; CHECK-NEXT: b.ne LBB0_1 ; CHECK-NEXT: b.ne LBB0_1
; CHECK-NEXT: ; %bb.2: ; %exit ; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh3, Lloh7 ; CHECK-NEXT: .loh AdrpLdr Lloh4, Lloh7
; CHECK-NEXT: .loh AdrpLdr Lloh2, Lloh6 ; CHECK-NEXT: .loh AdrpLdr Lloh2, Lloh6
; CHECK-NEXT: .loh AdrpLdr Lloh1, Lloh5 ; CHECK-NEXT: .loh AdrpLdr Lloh1, Lloh5
; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh4 ; CHECK-NEXT: .loh AdrpAdrp Lloh0, Lloh4
; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh3
; ;
; CHECK-BE-LABEL: zext_v16i8_to_v16i32_in_loop: ; CHECK-BE-LABEL: zext_v16i8_to_v16i32_in_loop:
; CHECK-BE: // %bb.0: // %entry ; CHECK-BE: // %bb.0: // %entry
Context not available.
; CHECK-BE-NEXT: .LBB0_1: // %loop ; CHECK-BE-NEXT: .LBB0_1: // %loop
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: add x9, x0, x8 ; CHECK-BE-NEXT: add x9, x0, x8
; CHECK-BE-NEXT: add x10, x1, #32
; CHECK-BE-NEXT: add x8, x8, #16 ; CHECK-BE-NEXT: add x8, x8, #16
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ld1 { v4.16b }, [x9] ; CHECK-BE-NEXT: ld1 { v4.16b }, [x9]
; CHECK-BE-NEXT: add x9, x1, #48 ; CHECK-BE-NEXT: add x9, x1, #48
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: tbl v5.16b, { v4.16b }, v3.16b ; CHECK-BE-NEXT: tbl v5.16b, { v4.16b }, v3.16b
; CHECK-BE-NEXT: tbl v6.16b, { v4.16b }, v0.16b ; CHECK-BE-NEXT: tbl v6.16b, { v4.16b }, v2.16b
; CHECK-BE-NEXT: tbl v7.16b, { v4.16b }, v2.16b ; CHECK-BE-NEXT: tbl v7.16b, { v4.16b }, v1.16b
; CHECK-BE-NEXT: tbl v4.16b, { v4.16b }, v1.16b ; CHECK-BE-NEXT: tbl v4.16b, { v4.16b }, v0.16b
; CHECK-BE-NEXT: st1 { v5.16b }, [x9] ; CHECK-BE-NEXT: st1 { v5.16b }, [x9]
; CHECK-BE-NEXT: add x9, x1, #32
; CHECK-BE-NEXT: st1 { v6.16b }, [x9]
; CHECK-BE-NEXT: add x9, x1, #16 ; CHECK-BE-NEXT: add x9, x1, #16
; CHECK-BE-NEXT: st1 { v6.16b }, [x1] ; CHECK-BE-NEXT: st1 { v4.16b }, [x1]
; CHECK-BE-NEXT: add x1, x1, #64 ; CHECK-BE-NEXT: add x1, x1, #64
; CHECK-BE-NEXT: st1 { v7.16b }, [x10] ; CHECK-BE-NEXT: st1 { v7.16b }, [x9]
; CHECK-BE-NEXT: st1 { v4.16b }, [x9]
; CHECK-BE-NEXT: b.ne .LBB0_1 ; CHECK-BE-NEXT: b.ne .LBB0_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
Context not available.
; CHECK-BE-NEXT: // in Loop: Header=BB1_2 Depth=1 ; CHECK-BE-NEXT: // in Loop: Header=BB1_2 Depth=1
; CHECK-BE-NEXT: add x9, x0, x8 ; CHECK-BE-NEXT: add x9, x0, x8
; CHECK-BE-NEXT: add x10, x1, #32 ; CHECK-BE-NEXT: add x10, x1, #32
; CHECK-BE-NEXT: add x11, x1, #16
; CHECK-BE-NEXT: ld1 { v0.16b }, [x9] ; CHECK-BE-NEXT: ld1 { v0.16b }, [x9]
; CHECK-BE-NEXT: add x9, x1, #48 ; CHECK-BE-NEXT: add x9, x1, #48
; CHECK-BE-NEXT: ushll2 v1.8h, v0.16b, #0 ; CHECK-BE-NEXT: ushll2 v1.8h, v0.16b, #0
Context not available.
; CHECK-BE-NEXT: ushll2 v2.4s, v1.8h, #0 ; CHECK-BE-NEXT: ushll2 v2.4s, v1.8h, #0
; CHECK-BE-NEXT: ushll v1.4s, v1.4h, #0 ; CHECK-BE-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-BE-NEXT: ushll2 v3.4s, v0.8h, #0 ; CHECK-BE-NEXT: ushll2 v3.4s, v0.8h, #0
; CHECK-BE-NEXT: st1 { v2.4s }, [x9]
; CHECK-BE-NEXT: ushll v0.4s, v0.4h, #0 ; CHECK-BE-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-BE-NEXT: st1 { v2.4s }, [x9]
; CHECK-BE-NEXT: add x9, x1, #16
; CHECK-BE-NEXT: st1 { v1.4s }, [x10] ; CHECK-BE-NEXT: st1 { v1.4s }, [x10]
; CHECK-BE-NEXT: st1 { v3.4s }, [x11] ; CHECK-BE-NEXT: st1 { v3.4s }, [x9]
; CHECK-BE-NEXT: st1 { v0.4s }, [x1] ; CHECK-BE-NEXT: st1 { v0.4s }, [x1]
; CHECK-BE-NEXT: b .LBB1_1 ; CHECK-BE-NEXT: b .LBB1_1
; CHECK-BE-NEXT: .LBB1_4: // %exit ; CHECK-BE-NEXT: .LBB1_4: // %exit
Context not available.
; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-BE-NEXT: ushll2 v2.4s, v1.8h, #0 ; CHECK-BE-NEXT: ushll2 v2.4s, v1.8h, #0
; CHECK-BE-NEXT: ushll v1.4s, v1.4h, #0 ; CHECK-BE-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-BE-NEXT: ushll2 v3.4s, v0.8h, #0
; CHECK-BE-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-BE-NEXT: st1 { v2.4s }, [x8] ; CHECK-BE-NEXT: st1 { v2.4s }, [x8]
; CHECK-BE-NEXT: add x8, x1, #32 ; CHECK-BE-NEXT: add x8, x1, #32
; CHECK-BE-NEXT: st1 { v1.4s }, [x8] ; CHECK-BE-NEXT: st1 { v1.4s }, [x8]
; CHECK-BE-NEXT: add x8, x1, #16 ; CHECK-BE-NEXT: add x8, x1, #16
; CHECK-BE-NEXT: ushll2 v1.4s, v0.8h, #0 ; CHECK-BE-NEXT: st1 { v3.4s }, [x8]
; CHECK-BE-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-BE-NEXT: st1 { v1.4s }, [x8]
; CHECK-BE-NEXT: st1 { v0.4s }, [x1] ; CHECK-BE-NEXT: st1 { v0.4s }, [x1]
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
entry: entry:
Context not available.
; CHECK-BE-NEXT: .LBB3_1: // %loop ; CHECK-BE-NEXT: .LBB3_1: // %loop
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: add x9, x0, x8 ; CHECK-BE-NEXT: add x9, x0, x8
; CHECK-BE-NEXT: add x10, x1, #32
; CHECK-BE-NEXT: add x8, x8, #16 ; CHECK-BE-NEXT: add x8, x8, #16
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ld1 { v0.16b }, [x9] ; CHECK-BE-NEXT: ld1 { v0.16b }, [x9]
; CHECK-BE-NEXT: add x9, x1, #48 ; CHECK-BE-NEXT: add x9, x1, #48
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ushll2 v1.8h, v0.16b, #0 ; CHECK-BE-NEXT: ushll2 v1.8h, v0.16b, #0
; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-BE-NEXT: ushll2 v2.4s, v1.8h, #0 ; CHECK-BE-NEXT: ushll2 v2.4s, v1.8h, #0
; CHECK-BE-NEXT: ushll v1.4s, v1.4h, #0 ; CHECK-BE-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-BE-NEXT: ushll2 v3.4s, v0.8h, #0
; CHECK-BE-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-BE-NEXT: st1 { v2.4s }, [x9] ; CHECK-BE-NEXT: st1 { v2.4s }, [x9]
; CHECK-BE-NEXT: add x9, x1, #32
; CHECK-BE-NEXT: st1 { v1.4s }, [x9]
; CHECK-BE-NEXT: add x9, x1, #16 ; CHECK-BE-NEXT: add x9, x1, #16
; CHECK-BE-NEXT: ushll v2.4s, v0.4h, #0 ; CHECK-BE-NEXT: st1 { v0.4s }, [x1]
; CHECK-BE-NEXT: st1 { v1.4s }, [x10]
; CHECK-BE-NEXT: ushll2 v0.4s, v0.8h, #0
; CHECK-BE-NEXT: st1 { v2.4s }, [x1]
; CHECK-BE-NEXT: add x1, x1, #64 ; CHECK-BE-NEXT: add x1, x1, #64
; CHECK-BE-NEXT: st1 { v0.4s }, [x9] ; CHECK-BE-NEXT: st1 { v3.4s }, [x9]
; CHECK-BE-NEXT: b.ne .LBB3_1 ; CHECK-BE-NEXT: b.ne .LBB3_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
Context not available.
; CHECK-BE-NEXT: .LBB4_1: // %loop ; CHECK-BE-NEXT: .LBB4_1: // %loop
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: add x9, x0, x8 ; CHECK-BE-NEXT: add x9, x0, x8
; CHECK-BE-NEXT: add x10, x1, #32
; CHECK-BE-NEXT: add x8, x8, #16 ; CHECK-BE-NEXT: add x8, x8, #16
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ld1 { v0.16b }, [x9] ; CHECK-BE-NEXT: ld1 { v0.16b }, [x9]
; CHECK-BE-NEXT: add x9, x1, #48 ; CHECK-BE-NEXT: add x9, x1, #48
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ushll2 v1.8h, v0.16b, #0 ; CHECK-BE-NEXT: ushll2 v1.8h, v0.16b, #0
; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-BE-NEXT: ushll2 v2.4s, v1.8h, #0 ; CHECK-BE-NEXT: ushll2 v2.4s, v1.8h, #0
; CHECK-BE-NEXT: ushll v1.4s, v1.4h, #0 ; CHECK-BE-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-BE-NEXT: ushll2 v3.4s, v0.8h, #0
; CHECK-BE-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-BE-NEXT: st1 { v2.4s }, [x9] ; CHECK-BE-NEXT: st1 { v2.4s }, [x9]
; CHECK-BE-NEXT: add x9, x1, #32
; CHECK-BE-NEXT: st1 { v1.4s }, [x9]
; CHECK-BE-NEXT: add x9, x1, #16 ; CHECK-BE-NEXT: add x9, x1, #16
; CHECK-BE-NEXT: ushll v2.4s, v0.4h, #0 ; CHECK-BE-NEXT: st1 { v0.4s }, [x1]
; CHECK-BE-NEXT: st1 { v1.4s }, [x10]
; CHECK-BE-NEXT: ushll2 v0.4s, v0.8h, #0
; CHECK-BE-NEXT: st1 { v2.4s }, [x1]
; CHECK-BE-NEXT: add x1, x1, #64 ; CHECK-BE-NEXT: add x1, x1, #64
; CHECK-BE-NEXT: st1 { v0.4s }, [x9] ; CHECK-BE-NEXT: st1 { v3.4s }, [x9]
; CHECK-BE-NEXT: b.ne .LBB4_1 ; CHECK-BE-NEXT: b.ne .LBB4_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
Context not available.
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: add x9, x0, x8 ; CHECK-BE-NEXT: add x9, x0, x8
; CHECK-BE-NEXT: add x8, x8, #16 ; CHECK-BE-NEXT: add x8, x8, #16
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ld1 { v0.16b }, [x9] ; CHECK-BE-NEXT: ld1 { v0.16b }, [x9]
; CHECK-BE-NEXT: add x9, x1, #16 ; CHECK-BE-NEXT: add x9, x1, #16
; CHECK-BE-NEXT: ushll v1.8h, v0.8b, #0 ; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ushll2 v0.8h, v0.16b, #0 ; CHECK-BE-NEXT: ushll2 v1.8h, v0.16b, #0
; CHECK-BE-NEXT: st1 { v1.8h }, [x1] ; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-BE-NEXT: st1 { v0.8h }, [x1]
; CHECK-BE-NEXT: add x1, x1, #32 ; CHECK-BE-NEXT: add x1, x1, #32
; CHECK-BE-NEXT: st1 { v0.8h }, [x9] ; CHECK-BE-NEXT: st1 { v1.8h }, [x9]
; CHECK-BE-NEXT: b.ne .LBB5_1 ; CHECK-BE-NEXT: b.ne .LBB5_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
Context not available.
; CHECK-LABEL: zext_v8i8_to_v8i32_in_loop: ; CHECK-LABEL: zext_v8i8_to_v8i32_in_loop:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: Lloh8: ; CHECK-NEXT: Lloh8:
; CHECK-NEXT: adrp x9, lCPI6_0@PAGE ; CHECK-NEXT: adrp x8, lCPI6_0@PAGE
; CHECK-NEXT: Lloh9: ; CHECK-NEXT: Lloh9:
; CHECK-NEXT: adrp x10, lCPI6_1@PAGE ; CHECK-NEXT: adrp x9, lCPI6_1@PAGE
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: Lloh10: ; CHECK-NEXT: Lloh10:
; CHECK-NEXT: ldr q0, [x9, lCPI6_0@PAGEOFF] ; CHECK-NEXT: ldr q0, [x8, lCPI6_0@PAGEOFF]
; CHECK-NEXT: Lloh11: ; CHECK-NEXT: Lloh11:
; CHECK-NEXT: ldr q1, [x10, lCPI6_1@PAGEOFF] ; CHECK-NEXT: ldr q1, [x9, lCPI6_1@PAGEOFF]
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: LBB6_1: ; %loop ; CHECK-NEXT: LBB6_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr d2, [x0, x8] ; CHECK-NEXT: ldr d2, [x0, x8]
Context not available.
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: add x9, x0, x8 ; CHECK-BE-NEXT: add x9, x0, x8
; CHECK-BE-NEXT: add x8, x8, #16 ; CHECK-BE-NEXT: add x8, x8, #16
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ld1 { v2.8b }, [x9] ; CHECK-BE-NEXT: ld1 { v2.8b }, [x9]
; CHECK-BE-NEXT: add x9, x1, #16 ; CHECK-BE-NEXT: add x9, x1, #16
; CHECK-BE-NEXT: tbl v3.16b, { v2.16b }, v0.16b ; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: tbl v2.16b, { v2.16b }, v1.16b ; CHECK-BE-NEXT: tbl v3.16b, { v2.16b }, v1.16b
; CHECK-BE-NEXT: st1 { v3.16b }, [x1] ; CHECK-BE-NEXT: tbl v2.16b, { v2.16b }, v0.16b
; CHECK-BE-NEXT: st1 { v2.16b }, [x1]
; CHECK-BE-NEXT: add x1, x1, #64 ; CHECK-BE-NEXT: add x1, x1, #64
; CHECK-BE-NEXT: st1 { v2.16b }, [x9] ; CHECK-BE-NEXT: st1 { v3.16b }, [x9]
; CHECK-BE-NEXT: b.ne .LBB6_1 ; CHECK-BE-NEXT: b.ne .LBB6_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
Context not available.
; CHECK-NEXT: ldr q0, [x0, x8] ; CHECK-NEXT: ldr q0, [x0, x8]
; CHECK-NEXT: add x8, x8, #16 ; CHECK-NEXT: add x8, x8, #16
; CHECK-NEXT: cmp x8, #128 ; CHECK-NEXT: cmp x8, #128
; CHECK-NEXT: ushll.8h v1, v0, #0 ; CHECK-NEXT: ushll2.8h v1, v0, #0
; CHECK-NEXT: ushll2.8h v0, v0, #0 ; CHECK-NEXT: ushll.8h v0, v0, #0
; CHECK-NEXT: ushll2.4s v2, v1, #0 ; CHECK-NEXT: ushll2.4s v2, v1, #0
; CHECK-NEXT: ushll2.4s v3, v0, #0 ; CHECK-NEXT: ushll.4s v1, v1, #0
; CHECK-NEXT: ushll2.4s v4, v0, #0
; CHECK-NEXT: ushll.4s v0, v0, #0 ; CHECK-NEXT: ushll.4s v0, v0, #0
; CHECK-NEXT: ushll2.2d v4, v3, #0
; CHECK-NEXT: ushll2.2d v5, v0, #0
; CHECK-NEXT: ushll.2d v0, v0, #0
; CHECK-NEXT: ushll.2d v3, v3, #0
; CHECK-NEXT: stp q0, q5, [x1, #64]
; CHECK-NEXT: ushll.4s v0, v1, #0
; CHECK-NEXT: stp q3, q4, [x1, #96]
; CHECK-NEXT: ushll2.2d v3, v2, #0 ; CHECK-NEXT: ushll2.2d v3, v2, #0
; CHECK-NEXT: ushll.2d v2, v2, #0 ; CHECK-NEXT: ushll.2d v2, v2, #0
; CHECK-NEXT: ushll2.2d v1, v0, #0 ; CHECK-NEXT: ushll2.2d v5, v1, #0
; CHECK-NEXT: ushll.2d v1, v1, #0
; CHECK-NEXT: stp q2, q3, [x1, #96]
; CHECK-NEXT: ushll2.2d v3, v4, #0
; CHECK-NEXT: ushll.2d v2, v4, #0
; CHECK-NEXT: ushll2.2d v4, v0, #0
; CHECK-NEXT: ushll.2d v0, v0, #0 ; CHECK-NEXT: ushll.2d v0, v0, #0
; CHECK-NEXT: stp q1, q5, [x1, #64]
; CHECK-NEXT: stp q2, q3, [x1, #32] ; CHECK-NEXT: stp q2, q3, [x1, #32]
; CHECK-NEXT: stp q0, q1, [x1], #128 ; CHECK-NEXT: stp q0, q4, [x1], #128
; CHECK-NEXT: b.ne LBB7_1 ; CHECK-NEXT: b.ne LBB7_1
; CHECK-NEXT: ; %bb.2: ; %exit ; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
Context not available.
; CHECK-BE-NEXT: .LBB7_1: // %loop ; CHECK-BE-NEXT: .LBB7_1: // %loop
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: add x9, x0, x8 ; CHECK-BE-NEXT: add x9, x0, x8
; CHECK-BE-NEXT: add x10, x1, #96
; CHECK-BE-NEXT: add x8, x8, #16 ; CHECK-BE-NEXT: add x8, x8, #16
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ld1 { v0.16b }, [x9] ; CHECK-BE-NEXT: ld1 { v0.16b }, [x9]
; CHECK-BE-NEXT: add x9, x1, #112 ; CHECK-BE-NEXT: add x9, x1, #112
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ushll2 v1.8h, v0.16b, #0 ; CHECK-BE-NEXT: ushll2 v1.8h, v0.16b, #0
; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-BE-NEXT: ushll2 v2.4s, v1.8h, #0 ; CHECK-BE-NEXT: ushll2 v2.4s, v1.8h, #0
; CHECK-BE-NEXT: ushll v1.4s, v1.4h, #0 ; CHECK-BE-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-BE-NEXT: ushll2 v4.4s, v0.8h, #0
; CHECK-BE-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-BE-NEXT: ushll2 v3.2d, v2.4s, #0 ; CHECK-BE-NEXT: ushll2 v3.2d, v2.4s, #0
; CHECK-BE-NEXT: ushll v2.2d, v2.2s, #0 ; CHECK-BE-NEXT: ushll v2.2d, v2.2s, #0
; CHECK-BE-NEXT: ushll2 v5.2d, v1.4s, #0
; CHECK-BE-NEXT: ushll v1.2d, v1.2s, #0
; CHECK-BE-NEXT: st1 { v3.2d }, [x9] ; CHECK-BE-NEXT: st1 { v3.2d }, [x9]
; CHECK-BE-NEXT: add x9, x1, #96
; CHECK-BE-NEXT: ushll2 v3.2d, v4.4s, #0
; CHECK-BE-NEXT: st1 { v2.2d }, [x9]
; CHECK-BE-NEXT: add x9, x1, #80 ; CHECK-BE-NEXT: add x9, x1, #80
; CHECK-BE-NEXT: ushll2 v3.2d, v1.4s, #0 ; CHECK-BE-NEXT: ushll v2.2d, v4.2s, #0
; CHECK-BE-NEXT: st1 { v2.2d }, [x10] ; CHECK-BE-NEXT: st1 { v5.2d }, [x9]
; CHECK-BE-NEXT: ushll2 v2.4s, v0.8h, #0 ; CHECK-BE-NEXT: add x9, x1, #48
; CHECK-BE-NEXT: add x10, x1, #48
; CHECK-BE-NEXT: st1 { v3.2d }, [x9] ; CHECK-BE-NEXT: st1 { v3.2d }, [x9]
; CHECK-BE-NEXT: ushll2 v3.2d, v0.4s, #0
; CHECK-BE-NEXT: ushll v0.2d, v0.2s, #0
; CHECK-BE-NEXT: add x9, x1, #64 ; CHECK-BE-NEXT: add x9, x1, #64
; CHECK-BE-NEXT: ushll v1.2d, v1.2s, #0
; CHECK-BE-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-BE-NEXT: ushll2 v4.2d, v2.4s, #0
; CHECK-BE-NEXT: st1 { v1.2d }, [x9] ; CHECK-BE-NEXT: st1 { v1.2d }, [x9]
; CHECK-BE-NEXT: ushll v1.2d, v0.2s, #0 ; CHECK-BE-NEXT: add x9, x1, #32
; CHECK-BE-NEXT: st1 { v2.2d }, [x9]
; CHECK-BE-NEXT: add x9, x1, #16 ; CHECK-BE-NEXT: add x9, x1, #16
; CHECK-BE-NEXT: st1 { v4.2d }, [x10] ; CHECK-BE-NEXT: st1 { v0.2d }, [x1]
; CHECK-BE-NEXT: add x10, x1, #32
; CHECK-BE-NEXT: st1 { v1.2d }, [x1]
; CHECK-BE-NEXT: add x1, x1, #128 ; CHECK-BE-NEXT: add x1, x1, #128
; CHECK-BE-NEXT: ushll2 v0.2d, v0.4s, #0 ; CHECK-BE-NEXT: st1 { v3.2d }, [x9]
; CHECK-BE-NEXT: ushll v2.2d, v2.2s, #0
; CHECK-BE-NEXT: st1 { v0.2d }, [x9]
; CHECK-BE-NEXT: st1 { v2.2d }, [x10]
; CHECK-BE-NEXT: b.ne .LBB7_1 ; CHECK-BE-NEXT: b.ne .LBB7_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
Context not available.
; CHECK-BE-NEXT: .LBB8_1: // %loop ; CHECK-BE-NEXT: .LBB8_1: // %loop
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: add x9, x0, x8 ; CHECK-BE-NEXT: add x9, x0, x8
; CHECK-BE-NEXT: add x10, x1, #32
; CHECK-BE-NEXT: add x8, x8, #16 ; CHECK-BE-NEXT: add x8, x8, #16
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ld1 { v0.8b }, [x9] ; CHECK-BE-NEXT: ld1 { v0.8b }, [x9]
; CHECK-BE-NEXT: add x9, x1, #48 ; CHECK-BE-NEXT: add x9, x1, #48
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-BE-NEXT: ushll2 v1.4s, v0.8h, #0 ; CHECK-BE-NEXT: ushll2 v1.4s, v0.8h, #0
; CHECK-BE-NEXT: ushll v0.4s, v0.4h, #0 ; CHECK-BE-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-BE-NEXT: ushll2 v2.2d, v1.4s, #0 ; CHECK-BE-NEXT: ushll2 v2.2d, v1.4s, #0
; CHECK-BE-NEXT: ushll v1.2d, v1.2s, #0 ; CHECK-BE-NEXT: ushll v1.2d, v1.2s, #0
; CHECK-BE-NEXT: ushll2 v3.2d, v0.4s, #0
; CHECK-BE-NEXT: ushll v0.2d, v0.2s, #0
; CHECK-BE-NEXT: st1 { v2.2d }, [x9] ; CHECK-BE-NEXT: st1 { v2.2d }, [x9]
; CHECK-BE-NEXT: add x9, x1, #32
; CHECK-BE-NEXT: st1 { v1.2d }, [x9]
; CHECK-BE-NEXT: add x9, x1, #16 ; CHECK-BE-NEXT: add x9, x1, #16
; CHECK-BE-NEXT: ushll v2.2d, v0.2s, #0 ; CHECK-BE-NEXT: st1 { v0.2d }, [x1]
; CHECK-BE-NEXT: st1 { v1.2d }, [x10]
; CHECK-BE-NEXT: ushll2 v0.2d, v0.4s, #0
; CHECK-BE-NEXT: st1 { v2.2d }, [x1]
; CHECK-BE-NEXT: add x1, x1, #128 ; CHECK-BE-NEXT: add x1, x1, #128
; CHECK-BE-NEXT: st1 { v0.2d }, [x9] ; CHECK-BE-NEXT: st1 { v3.2d }, [x9]
; CHECK-BE-NEXT: b.ne .LBB8_1 ; CHECK-BE-NEXT: b.ne .LBB8_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
Context not available.
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: add x9, x0, x8 ; CHECK-BE-NEXT: add x9, x0, x8
; CHECK-BE-NEXT: add x8, x8, #16 ; CHECK-BE-NEXT: add x8, x8, #16
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ld1 { v0.8b }, [x9] ; CHECK-BE-NEXT: ld1 { v0.8b }, [x9]
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-BE-NEXT: st1 { v0.8h }, [x1] ; CHECK-BE-NEXT: st1 { v0.8h }, [x1]
; CHECK-BE-NEXT: add x1, x1, #32 ; CHECK-BE-NEXT: add x1, x1, #32
Context not available.
; CHECK-NEXT: ushll.8h v0, v0, #0 ; CHECK-NEXT: ushll.8h v0, v0, #0
; CHECK-NEXT: ushll2.4s v1, v0, #0 ; CHECK-NEXT: ushll2.4s v1, v0, #0
; CHECK-NEXT: ushll.4s v0, v0, #0 ; CHECK-NEXT: ushll.4s v0, v0, #0
; CHECK-NEXT: mov.s w11, v1[1] ; CHECK-NEXT: mov.s w9, v1[1]
; CHECK-NEXT: mov.s w13, v0[1] ; CHECK-NEXT: mov.s w11, v0[1]
; CHECK-NEXT: fmov w12, s1 ; CHECK-NEXT: fmov w10, s1
; CHECK-NEXT: mov.s w14, v1[2] ; CHECK-NEXT: fmov w14, s0
; CHECK-NEXT: fmov w15, s0 ; CHECK-NEXT: mov.s w13, v1[2]
; CHECK-NEXT: mov.s w16, v0[2] ; CHECK-NEXT: mov.s w16, v0[2]
; CHECK-NEXT: mov.s w9, v1[3] ; CHECK-NEXT: mov.s w12, v1[3]
; CHECK-NEXT: mov.s w10, v0[3] ; CHECK-NEXT: mov.s w15, v0[3]
; CHECK-NEXT: orr x11, x12, x11, lsl #20 ; CHECK-NEXT: orr x9, x10, x9, lsl #20
; CHECK-NEXT: orr x12, x15, x13, lsl #20 ; CHECK-NEXT: orr x10, x14, x11, lsl #20
; CHECK-NEXT: orr x11, x11, x14, lsl #40 ; CHECK-NEXT: orr x9, x9, x13, lsl #40
; CHECK-NEXT: orr x12, x12, x16, lsl #40 ; CHECK-NEXT: orr x10, x10, x16, lsl #40
; CHECK-NEXT: lsr w13, w9, #4 ; CHECK-NEXT: lsr w11, w12, #4
; CHECK-NEXT: lsr w14, w10, #4 ; CHECK-NEXT: lsr w13, w15, #4
; CHECK-NEXT: orr x9, x11, x9, lsl #60 ; CHECK-NEXT: orr x9, x9, x12, lsl #60
; CHECK-NEXT: orr x10, x12, x10, lsl #60 ; CHECK-NEXT: orr x10, x10, x15, lsl #60
; CHECK-NEXT: strh w13, [x1, #18] ; CHECK-NEXT: strh w11, [x1, #18]
; CHECK-NEXT: strh w14, [x1, #8] ; CHECK-NEXT: strh w13, [x1, #8]
; CHECK-NEXT: stur x9, [x1, #10] ; CHECK-NEXT: stur x9, [x1, #10]
; CHECK-NEXT: str x10, [x1], #64 ; CHECK-NEXT: str x10, [x1], #64
; CHECK-NEXT: b.ne LBB10_1 ; CHECK-NEXT: b.ne LBB10_1
Context not available.
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: add x9, x0, x8 ; CHECK-BE-NEXT: add x9, x0, x8
; CHECK-BE-NEXT: add x8, x8, #16 ; CHECK-BE-NEXT: add x8, x8, #16
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ld1 { v0.8b }, [x9] ; CHECK-BE-NEXT: ld1 { v0.8b }, [x9]
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-BE-NEXT: ushll2 v1.4s, v0.8h, #0 ; CHECK-BE-NEXT: ushll2 v1.4s, v0.8h, #0
; CHECK-BE-NEXT: ushll v0.4s, v0.4h, #0 ; CHECK-BE-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-BE-NEXT: mov w9, v1.s[1] ; CHECK-BE-NEXT: mov w9, v1.s[1]
; CHECK-BE-NEXT: mov w11, v1.s[2] ; CHECK-BE-NEXT: mov w10, v0.s[1]
; CHECK-BE-NEXT: fmov w12, s1 ; CHECK-BE-NEXT: fmov w12, s1
; CHECK-BE-NEXT: mov w13, v0.s[1] ; CHECK-BE-NEXT: fmov w14, s0
; CHECK-BE-NEXT: mov w15, v0.s[2] ; CHECK-BE-NEXT: mov w11, v1.s[2]
; CHECK-BE-NEXT: mov w10, v1.s[3] ; CHECK-BE-NEXT: mov w13, v0.s[2]
; CHECK-BE-NEXT: mov w14, v0.s[3] ; CHECK-BE-NEXT: mov w15, v1.s[3]
; CHECK-BE-NEXT: lsl x9, x9, #40 ; CHECK-BE-NEXT: lsl x9, x9, #40
; CHECK-BE-NEXT: lsl x10, x10, #40
; CHECK-BE-NEXT: orr x9, x9, x12, lsl #60 ; CHECK-BE-NEXT: orr x9, x9, x12, lsl #60
; CHECK-BE-NEXT: orr x10, x10, x14, lsl #60
; CHECK-BE-NEXT: lsr x12, x12, #4 ; CHECK-BE-NEXT: lsr x12, x12, #4
; CHECK-BE-NEXT: strh w15, [x1, #18]
; CHECK-BE-NEXT: orr x9, x9, x11, lsl #20 ; CHECK-BE-NEXT: orr x9, x9, x11, lsl #20
; CHECK-BE-NEXT: fmov w11, s0 ; CHECK-BE-NEXT: orr x10, x10, x13, lsl #20
; CHECK-BE-NEXT: lsl x13, x13, #40 ; CHECK-BE-NEXT: mov w11, v0.s[3]
; CHECK-BE-NEXT: lsr x13, x14, #4
; CHECK-BE-NEXT: lsr x9, x9, #16 ; CHECK-BE-NEXT: lsr x9, x9, #16
; CHECK-BE-NEXT: lsr x10, x10, #16
; CHECK-BE-NEXT: bfi x9, x12, #48, #4 ; CHECK-BE-NEXT: bfi x9, x12, #48, #4
; CHECK-BE-NEXT: strh w10, [x1, #18] ; CHECK-BE-NEXT: bfi x10, x13, #48, #4
; CHECK-BE-NEXT: orr x13, x13, x11, lsl #60 ; CHECK-BE-NEXT: strh w11, [x1, #8]
; CHECK-BE-NEXT: lsr x11, x11, #4
; CHECK-BE-NEXT: orr x13, x13, x15, lsl #20
; CHECK-BE-NEXT: strh w14, [x1, #8]
; CHECK-BE-NEXT: lsr x12, x13, #16
; CHECK-BE-NEXT: stur x9, [x1, #10] ; CHECK-BE-NEXT: stur x9, [x1, #10]
; CHECK-BE-NEXT: bfi x12, x11, #48, #4 ; CHECK-BE-NEXT: str x10, [x1], #64
; CHECK-BE-NEXT: str x12, [x1], #64
; CHECK-BE-NEXT: b.ne .LBB10_1 ; CHECK-BE-NEXT: b.ne .LBB10_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
Context not available.
; CHECK-LABEL: zext_v12i8_to_v12i32_in_loop: ; CHECK-LABEL: zext_v12i8_to_v12i32_in_loop:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: Lloh12: ; CHECK-NEXT: Lloh12:
; CHECK-NEXT: adrp x9, lCPI12_0@PAGE ; CHECK-NEXT: adrp x8, lCPI12_0@PAGE
; CHECK-NEXT: Lloh13: ; CHECK-NEXT: Lloh13:
; CHECK-NEXT: adrp x10, lCPI12_1@PAGE ; CHECK-NEXT: adrp x9, lCPI12_1@PAGE
; CHECK-NEXT: Lloh14: ; CHECK-NEXT: Lloh14:
; CHECK-NEXT: adrp x11, lCPI12_2@PAGE ; CHECK-NEXT: adrp x10, lCPI12_2@PAGE
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: Lloh15: ; CHECK-NEXT: Lloh15:
; CHECK-NEXT: ldr q0, [x9, lCPI12_0@PAGEOFF] ; CHECK-NEXT: ldr q0, [x8, lCPI12_0@PAGEOFF]
; CHECK-NEXT: Lloh16: ; CHECK-NEXT: Lloh16:
; CHECK-NEXT: ldr q1, [x10, lCPI12_1@PAGEOFF] ; CHECK-NEXT: ldr q1, [x9, lCPI12_1@PAGEOFF]
; CHECK-NEXT: Lloh17: ; CHECK-NEXT: Lloh17:
; CHECK-NEXT: ldr q2, [x11, lCPI12_2@PAGEOFF] ; CHECK-NEXT: ldr q2, [x10, lCPI12_2@PAGEOFF]
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: LBB12_1: ; %loop ; CHECK-NEXT: LBB12_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr q3, [x0, x8] ; CHECK-NEXT: ldr q3, [x0, x8]
Context not available.
; CHECK-BE-NEXT: .LBB12_1: // %loop ; CHECK-BE-NEXT: .LBB12_1: // %loop
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: add x9, x0, x8 ; CHECK-BE-NEXT: add x9, x0, x8
; CHECK-BE-NEXT: add x10, x1, #16
; CHECK-BE-NEXT: add x8, x8, #16 ; CHECK-BE-NEXT: add x8, x8, #16
; CHECK-BE-NEXT: cmp x8, #128 ; CHECK-BE-NEXT: add x10, x1, #16
; CHECK-BE-NEXT: ld1 { v3.16b }, [x9] ; CHECK-BE-NEXT: ld1 { v3.16b }, [x9]
; CHECK-BE-NEXT: add x9, x1, #32 ; CHECK-BE-NEXT: add x9, x1, #32
; CHECK-BE-NEXT: tbl v4.16b, { v3.16b }, v0.16b ; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: tbl v5.16b, { v3.16b }, v2.16b ; CHECK-BE-NEXT: tbl v4.16b, { v3.16b }, v2.16b
; CHECK-BE-NEXT: tbl v3.16b, { v3.16b }, v1.16b ; CHECK-BE-NEXT: tbl v5.16b, { v3.16b }, v1.16b
; CHECK-BE-NEXT: st1 { v4.16b }, [x1] ; CHECK-BE-NEXT: tbl v3.16b, { v3.16b }, v0.16b
; CHECK-BE-NEXT: st1 { v3.16b }, [x1]
; CHECK-BE-NEXT: add x1, x1, #64 ; CHECK-BE-NEXT: add x1, x1, #64
; CHECK-BE-NEXT: st1 { v5.16b }, [x9] ; CHECK-BE-NEXT: st1 { v4.16b }, [x9]
; CHECK-BE-NEXT: st1 { v3.16b }, [x10] ; CHECK-BE-NEXT: st1 { v5.16b }, [x10]
; CHECK-BE-NEXT: b.ne .LBB12_1 ; CHECK-BE-NEXT: b.ne .LBB12_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
Context not available.
; CHECK-NEXT: ldr x9, [x0, x8] ; CHECK-NEXT: ldr x9, [x0, x8]
; CHECK-NEXT: add x8, x8, #16 ; CHECK-NEXT: add x8, x8, #16
; CHECK-NEXT: cmp x8, #128 ; CHECK-NEXT: cmp x8, #128
; CHECK-NEXT: and w10, w9, #0xf ; CHECK-NEXT: and w11, w9, #0xf
; CHECK-NEXT: ubfx w11, w9, #4, #4 ; CHECK-NEXT: ubfx w10, w9, #4, #4
; CHECK-NEXT: fmov s1, w10 ; CHECK-NEXT: fmov s1, w11
; CHECK-NEXT: mov.b v1[1], w10
; CHECK-NEXT: ubfx w10, w9, #8, #4 ; CHECK-NEXT: ubfx w10, w9, #8, #4
; CHECK-NEXT: mov.b v1[1], w11
; CHECK-NEXT: mov.b v1[2], w10 ; CHECK-NEXT: mov.b v1[2], w10
; CHECK-NEXT: ubfx w10, w9, #12, #4 ; CHECK-NEXT: ubfx w10, w9, #12, #4
; CHECK-NEXT: mov.b v1[3], w10 ; CHECK-NEXT: mov.b v1[3], w10
Context not available.
; CHECK-NEXT: ext.16b v2, v1, v1, #8 ; CHECK-NEXT: ext.16b v2, v1, v1, #8
; CHECK-NEXT: zip2.8b v3, v1, v0 ; CHECK-NEXT: zip2.8b v3, v1, v0
; CHECK-NEXT: zip1.8b v1, v1, v0 ; CHECK-NEXT: zip1.8b v1, v1, v0
; CHECK-NEXT: zip1.8b v4, v2, v0 ; CHECK-NEXT: zip2.8b v4, v2, v0
; CHECK-NEXT: zip2.8b v2, v2, v0 ; CHECK-NEXT: zip1.8b v2, v2, v0
; CHECK-NEXT: ushll.4s v3, v3, #0 ; CHECK-NEXT: ushll.4s v3, v3, #0
; CHECK-NEXT: ushll.4s v1, v1, #0 ; CHECK-NEXT: ushll.4s v1, v1, #0
; CHECK-NEXT: and.16b v3, v3, v0 ; CHECK-NEXT: and.16b v3, v3, v0
; CHECK-NEXT: ushll.4s v4, v4, #0
; CHECK-NEXT: ushll.4s v2, v2, #0
; CHECK-NEXT: and.16b v1, v1, v0 ; CHECK-NEXT: and.16b v1, v1, v0
; CHECK-NEXT: stp q1, q3, [x1] ; CHECK-NEXT: and.16b v4, v4, v0
; CHECK-NEXT: ushll.4s v1, v2, #0
; CHECK-NEXT: ushll.4s v2, v4, #0
; CHECK-NEXT: and.16b v1, v1, v0
; CHECK-NEXT: and.16b v2, v2, v0 ; CHECK-NEXT: and.16b v2, v2, v0
; CHECK-NEXT: stp q2, q1, [x1, #32] ; CHECK-NEXT: stp q1, q3, [x1]
; CHECK-NEXT: stp q2, q4, [x1, #32]
; CHECK-NEXT: add x1, x1, #64 ; CHECK-NEXT: add x1, x1, #64
; CHECK-NEXT: b.ne LBB13_1 ; CHECK-NEXT: b.ne LBB13_1
; CHECK-NEXT: ; %bb.2: ; %exit ; CHECK-NEXT: ; %bb.2: ; %exit
Context not available.
; CHECK-BE-NEXT: fmov s1, w10 ; CHECK-BE-NEXT: fmov s1, w10
; CHECK-BE-NEXT: ubfx x10, x9, #52, #4 ; CHECK-BE-NEXT: ubfx x10, x9, #52, #4
; CHECK-BE-NEXT: mov v1.b[1], w11 ; CHECK-BE-NEXT: mov v1.b[1], w11
; CHECK-BE-NEXT: add x11, x1, #32
; CHECK-BE-NEXT: mov v1.b[2], w10 ; CHECK-BE-NEXT: mov v1.b[2], w10
; CHECK-BE-NEXT: ubfx x10, x9, #48, #4 ; CHECK-BE-NEXT: ubfx x10, x9, #48, #4
; CHECK-BE-NEXT: mov v1.b[3], w10 ; CHECK-BE-NEXT: mov v1.b[3], w10
Context not available.
; CHECK-BE-NEXT: ubfx w10, w9, #4, #4 ; CHECK-BE-NEXT: ubfx w10, w9, #4, #4
; CHECK-BE-NEXT: and w9, w9, #0xf ; CHECK-BE-NEXT: and w9, w9, #0xf
; CHECK-BE-NEXT: mov v1.b[14], w10 ; CHECK-BE-NEXT: mov v1.b[14], w10
; CHECK-BE-NEXT: add x10, x1, #48 ; CHECK-BE-NEXT: add x10, x1, #32
; CHECK-BE-NEXT: mov v1.b[15], w9 ; CHECK-BE-NEXT: mov v1.b[15], w9
; CHECK-BE-NEXT: add x9, x1, #16 ; CHECK-BE-NEXT: add x9, x1, #16
; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8 ; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
; CHECK-BE-NEXT: zip2 v3.8b, v1.8b, v0.8b ; CHECK-BE-NEXT: zip2 v3.8b, v1.8b, v0.8b
; CHECK-BE-NEXT: zip1 v1.8b, v1.8b, v0.8b ; CHECK-BE-NEXT: zip1 v1.8b, v1.8b, v0.8b
; CHECK-BE-NEXT: zip1 v4.8b, v2.8b, v0.8b ; CHECK-BE-NEXT: zip2 v4.8b, v2.8b, v0.8b
; CHECK-BE-NEXT: zip2 v2.8b, v2.8b, v0.8b ; CHECK-BE-NEXT: zip1 v2.8b, v2.8b, v0.8b
; CHECK-BE-NEXT: rev16 v1.8b, v1.8b
; CHECK-BE-NEXT: rev16 v3.8b, v3.8b ; CHECK-BE-NEXT: rev16 v3.8b, v3.8b
; CHECK-BE-NEXT: rev16 v1.8b, v1.8b
; CHECK-BE-NEXT: rev16 v4.8b, v4.8b ; CHECK-BE-NEXT: rev16 v4.8b, v4.8b
; CHECK-BE-NEXT: rev16 v2.8b, v2.8b ; CHECK-BE-NEXT: rev16 v2.8b, v2.8b
; CHECK-BE-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-BE-NEXT: ushll v3.4s, v3.4h, #0 ; CHECK-BE-NEXT: ushll v3.4s, v3.4h, #0
; CHECK-BE-NEXT: and v1.16b, v1.16b, v0.16b ; CHECK-BE-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-BE-NEXT: st1 { v1.4s }, [x1]
; CHECK-BE-NEXT: add x1, x1, #64
; CHECK-BE-NEXT: ushll v1.4s, v2.4h, #0
; CHECK-BE-NEXT: ushll v2.4s, v4.4h, #0
; CHECK-BE-NEXT: and v3.16b, v3.16b, v0.16b ; CHECK-BE-NEXT: and v3.16b, v3.16b, v0.16b
; CHECK-BE-NEXT: ushll v4.4s, v4.4h, #0
; CHECK-BE-NEXT: ushll v2.4s, v2.4h, #0
; CHECK-BE-NEXT: and v1.16b, v1.16b, v0.16b ; CHECK-BE-NEXT: and v1.16b, v1.16b, v0.16b
; CHECK-BE-NEXT: st1 { v3.4s }, [x9] ; CHECK-BE-NEXT: st1 { v3.4s }, [x9]
; CHECK-BE-NEXT: add x9, x1, #48
; CHECK-BE-NEXT: and v4.16b, v4.16b, v0.16b
; CHECK-BE-NEXT: and v2.16b, v2.16b, v0.16b ; CHECK-BE-NEXT: and v2.16b, v2.16b, v0.16b
; CHECK-BE-NEXT: st1 { v1.4s }, [x10] ; CHECK-BE-NEXT: st1 { v1.4s }, [x1]
; CHECK-BE-NEXT: st1 { v2.4s }, [x11] ; CHECK-BE-NEXT: add x1, x1, #64
; CHECK-BE-NEXT: st1 { v4.4s }, [x9]
; CHECK-BE-NEXT: st1 { v2.4s }, [x10]
; CHECK-BE-NEXT: b.ne .LBB13_1 ; CHECK-BE-NEXT: b.ne .LBB13_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
Context not available.
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: add x9, x0, x8 ; CHECK-NEXT: add x9, x0, x8
; CHECK-NEXT: add x8, x8, #32 ; CHECK-NEXT: add x8, x8, #32
; CHECK-NEXT: ldp q1, q0, [x9]
; CHECK-NEXT: cmp x8, #256 ; CHECK-NEXT: cmp x8, #256
; CHECK-NEXT: ldp q0, q1, [x9] ; CHECK-NEXT: ushll2.4s v2, v0, #0
; CHECK-NEXT: ushll.4s v2, v0, #0 ; CHECK-NEXT: ushll2.4s v3, v1, #0
; CHECK-NEXT: ushll2.4s v0, v0, #0 ; CHECK-NEXT: ushll.4s v0, v0, #0
; CHECK-NEXT: ushll.4s v3, v1, #0 ; CHECK-NEXT: ushll.4s v1, v1, #0
; CHECK-NEXT: ushll2.4s v1, v1, #0 ; CHECK-NEXT: ushll2.2d v4, v2, #0
; CHECK-NEXT: ushll2.2d v5, v0, #0 ; CHECK-NEXT: ushll.2d v2, v2, #0
; CHECK-NEXT: ushll2.2d v4, v1, #0 ; CHECK-NEXT: ushll2.2d v5, v3, #0
; CHECK-NEXT: ushll.2d v1, v1, #0
; CHECK-NEXT: ushll.2d v0, v0, #0
; CHECK-NEXT: stp q1, q4, [x1, #96]
; CHECK-NEXT: ushll2.2d v1, v3, #0
; CHECK-NEXT: stp q0, q5, [x1, #32]
; CHECK-NEXT: ushll.2d v3, v3, #0 ; CHECK-NEXT: ushll.2d v3, v3, #0
; CHECK-NEXT: ushll2.2d v0, v2, #0 ; CHECK-NEXT: stp q2, q4, [x1, #96]
; CHECK-NEXT: stp q3, q1, [x1, #64] ; CHECK-NEXT: ushll2.2d v4, v0, #0
; CHECK-NEXT: ushll.2d v1, v2, #0 ; CHECK-NEXT: ushll.2d v0, v0, #0
; CHECK-NEXT: stp q1, q0, [x1], #128 ; CHECK-NEXT: ushll2.2d v2, v1, #0
; CHECK-NEXT: ushll.2d v1, v1, #0
; CHECK-NEXT: stp q3, q5, [x1, #32]
; CHECK-NEXT: stp q0, q4, [x1, #64]
; CHECK-NEXT: stp q1, q2, [x1], #128
; CHECK-NEXT: b.ne LBB14_1 ; CHECK-NEXT: b.ne LBB14_1
; CHECK-NEXT: ; %bb.2: ; %exit ; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
Context not available.
; CHECK-BE-NEXT: .LBB14_1: // %loop ; CHECK-BE-NEXT: .LBB14_1: // %loop
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: add x9, x0, x8 ; CHECK-BE-NEXT: add x9, x0, x8
; CHECK-BE-NEXT: add x10, x1, #48
; CHECK-BE-NEXT: add x8, x8, #32 ; CHECK-BE-NEXT: add x8, x8, #32
; CHECK-BE-NEXT: cmp x8, #256
; CHECK-BE-NEXT: ld1 { v0.8h }, [x9] ; CHECK-BE-NEXT: ld1 { v0.8h }, [x9]
; CHECK-BE-NEXT: add x9, x9, #16 ; CHECK-BE-NEXT: add x9, x9, #16
; CHECK-BE-NEXT: ld1 { v2.8h }, [x9] ; CHECK-BE-NEXT: cmp x8, #256
; CHECK-BE-NEXT: add x9, x1, #32 ; CHECK-BE-NEXT: ld1 { v1.8h }, [x9]
; CHECK-BE-NEXT: ushll2 v1.4s, v0.8h, #0 ; CHECK-BE-NEXT: add x9, x1, #48
; CHECK-BE-NEXT: ushll2 v2.4s, v0.8h, #0
; CHECK-BE-NEXT: ushll v0.4s, v0.4h, #0 ; CHECK-BE-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-BE-NEXT: ushll2 v3.2d, v1.4s, #0 ; CHECK-BE-NEXT: ushll2 v3.4s, v1.8h, #0
; CHECK-BE-NEXT: ushll v1.2d, v1.2s, #0 ; CHECK-BE-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-BE-NEXT: st1 { v3.2d }, [x10] ; CHECK-BE-NEXT: ushll2 v4.2d, v2.4s, #0
; CHECK-BE-NEXT: add x10, x1, #112 ; CHECK-BE-NEXT: ushll v2.2d, v2.2s, #0
; CHECK-BE-NEXT: st1 { v1.2d }, [x9] ; CHECK-BE-NEXT: ushll2 v5.2d, v0.4s, #0
; CHECK-BE-NEXT: ushll v0.2d, v0.2s, #0
; CHECK-BE-NEXT: st1 { v4.2d }, [x9]
; CHECK-BE-NEXT: add x9, x1, #32
; CHECK-BE-NEXT: ushll2 v4.2d, v3.4s, #0
; CHECK-BE-NEXT: st1 { v2.2d }, [x9]
; CHECK-BE-NEXT: add x9, x1, #16 ; CHECK-BE-NEXT: add x9, x1, #16
; CHECK-BE-NEXT: ushll2 v3.2d, v0.4s, #0 ; CHECK-BE-NEXT: ushll v2.2d, v3.2s, #0
; CHECK-BE-NEXT: ushll2 v1.4s, v2.8h, #0 ; CHECK-BE-NEXT: st1 { v5.2d }, [x9]
; CHECK-BE-NEXT: st1 { v3.2d }, [x9] ; CHECK-BE-NEXT: add x9, x1, #112
; CHECK-BE-NEXT: ushll2 v3.2d, v1.4s, #0
; CHECK-BE-NEXT: st1 { v4.2d }, [x9]
; CHECK-BE-NEXT: add x9, x1, #96 ; CHECK-BE-NEXT: add x9, x1, #96
; CHECK-BE-NEXT: ushll2 v4.2d, v1.4s, #0
; CHECK-BE-NEXT: ushll v0.2d, v0.2s, #0
; CHECK-BE-NEXT: ushll v1.2d, v1.2s, #0 ; CHECK-BE-NEXT: ushll v1.2d, v1.2s, #0
; CHECK-BE-NEXT: st1 { v4.2d }, [x10] ; CHECK-BE-NEXT: st1 { v2.2d }, [x9]
; CHECK-BE-NEXT: ushll v2.4s, v2.4h, #0 ; CHECK-BE-NEXT: add x9, x1, #80
; CHECK-BE-NEXT: add x10, x1, #80 ; CHECK-BE-NEXT: st1 { v3.2d }, [x9]
; CHECK-BE-NEXT: st1 { v0.2d }, [x1]
; CHECK-BE-NEXT: st1 { v1.2d }, [x9]
; CHECK-BE-NEXT: add x9, x1, #64 ; CHECK-BE-NEXT: add x9, x1, #64
; CHECK-BE-NEXT: st1 { v0.2d }, [x1]
; CHECK-BE-NEXT: add x1, x1, #128 ; CHECK-BE-NEXT: add x1, x1, #128
; CHECK-BE-NEXT: ushll v3.2d, v2.2s, #0 ; CHECK-BE-NEXT: st1 { v1.2d }, [x9]
; CHECK-BE-NEXT: ushll2 v2.2d, v2.4s, #0
; CHECK-BE-NEXT: st1 { v3.2d }, [x9]
; CHECK-BE-NEXT: st1 { v2.2d }, [x10]
; CHECK-BE-NEXT: b.ne .LBB14_1 ; CHECK-BE-NEXT: b.ne .LBB14_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
Context not available.
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: add x9, x0, x8 ; CHECK-NEXT: add x9, x0, x8
; CHECK-NEXT: add x8, x8, #64 ; CHECK-NEXT: add x8, x8, #64
; CHECK-NEXT: cmp x8, #512
; CHECK-NEXT: ldp q1, q0, [x9, #32] ; CHECK-NEXT: ldp q1, q0, [x9, #32]
; CHECK-NEXT: ushll2.2d v5, v1, #0 ; CHECK-NEXT: cmp x8, #512
; CHECK-NEXT: ushll.2d v1, v1, #0 ; CHECK-NEXT: ldp q5, q4, [x9]
; CHECK-NEXT: ldp q3, q2, [x9] ; CHECK-NEXT: ushll2.2d v2, v0, #0
; CHECK-NEXT: ushll2.2d v4, v0, #0
; CHECK-NEXT: stp q1, q5, [x1, #64]
; CHECK-NEXT: ushll.2d v0, v0, #0 ; CHECK-NEXT: ushll.2d v0, v0, #0
; CHECK-NEXT: stp q0, q4, [x1, #96] ; CHECK-NEXT: ushll2.2d v3, v1, #0
; CHECK-NEXT: ushll2.2d v1, v3, #0 ; CHECK-NEXT: ushll.2d v1, v1, #0
; CHECK-NEXT: ushll2.2d v0, v2, #0 ; CHECK-NEXT: stp q0, q2, [x1, #96]
; CHECK-NEXT: ushll.2d v2, v2, #0 ; CHECK-NEXT: ushll2.2d v2, v4, #0
; CHECK-NEXT: stp q2, q0, [x1, #32] ; CHECK-NEXT: ushll.2d v0, v4, #0
; CHECK-NEXT: ushll.2d v0, v3, #0 ; CHECK-NEXT: stp q1, q3, [x1, #64]
; CHECK-NEXT: stp q0, q1, [x1], #128 ; CHECK-NEXT: ushll2.2d v3, v5, #0
; CHECK-NEXT: ushll.2d v1, v5, #0
; CHECK-NEXT: stp q0, q2, [x1, #32]
; CHECK-NEXT: stp q1, q3, [x1], #128
; CHECK-NEXT: b.ne LBB15_1 ; CHECK-NEXT: b.ne LBB15_1
; CHECK-NEXT: ; %bb.2: ; %exit ; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
Context not available.
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: add x9, x0, x8 ; CHECK-BE-NEXT: add x9, x0, x8
; CHECK-BE-NEXT: add x8, x8, #64 ; CHECK-BE-NEXT: add x8, x8, #64
; CHECK-BE-NEXT: ld1 { v0.4s }, [x9]
; CHECK-BE-NEXT: add x10, x9, #48 ; CHECK-BE-NEXT: add x10, x9, #48
; CHECK-BE-NEXT: add x11, x9, #32
; CHECK-BE-NEXT: cmp x8, #512 ; CHECK-BE-NEXT: cmp x8, #512
; CHECK-BE-NEXT: ld1 { v0.4s }, [x9]
; CHECK-BE-NEXT: add x9, x9, #16
; CHECK-BE-NEXT: ld1 { v1.4s }, [x10] ; CHECK-BE-NEXT: ld1 { v1.4s }, [x10]
; CHECK-BE-NEXT: add x10, x1, #16 ; CHECK-BE-NEXT: add x10, x9, #32
; CHECK-BE-NEXT: ld1 { v2.4s }, [x11] ; CHECK-BE-NEXT: add x9, x9, #16
; CHECK-BE-NEXT: ushll2 v3.2d, v0.4s, #0
; CHECK-BE-NEXT: ld1 { v4.4s }, [x9] ; CHECK-BE-NEXT: ld1 { v4.4s }, [x9]
; CHECK-BE-NEXT: add x9, x1, #112 ; CHECK-BE-NEXT: ld1 { v2.4s }, [x10]
; CHECK-BE-NEXT: st1 { v3.2d }, [x10] ; CHECK-BE-NEXT: add x9, x1, #16
; CHECK-BE-NEXT: ushll2 v3.2d, v0.4s, #0
; CHECK-BE-NEXT: ushll v0.2d, v0.2s, #0
; CHECK-BE-NEXT: add x10, x1, #80 ; CHECK-BE-NEXT: add x10, x1, #80
; CHECK-BE-NEXT: ushll2 v3.2d, v1.4s, #0 ; CHECK-BE-NEXT: ushll2 v5.2d, v1.4s, #0
; CHECK-BE-NEXT: ushll2 v5.2d, v2.4s, #0 ; CHECK-BE-NEXT: ushll2 v6.2d, v2.4s, #0
; CHECK-BE-NEXT: st1 { v3.2d }, [x9] ; CHECK-BE-NEXT: st1 { v3.2d }, [x9]
; CHECK-BE-NEXT: add x9, x1, #48 ; CHECK-BE-NEXT: ushll2 v3.2d, v4.4s, #0
; CHECK-BE-NEXT: st1 { v5.2d }, [x10] ; CHECK-BE-NEXT: add x9, x1, #112
; CHECK-BE-NEXT: add x10, x1, #96
; CHECK-BE-NEXT: ushll v0.2d, v0.2s, #0
; CHECK-BE-NEXT: ushll v3.2d, v4.2s, #0
; CHECK-BE-NEXT: ushll2 v4.2d, v4.4s, #0
; CHECK-BE-NEXT: st1 { v0.2d }, [x1] ; CHECK-BE-NEXT: st1 { v0.2d }, [x1]
; CHECK-BE-NEXT: ushll v1.2d, v1.2s, #0 ; CHECK-BE-NEXT: ushll v0.2d, v1.2s, #0
; CHECK-BE-NEXT: st1 { v4.2d }, [x9] ; CHECK-BE-NEXT: ushll v1.2d, v2.2s, #0
; CHECK-BE-NEXT: st1 { v5.2d }, [x9]
; CHECK-BE-NEXT: add x9, x1, #48
; CHECK-BE-NEXT: ushll v2.2d, v4.2s, #0
; CHECK-BE-NEXT: st1 { v3.2d }, [x9]
; CHECK-BE-NEXT: add x9, x1, #64 ; CHECK-BE-NEXT: add x9, x1, #64
; CHECK-BE-NEXT: st1 { v1.2d }, [x10] ; CHECK-BE-NEXT: st1 { v6.2d }, [x10]
; CHECK-BE-NEXT: add x10, x1, #32 ; CHECK-BE-NEXT: add x10, x1, #96
; CHECK-BE-NEXT: st1 { v1.2d }, [x9]
; CHECK-BE-NEXT: add x9, x1, #32
; CHECK-BE-NEXT: add x1, x1, #128 ; CHECK-BE-NEXT: add x1, x1, #128
; CHECK-BE-NEXT: ushll v2.2d, v2.2s, #0 ; CHECK-BE-NEXT: st1 { v0.2d }, [x10]
; CHECK-BE-NEXT: st1 { v3.2d }, [x10]
; CHECK-BE-NEXT: st1 { v2.2d }, [x9] ; CHECK-BE-NEXT: st1 { v2.2d }, [x9]
; CHECK-BE-NEXT: b.ne .LBB15_1 ; CHECK-BE-NEXT: b.ne .LBB15_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
Context not available.
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr d0, [x0, x8] ; CHECK-NEXT: ldr d0, [x0, x8]
; CHECK-NEXT: add x9, x1, #112 ; CHECK-NEXT: add x9, x1, #112
; CHECK-NEXT: add x10, x1, #80
; CHECK-NEXT: str xzr, [x1, #120]
; CHECK-NEXT: str xzr, [x1, #104]
; CHECK-NEXT: add x8, x8, #16 ; CHECK-NEXT: add x8, x8, #16
; CHECK-NEXT: str xzr, [x1, #88] ; CHECK-NEXT: str xzr, [x1, #120]
; CHECK-NEXT: cmp x8, #128 ; CHECK-NEXT: cmp x8, #128
; CHECK-NEXT: ushll.8h v0, v0, #0 ; CHECK-NEXT: ushll.8h v0, v0, #0
; CHECK-NEXT: str xzr, [x1, #104]
; CHECK-NEXT: str xzr, [x1, #88]
; CHECK-NEXT: str xzr, [x1, #72] ; CHECK-NEXT: str xzr, [x1, #72]
; CHECK-NEXT: str xzr, [x1, #56]
; CHECK-NEXT: ushll2.4s v1, v0, #0 ; CHECK-NEXT: ushll2.4s v1, v0, #0
; CHECK-NEXT: str xzr, [x1, #40]
; CHECK-NEXT: ushll.4s v0, v0, #0 ; CHECK-NEXT: ushll.4s v0, v0, #0
; CHECK-NEXT: str xzr, [x1, #56]
; CHECK-NEXT: str xzr, [x1, #40]
; CHECK-NEXT: str xzr, [x1, #24] ; CHECK-NEXT: str xzr, [x1, #24]
; CHECK-NEXT: ushll2.2d v2, v1, #0 ; CHECK-NEXT: ushll2.2d v2, v1, #0
; CHECK-NEXT: str xzr, [x1, #8]
; CHECK-NEXT: ushll.2d v1, v1, #0 ; CHECK-NEXT: ushll.2d v1, v1, #0
; CHECK-NEXT: ushll2.2d v3, v0, #0
; CHECK-NEXT: ushll.2d v0, v0, #0
; CHECK-NEXT: str xzr, [x1, #8]
; CHECK-NEXT: st1.d { v2 }[1], [x9] ; CHECK-NEXT: st1.d { v2 }[1], [x9]
; CHECK-NEXT: add x9, x1, #80
; CHECK-NEXT: st1.d { v1 }[1], [x9]
; CHECK-NEXT: add x9, x1, #48 ; CHECK-NEXT: add x9, x1, #48
; CHECK-NEXT: str d2, [x1, #96] ; CHECK-NEXT: str d2, [x1, #96]
; CHECK-NEXT: ushll2.2d v2, v0, #0 ; CHECK-NEXT: st1.d { v3 }[1], [x9]
; CHECK-NEXT: st1.d { v1 }[1], [x10] ; CHECK-NEXT: add x9, x1, #16
; CHECK-NEXT: ushll.2d v0, v0, #0
; CHECK-NEXT: str d1, [x1, #64] ; CHECK-NEXT: str d1, [x1, #64]
; CHECK-NEXT: str d2, [x1, #32] ; CHECK-NEXT: str d3, [x1, #32]
; CHECK-NEXT: add x10, x1, #16
; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: str d0, [x1]
; CHECK-NEXT: add x1, x1, #256 ; CHECK-NEXT: add x1, x1, #256
; CHECK-NEXT: st1.d { v2 }[1], [x9] ; CHECK-NEXT: st1.d { v0 }[1], [x9]
; CHECK-NEXT: st1.d { v0 }[1], [x10]
; CHECK-NEXT: b.ne LBB16_1 ; CHECK-NEXT: b.ne LBB16_1
; CHECK-NEXT: ; %bb.2: ; %exit ; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
Context not available.
; CHECK-BE-NEXT: .LBB16_1: // %loop ; CHECK-BE-NEXT: .LBB16_1: // %loop
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: add x9, x0, x8 ; CHECK-BE-NEXT: add x9, x0, x8
; CHECK-BE-NEXT: add x10, x1, #88
; CHECK-BE-NEXT: add x8, x8, #16 ; CHECK-BE-NEXT: add x8, x8, #16
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ld1 { v0.8b }, [x9] ; CHECK-BE-NEXT: ld1 { v0.8b }, [x9]
; CHECK-BE-NEXT: add x9, x1, #120 ; CHECK-BE-NEXT: add x9, x1, #120
; CHECK-BE-NEXT: str xzr, [x1, #112] ; CHECK-BE-NEXT: str xzr, [x1, #112]
; CHECK-BE-NEXT: str xzr, [x1, #96] ; CHECK-BE-NEXT: str xzr, [x1, #96]
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: str xzr, [x1, #80] ; CHECK-BE-NEXT: str xzr, [x1, #80]
; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-BE-NEXT: str xzr, [x1, #64] ; CHECK-BE-NEXT: str xzr, [x1, #64]
; CHECK-BE-NEXT: str xzr, [x1, #48] ; CHECK-BE-NEXT: str xzr, [x1, #48]
; CHECK-BE-NEXT: ushll2 v1.4s, v0.8h, #0
; CHECK-BE-NEXT: str xzr, [x1, #32] ; CHECK-BE-NEXT: str xzr, [x1, #32]
; CHECK-BE-NEXT: ushll2 v1.4s, v0.8h, #0
; CHECK-BE-NEXT: ushll v0.4s, v0.4h, #0 ; CHECK-BE-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-BE-NEXT: str xzr, [x1, #16] ; CHECK-BE-NEXT: str xzr, [x1, #16]
; CHECK-BE-NEXT: ushll2 v2.2d, v1.4s, #0
; CHECK-BE-NEXT: str xzr, [x1] ; CHECK-BE-NEXT: str xzr, [x1]
; CHECK-BE-NEXT: ushll2 v2.2d, v1.4s, #0
; CHECK-BE-NEXT: ushll v1.2d, v1.2s, #0 ; CHECK-BE-NEXT: ushll v1.2d, v1.2s, #0
; CHECK-BE-NEXT: ushll2 v3.2d, v0.4s, #0
; CHECK-BE-NEXT: ushll v0.2d, v0.2s, #0
; CHECK-BE-NEXT: st1 { v2.d }[1], [x9] ; CHECK-BE-NEXT: st1 { v2.d }[1], [x9]
; CHECK-BE-NEXT: add x9, x1, #88
; CHECK-BE-NEXT: st1 { v1.d }[1], [x9]
; CHECK-BE-NEXT: add x9, x1, #56 ; CHECK-BE-NEXT: add x9, x1, #56
; CHECK-BE-NEXT: str d2, [x1, #104] ; CHECK-BE-NEXT: str d2, [x1, #104]
; CHECK-BE-NEXT: ushll2 v2.2d, v0.4s, #0 ; CHECK-BE-NEXT: st1 { v3.d }[1], [x9]
; CHECK-BE-NEXT: st1 { v1.d }[1], [x10] ; CHECK-BE-NEXT: add x9, x1, #24
; CHECK-BE-NEXT: ushll v0.2d, v0.2s, #0
; CHECK-BE-NEXT: str d1, [x1, #72] ; CHECK-BE-NEXT: str d1, [x1, #72]
; CHECK-BE-NEXT: str d2, [x1, #40] ; CHECK-BE-NEXT: str d3, [x1, #40]
; CHECK-BE-NEXT: add x10, x1, #24
; CHECK-BE-NEXT: str d0, [x1, #8] ; CHECK-BE-NEXT: str d0, [x1, #8]
; CHECK-BE-NEXT: add x1, x1, #256 ; CHECK-BE-NEXT: add x1, x1, #256
; CHECK-BE-NEXT: st1 { v2.d }[1], [x9] ; CHECK-BE-NEXT: st1 { v0.d }[1], [x9]
; CHECK-BE-NEXT: st1 { v0.d }[1], [x10]
; CHECK-BE-NEXT: b.ne .LBB16_1 ; CHECK-BE-NEXT: b.ne .LBB16_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
Context not available.
; CHECK-NEXT: mov x8, xzr ; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: Lloh20: ; CHECK-NEXT: Lloh20:
; CHECK-NEXT: ldr q0, [x9, lCPI17_0@PAGEOFF] ; CHECK-NEXT: ldr q0, [x9, lCPI17_0@PAGEOFF]
; CHECK-NEXT: add x9, x0, #8
; CHECK-NEXT: Lloh21: ; CHECK-NEXT: Lloh21:
; CHECK-NEXT: ldr q1, [x10, lCPI17_1@PAGEOFF] ; CHECK-NEXT: ldr q1, [x10, lCPI17_1@PAGEOFF]
; CHECK-NEXT: add x9, x0, #8
; CHECK-NEXT: LBB17_1: ; %loop ; CHECK-NEXT: LBB17_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldp d2, d4, [x9, #-8]
; CHECK-NEXT: add x10, x1, x8 ; CHECK-NEXT: add x10, x1, x8
; CHECK-NEXT: ldp q6, q5, [x10, #32]
; CHECK-NEXT: add x8, x8, #128 ; CHECK-NEXT: add x8, x8, #128
; CHECK-NEXT: ldp d2, d3, [x9, #-8] ; CHECK-NEXT: ldp q17, q16, [x10]
; CHECK-NEXT: add x9, x9, #16
; CHECK-NEXT: cmp x8, #1024 ; CHECK-NEXT: cmp x8, #1024
; CHECK-NEXT: ldp q5, q4, [x10, #32] ; CHECK-NEXT: tbl.16b v3, { v2 }, v1
; CHECK-NEXT: tbl.16b v6, { v2 }, v1
; CHECK-NEXT: tbl.16b v2, { v2 }, v0 ; CHECK-NEXT: tbl.16b v2, { v2 }, v0
; CHECK-NEXT: tbl.16b v17, { v3 }, v0 ; CHECK-NEXT: tbl.16b v7, { v4 }, v1
; CHECK-NEXT: tbl.16b v3, { v3 }, v1 ; CHECK-NEXT: tbl.16b v4, { v4 }, v0
; CHECK-NEXT: ldp q16, q7, [x10] ; CHECK-NEXT: add x9, x9, #16
; CHECK-NEXT: uaddw2.2d v4, v4, v6 ; CHECK-NEXT: uaddw2.2d v5, v5, v3
; CHECK-NEXT: uaddw.2d v5, v5, v6 ; CHECK-NEXT: uaddw.2d v3, v6, v3
; CHECK-NEXT: stp q5, q4, [x10, #32] ; CHECK-NEXT: uaddw2.2d v6, v16, v2
; CHECK-NEXT: ldp q19, q18, [x10, #96] ; CHECK-NEXT: ldp q18, q16, [x10, #96]
; CHECK-NEXT: uaddw2.2d v7, v7, v2 ; CHECK-NEXT: uaddw.2d v2, v17, v2
; CHECK-NEXT: uaddw.2d v2, v16, v2 ; CHECK-NEXT: stp q3, q5, [x10, #32]
; CHECK-NEXT: stp q2, q7, [x10] ; CHECK-NEXT: ldp q17, q5, [x10, #64]
; CHECK-NEXT: ldp q6, q20, [x10, #64] ; CHECK-NEXT: uaddw2.2d v16, v16, v7
; CHECK-NEXT: uaddw2.2d v4, v18, v3 ; CHECK-NEXT: uaddw.2d v7, v18, v7
; CHECK-NEXT: uaddw.2d v3, v19, v3 ; CHECK-NEXT: stp q2, q6, [x10]
; CHECK-NEXT: stp q3, q4, [x10, #96] ; CHECK-NEXT: uaddw2.2d v3, v5, v4
; CHECK-NEXT: uaddw2.2d v2, v20, v17 ; CHECK-NEXT: uaddw.2d v4, v17, v4
; CHECK-NEXT: uaddw.2d v4, v6, v17 ; CHECK-NEXT: stp q7, q16, [x10, #96]
; CHECK-NEXT: stp q4, q2, [x10, #64] ; CHECK-NEXT: stp q4, q3, [x10, #64]
; CHECK-NEXT: b.ne LBB17_1 ; CHECK-NEXT: b.ne LBB17_1
; CHECK-NEXT: ; %bb.2: ; %exit ; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
Context not available.
; CHECK-BE-NEXT: add x9, x0, #8 ; CHECK-BE-NEXT: add x9, x0, #8
; CHECK-BE-NEXT: .LBB17_1: // %loop ; CHECK-BE-NEXT: .LBB17_1: // %loop
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: sub x12, x9, #8 ; CHECK-BE-NEXT: sub x10, x9, #8
; CHECK-BE-NEXT: add x10, x1, x8
; CHECK-BE-NEXT: ld1 { v2.8b }, [x9] ; CHECK-BE-NEXT: ld1 { v2.8b }, [x9]
; CHECK-BE-NEXT: add x9, x9, #16
; CHECK-BE-NEXT: ld1 { v3.8b }, [x10]
; CHECK-BE-NEXT: add x10, x1, x8
; CHECK-BE-NEXT: add x8, x8, #128
; CHECK-BE-NEXT: add x15, x10, #96
; CHECK-BE-NEXT: add x11, x10, #32 ; CHECK-BE-NEXT: add x11, x10, #32
; CHECK-BE-NEXT: add x13, x10, #48 ; CHECK-BE-NEXT: add x14, x10, #64
; CHECK-BE-NEXT: add x14, x10, #16 ; CHECK-BE-NEXT: tbl v4.16b, { v2.16b }, v1.16b
; CHECK-BE-NEXT: ld1 { v4.8b }, [x12]
; CHECK-BE-NEXT: add x15, x10, #64
; CHECK-BE-NEXT: ld1 { v3.2d }, [x11]
; CHECK-BE-NEXT: add x12, x10, #96
; CHECK-BE-NEXT: tbl v6.16b, { v2.16b }, v1.16b
; CHECK-BE-NEXT: add x16, x10, #112
; CHECK-BE-NEXT: tbl v2.16b, { v2.16b }, v0.16b ; CHECK-BE-NEXT: tbl v2.16b, { v2.16b }, v0.16b
; CHECK-BE-NEXT: ld1 { v7.2d }, [x13] ; CHECK-BE-NEXT: ld1 { v16.2d }, [x15]
; CHECK-BE-NEXT: tbl v16.16b, { v4.16b }, v0.16b ; CHECK-BE-NEXT: tbl v5.16b, { v3.16b }, v1.16b
; CHECK-BE-NEXT: tbl v3.16b, { v3.16b }, v0.16b
; CHECK-BE-NEXT: ld1 { v6.2d }, [x10]
; CHECK-BE-NEXT: ld1 { v19.2d }, [x14]
; CHECK-BE-NEXT: ld1 { v21.2d }, [x11]
; CHECK-BE-NEXT: add x12, x10, #48
; CHECK-BE-NEXT: add x13, x10, #16
; CHECK-BE-NEXT: add x16, x10, #112
; CHECK-BE-NEXT: add x17, x10, #80 ; CHECK-BE-NEXT: add x17, x10, #80
; CHECK-BE-NEXT: tbl v4.16b, { v4.16b }, v1.16b ; CHECK-BE-NEXT: rev32 v7.8b, v4.8b
; CHECK-BE-NEXT: ld1 { v18.2d }, [x14] ; CHECK-BE-NEXT: ext v4.16b, v4.16b, v4.16b, #8
; CHECK-BE-NEXT: rev32 v17.8b, v6.8b ; CHECK-BE-NEXT: rev32 v17.8b, v2.8b
; CHECK-BE-NEXT: add x8, x8, #128 ; CHECK-BE-NEXT: ext v18.16b, v5.16b, v5.16b, #8
; CHECK-BE-NEXT: ext v6.16b, v6.16b, v6.16b, #8 ; CHECK-BE-NEXT: ext v20.16b, v3.16b, v3.16b, #8
; CHECK-BE-NEXT: ld1 { v5.2d }, [x10] ; CHECK-BE-NEXT: ext v2.16b, v2.16b, v2.16b, #8
; CHECK-BE-NEXT: ext v23.16b, v16.16b, v16.16b, #8 ; CHECK-BE-NEXT: rev32 v5.8b, v5.8b
; CHECK-BE-NEXT: add x9, x9, #16 ; CHECK-BE-NEXT: rev32 v3.8b, v3.8b
; CHECK-BE-NEXT: ext v21.16b, v4.16b, v4.16b, #8
; CHECK-BE-NEXT: ld1 { v20.2d }, [x12]
; CHECK-BE-NEXT: rev32 v4.8b, v4.8b
; CHECK-BE-NEXT: cmp x8, #1024 ; CHECK-BE-NEXT: cmp x8, #1024
; CHECK-BE-NEXT: ext v19.16b, v2.16b, v2.16b, #8 ; CHECK-BE-NEXT: rev32 v4.8b, v4.8b
; CHECK-BE-NEXT: ld1 { v22.2d }, [x15] ; CHECK-BE-NEXT: uaddw v7.2d, v16.2d, v7.2s
; CHECK-BE-NEXT: ld1 { v16.2d }, [x16]
; CHECK-BE-NEXT: rev32 v18.8b, v18.8b
; CHECK-BE-NEXT: rev32 v20.8b, v20.8b
; CHECK-BE-NEXT: rev32 v2.8b, v2.8b ; CHECK-BE-NEXT: rev32 v2.8b, v2.8b
; CHECK-BE-NEXT: rev32 v21.8b, v21.8b ; CHECK-BE-NEXT: uaddw v17.2d, v19.2d, v17.2s
; CHECK-BE-NEXT: ld1 { v24.2d }, [x16] ; CHECK-BE-NEXT: ld1 { v19.2d }, [x12]
; CHECK-BE-NEXT: uaddw v3.2d, v3.2d, v4.2s ; CHECK-BE-NEXT: uaddw v5.2d, v21.2d, v5.2s
; CHECK-BE-NEXT: rev32 v4.8b, v23.8b ; CHECK-BE-NEXT: ld1 { v21.2d }, [x13]
; CHECK-BE-NEXT: ld1 { v23.2d }, [x17] ; CHECK-BE-NEXT: uaddw v3.2d, v6.2d, v3.2s
; CHECK-BE-NEXT: rev32 v16.8b, v16.8b ; CHECK-BE-NEXT: ld1 { v6.2d }, [x17]
; CHECK-BE-NEXT: rev32 v6.8b, v6.8b ; CHECK-BE-NEXT: uaddw v4.2d, v16.2d, v4.2s
; CHECK-BE-NEXT: rev32 v19.8b, v19.8b ; CHECK-BE-NEXT: st1 { v7.2d }, [x15]
; CHECK-BE-NEXT: st1 { v3.2d }, [x11] ; CHECK-BE-NEXT: uaddw v7.2d, v19.2d, v18.2s
; CHECK-BE-NEXT: uaddw v3.2d, v7.2d, v21.2s ; CHECK-BE-NEXT: uaddw v16.2d, v21.2d, v20.2s
; CHECK-BE-NEXT: uaddw v4.2d, v18.2d, v4.2s ; CHECK-BE-NEXT: uaddw v2.2d, v6.2d, v2.2s
; CHECK-BE-NEXT: uaddw v5.2d, v5.2d, v16.2s ; CHECK-BE-NEXT: st1 { v17.2d }, [x14]
; CHECK-BE-NEXT: uaddw v7.2d, v20.2d, v17.2s ; CHECK-BE-NEXT: st1 { v5.2d }, [x11]
; CHECK-BE-NEXT: st1 { v3.2d }, [x13] ; CHECK-BE-NEXT: st1 { v3.2d }, [x10]
; CHECK-BE-NEXT: uaddw v2.2d, v22.2d, v2.2s ; CHECK-BE-NEXT: st1 { v4.2d }, [x16]
; CHECK-BE-NEXT: st1 { v4.2d }, [x14]
; CHECK-BE-NEXT: uaddw v3.2d, v24.2d, v6.2s
; CHECK-BE-NEXT: st1 { v5.2d }, [x10]
; CHECK-BE-NEXT: uaddw v4.2d, v23.2d, v19.2s
; CHECK-BE-NEXT: st1 { v7.2d }, [x12] ; CHECK-BE-NEXT: st1 { v7.2d }, [x12]
; CHECK-BE-NEXT: st1 { v2.2d }, [x15] ; CHECK-BE-NEXT: st1 { v16.2d }, [x13]
; CHECK-BE-NEXT: st1 { v3.2d }, [x16] ; CHECK-BE-NEXT: st1 { v2.2d }, [x17]
; CHECK-BE-NEXT: st1 { v4.2d }, [x17]
; CHECK-BE-NEXT: b.ne .LBB17_1 ; CHECK-BE-NEXT: b.ne .LBB17_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
Context not available.
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: add x10, x0, x8 ; CHECK-NEXT: add x10, x0, x8
; CHECK-NEXT: add x8, x8, #16 ; CHECK-NEXT: add x8, x8, #16
; CHECK-NEXT: cmp x8, #128
; CHECK-NEXT: ldp q0, q1, [x10] ; CHECK-NEXT: ldp q0, q1, [x10]
; CHECK-NEXT: ushll.8h v2, v0, #0 ; CHECK-NEXT: cmp x8, #128
; CHECK-NEXT: ushll2.8h v0, v0, #0 ; CHECK-NEXT: ushll2.8h v2, v0, #0
; CHECK-NEXT: ushll.4s v4, v2, #0 ; CHECK-NEXT: ushll.8h v0, v0, #0
; CHECK-NEXT: ushll2.8h v6, v1, #0
; CHECK-NEXT: ushll.8h v1, v1, #0
; CHECK-NEXT: ushll2.4s v3, v2, #0
; CHECK-NEXT: ushll.4s v2, v2, #0
; CHECK-NEXT: ushll2.4s v5, v0, #0 ; CHECK-NEXT: ushll2.4s v5, v0, #0
; CHECK-NEXT: ushll2.4s v2, v2, #0
; CHECK-NEXT: ushll.4s v0, v0, #0 ; CHECK-NEXT: ushll.4s v0, v0, #0
; CHECK-NEXT: ushll2.2d v6, v5, #0 ; CHECK-NEXT: ushll2.2d v4, v3, #0
; CHECK-NEXT: ushll.2d v3, v3, #0
; CHECK-NEXT: ushll2.2d v7, v2, #0
; CHECK-NEXT: ushll.2d v2, v2, #0
; CHECK-NEXT: stp q3, q4, [x9, #-32]
; CHECK-NEXT: ushll2.2d v4, v5, #0
; CHECK-NEXT: ushll2.4s v3, v6, #0
; CHECK-NEXT: ushll.2d v5, v5, #0 ; CHECK-NEXT: ushll.2d v5, v5, #0
; CHECK-NEXT: ushll2.8h v3, v1, #0 ; CHECK-NEXT: stp q2, q7, [x9, #-64]
; CHECK-NEXT: ushll2.2d v7, v0, #0 ; CHECK-NEXT: ushll2.2d v7, v0, #0
; CHECK-NEXT: stp q5, q6, [x9, #-32]
; CHECK-NEXT: ushll.2d v0, v0, #0 ; CHECK-NEXT: ushll.2d v0, v0, #0
; CHECK-NEXT: ushll2.2d v5, v2, #0 ; CHECK-NEXT: ushll.4s v2, v6, #0
; CHECK-NEXT: ushll.2d v2, v2, #0 ; CHECK-NEXT: stp q5, q4, [x9, #-96]
; CHECK-NEXT: stp q0, q7, [x9, #-64] ; CHECK-NEXT: ushll2.2d v4, v3, #0
; CHECK-NEXT: ushll2.2d v0, v4, #0 ; CHECK-NEXT: ushll2.4s v5, v1, #0
; CHECK-NEXT: stp q2, q5, [x9, #-96] ; CHECK-NEXT: ushll.2d v3, v3, #0
; CHECK-NEXT: ushll2.4s v5, v3, #0 ; CHECK-NEXT: stp q0, q7, [x9, #-128]
; CHECK-NEXT: ushll.2d v2, v4, #0 ; CHECK-NEXT: ushll.4s v0, v1, #0
; CHECK-NEXT: ushll2.2d v4, v5, #0 ; CHECK-NEXT: ushll2.2d v6, v2, #0
; CHECK-NEXT: stp q2, q0, [x9, #-128] ; CHECK-NEXT: ushll.2d v1, v2, #0
; CHECK-NEXT: ushll.2d v0, v5, #0 ; CHECK-NEXT: ushll2.2d v2, v5, #0
; CHECK-NEXT: ushll.4s v2, v3, #0 ; CHECK-NEXT: stp q3, q4, [x9, #96]
; CHECK-NEXT: stp q0, q4, [x9, #96] ; CHECK-NEXT: ushll.2d v3, v5, #0
; CHECK-NEXT: ushll.8h v0, v1, #0 ; CHECK-NEXT: ushll2.2d v4, v0, #0
; CHECK-NEXT: ushll2.2d v1, v2, #0
; CHECK-NEXT: ushll.2d v2, v2, #0
; CHECK-NEXT: ushll2.4s v3, v0, #0
; CHECK-NEXT: stp q2, q1, [x9, #64]
; CHECK-NEXT: ushll2.2d v1, v3, #0
; CHECK-NEXT: ushll.2d v2, v3, #0
; CHECK-NEXT: ushll.4s v0, v0, #0
; CHECK-NEXT: stp q2, q1, [x9, #32]
; CHECK-NEXT: ushll2.2d v1, v0, #0
; CHECK-NEXT: ushll.2d v0, v0, #0 ; CHECK-NEXT: ushll.2d v0, v0, #0
; CHECK-NEXT: stp q0, q1, [x9], #128 ; CHECK-NEXT: stp q1, q6, [x9, #64]
; CHECK-NEXT: stp q3, q2, [x9, #32]
; CHECK-NEXT: stp q0, q4, [x9], #128
; CHECK-NEXT: b.ne LBB18_1 ; CHECK-NEXT: b.ne LBB18_1
; CHECK-NEXT: ; %bb.2: ; %exit ; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
Context not available.
; CHECK-BE-NEXT: .LBB18_1: // %loop ; CHECK-BE-NEXT: .LBB18_1: // %loop
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: add x10, x0, x8 ; CHECK-BE-NEXT: add x10, x0, x8
; CHECK-BE-NEXT: sub x11, x9, #32
; CHECK-BE-NEXT: add x8, x8, #16 ; CHECK-BE-NEXT: add x8, x8, #16
; CHECK-BE-NEXT: add x11, x10, #16
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ld1 { v0.16b }, [x10] ; CHECK-BE-NEXT: ld1 { v0.16b }, [x10]
; CHECK-BE-NEXT: add x10, x10, #16
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ld1 { v5.16b }, [x10]
; CHECK-BE-NEXT: sub x10, x9, #16 ; CHECK-BE-NEXT: sub x10, x9, #16
; CHECK-BE-NEXT: ld1 { v3.16b }, [x11]
; CHECK-BE-NEXT: sub x11, x9, #32
; CHECK-BE-NEXT: ushll2 v1.8h, v0.16b, #0 ; CHECK-BE-NEXT: ushll2 v1.8h, v0.16b, #0
; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-BE-NEXT: ushll2 v2.4s, v1.8h, #0 ; CHECK-BE-NEXT: ushll2 v2.4s, v1.8h, #0
; CHECK-BE-NEXT: ushll2 v3.4s, v0.8h, #0
; CHECK-BE-NEXT: ushll v1.4s, v1.4h, #0 ; CHECK-BE-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-BE-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-BE-NEXT: ushll2 v4.2d, v2.4s, #0 ; CHECK-BE-NEXT: ushll2 v4.2d, v2.4s, #0
; CHECK-BE-NEXT: ushll v2.2d, v2.2s, #0 ; CHECK-BE-NEXT: ushll v2.2d, v2.2s, #0
; CHECK-BE-NEXT: ushll2 v6.2d, v1.4s, #0
; CHECK-BE-NEXT: ushll v1.2d, v1.2s, #0
; CHECK-BE-NEXT: st1 { v4.2d }, [x10] ; CHECK-BE-NEXT: st1 { v4.2d }, [x10]
; CHECK-BE-NEXT: sub x10, x9, #48 ; CHECK-BE-NEXT: ushll2 v4.2d, v3.4s, #0
; CHECK-BE-NEXT: ushll2 v4.2d, v1.4s, #0 ; CHECK-BE-NEXT: ushll v3.2d, v3.2s, #0
; CHECK-BE-NEXT: st1 { v2.2d }, [x11] ; CHECK-BE-NEXT: st1 { v2.2d }, [x11]
; CHECK-BE-NEXT: ushll2 v2.4s, v0.8h, #0 ; CHECK-BE-NEXT: ushll2 v2.8h, v5.16b, #0
; CHECK-BE-NEXT: sub x11, x9, #80 ; CHECK-BE-NEXT: sub x11, x9, #80
; CHECK-BE-NEXT: st1 { v4.2d }, [x10] ; CHECK-BE-NEXT: sub x10, x9, #48
; CHECK-BE-NEXT: sub x10, x9, #64 ; CHECK-BE-NEXT: st1 { v4.2d }, [x11]
; CHECK-BE-NEXT: ushll2 v5.2d, v2.4s, #0 ; CHECK-BE-NEXT: ushll v4.8h, v5.8b, #0
; CHECK-BE-NEXT: ushll v1.2d, v1.2s, #0 ; CHECK-BE-NEXT: sub x11, x9, #64
; CHECK-BE-NEXT: ushll v0.4s, v0.4h, #0 ; CHECK-BE-NEXT: ushll2 v5.4s, v2.8h, #0
; CHECK-BE-NEXT: st1 { v5.2d }, [x11] ; CHECK-BE-NEXT: st1 { v1.2d }, [x11]
; CHECK-BE-NEXT: sub x11, x9, #96 ; CHECK-BE-NEXT: sub x11, x9, #96
; CHECK-BE-NEXT: st1 { v1.2d }, [x10] ; CHECK-BE-NEXT: ushll2 v1.2d, v0.4s, #0
; CHECK-BE-NEXT: ushll v4.8h, v3.8b, #0 ; CHECK-BE-NEXT: ushll v2.4s, v2.4h, #0
; CHECK-BE-NEXT: sub x10, x9, #112 ; CHECK-BE-NEXT: ushll v0.2d, v0.2s, #0
; CHECK-BE-NEXT: ushll2 v3.8h, v3.16b, #0 ; CHECK-BE-NEXT: st1 { v6.2d }, [x10]
; CHECK-BE-NEXT: ushll v5.2d, v0.2s, #0 ; CHECK-BE-NEXT: sub x10, x9, #128
; CHECK-BE-NEXT: ushll2 v0.2d, v0.4s, #0 ; CHECK-BE-NEXT: st1 { v3.2d }, [x11]
; CHECK-BE-NEXT: ushll v2.2d, v2.2s, #0 ; CHECK-BE-NEXT: ushll2 v3.4s, v4.8h, #0
; CHECK-BE-NEXT: ushll v1.4s, v4.4h, #0 ; CHECK-BE-NEXT: ushll2 v6.2d, v5.4s, #0
; CHECK-BE-NEXT: sub x11, x9, #112
; CHECK-BE-NEXT: ushll v5.2d, v5.2s, #0
; CHECK-BE-NEXT: st1 { v0.2d }, [x10] ; CHECK-BE-NEXT: st1 { v0.2d }, [x10]
; CHECK-BE-NEXT: ushll2 v6.4s, v3.8h, #0 ; CHECK-BE-NEXT: st1 { v1.2d }, [x11]
; CHECK-BE-NEXT: st1 { v2.2d }, [x11] ; CHECK-BE-NEXT: ushll2 v1.2d, v2.4s, #0
; CHECK-BE-NEXT: sub x11, x9, #128
; CHECK-BE-NEXT: add x10, x9, #112 ; CHECK-BE-NEXT: add x10, x9, #112
; CHECK-BE-NEXT: ushll v2.2d, v1.2s, #0 ; CHECK-BE-NEXT: ushll v4.4s, v4.4h, #0
; CHECK-BE-NEXT: ushll2 v0.2d, v1.4s, #0 ; CHECK-BE-NEXT: ushll2 v0.2d, v3.4s, #0
; CHECK-BE-NEXT: ushll2 v1.2d, v6.4s, #0 ; CHECK-BE-NEXT: st1 { v6.2d }, [x10]
; CHECK-BE-NEXT: st1 { v5.2d }, [x11] ; CHECK-BE-NEXT: add x10, x9, #96
; CHECK-BE-NEXT: ushll v3.4s, v3.4h, #0 ; CHECK-BE-NEXT: ushll v2.2d, v2.2s, #0
; CHECK-BE-NEXT: add x11, x9, #96 ; CHECK-BE-NEXT: ushll v3.2d, v3.2s, #0
; CHECK-BE-NEXT: st1 { v1.2d }, [x10] ; CHECK-BE-NEXT: st1 { v5.2d }, [x10]
; CHECK-BE-NEXT: add x10, x9, #80 ; CHECK-BE-NEXT: add x10, x9, #80
; CHECK-BE-NEXT: ushll v5.2d, v6.2s, #0 ; CHECK-BE-NEXT: st1 { v1.2d }, [x10]
; CHECK-BE-NEXT: st1 { v2.2d }, [x9] ; CHECK-BE-NEXT: add x10, x9, #48
; CHECK-BE-NEXT: ushll2 v1.4s, v4.8h, #0 ; CHECK-BE-NEXT: ushll2 v1.2d, v4.4s, #0
; CHECK-BE-NEXT: ushll2 v4.2d, v3.4s, #0 ; CHECK-BE-NEXT: st1 { v0.2d }, [x10]
; CHECK-BE-NEXT: st1 { v5.2d }, [x11] ; CHECK-BE-NEXT: ushll v0.2d, v4.2s, #0
; CHECK-BE-NEXT: add x11, x9, #48
; CHECK-BE-NEXT: st1 { v4.2d }, [x10]
; CHECK-BE-NEXT: add x10, x9, #64 ; CHECK-BE-NEXT: add x10, x9, #64
; CHECK-BE-NEXT: ushll2 v5.2d, v1.4s, #0 ; CHECK-BE-NEXT: st1 { v2.2d }, [x10]
; CHECK-BE-NEXT: ushll v3.2d, v3.2s, #0
; CHECK-BE-NEXT: st1 { v5.2d }, [x11]
; CHECK-BE-NEXT: add x11, x9, #16
; CHECK-BE-NEXT: st1 { v3.2d }, [x10]
; CHECK-BE-NEXT: add x10, x9, #32 ; CHECK-BE-NEXT: add x10, x9, #32
; CHECK-BE-NEXT: st1 { v3.2d }, [x10]
; CHECK-BE-NEXT: add x10, x9, #16
; CHECK-BE-NEXT: st1 { v0.2d }, [x9]
; CHECK-BE-NEXT: add x9, x9, #128 ; CHECK-BE-NEXT: add x9, x9, #128
; CHECK-BE-NEXT: ushll v1.2d, v1.2s, #0
; CHECK-BE-NEXT: st1 { v0.2d }, [x11]
; CHECK-BE-NEXT: st1 { v1.2d }, [x10] ; CHECK-BE-NEXT: st1 { v1.2d }, [x10]
; CHECK-BE-NEXT: b.ne .LBB18_1 ; CHECK-BE-NEXT: b.ne .LBB18_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
Context not available.
define void @zext_v16i8_to_v16i32_in_loop_scalable_vectors(ptr %src, ptr %dst) { define void @zext_v16i8_to_v16i32_in_loop_scalable_vectors(ptr %src, ptr %dst) {
; CHECK-LABEL: zext_v16i8_to_v16i32_in_loop_scalable_vectors: ; CHECK-LABEL: zext_v16i8_to_v16i32_in_loop_scalable_vectors:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: LBB19_1: ; %loop ; CHECK-NEXT: LBB19_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: add x9, x0, x8
; CHECK-NEXT: ld1b { z0.s }, p0/z, [x0, x8] ; CHECK-NEXT: ld1b { z0.s }, p0/z, [x0, x8]
; CHECK-NEXT: add x9, x0, x8
; CHECK-NEXT: ld1b { z1.s }, p0/z, [x9, #2, mul vl] ; CHECK-NEXT: ld1b { z1.s }, p0/z, [x9, #2, mul vl]
; CHECK-NEXT: ld1b { z2.s }, p0/z, [x9, #3, mul vl] ; CHECK-NEXT: ld1b { z2.s }, p0/z, [x9, #3, mul vl]
; CHECK-NEXT: ld1b { z3.s }, p0/z, [x9, #1, mul vl] ; CHECK-NEXT: ld1b { z3.s }, p0/z, [x9, #1, mul vl]
; CHECK-NEXT: add z0.s, z0.s, z0.s
; CHECK-NEXT: add x9, x1, x8, lsl #2 ; CHECK-NEXT: add x9, x1, x8, lsl #2
; CHECK-NEXT: add z0.s, z0.s, z0.s
; CHECK-NEXT: add z1.s, z1.s, z1.s
; CHECK-NEXT: add z2.s, z2.s, z2.s
; CHECK-NEXT: add z3.s, z3.s, z3.s
; CHECK-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2] ; CHECK-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2]
; CHECK-NEXT: add x8, x8, #16 ; CHECK-NEXT: add x8, x8, #16
; CHECK-NEXT: cmp x8, #128 ; CHECK-NEXT: cmp x8, #128
; CHECK-NEXT: add z1.s, z1.s, z1.s
; CHECK-NEXT: add z0.s, z3.s, z3.s
; CHECK-NEXT: add z2.s, z2.s, z2.s
; CHECK-NEXT: st1w { z1.s }, p0, [x9, #2, mul vl] ; CHECK-NEXT: st1w { z1.s }, p0, [x9, #2, mul vl]
; CHECK-NEXT: st1w { z2.s }, p0, [x9, #3, mul vl] ; CHECK-NEXT: st1w { z2.s }, p0, [x9, #3, mul vl]
; CHECK-NEXT: st1w { z0.s }, p0, [x9, #1, mul vl] ; CHECK-NEXT: st1w { z3.s }, p0, [x9, #1, mul vl]
; CHECK-NEXT: b.ne LBB19_1 ; CHECK-NEXT: b.ne LBB19_1
; CHECK-NEXT: ; %bb.2: ; %exit ; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; CHECK-BE-LABEL: zext_v16i8_to_v16i32_in_loop_scalable_vectors: ; CHECK-BE-LABEL: zext_v16i8_to_v16i32_in_loop_scalable_vectors:
; CHECK-BE: // %bb.0: // %entry ; CHECK-BE: // %bb.0: // %entry
; CHECK-BE-NEXT: mov x8, xzr
; CHECK-BE-NEXT: ptrue p0.s ; CHECK-BE-NEXT: ptrue p0.s
; CHECK-BE-NEXT: mov x8, xzr
; CHECK-BE-NEXT: .LBB19_1: // %loop ; CHECK-BE-NEXT: .LBB19_1: // %loop
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: add x9, x0, x8
; CHECK-BE-NEXT: ld1b { z0.s }, p0/z, [x0, x8] ; CHECK-BE-NEXT: ld1b { z0.s }, p0/z, [x0, x8]
; CHECK-BE-NEXT: add x9, x0, x8
; CHECK-BE-NEXT: ld1b { z1.s }, p0/z, [x9, #2, mul vl] ; CHECK-BE-NEXT: ld1b { z1.s }, p0/z, [x9, #2, mul vl]
; CHECK-BE-NEXT: ld1b { z2.s }, p0/z, [x9, #3, mul vl] ; CHECK-BE-NEXT: ld1b { z2.s }, p0/z, [x9, #3, mul vl]
; CHECK-BE-NEXT: ld1b { z3.s }, p0/z, [x9, #1, mul vl] ; CHECK-BE-NEXT: ld1b { z3.s }, p0/z, [x9, #1, mul vl]
; CHECK-BE-NEXT: add z0.s, z0.s, z0.s
; CHECK-BE-NEXT: add x9, x1, x8, lsl #2 ; CHECK-BE-NEXT: add x9, x1, x8, lsl #2
; CHECK-BE-NEXT: add z0.s, z0.s, z0.s
; CHECK-BE-NEXT: add z1.s, z1.s, z1.s
; CHECK-BE-NEXT: add z2.s, z2.s, z2.s
; CHECK-BE-NEXT: add z3.s, z3.s, z3.s
; CHECK-BE-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2] ; CHECK-BE-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2]
; CHECK-BE-NEXT: add x8, x8, #16 ; CHECK-BE-NEXT: add x8, x8, #16
; CHECK-BE-NEXT: cmp x8, #128 ; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: add z1.s, z1.s, z1.s
; CHECK-BE-NEXT: add z0.s, z3.s, z3.s
; CHECK-BE-NEXT: add z2.s, z2.s, z2.s
; CHECK-BE-NEXT: st1w { z1.s }, p0, [x9, #2, mul vl] ; CHECK-BE-NEXT: st1w { z1.s }, p0, [x9, #2, mul vl]
; CHECK-BE-NEXT: st1w { z2.s }, p0, [x9, #3, mul vl] ; CHECK-BE-NEXT: st1w { z2.s }, p0, [x9, #3, mul vl]
; CHECK-BE-NEXT: st1w { z0.s }, p0, [x9, #1, mul vl] ; CHECK-BE-NEXT: st1w { z3.s }, p0, [x9, #1, mul vl]
; CHECK-BE-NEXT: b.ne .LBB19_1 ; CHECK-BE-NEXT: b.ne .LBB19_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
Context not available.
; CHECK-LABEL: zext_v20i8_to_v20i24_in_loop: ; CHECK-LABEL: zext_v20i8_to_v20i24_in_loop:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: Lloh22: ; CHECK-NEXT: Lloh22:
; CHECK-NEXT: adrp x9, lCPI20_0@PAGE ; CHECK-NEXT: adrp x8, lCPI20_0@PAGE
; CHECK-NEXT: Lloh23: ; CHECK-NEXT: Lloh23:
; CHECK-NEXT: adrp x10, lCPI20_1@PAGE ; CHECK-NEXT: adrp x9, lCPI20_1@PAGE
; CHECK-NEXT: Lloh24: ; CHECK-NEXT: Lloh24:
; CHECK-NEXT: adrp x11, lCPI20_2@PAGE ; CHECK-NEXT: adrp x10, lCPI20_2@PAGE
; CHECK-NEXT: Lloh25: ; CHECK-NEXT: Lloh25:
; CHECK-NEXT: adrp x12, lCPI20_3@PAGE ; CHECK-NEXT: ldr q0, [x8, lCPI20_0@PAGEOFF]
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: Lloh26: ; CHECK-NEXT: Lloh26:
; CHECK-NEXT: ldr q0, [x9, lCPI20_0@PAGEOFF] ; CHECK-NEXT: adrp x8, lCPI20_3@PAGE
; CHECK-NEXT: Lloh27: ; CHECK-NEXT: Lloh27:
; CHECK-NEXT: ldr q1, [x10, lCPI20_1@PAGEOFF] ; CHECK-NEXT: ldr q1, [x9, lCPI20_1@PAGEOFF]
; CHECK-NEXT: Lloh28: ; CHECK-NEXT: Lloh28:
; CHECK-NEXT: ldr q2, [x11, lCPI20_2@PAGEOFF] ; CHECK-NEXT: ldr q2, [x10, lCPI20_2@PAGEOFF]
; CHECK-NEXT: Lloh29: ; CHECK-NEXT: Lloh29:
; CHECK-NEXT: ldr q3, [x12, lCPI20_3@PAGEOFF] ; CHECK-NEXT: ldr q3, [x8, lCPI20_3@PAGEOFF]
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: LBB20_1: ; %loop ; CHECK-NEXT: LBB20_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: add x9, x0, x8 ; CHECK-NEXT: add x9, x0, x8
; CHECK-NEXT: add x8, x8, #16 ; CHECK-NEXT: add x8, x8, #16
; CHECK-NEXT: cmp x8, #128 ; CHECK-NEXT: ldp q5, q4, [x9]
; CHECK-NEXT: ldp q4, q5, [x9]
; CHECK-NEXT: add x9, x1, #56 ; CHECK-NEXT: add x9, x1, #56
; CHECK-NEXT: tbl.16b v6, { v4 }, v2 ; CHECK-NEXT: cmp x8, #128
; CHECK-NEXT: tbl.16b v7, { v4 }, v1 ; CHECK-NEXT: tbl.16b v4, { v4 }, v3
; CHECK-NEXT: tbl.16b v4, { v4 }, v0 ; CHECK-NEXT: tbl.16b v6, { v5 }, v2
; CHECK-NEXT: tbl.16b v5, { v5 }, v3 ; CHECK-NEXT: tbl.16b v7, { v5 }, v1
; CHECK-NEXT: tbl.16b v5, { v5 }, v0
; CHECK-NEXT: stp q7, q6, [x1, #16] ; CHECK-NEXT: stp q7, q6, [x1, #16]
; CHECK-NEXT: str q4, [x1] ; CHECK-NEXT: str q5, [x1]
; CHECK-NEXT: str d5, [x1, #48] ; CHECK-NEXT: str d4, [x1, #48]
; CHECK-NEXT: add x1, x1, #64 ; CHECK-NEXT: add x1, x1, #64
; CHECK-NEXT: st1.s { v5 }[2], [x9] ; CHECK-NEXT: st1.s { v4 }[2], [x9]
; CHECK-NEXT: b.ne LBB20_1 ; CHECK-NEXT: b.ne LBB20_1
; CHECK-NEXT: ; %bb.2: ; %exit ; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh25, Lloh29 ; CHECK-NEXT: .loh AdrpLdr Lloh26, Lloh29
; CHECK-NEXT: .loh AdrpLdr Lloh24, Lloh28 ; CHECK-NEXT: .loh AdrpLdr Lloh24, Lloh28
; CHECK-NEXT: .loh AdrpLdr Lloh23, Lloh27 ; CHECK-NEXT: .loh AdrpLdr Lloh23, Lloh27
; CHECK-NEXT: .loh AdrpLdr Lloh22, Lloh26 ; CHECK-NEXT: .loh AdrpAdrp Lloh22, Lloh26
; CHECK-NEXT: .loh AdrpLdr Lloh22, Lloh25
; ;
; CHECK-BE-LABEL: zext_v20i8_to_v20i24_in_loop: ; CHECK-BE-LABEL: zext_v20i8_to_v20i24_in_loop:
; CHECK-BE: // %bb.0: // %entry ; CHECK-BE: // %bb.0: // %entry
Context not available.
; CHECK-BE-NEXT: add x9, x0, x8 ; CHECK-BE-NEXT: add x9, x0, x8
; CHECK-BE-NEXT: add x8, x8, #16 ; CHECK-BE-NEXT: add x8, x8, #16
; CHECK-BE-NEXT: add x10, x9, #16 ; CHECK-BE-NEXT: add x10, x9, #16
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ld1 { v5.16b }, [x9] ; CHECK-BE-NEXT: ld1 { v5.16b }, [x9]
; CHECK-BE-NEXT: add x9, x1, #32 ; CHECK-BE-NEXT: add x9, x1, #32
; CHECK-BE-NEXT: ld1 { v4.16b }, [x10] ; CHECK-BE-NEXT: ld1 { v4.16b }, [x10]
; CHECK-BE-NEXT: add x10, x1, #56 ; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: tbl v6.16b, { v5.16b }, v3.16b ; CHECK-BE-NEXT: tbl v6.16b, { v5.16b }, v3.16b
; CHECK-BE-NEXT: tbl v7.16b, { v5.16b }, v1.16b ; CHECK-BE-NEXT: tbl v7.16b, { v5.16b }, v2.16b
; CHECK-BE-NEXT: tbl v5.16b, { v5.16b }, v1.16b
; CHECK-BE-NEXT: tbl v4.16b, { v4.16b }, v0.16b ; CHECK-BE-NEXT: tbl v4.16b, { v4.16b }, v0.16b
; CHECK-BE-NEXT: tbl v5.16b, { v5.16b }, v2.16b
; CHECK-BE-NEXT: st1 { v6.16b }, [x9] ; CHECK-BE-NEXT: st1 { v6.16b }, [x9]
; CHECK-BE-NEXT: add x9, x1, #16 ; CHECK-BE-NEXT: add x9, x1, #16
; CHECK-BE-NEXT: st1 { v7.16b }, [x1] ; CHECK-BE-NEXT: rev32 v16.16b, v4.16b
; CHECK-BE-NEXT: rev64 v16.16b, v4.16b ; CHECK-BE-NEXT: rev64 v4.16b, v4.16b
; CHECK-BE-NEXT: rev32 v4.16b, v4.16b ; CHECK-BE-NEXT: st1 { v7.16b }, [x9]
; CHECK-BE-NEXT: st1 { v5.16b }, [x9] ; CHECK-BE-NEXT: add x9, x1, #56
; CHECK-BE-NEXT: str d16, [x1, #48] ; CHECK-BE-NEXT: st1 { v5.16b }, [x1]
; CHECK-BE-NEXT: str d4, [x1, #48]
; CHECK-BE-NEXT: add x1, x1, #64 ; CHECK-BE-NEXT: add x1, x1, #64
; CHECK-BE-NEXT: st1 { v4.s }[2], [x10] ; CHECK-BE-NEXT: st1 { v16.s }[2], [x9]
; CHECK-BE-NEXT: b.ne .LBB20_1 ; CHECK-BE-NEXT: b.ne .LBB20_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
Context not available.
; CHECK-LABEL: zext_v23i8_to_v23i48_in_loop: ; CHECK-LABEL: zext_v23i8_to_v23i48_in_loop:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: Lloh30: ; CHECK-NEXT: Lloh30:
; CHECK-NEXT: adrp x9, lCPI21_0@PAGE ; CHECK-NEXT: adrp x8, lCPI21_0@PAGE
; CHECK-NEXT: Lloh31: ; CHECK-NEXT: Lloh31:
; CHECK-NEXT: adrp x10, lCPI21_1@PAGE ; CHECK-NEXT: adrp x9, lCPI21_1@PAGE
; CHECK-NEXT: Lloh32: ; CHECK-NEXT: Lloh32:
; CHECK-NEXT: adrp x11, lCPI21_2@PAGE ; CHECK-NEXT: adrp x10, lCPI21_2@PAGE
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: Lloh33: ; CHECK-NEXT: Lloh33:
; CHECK-NEXT: ldr q0, [x9, lCPI21_0@PAGEOFF] ; CHECK-NEXT: ldr q0, [x8, lCPI21_0@PAGEOFF]
; CHECK-NEXT: Lloh34: ; CHECK-NEXT: Lloh34:
; CHECK-NEXT: adrp x9, lCPI21_3@PAGE ; CHECK-NEXT: ldr q1, [x9, lCPI21_1@PAGEOFF]
; CHECK-NEXT: Lloh35: ; CHECK-NEXT: Lloh35:
; CHECK-NEXT: ldr q1, [x10, lCPI21_1@PAGEOFF] ; CHECK-NEXT: ldr q2, [x10, lCPI21_2@PAGEOFF]
; CHECK-NEXT: Lloh36: ; CHECK-NEXT: Lloh36:
; CHECK-NEXT: adrp x10, lCPI21_4@PAGE ; CHECK-NEXT: adrp x8, lCPI21_3@PAGE
; CHECK-NEXT: Lloh37: ; CHECK-NEXT: Lloh37:
; CHECK-NEXT: ldr q2, [x11, lCPI21_2@PAGEOFF] ; CHECK-NEXT: adrp x9, lCPI21_4@PAGE
; CHECK-NEXT: Lloh38: ; CHECK-NEXT: Lloh38:
; CHECK-NEXT: adrp x11, lCPI21_5@PAGE ; CHECK-NEXT: adrp x10, lCPI21_5@PAGE
; CHECK-NEXT: Lloh39: ; CHECK-NEXT: Lloh39:
; CHECK-NEXT: ldr q3, [x9, lCPI21_3@PAGEOFF] ; CHECK-NEXT: ldr q3, [x8, lCPI21_3@PAGEOFF]
; CHECK-NEXT: Lloh40: ; CHECK-NEXT: Lloh40:
; CHECK-NEXT: ldr q4, [x10, lCPI21_4@PAGEOFF] ; CHECK-NEXT: ldr q4, [x9, lCPI21_4@PAGEOFF]
; CHECK-NEXT: Lloh41: ; CHECK-NEXT: Lloh41:
; CHECK-NEXT: ldr q5, [x11, lCPI21_5@PAGEOFF] ; CHECK-NEXT: ldr q5, [x10, lCPI21_5@PAGEOFF]
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: LBB21_1: ; %loop ; CHECK-NEXT: LBB21_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: add x9, x0, x8 ; CHECK-NEXT: add x9, x0, x8
; CHECK-NEXT: movi.2d v19, #0000000000000000
; CHECK-NEXT: add x8, x8, #16 ; CHECK-NEXT: add x8, x8, #16
; CHECK-NEXT: movi.2d v6, #0000000000000000 ; CHECK-NEXT: ldp q7, q6, [x9]
; CHECK-NEXT: cmp x8, #128 ; CHECK-NEXT: cmp x8, #128
; CHECK-NEXT: ldp q16, q7, [x9]
; CHECK-NEXT: strh wzr, [x1, #136] ; CHECK-NEXT: strh wzr, [x1, #136]
; CHECK-NEXT: tbl.16b v18, { v16 }, v5 ; CHECK-NEXT: tbl.16b v16, { v6 }, v1
; CHECK-NEXT: tbl.16b v19, { v16 }, v4 ; CHECK-NEXT: tbl.16b v17, { v6 }, v0
; CHECK-NEXT: mov.b v6[4], v7[6] ; CHECK-NEXT: mov.b v19[4], v6[6]
; CHECK-NEXT: tbl.16b v18, { v7 }, v5
; CHECK-NEXT: tbl.16b v20, { v7 }, v4
; CHECK-NEXT: tbl.16b v21, { v7 }, v3
; CHECK-NEXT: stp q17, q16, [x1, #96]
; CHECK-NEXT: tbl.16b v16, { v7 }, v2
; CHECK-NEXT: tbl.16b v17, { v7 }, v1 ; CHECK-NEXT: tbl.16b v17, { v7 }, v1
; CHECK-NEXT: tbl.16b v7, { v7 }, v0 ; CHECK-NEXT: tbl.16b v7, { v7 }, v0
; CHECK-NEXT: tbl.16b v20, { v16 }, v3 ; CHECK-NEXT: fmov x9, d19
; CHECK-NEXT: stp q19, q18, [x1, #64] ; CHECK-NEXT: stp q20, q18, [x1, #64]
; CHECK-NEXT: fmov x9, d6 ; CHECK-NEXT: stp q16, q21, [x1, #32]
; CHECK-NEXT: stp q7, q17, [x1, #96] ; CHECK-NEXT: stp q7, q17, [x1]
; CHECK-NEXT: tbl.16b v17, { v16 }, v2
; CHECK-NEXT: tbl.16b v7, { v16 }, v1
; CHECK-NEXT: tbl.16b v16, { v16 }, v0
; CHECK-NEXT: stp q17, q20, [x1, #32]
; CHECK-NEXT: stp q16, q7, [x1]
; CHECK-NEXT: str x9, [x1, #128]! ; CHECK-NEXT: str x9, [x1, #128]!
; CHECK-NEXT: b.ne LBB21_1 ; CHECK-NEXT: b.ne LBB21_1
; CHECK-NEXT: ; %bb.2: ; %exit ; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh38, Lloh41 ; CHECK-NEXT: .loh AdrpLdr Lloh38, Lloh41
; CHECK-NEXT: .loh AdrpLdr Lloh36, Lloh40 ; CHECK-NEXT: .loh AdrpLdr Lloh37, Lloh40
; CHECK-NEXT: .loh AdrpLdr Lloh34, Lloh39 ; CHECK-NEXT: .loh AdrpLdr Lloh36, Lloh39
; CHECK-NEXT: .loh AdrpAdrp Lloh32, Lloh38 ; CHECK-NEXT: .loh AdrpAdrp Lloh32, Lloh38
; CHECK-NEXT: .loh AdrpLdr Lloh32, Lloh37 ; CHECK-NEXT: .loh AdrpLdr Lloh32, Lloh35
; CHECK-NEXT: .loh AdrpAdrp Lloh31, Lloh36 ; CHECK-NEXT: .loh AdrpAdrp Lloh31, Lloh37
; CHECK-NEXT: .loh AdrpLdr Lloh31, Lloh35 ; CHECK-NEXT: .loh AdrpLdr Lloh31, Lloh34
; CHECK-NEXT: .loh AdrpAdrp Lloh30, Lloh34 ; CHECK-NEXT: .loh AdrpAdrp Lloh30, Lloh36
; CHECK-NEXT: .loh AdrpLdr Lloh30, Lloh33 ; CHECK-NEXT: .loh AdrpLdr Lloh30, Lloh33
; ;
; CHECK-BE-LABEL: zext_v23i8_to_v23i48_in_loop: ; CHECK-BE-LABEL: zext_v23i8_to_v23i48_in_loop:
Context not available.
; CHECK-BE-NEXT: .LBB21_1: // %loop ; CHECK-BE-NEXT: .LBB21_1: // %loop
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: add x9, x0, x8 ; CHECK-BE-NEXT: add x9, x0, x8
; CHECK-BE-NEXT: add x11, x1, #64
; CHECK-BE-NEXT: add x10, x1, #80
; CHECK-BE-NEXT: add x8, x8, #16 ; CHECK-BE-NEXT: add x8, x8, #16
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ld1 { v7.16b }, [x9] ; CHECK-BE-NEXT: ld1 { v7.16b }, [x9]
; CHECK-BE-NEXT: add x9, x9, #16 ; CHECK-BE-NEXT: add x9, x9, #16
; CHECK-BE-NEXT: ld1 { v18.16b }, [x9] ; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: add x9, x1, #48 ; CHECK-BE-NEXT: ld1 { v17.16b }, [x9]
; CHECK-BE-NEXT: tbl v17.16b, { v7.16b }, v5.16b ; CHECK-BE-NEXT: add x9, x1, #80
; CHECK-BE-NEXT: tbl v16.16b, { v7.16b }, v6.16b ; CHECK-BE-NEXT: tbl v16.16b, { v7.16b }, v6.16b
; CHECK-BE-NEXT: tbl v19.16b, { v7.16b }, v3.16b ; CHECK-BE-NEXT: tbl v18.16b, { v7.16b }, v5.16b
; CHECK-BE-NEXT: tbl v20.16b, { v18.16b }, v0.16b ; CHECK-BE-NEXT: tbl v19.16b, { v7.16b }, v4.16b
; CHECK-BE-NEXT: st1 { v17.16b }, [x11] ; CHECK-BE-NEXT: tbl v20.16b, { v7.16b }, v3.16b
; CHECK-BE-NEXT: add x11, x1, #16 ; CHECK-BE-NEXT: tbl v21.16b, { v17.16b }, v0.16b
; CHECK-BE-NEXT: tbl v17.16b, { v7.16b }, v4.16b ; CHECK-BE-NEXT: st1 { v16.16b }, [x9]
; CHECK-BE-NEXT: st1 { v16.16b }, [x10] ; CHECK-BE-NEXT: add x9, x1, #64
; CHECK-BE-NEXT: add x10, x1, #32 ; CHECK-BE-NEXT: tbl v16.16b, { v7.16b }, v2.16b
; CHECK-BE-NEXT: tbl v16.16b, { v7.16b }, v1.16b ; CHECK-BE-NEXT: st1 { v18.16b }, [x9]
; CHECK-BE-NEXT: tbl v7.16b, { v7.16b }, v2.16b ; CHECK-BE-NEXT: add x9, x1, #48
; CHECK-BE-NEXT: tbl v21.16b, { v18.16b }, v1.16b ; CHECK-BE-NEXT: tbl v18.16b, { v17.16b }, v2.16b
; CHECK-BE-NEXT: st1 { v17.16b }, [x9] ; CHECK-BE-NEXT: st1 { v19.16b }, [x9]
; CHECK-BE-NEXT: tbl v17.16b, { v18.16b }, v2.16b ; CHECK-BE-NEXT: add x9, x1, #32
; CHECK-BE-NEXT: tbl v17.16b, { v17.16b }, v1.16b
; CHECK-BE-NEXT: st1 { v20.16b }, [x9]
; CHECK-BE-NEXT: add x9, x1, #16
; CHECK-BE-NEXT: rev64 v19.16b, v21.16b
; CHECK-BE-NEXT: st1 { v16.16b }, [x9]
; CHECK-BE-NEXT: rev16 v16.16b, v21.16b
; CHECK-BE-NEXT: add x9, x1, #112 ; CHECK-BE-NEXT: add x9, x1, #112
; CHECK-BE-NEXT: rev64 v18.16b, v20.16b ; CHECK-BE-NEXT: st1 { v18.16b }, [x9]
; CHECK-BE-NEXT: st1 { v19.16b }, [x10] ; CHECK-BE-NEXT: add x9, x1, #96
; CHECK-BE-NEXT: rev16 v19.16b, v20.16b ; CHECK-BE-NEXT: tbl v7.16b, { v7.16b }, v1.16b
; CHECK-BE-NEXT: add x10, x1, #96
; CHECK-BE-NEXT: st1 { v7.16b }, [x11]
; CHECK-BE-NEXT: add x11, x1, #136
; CHECK-BE-NEXT: st1 { v17.16b }, [x9] ; CHECK-BE-NEXT: st1 { v17.16b }, [x9]
; CHECK-BE-NEXT: fmov x9, d18 ; CHECK-BE-NEXT: add x9, x1, #136
; CHECK-BE-NEXT: st1 { v21.16b }, [x10] ; CHECK-BE-NEXT: st1 { v16.h }[4], [x9]
; CHECK-BE-NEXT: st1 { v19.h }[4], [x11] ; CHECK-BE-NEXT: fmov x9, d19
; CHECK-BE-NEXT: st1 { v16.16b }, [x1] ; CHECK-BE-NEXT: st1 { v7.16b }, [x1]
; CHECK-BE-NEXT: str x9, [x1, #128]! ; CHECK-BE-NEXT: str x9, [x1, #128]!
; CHECK-BE-NEXT: b.ne .LBB21_1 ; CHECK-BE-NEXT: b.ne .LBB21_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
; CHECK : Lloh30:
Context not available.
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr d0, [x0, x8] ; CHECK-NEXT: ldr d0, [x0, x8]
; CHECK-NEXT: add x8, x8, #16 ; CHECK-NEXT: add x8, x8, #16
; CHECK-NEXT: cmp x8, #128
; CHECK-NEXT: strb wzr, [x1, #32] ; CHECK-NEXT: strb wzr, [x1, #32]
; CHECK-NEXT: cmp x8, #128
; CHECK-NEXT: ushll.8h v0, v0, #0 ; CHECK-NEXT: ushll.8h v0, v0, #0
; CHECK-NEXT: ushll.4s v1, v0, #0 ; CHECK-NEXT: ushll2.4s v1, v0, #0
; CHECK-NEXT: ushll2.4s v0, v0, #0 ; CHECK-NEXT: ushll.4s v0, v0, #0
; CHECK-NEXT: ushll.2d v2, v1, #0 ; CHECK-NEXT: ushll2.2d v2, v1, #0
; CHECK-NEXT: ushll.2d v1, v1, #0
; CHECK-NEXT: ushll2.2d v3, v0, #0 ; CHECK-NEXT: ushll2.2d v3, v0, #0
; CHECK-NEXT: ushll2.2d v1, v1, #0
; CHECK-NEXT: mov.d x9, v3[1]
; CHECK-NEXT: fmov x10, d3
; CHECK-NEXT: mov.d x12, v1[1]
; CHECK-NEXT: ushll.2d v0, v0, #0 ; CHECK-NEXT: ushll.2d v0, v0, #0
; CHECK-NEXT: lsl x9, x9, #39 ; CHECK-NEXT: mov.d x9, v2[1]
; CHECK-NEXT: orr x9, x9, x10, lsl #6 ; CHECK-NEXT: mov.d x10, v1[1]
; CHECK-NEXT: fmov x10, d1
; CHECK-NEXT: mov.d x11, v0[1]
; CHECK-NEXT: lsl x12, x12, #35
; CHECK-NEXT: mov.d x14, v2[1]
; CHECK-NEXT: fmov x13, d0
; CHECK-NEXT: orr x10, x12, x10, lsl #2
; CHECK-NEXT: fmov x12, d2 ; CHECK-NEXT: fmov x12, d2
; CHECK-NEXT: lsl x11, x11, #37 ; CHECK-NEXT: mov.d x11, v3[1]
; CHECK-NEXT: orr x11, x11, x13, lsl #4 ; CHECK-NEXT: mov.d x13, v0[1]
; CHECK-NEXT: orr x12, x12, x14, lsl #33 ; CHECK-NEXT: lsl x9, x9, #39
; CHECK-NEXT: stp x11, x9, [x1, #16] ; CHECK-NEXT: lsl x10, x10, #37
; CHECK-NEXT: stp x12, x10, [x1], #128 ; CHECK-NEXT: lsl x11, x11, #35
; CHECK-NEXT: orr x9, x9, x12, lsl #6
; CHECK-NEXT: fmov x12, d1
; CHECK-NEXT: orr x10, x10, x12, lsl #4
; CHECK-NEXT: fmov x12, d3
; CHECK-NEXT: stp x10, x9, [x1, #16]
; CHECK-NEXT: orr x11, x11, x12, lsl #2
; CHECK-NEXT: fmov x12, d0
; CHECK-NEXT: orr x9, x12, x13, lsl #33
; CHECK-NEXT: stp x9, x11, [x1], #128
; CHECK-NEXT: b.ne LBB22_1 ; CHECK-NEXT: b.ne LBB22_1
; CHECK-NEXT: ; %bb.2: ; %exit ; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
Context not available.
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: add x9, x0, x8 ; CHECK-BE-NEXT: add x9, x0, x8
; CHECK-BE-NEXT: add x8, x8, #16 ; CHECK-BE-NEXT: add x8, x8, #16
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ld1 { v0.8b }, [x9] ; CHECK-BE-NEXT: ld1 { v0.8b }, [x9]
; CHECK-BE-NEXT: cmp x8, #128
; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-BE-NEXT: ushll v1.4s, v0.4h, #0 ; CHECK-BE-NEXT: ushll2 v1.4s, v0.8h, #0
; CHECK-BE-NEXT: ushll2 v0.4s, v0.8h, #0 ; CHECK-BE-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-BE-NEXT: ushll v2.2d, v1.2s, #0 ; CHECK-BE-NEXT: ushll v2.2d, v1.2s, #0
; CHECK-BE-NEXT: ushll2 v1.2d, v1.4s, #0
; CHECK-BE-NEXT: ushll2 v3.2d, v0.4s, #0 ; CHECK-BE-NEXT: ushll2 v3.2d, v0.4s, #0
; CHECK-BE-NEXT: ushll v0.2d, v0.2s, #0 ; CHECK-BE-NEXT: ushll v0.2d, v0.2s, #0
; CHECK-BE-NEXT: mov x9, v3.d[1] ; CHECK-BE-NEXT: mov x9, v2.d[1]
; CHECK-BE-NEXT: ushll2 v1.2d, v1.4s, #0 ; CHECK-BE-NEXT: mov x10, v1.d[1]
; CHECK-BE-NEXT: fmov x10, d3 ; CHECK-BE-NEXT: fmov x13, d1
; CHECK-BE-NEXT: mov x11, v0.d[1] ; CHECK-BE-NEXT: mov x11, v3.d[1]
; CHECK-BE-NEXT: mov x12, v0.d[1]
; CHECK-BE-NEXT: fmov x14, d2
; CHECK-BE-NEXT: fmov x15, d3
; CHECK-BE-NEXT: lsl x9, x9, #2
; CHECK-BE-NEXT: orr x13, x10, x13, lsl #33
; CHECK-BE-NEXT: strb w10, [x1, #32]
; CHECK-BE-NEXT: lsl x11, x11, #4
; CHECK-BE-NEXT: lsl x12, x12, #6
; CHECK-BE-NEXT: orr x14, x9, x14, lsl #35
; CHECK-BE-NEXT: extr x9, x9, x13, #8
; CHECK-BE-NEXT: fmov x13, d0 ; CHECK-BE-NEXT: fmov x13, d0
; CHECK-BE-NEXT: mov x12, v1.d[1] ; CHECK-BE-NEXT: orr x15, x11, x15, lsl #37
; CHECK-BE-NEXT: strb w9, [x1, #32] ; CHECK-BE-NEXT: extr x10, x11, x14, #8
; CHECK-BE-NEXT: orr x10, x9, x10, lsl #33 ; CHECK-BE-NEXT: orr x11, x12, x13, lsl #39
; CHECK-BE-NEXT: fmov x15, d1 ; CHECK-BE-NEXT: extr x12, x12, x15, #8
; CHECK-BE-NEXT: mov x14, v2.d[1] ; CHECK-BE-NEXT: stp x10, x9, [x1, #16]
; CHECK-BE-NEXT: lsl x11, x11, #2 ; CHECK-BE-NEXT: lsr x9, x11, #8
; CHECK-BE-NEXT: lsl x12, x12, #4 ; CHECK-BE-NEXT: stp x9, x12, [x1], #128
; CHECK-BE-NEXT: orr x13, x11, x13, lsl #35
; CHECK-BE-NEXT: extr x10, x11, x10, #8
; CHECK-BE-NEXT: fmov x11, d2
; CHECK-BE-NEXT: orr x15, x12, x15, lsl #37
; CHECK-BE-NEXT: lsl x14, x14, #6
; CHECK-BE-NEXT: extr x9, x12, x13, #8
; CHECK-BE-NEXT: orr x11, x14, x11, lsl #39
; CHECK-BE-NEXT: extr x12, x14, x15, #8
; CHECK-BE-NEXT: lsr x11, x11, #8
; CHECK-BE-NEXT: stp x9, x10, [x1, #16]
; CHECK-BE-NEXT: stp x11, x12, [x1], #128
; CHECK-BE-NEXT: b.ne .LBB22_1 ; CHECK-BE-NEXT: b.ne .LBB22_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: ret ; CHECK-BE-NEXT: ret
Context not available.
define i32 @test_pr62620_widening_instr(ptr %p1, ptr %p2, i64 %lx, i32 %h) { define i32 @test_pr62620_widening_instr(ptr %p1, ptr %p2, i64 %lx, i32 %h) {
; CHECK-LABEL: test_pr62620_widening_instr: ; CHECK-LABEL: test_pr62620_widening_instr:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: mov x8, x0
; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: lsl x9, x2, #4 ; CHECK-NEXT: lsl x9, x2, #4
; CHECK-NEXT: mov w8, wzr
; CHECK-NEXT: LBB23_1: ; %loop ; CHECK-NEXT: LBB23_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr q0, [x8, x9] ; CHECK-NEXT: ldr q0, [x0, x9]
; CHECK-NEXT: subs w3, w3, #1
; CHECK-NEXT: ldr q1, [x1, x9] ; CHECK-NEXT: ldr q1, [x1, x9]
; CHECK-NEXT: subs w3, w3, #1
; CHECK-NEXT: uabdl.8h v2, v0, v1 ; CHECK-NEXT: uabdl.8h v2, v0, v1
; CHECK-NEXT: uabal2.8h v2, v0, v1 ; CHECK-NEXT: uabal2.8h v2, v0, v1
; CHECK-NEXT: uaddlv.8h s0, v2 ; CHECK-NEXT: uaddlv.8h s0, v2
; CHECK-NEXT: fmov w10, s0 ; CHECK-NEXT: fmov w10, s0
; CHECK-NEXT: add w0, w10, w0 ; CHECK-NEXT: add w8, w10, w8
; CHECK-NEXT: b.ne LBB23_1 ; CHECK-NEXT: b.ne LBB23_1
; CHECK-NEXT: ; %bb.2: ; %exit ; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: mov w0, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; CHECK-BE-LABEL: test_pr62620_widening_instr: ; CHECK-BE-LABEL: test_pr62620_widening_instr:
; CHECK-BE: // %bb.0: // %entry ; CHECK-BE: // %bb.0: // %entry
; CHECK-BE-NEXT: mov x8, x0
; CHECK-BE-NEXT: lsl x9, x2, #4 ; CHECK-BE-NEXT: lsl x9, x2, #4
; CHECK-BE-NEXT: mov x8, x0
; CHECK-BE-NEXT: mov w0, wzr ; CHECK-BE-NEXT: mov w0, wzr
; CHECK-BE-NEXT: add x8, x8, x9 ; CHECK-BE-NEXT: add x8, x8, x9
; CHECK-BE-NEXT: add x9, x1, x9 ; CHECK-BE-NEXT: add x9, x1, x9
; CHECK-BE-NEXT: .LBB23_1: // %loop ; CHECK-BE-NEXT: .LBB23_1: // %loop
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: ld1 { v0.16b }, [x8] ; CHECK-BE-NEXT: ld1 { v0.16b }, [x8]
; CHECK-BE-NEXT: subs w3, w3, #1
; CHECK-BE-NEXT: ld1 { v1.16b }, [x9] ; CHECK-BE-NEXT: ld1 { v1.16b }, [x9]
; CHECK-BE-NEXT: subs w3, w3, #1
; CHECK-BE-NEXT: uabdl v2.8h, v0.8b, v1.8b ; CHECK-BE-NEXT: uabdl v2.8h, v0.8b, v1.8b
; CHECK-BE-NEXT: uabal2 v2.8h, v0.16b, v1.16b ; CHECK-BE-NEXT: uabal2 v2.8h, v0.16b, v1.16b
; CHECK-BE-NEXT: uaddlv s0, v2.8h ; CHECK-BE-NEXT: uaddlv s0, v2.8h
Context not available.
; CHECK-NEXT: LBB24_1: ; %loop ; CHECK-NEXT: LBB24_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr q0, [x1], #16 ; CHECK-NEXT: ldr q0, [x1], #16
; CHECK-NEXT: ldr q1, [x0] ; CHECK-NEXT: ldr q3, [x0]
; CHECK-NEXT: subs w2, w2, #1
; CHECK-NEXT: ldr q2, [x8, #16]! ; CHECK-NEXT: ldr q2, [x8, #16]!
; CHECK-NEXT: ushll2.8h v3, v0, #0 ; CHECK-NEXT: subs w2, w2, #1
; CHECK-NEXT: ushll2.8h v1, v0, #0
; CHECK-NEXT: ushll.8h v0, v0, #0 ; CHECK-NEXT: ushll.8h v0, v0, #0
; CHECK-NEXT: umull2.4s v4, v2, v3 ; CHECK-NEXT: umull2.4s v4, v2, v1
; CHECK-NEXT: umull.4s v2, v2, v3 ; CHECK-NEXT: umull.4s v1, v2, v1
; CHECK-NEXT: umull.4s v3, v1, v0 ; CHECK-NEXT: umull2.4s v2, v3, v0
; CHECK-NEXT: umull2.4s v0, v1, v0 ; CHECK-NEXT: umull.4s v0, v3, v0
; CHECK-NEXT: stp q2, q4, [x0, #32] ; CHECK-NEXT: stp q1, q4, [x0, #32]
; CHECK-NEXT: str q3, [x0] ; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: mov x0, x8 ; CHECK-NEXT: mov x0, x8
; CHECK-NEXT: str q0, [x8] ; CHECK-NEXT: str q2, [x8]
; CHECK-NEXT: b.ne LBB24_1 ; CHECK-NEXT: b.ne LBB24_1
; CHECK-NEXT: ; %bb.2: ; %exit ; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: mov w0, wzr
Context not available.
; CHECK-BE-NEXT: .LBB24_1: // %loop ; CHECK-BE-NEXT: .LBB24_1: // %loop
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: ld1 { v0.16b }, [x1] ; CHECK-BE-NEXT: ld1 { v0.16b }, [x1]
; CHECK-BE-NEXT: ld1 { v1.8h }, [x0]
; CHECK-BE-NEXT: add x8, x0, #16 ; CHECK-BE-NEXT: add x8, x0, #16
; CHECK-BE-NEXT: ld1 { v3.8h }, [x8]
; CHECK-BE-NEXT: add x9, x0, #48 ; CHECK-BE-NEXT: add x9, x0, #48
; CHECK-BE-NEXT: add x10, x0, #32 ; CHECK-BE-NEXT: add x10, x0, #32
; CHECK-BE-NEXT: ld1 { v1.8h }, [x0]
; CHECK-BE-NEXT: subs w2, w2, #1 ; CHECK-BE-NEXT: subs w2, w2, #1
; CHECK-BE-NEXT: add x1, x1, #16 ; CHECK-BE-NEXT: add x1, x1, #16
; CHECK-BE-NEXT: ld1 { v4.8h }, [x8]
; CHECK-BE-NEXT: ushll v2.8h, v0.8b, #0 ; CHECK-BE-NEXT: ushll v2.8h, v0.8b, #0
; CHECK-BE-NEXT: ushll2 v0.8h, v0.16b, #0 ; CHECK-BE-NEXT: ushll2 v0.8h, v0.16b, #0
; CHECK-BE-NEXT: umull v3.4s, v1.4h, v2.4h ; CHECK-BE-NEXT: umull v4.4s, v1.4h, v2.4h
; CHECK-BE-NEXT: umull2 v5.4s, v3.8h, v0.8h
; CHECK-BE-NEXT: umull v0.4s, v3.4h, v0.4h
; CHECK-BE-NEXT: umull2 v1.4s, v1.8h, v2.8h ; CHECK-BE-NEXT: umull2 v1.4s, v1.8h, v2.8h
; CHECK-BE-NEXT: umull2 v2.4s, v4.8h, v0.8h ; CHECK-BE-NEXT: st1 { v4.4s }, [x0]
; CHECK-BE-NEXT: umull v0.4s, v4.4h, v0.4h
; CHECK-BE-NEXT: st1 { v3.4s }, [x0]
; CHECK-BE-NEXT: mov x0, x8 ; CHECK-BE-NEXT: mov x0, x8
; CHECK-BE-NEXT: st1 { v1.4s }, [x8] ; CHECK-BE-NEXT: st1 { v5.4s }, [x9]
; CHECK-BE-NEXT: st1 { v2.4s }, [x9]
; CHECK-BE-NEXT: st1 { v0.4s }, [x10] ; CHECK-BE-NEXT: st1 { v0.4s }, [x10]
; CHECK-BE-NEXT: st1 { v1.4s }, [x8]
; CHECK-BE-NEXT: b.ne .LBB24_1 ; CHECK-BE-NEXT: b.ne .LBB24_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: mov w0, wzr ; CHECK-BE-NEXT: mov w0, wzr
Context not available.
; CHECK-NEXT: Lloh43: ; CHECK-NEXT: Lloh43:
; CHECK-NEXT: adrp x9, lCPI25_1@PAGE ; CHECK-NEXT: adrp x9, lCPI25_1@PAGE
; CHECK-NEXT: Lloh44: ; CHECK-NEXT: Lloh44:
; CHECK-NEXT: adrp x10, lCPI25_2@PAGE ; CHECK-NEXT: adrp x10, lCPI25_3@PAGE
; CHECK-NEXT: Lloh45: ; CHECK-NEXT: Lloh45:
; CHECK-NEXT: adrp x11, lCPI25_3@PAGE
; CHECK-NEXT: Lloh46:
; CHECK-NEXT: ldr q0, [x8, lCPI25_0@PAGEOFF] ; CHECK-NEXT: ldr q0, [x8, lCPI25_0@PAGEOFF]
; CHECK-NEXT: mov x8, x1 ; CHECK-NEXT: Lloh46:
; CHECK-NEXT: adrp x8, lCPI25_2@PAGE
; CHECK-NEXT: Lloh47: ; CHECK-NEXT: Lloh47:
; CHECK-NEXT: ldr q1, [x9, lCPI25_1@PAGEOFF] ; CHECK-NEXT: ldr q1, [x9, lCPI25_1@PAGEOFF]
; CHECK-NEXT: Lloh48: ; CHECK-NEXT: Lloh48:
; CHECK-NEXT: ldr q2, [x10, lCPI25_2@PAGEOFF] ; CHECK-NEXT: ldr q2, [x8, lCPI25_2@PAGEOFF]
; CHECK-NEXT: Lloh49: ; CHECK-NEXT: Lloh49:
; CHECK-NEXT: ldr q3, [x11, lCPI25_3@PAGEOFF] ; CHECK-NEXT: ldr q3, [x10, lCPI25_3@PAGEOFF]
; CHECK-NEXT: mov x8, x1
; CHECK-NEXT: LBB25_1: ; %loop ; CHECK-NEXT: LBB25_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr q4, [x0] ; CHECK-NEXT: ldr q4, [x0]
; CHECK-NEXT: ldp q16, q7, [x1, #32]
; CHECK-NEXT: ldr q18, [x8, #16]!
; CHECK-NEXT: subs w2, w2, #1 ; CHECK-NEXT: subs w2, w2, #1
; CHECK-NEXT: ldp q7, q17, [x1, #32] ; CHECK-NEXT: tbl.16b v5, { v4 }, v3
; CHECK-NEXT: tbl.16b v16, { v4 }, v3 ; CHECK-NEXT: tbl.16b v6, { v4 }, v0
; CHECK-NEXT: tbl.16b v18, { v4 }, v0 ; CHECK-NEXT: tbl.16b v17, { v4 }, v2
; CHECK-NEXT: tbl.16b v19, { v4 }, v1 ; CHECK-NEXT: tbl.16b v4, { v4 }, v1
; CHECK-NEXT: tbl.16b v4, { v4 }, v2 ; CHECK-NEXT: umull2.2d v19, v5, v7
; CHECK-NEXT: ldr q5, [x1] ; CHECK-NEXT: umull.2d v5, v5, v7
; CHECK-NEXT: ldr q6, [x8, #16]! ; CHECK-NEXT: ldr q7, [x1]
; CHECK-NEXT: umull2.2d v20, v16, v17 ; CHECK-NEXT: umull2.2d v20, v6, v16
; CHECK-NEXT: umull2.2d v21, v17, v18
; CHECK-NEXT: umull.2d v17, v17, v18
; CHECK-NEXT: umull2.2d v18, v4, v7
; CHECK-NEXT: umull.2d v4, v4, v7
; CHECK-NEXT: mov x1, x8 ; CHECK-NEXT: mov x1, x8
; CHECK-NEXT: umull2.2d v21, v18, v7 ; CHECK-NEXT: stp q5, q19, [x0, #96]
; CHECK-NEXT: umull.2d v16, v16, v17 ; CHECK-NEXT: umull.2d v5, v6, v16
; CHECK-NEXT: umull2.2d v17, v4, v6 ; CHECK-NEXT: str q20, [x0, #80]
; CHECK-NEXT: umull.2d v4, v4, v6 ; CHECK-NEXT: stp q4, q18, [x0]
; CHECK-NEXT: umull2.2d v6, v19, v5 ; CHECK-NEXT: stp q17, q21, [x0, #32]
; CHECK-NEXT: str q21, [x0, #80] ; CHECK-NEXT: str q5, [x0, #64]!
; CHECK-NEXT: umull.2d v5, v19, v5
; CHECK-NEXT: stp q16, q20, [x0, #96]
; CHECK-NEXT: umull.2d v7, v18, v7
; CHECK-NEXT: stp q4, q17, [x0, #32]
; CHECK-NEXT: stp q5, q6, [x0]
; CHECK-NEXT: str q7, [x0, #64]!
; CHECK-NEXT: b.ne LBB25_1 ; CHECK-NEXT: b.ne LBB25_1
; CHECK-NEXT: ; %bb.2: ; %exit ; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh45, Lloh49 ; CHECK-NEXT: .loh AdrpLdr Lloh46, Lloh48
; CHECK-NEXT: .loh AdrpLdr Lloh44, Lloh48 ; CHECK-NEXT: .loh AdrpLdr Lloh44, Lloh49
; CHECK-NEXT: .loh AdrpLdr Lloh43, Lloh47 ; CHECK-NEXT: .loh AdrpLdr Lloh43, Lloh47
; CHECK-NEXT: .loh AdrpLdr Lloh42, Lloh46 ; CHECK-NEXT: .loh AdrpAdrp Lloh42, Lloh46
; CHECK-NEXT: .loh AdrpLdr Lloh42, Lloh45
; ;
; CHECK-BE-LABEL: test_widening_instr_mull_64: ; CHECK-BE-LABEL: test_widening_instr_mull_64:
; CHECK-BE: // %bb.0: // %entry ; CHECK-BE: // %bb.0: // %entry
Context not available.
; CHECK-BE-NEXT: .LBB25_1: // %loop ; CHECK-BE-NEXT: .LBB25_1: // %loop
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: ld1 { v4.16b }, [x0] ; CHECK-BE-NEXT: ld1 { v4.16b }, [x0]
; CHECK-BE-NEXT: add x8, x1, #48 ; CHECK-BE-NEXT: add x9, x1, #48
; CHECK-BE-NEXT: add x9, x1, #32 ; CHECK-BE-NEXT: add x8, x1, #32
; CHECK-BE-NEXT: subs w2, w2, #1 ; CHECK-BE-NEXT: ld1 { v18.4s }, [x9]
; CHECK-BE-NEXT: ld1 { v5.4s }, [x1] ; CHECK-BE-NEXT: ld1 { v16.4s }, [x1]
; CHECK-BE-NEXT: add x1, x1, #16 ; CHECK-BE-NEXT: add x1, x1, #16
; CHECK-BE-NEXT: ld1 { v6.4s }, [x8] ; CHECK-BE-NEXT: ld1 { v20.4s }, [x8]
; CHECK-BE-NEXT: ld1 { v22.4s }, [x1]
; CHECK-BE-NEXT: add x8, x0, #96 ; CHECK-BE-NEXT: add x8, x0, #96
; CHECK-BE-NEXT: tbl v7.16b, { v4.16b }, v3.16b ; CHECK-BE-NEXT: tbl v5.16b, { v4.16b }, v3.16b
; CHECK-BE-NEXT: tbl v17.16b, { v4.16b }, v1.16b ; CHECK-BE-NEXT: tbl v6.16b, { v4.16b }, v2.16b
; CHECK-BE-NEXT: ld1 { v20.4s }, [x1] ; CHECK-BE-NEXT: tbl v7.16b, { v4.16b }, v1.16b
; CHECK-BE-NEXT: tbl v16.16b, { v4.16b }, v0.16b ; CHECK-BE-NEXT: tbl v4.16b, { v4.16b }, v0.16b
; CHECK-BE-NEXT: tbl v4.16b, { v4.16b }, v2.16b ; CHECK-BE-NEXT: ext v24.16b, v18.16b, v18.16b, #8
; CHECK-BE-NEXT: ld1 { v18.4s }, [x9]
; CHECK-BE-NEXT: rev32 v19.8b, v7.8b
; CHECK-BE-NEXT: add x9, x0, #32 ; CHECK-BE-NEXT: add x9, x0, #32
; CHECK-BE-NEXT: ext v23.16b, v6.16b, v6.16b, #8 ; CHECK-BE-NEXT: ext v25.16b, v20.16b, v20.16b, #8
; CHECK-BE-NEXT: rev32 v22.8b, v17.8b ; CHECK-BE-NEXT: add x10, x0, #16
; CHECK-BE-NEXT: subs w2, w2, #1
; CHECK-BE-NEXT: ext v17.16b, v5.16b, v5.16b, #8
; CHECK-BE-NEXT: ext v19.16b, v6.16b, v6.16b, #8
; CHECK-BE-NEXT: rev32 v5.8b, v5.8b
; CHECK-BE-NEXT: rev32 v21.8b, v7.8b
; CHECK-BE-NEXT: rev32 v23.8b, v4.8b
; CHECK-BE-NEXT: ext v7.16b, v7.16b, v7.16b, #8 ; CHECK-BE-NEXT: ext v7.16b, v7.16b, v7.16b, #8
; CHECK-BE-NEXT: ext v24.16b, v4.16b, v4.16b, #8 ; CHECK-BE-NEXT: ext v4.16b, v4.16b, v4.16b, #8
; CHECK-BE-NEXT: umull v6.2d, v19.2s, v6.2s ; CHECK-BE-NEXT: rev32 v6.8b, v6.8b
; CHECK-BE-NEXT: umull v19.2d, v22.2s, v20.2s ; CHECK-BE-NEXT: rev32 v17.8b, v17.8b
; CHECK-BE-NEXT: ext v22.16b, v18.16b, v18.16b, #8 ; CHECK-BE-NEXT: rev32 v19.8b, v19.8b
; CHECK-BE-NEXT: ext v21.16b, v5.16b, v5.16b, #8 ; CHECK-BE-NEXT: umull v5.2d, v5.2s, v18.2s
; CHECK-BE-NEXT: st1 { v6.2d }, [x8] ; CHECK-BE-NEXT: umull v18.2d, v21.2s, v22.2s
; CHECK-BE-NEXT: rev32 v6.8b, v7.8b ; CHECK-BE-NEXT: ext v21.16b, v22.16b, v22.16b, #8
; CHECK-BE-NEXT: ext v7.16b, v17.16b, v17.16b, #8 ; CHECK-BE-NEXT: rev32 v7.8b, v7.8b
; CHECK-BE-NEXT: rev32 v17.8b, v16.8b ; CHECK-BE-NEXT: umull v22.2d, v23.2s, v16.2s
; CHECK-BE-NEXT: ext v16.16b, v16.16b, v16.16b, #8 ; CHECK-BE-NEXT: ext v16.16b, v16.16b, v16.16b, #8
; CHECK-BE-NEXT: add x8, x0, #112
; CHECK-BE-NEXT: st1 { v19.2d }, [x9]
; CHECK-BE-NEXT: rev32 v19.8b, v24.8b
; CHECK-BE-NEXT: umull v6.2d, v6.2s, v23.2s
; CHECK-BE-NEXT: rev32 v4.8b, v4.8b ; CHECK-BE-NEXT: rev32 v4.8b, v4.8b
; CHECK-BE-NEXT: umull v5.2d, v17.2s, v5.2s ; CHECK-BE-NEXT: umull v17.2d, v17.2s, v24.2s
; CHECK-BE-NEXT: umull v19.2d, v19.2s, v25.2s
; CHECK-BE-NEXT: st1 { v5.2d }, [x8]
; CHECK-BE-NEXT: umull v5.2d, v6.2s, v20.2s
; CHECK-BE-NEXT: umull v6.2d, v7.2s, v21.2s
; CHECK-BE-NEXT: add x8, x0, #112
; CHECK-BE-NEXT: umull v4.2d, v4.2s, v16.2s
; CHECK-BE-NEXT: st1 { v18.2d }, [x9]
; CHECK-BE-NEXT: add x9, x0, #80 ; CHECK-BE-NEXT: add x9, x0, #80
; CHECK-BE-NEXT: rev32 v7.8b, v7.8b ; CHECK-BE-NEXT: st1 { v22.2d }, [x0]
; CHECK-BE-NEXT: rev32 v16.8b, v16.8b ; CHECK-BE-NEXT: st1 { v17.2d }, [x8]
; CHECK-BE-NEXT: st1 { v6.2d }, [x8] ; CHECK-BE-NEXT: add x8, x0, #64
; CHECK-BE-NEXT: add x8, x0, #48 ; CHECK-BE-NEXT: st1 { v19.2d }, [x9]
; CHECK-BE-NEXT: ext v6.16b, v20.16b, v20.16b, #8 ; CHECK-BE-NEXT: add x9, x0, #48
; CHECK-BE-NEXT: st1 { v5.2d }, [x0] ; CHECK-BE-NEXT: mov x0, x8
; CHECK-BE-NEXT: umull v17.2d, v19.2s, v22.2s
; CHECK-BE-NEXT: umull v4.2d, v4.2s, v18.2s
; CHECK-BE-NEXT: umull v5.2d, v7.2s, v6.2s
; CHECK-BE-NEXT: umull v6.2d, v16.2s, v21.2s
; CHECK-BE-NEXT: st1 { v17.2d }, [x9]
; CHECK-BE-NEXT: add x9, x0, #16
; CHECK-BE-NEXT: add x0, x0, #64
; CHECK-BE-NEXT: st1 { v5.2d }, [x8] ; CHECK-BE-NEXT: st1 { v5.2d }, [x8]
; CHECK-BE-NEXT: st1 { v4.2d }, [x0]
; CHECK-BE-NEXT: st1 { v6.2d }, [x9] ; CHECK-BE-NEXT: st1 { v6.2d }, [x9]
; CHECK-BE-NEXT: st1 { v4.2d }, [x10]
; CHECK-BE-NEXT: b.ne .LBB25_1 ; CHECK-BE-NEXT: b.ne .LBB25_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: mov w0, wzr ; CHECK-BE-NEXT: mov w0, wzr
Context not available.
; CHECK-NEXT: Lloh51: ; CHECK-NEXT: Lloh51:
; CHECK-NEXT: adrp x9, lCPI26_1@PAGE ; CHECK-NEXT: adrp x9, lCPI26_1@PAGE
; CHECK-NEXT: Lloh52: ; CHECK-NEXT: Lloh52:
; CHECK-NEXT: adrp x10, lCPI26_2@PAGE ; CHECK-NEXT: adrp x10, lCPI26_3@PAGE
; CHECK-NEXT: Lloh53: ; CHECK-NEXT: Lloh53:
; CHECK-NEXT: adrp x11, lCPI26_3@PAGE
; CHECK-NEXT: Lloh54:
; CHECK-NEXT: ldr q0, [x8, lCPI26_0@PAGEOFF] ; CHECK-NEXT: ldr q0, [x8, lCPI26_0@PAGEOFF]
; CHECK-NEXT: mov x8, x0 ; CHECK-NEXT: Lloh54:
; CHECK-NEXT: adrp x8, lCPI26_2@PAGE
; CHECK-NEXT: Lloh55: ; CHECK-NEXT: Lloh55:
; CHECK-NEXT: ldr q1, [x9, lCPI26_1@PAGEOFF] ; CHECK-NEXT: ldr q1, [x9, lCPI26_1@PAGEOFF]
; CHECK-NEXT: Lloh56: ; CHECK-NEXT: Lloh56:
; CHECK-NEXT: ldr q2, [x10, lCPI26_2@PAGEOFF] ; CHECK-NEXT: ldr q2, [x8, lCPI26_2@PAGEOFF]
; CHECK-NEXT: Lloh57: ; CHECK-NEXT: Lloh57:
; CHECK-NEXT: ldr q3, [x11, lCPI26_3@PAGEOFF] ; CHECK-NEXT: ldr q3, [x10, lCPI26_3@PAGEOFF]
; CHECK-NEXT: mov x8, x0
; CHECK-NEXT: LBB26_1: ; %loop ; CHECK-NEXT: LBB26_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr q4, [x1], #16 ; CHECK-NEXT: ldr q4, [x1], #16
; CHECK-NEXT: ldp q5, q6, [x0, #32] ; CHECK-NEXT: ldr q18, [x0]
; CHECK-NEXT: ldp q16, q17, [x0, #32]
; CHECK-NEXT: subs w2, w2, #1 ; CHECK-NEXT: subs w2, w2, #1
; CHECK-NEXT: tbl.16b v16, { v4 }, v0 ; CHECK-NEXT: tbl.16b v5, { v4 }, v0
; CHECK-NEXT: tbl.16b v18, { v4 }, v1 ; CHECK-NEXT: tbl.16b v6, { v4 }, v1
; CHECK-NEXT: tbl.16b v19, { v4 }, v2 ; CHECK-NEXT: tbl.16b v7, { v4 }, v2
; CHECK-NEXT: tbl.16b v4, { v4 }, v3 ; CHECK-NEXT: tbl.16b v4, { v4 }, v3
; CHECK-NEXT: ldr q7, [x0] ; CHECK-NEXT: mul.4s v5, v16, v5
; CHECK-NEXT: ldr q17, [x8, #16]! ; CHECK-NEXT: ldr q16, [x8, #16]!
; CHECK-NEXT: mul.4s v5, v5, v16 ; CHECK-NEXT: mul.4s v6, v17, v6
; CHECK-NEXT: mul.4s v6, v6, v18 ; CHECK-NEXT: mul.4s v7, v18, v7
; CHECK-NEXT: mul.4s v7, v7, v19 ; CHECK-NEXT: mul.4s v4, v16, v4
; CHECK-NEXT: mul.4s v4, v17, v4
; CHECK-NEXT: stp q5, q6, [x0, #32] ; CHECK-NEXT: stp q5, q6, [x0, #32]
; CHECK-NEXT: str q7, [x0] ; CHECK-NEXT: str q7, [x0]
; CHECK-NEXT: mov x0, x8 ; CHECK-NEXT: mov x0, x8
Context not available.
; CHECK-NEXT: ; %bb.2: ; %exit ; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh53, Lloh57 ; CHECK-NEXT: .loh AdrpLdr Lloh54, Lloh56
; CHECK-NEXT: .loh AdrpLdr Lloh52, Lloh56 ; CHECK-NEXT: .loh AdrpLdr Lloh52, Lloh57
; CHECK-NEXT: .loh AdrpLdr Lloh51, Lloh55 ; CHECK-NEXT: .loh AdrpLdr Lloh51, Lloh55
; CHECK-NEXT: .loh AdrpLdr Lloh50, Lloh54 ; CHECK-NEXT: .loh AdrpAdrp Lloh50, Lloh54
; CHECK-NEXT: .loh AdrpLdr Lloh50, Lloh53
; ;
; CHECK-BE-LABEL: test_widening_instr_mull_2: ; CHECK-BE-LABEL: test_widening_instr_mull_2:
; CHECK-BE: // %bb.0: // %entry ; CHECK-BE: // %bb.0: // %entry
Context not available.
; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-BE-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-BE-NEXT: ld1 { v4.16b }, [x1] ; CHECK-BE-NEXT: ld1 { v4.16b }, [x1]
; CHECK-BE-NEXT: add x8, x0, #32 ; CHECK-BE-NEXT: add x8, x0, #32
; CHECK-BE-NEXT: ld1 { v16.4s }, [x0]
; CHECK-BE-NEXT: add x9, x0, #48 ; CHECK-BE-NEXT: add x9, x0, #48
; CHECK-BE-NEXT: add x10, x0, #16 ; CHECK-BE-NEXT: add x10, x0, #16
; CHECK-BE-NEXT: ld1 { v6.4s }, [x0] ; CHECK-BE-NEXT: ld1 { v17.4s }, [x8]
; CHECK-BE-NEXT: ld1 { v18.4s }, [x9]
; CHECK-BE-NEXT: ld1 { v19.4s }, [x10]
; CHECK-BE-NEXT: subs w2, w2, #1 ; CHECK-BE-NEXT: subs w2, w2, #1
; CHECK-BE-NEXT: add x1, x1, #16
; CHECK-BE-NEXT: ld1 { v16.4s }, [x8]
; CHECK-BE-NEXT: tbl v5.16b, { v4.16b }, v1.16b ; CHECK-BE-NEXT: tbl v5.16b, { v4.16b }, v1.16b
; CHECK-BE-NEXT: tbl v7.16b, { v4.16b }, v0.16b ; CHECK-BE-NEXT: tbl v6.16b, { v4.16b }, v3.16b
; CHECK-BE-NEXT: ld1 { v18.4s }, [x10] ; CHECK-BE-NEXT: tbl v7.16b, { v4.16b }, v2.16b
; CHECK-BE-NEXT: tbl v17.16b, { v4.16b }, v3.16b ; CHECK-BE-NEXT: tbl v4.16b, { v4.16b }, v0.16b
; CHECK-BE-NEXT: tbl v4.16b, { v4.16b }, v2.16b ; CHECK-BE-NEXT: add x1, x1, #16
; CHECK-BE-NEXT: rev32 v5.16b, v5.16b ; CHECK-BE-NEXT: rev32 v5.16b, v5.16b
; CHECK-BE-NEXT: rev32 v6.16b, v6.16b
; CHECK-BE-NEXT: rev32 v7.16b, v7.16b ; CHECK-BE-NEXT: rev32 v7.16b, v7.16b
; CHECK-BE-NEXT: rev32 v17.16b, v17.16b
; CHECK-BE-NEXT: rev32 v4.16b, v4.16b ; CHECK-BE-NEXT: rev32 v4.16b, v4.16b
; CHECK-BE-NEXT: mul v5.4s, v6.4s, v5.4s ; CHECK-BE-NEXT: mul v5.4s, v16.4s, v5.4s
; CHECK-BE-NEXT: ld1 { v6.4s }, [x9] ; CHECK-BE-NEXT: mul v6.4s, v17.4s, v6.4s
; CHECK-BE-NEXT: mul v7.4s, v18.4s, v7.4s ; CHECK-BE-NEXT: mul v7.4s, v18.4s, v7.4s
; CHECK-BE-NEXT: mul v4.4s, v19.4s, v4.4s
; CHECK-BE-NEXT: st1 { v5.4s }, [x0] ; CHECK-BE-NEXT: st1 { v5.4s }, [x0]
; CHECK-BE-NEXT: mov x0, x10 ; CHECK-BE-NEXT: mov x0, x10
; CHECK-BE-NEXT: mul v5.4s, v16.4s, v17.4s ; CHECK-BE-NEXT: st1 { v6.4s }, [x8]
; CHECK-BE-NEXT: st1 { v7.4s }, [x10] ; CHECK-BE-NEXT: st1 { v7.4s }, [x9]
; CHECK-BE-NEXT: mul v4.4s, v6.4s, v4.4s ; CHECK-BE-NEXT: st1 { v4.4s }, [x10]
; CHECK-BE-NEXT: st1 { v5.4s }, [x8]
; CHECK-BE-NEXT: st1 { v4.4s }, [x9]
; CHECK-BE-NEXT: b.ne .LBB26_1 ; CHECK-BE-NEXT: b.ne .LBB26_1
; CHECK-BE-NEXT: // %bb.2: // %exit ; CHECK-BE-NEXT: // %bb.2: // %exit
; CHECK-BE-NEXT: mov w0, wzr ; CHECK-BE-NEXT: mov w0, wzr
Context not available.

llvm/test/CodeGen/AArch64/zext.ll

llvm/test/MC/AArch64/elf-globaladdress.ll

llvm/test/MachineVerifier/test_g_concat_vectors.mir

llvm/test/Transforms/CanonicalizeFreezeInLoops/aarch64.ll

llvm/test/Transforms/CodeGenPrepare/AArch64/large-offset-gep.ll

llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-ldp.ll

llvm/test/Transforms/LoopStrengthReduce/AArch64/pr53625.ll

llvm/test/Transforms/LoopStrengthReduce/AArch64/small-constant.ll

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.generated.expected

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.nogenerated.expected