[LLVM][Transforms] Zext flag in various optimization passes for RISC-V

[karouzakisp]

Summary

Added zext flag for the target RISC-V,
in the passes that convert sext to zext because for RISC-V sext is always cheaper than zext.

[craig.topper]

Please upload with full context. It's impossible to review most of these changes in the web view otherwise.

llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp

413

I don't think this is correct.

was_sext is supposed to indicate that the sign bit of the input to the zext is known to be 0. Making the zext and sext equivalent. In this case the input is only a single bit, making the input only a sign bit. It is not known to be 0.

[karouzakisp]

Added -U999999 in
git show
to make possible the reviewing via the web interface.

[craig.topper]

llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp

383

I don't think this is correct if we want the semantics of was_sext to be that the input to the zext has its sign bit clear.

This transform is based on the consuming instruction rather than anything about the producer.

1269

This change seems unnecessary. computeKnownBits should already be able to prove that lshr produces a positive number.

If we want to have this flag explicitly set anytime the sign bit of the input is 0, we should call isKnownNonNegative from visitZExt instead.

llvm/lib/Transforms/Scalar/BDCE.cpp

124

This is based on the consumer. That doesn't match the semantic we're trying to have of this bit giving information about the input.

llvm/lib/Transforms/Utils/SimplifyIndVar.cpp

552

I don't think this is correct for all cases that CanUseZExt returns true. Many of the cases are based on the consumer rather than the producer.

[karouzakisp]

Removed some redudant and inappropriate settings of the flag in the Transforms. Also updated the transforms calling method name from setWasSext to setNonNeg to set the flag.

[karouzakisp]

Added nneg flag in InstCombine::visitZExt. Also Added nneg flag in CorrelatedValuePropagation::processZExt.

llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp

if (Instruction *I = commonCastTransforms(Sext))
     return I;
 
   Value *Src = Sext.getOperand(0);
   Type *SrcTy = Src->getType(), *DestTy = Sext.getType();
   unsigned SrcBitSize = SrcTy->getScalarSizeInBits();
   unsigned DestBitSize = DestTy->getScalarSizeInBits();
 
   // If the value being extended is zero or positive, use a zext instead.
-  if (isKnownNonNegative(Src, DL, 0, &AC, &Sext, &DT))
-    return CastInst::Create(Instruction::ZExt, Src, DestTy);
+  if (isKnownNonNegative(Src, DL, 0, &AC, &Sext, &DT)) {
+    auto *ZExtInst = CastInst::Create(Instruction::ZExt, Src, DestTy);
+    ZExtInst->setWasSext(true);
+    return ZExtInst;
+  }
 
   // Try to extend the entire expression tree to the wide destination type.
   if (shouldChangeType(SrcTy, DestTy) && canEvaluateSExtd(Src, DestTy)) {
     // Okay, we can transform this!  Insert the new expression now.
     LLVM_DEBUG(
         dbgs() << "ICE: EvaluateInDifferentType converting expression type"
                   " to avoid sign extend: "
                << Sext << '\n');

llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp

if (Ty->isIntOrIntVectorTy(1) ||
     return BinaryOperator::CreateAnd(Op0, Op1);
 
   if (Value *R = foldMulShl1(I, /* CommuteOperands */ false, Builder))
     return replaceInstUsesWith(I, R);
   if (Value *R = foldMulShl1(I, /* CommuteOperands */ true, Builder))
     return replaceInstUsesWith(I, R);
 
   // (zext bool X) * (zext bool Y) --> zext (and X, Y)
-  // (sext bool X) * (sext bool Y) --> zext (and X, Y)
   // Note: -1 * -1 == 1 * 1 == 1 (if the extends match, the result is the same)
-  if (((match(Op0, m_ZExt(m_Value(X))) && match(Op1, m_ZExt(m_Value(Y)))) ||
-       (match(Op0, m_SExt(m_Value(X))) && match(Op1, m_SExt(m_Value(Y))))) &&
+  if ((match(Op0, m_ZExt(m_Value(X))) && match(Op1, m_ZExt(m_Value(Y)))) &&
       X->getType()->isIntOrIntVectorTy(1) && X->getType() == Y->getType() &&
       (Op0->hasOneUse() || Op1->hasOneUse() || X == Y)) {
     Value *And = Builder.CreateAnd(X, Y, "mulbool");
     return CastInst::Create(Instruction::ZExt, And, Ty);
   }
+
+  // (sext bool X) * (sext bool Y) --> zext (and X, Y)
+  // Note: -1 * -1 == 1 * 1 == 1 (if the extends match, the result is the same)
+  if ((match(Op0, m_SExt(m_Value(X))) && match(Op1, m_SExt(m_Value(Y)))) &&
+      X->getType()->isIntOrIntVectorTy(1) && X->getType() == Y->getType() &&
+      (Op0->hasOneUse() || Op1->hasOneUse() || X == Y)) {
+    Value *And = Builder.CreateAnd(X, Y, "mulbool");
+    auto *ZExtInst = CastInst::Create(Instruction::ZExt, And, Ty);
+    ZExtInst->setWasSext(true);
+    return ZExtInst;
+  }
+
   // (sext bool X) * (zext bool Y) --> sext (and X, Y)
   // (zext bool X) * (sext bool Y) --> sext (and X, Y)
   // Note: -1 * 1 == 1 * -1  == -1
   if (((match(Op0, m_SExt(m_Value(X))) && match(Op1, m_ZExt(m_Value(Y)))) ||
        (match(Op0, m_ZExt(m_Value(X))) && match(Op1, m_SExt(m_Value(Y))))) &&
       X->getType()->isIntOrIntVectorTy(1) && X->getType() == Y->getType() &&
       (Op0->hasOneUse() || Op1->hasOneUse())) {
     Value *And = Builder.CreateAnd(X, Y, "mulbool");

llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp

Instruction *InstCombinerImpl::commonShiftTransforms(BinaryOperator &I) {
   Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
   assert(Op0->getType() == Op1->getType());
   Type *Ty = I.getType();
 
   // If the shift amount is a one-use `sext`, we can demote it to `zext`.
   Value *Y;
   if (match(Op1, m_OneUse(m_SExt(m_Value(Y))))) {
     Value *NewExt = Builder.CreateZExt(Y, Ty, Op1->getName());
+    if (auto *ZExtI = dyn_cast<ZExtInst>(NewExt))
+      ZExtI->setWasSext(true);
     return BinaryOperator::Create(I.getOpcode(), Op0, NewExt);
   }
 
   // See if we can fold away this shift.
   if (SimplifyDemandedInstructionBits(I))
     return &I;
 
   // Try to fold constant and into select arguments.
if (match(Op0, m_SExt(m_Value(X)))) {
       }
 
       if ((!Ty->isIntegerTy() || shouldChangeType(Ty, X->getType())) &&
           Op0->hasOneUse()) {
         // Are we moving the sign bit to the low bit and widening with high
         // zeros? lshr (sext iM X to iN), N-1 --> zext (lshr X, M-1) to iN
         if (ShAmtC == BitWidth - 1) {
           Value *NewLShr = Builder.CreateLShr(X, SrcTyBitWidth - 1);
-          return new ZExtInst(NewLShr, Ty);
+          auto *ZExt = new ZExtInst(NewLShr, Ty);
+          ZExt->setWasSext(true);
+          return ZExt;
         }
 
         // lshr (sext iM X to iN), N-M --> zext (ashr X, min(N-M, M-1)) to iN
         if (ShAmtC == BitWidth - SrcTyBitWidth) {
           // The new shift amount can't be more than the narrow source type.
           unsigned NewShAmt = std::min(ShAmtC, SrcTyBitWidth - 1);
           Value *AShr = Builder.CreateAShr(X, NewShAmt);
           return new ZExtInst(AShr, Ty);

llvm/lib/Transforms/Scalar/BDCE.cpp

for (Instruction &I : instructions(F)) {
     if (SExtInst *SE = dyn_cast<SExtInst>(&I)) {
       APInt Demanded = DB.getDemandedBits(SE);
       const uint32_t SrcBitSize = SE->getSrcTy()->getScalarSizeInBits();
       auto *const DstTy = SE->getDestTy();
       const uint32_t DestBitSize = DstTy->getScalarSizeInBits();
       if (Demanded.countLeadingZeros() >= (DestBitSize - SrcBitSize)) {
         clearAssumptionsOfUsers(SE, DB);
         IRBuilder<> Builder(SE);
-        I.replaceAllUsesWith(
-            Builder.CreateZExt(SE->getOperand(0), DstTy, SE->getName()));
+        Value *ZExt =
+            Builder.CreateZExt(SE->getOperand(0), DstTy, SE->getName());
+        if (auto *ZExtI = dyn_cast<ZExtInst>(ZExt))
+          ZExtI->setWasSext(true);
+        I.replaceAllUsesWith(ZExt);
         Worklist.push_back(SE);
         Changed = true;
         NumSExt2ZExt++;
         continue;
       }
     }
 
     for (Use &U : I.operands()) {

llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp

static bool processSExt(SExtInst *SDI, LazyValueInfo *LVI) {
   const Use &Base = SDI->getOperandUse(0);
   if (!LVI->getConstantRangeAtUse(Base).isAllNonNegative())
     return false;
 
   ++NumSExt;
   auto *ZExt = CastInst::CreateZExtOrBitCast(Base, SDI->getType(), "", SDI);
   ZExt->takeName(SDI);
   ZExt->setDebugLoc(SDI->getDebugLoc());
+  ZExt->setWasSext(true);
   SDI->replaceAllUsesWith(ZExt);
   SDI->eraseFromParent();
 
   return true;
 }
 
 static bool processBinOp(BinaryOperator *BinOp, LazyValueInfo *LVI) {
   using OBO = OverflowingBinaryOperator;

llvm/lib/Transforms/Utils/SCCPSolver.cpp

static bool replaceSignedInst(SCCPSolver &Solver,
   // Note: We do not fold sitofp -> uitofp here because that could be more
   // expensive in codegen and may not be reversible in the backend.
   case Instruction::SExt: {
     // If the source value is not negative, this is a zext.
     Value *Op0 = Inst.getOperand(0);
     if (InsertedValues.count(Op0) || !isNonNegative(Op0))
       return false;
     NewInst = new ZExtInst(Op0, Inst.getType(), "", &Inst);
+    NewInst->setWasSext(true);
     break;
   }
   case Instruction::AShr: {
     // If the shifted value is not negative, this is a logical shift right.
     Value *Op0 = Inst.getOperand(0);
     if (InsertedValues.count(Op0) || !isNonNegative(Op0))
       return false;
     NewInst = BinaryOperator::CreateLShr(Op0, Inst.getOperand(1), "", &Inst);

llvm/lib/Transforms/Utils/SimplifyIndVar.cpp

for (auto *ICI : ICmpUsers) {
     // TODO: If we see a signed comparison which can be turned into unsigned,
     // we can do it here for canonicalization purposes.
     ICmpInst::Predicate Pred = ICI->getPredicate();
     if (IsSwapped) Pred = ICmpInst::getSwappedPredicate(Pred);
     if (CanUseZExt(ICI)) {
       assert(DoesZExtCollapse && "Unprofitable zext?");
       Ext = new ZExtInst(Op1, IVTy, "zext", ICI);
       Pred = ICmpInst::getUnsignedPredicate(Pred);
+      Ext->setWasSext(true);
     } else {
       assert(DoesSExtCollapse && "Unprofitable sext?");
       Ext = new SExtInst(Op1, IVTy, "sext", ICI);
       assert(Pred == ICmpInst::getSignedPredicate(Pred) && "Must be signed!");
     }
     bool Changed;
     L->makeLoopInvariant(Ext, Changed);
     (void)Changed;

llvm/test/Transforms/BDCE/sext_multi_uses.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -passes=bdce < %s | FileCheck %s
 define i32 @ZEXT_0(i16 %a) {
 ; CHECK-LABEL: @ZEXT_0(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[EXT1:%.*]] = zext i16 [[A:%.*]] to i32
+; CHECK-NEXT:    [[EXT1:%.*]] = zext was_sext i16 [[A:%.*]] to i32
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[EXT1]], 65280
 ; CHECK-NEXT:    [[LSR:%.*]] = lshr i32 [[EXT1]], 8
 ; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[LSR]], 255
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[AND]], [[AND2]]
 ; CHECK-NEXT:    ret i32 [[OR]]
 ;
 entry:
   %ext = sext i16 %a to i32
   %and = and i32 %ext, 65280
   %lsr = lshr i32 %ext, 8
   %and2 = and i32 %lsr, 255
   %or = or i32 %and, %and2
   ret i32 %or
 }
 
 define i32 @ZEXT_1(i16 %a) {
 ; CHECK-LABEL: @ZEXT_1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[EXT1:%.*]] = zext i16 [[A:%.*]] to i32
+; CHECK-NEXT:    [[EXT1:%.*]] = zext was_sext i16 [[A:%.*]] to i32
 ; CHECK-NEXT:    [[LSR:%.*]] = lshr i32 [[EXT1]], 8
 ; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[LSR]], 255
 ; CHECK-NEXT:    [[AND:%.*]] = or i32 [[EXT1]], -65536
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[AND]], [[AND2]]
 ; CHECK-NEXT:    ret i32 [[OR]]
 ;
 entry:
   %ext = sext i16 %a to i32
entry:
   %and2 = and i32 %lsr, 255
   %and = xor i32 %ext, 4294901760
   %or = or i32 %and, %and2
   ret i32 %or
 }
 
 define i16 @clear_assumptions(i8 %x, i16 %y) {
 ; CHECK-LABEL: @clear_assumptions(
-; CHECK-NEXT:    [[EXT1:%.*]] = zext i8 [[X:%.*]] to i16
+; CHECK-NEXT:    [[EXT1:%.*]] = zext was_sext i8 [[X:%.*]] to i16
 ; CHECK-NEXT:    [[ADD:%.*]] = add i16 [[EXT1]], [[Y:%.*]]
 ; CHECK-NEXT:    [[AND:%.*]] = and i16 [[ADD]], 255
 ; CHECK-NEXT:    ret i16 [[AND]]
 ;
   %ext = sext i8 %x to i16
   %add = add nsw i16 %ext, %y
   %and = and i16 %add, 255
   ret i16 %and
 }

llvm/test/Transforms/CorrelatedValuePropagation/cond-at-use.ll

;
   %ashr = ashr i16 %x, %y
   %cmp = icmp sge i16 %x, 0
   %sel = select i1 %cmp, i16 %ashr, i16 24
   ret i16 %sel
 }
 
 define i32 @sext_convert(i16 %x) {
 ; CHECK-LABEL: @sext_convert(
-; CHECK-NEXT:    [[EXT:%.*]] = zext i16 [[X:%.*]] to i32
+; CHECK-NEXT:    [[EXT:%.*]] = zext was_sext i16 [[X:%.*]] to i32
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp sge i16 [[X]], 0
 ; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 [[EXT]], i32 24
 ; CHECK-NEXT:    ret i32 [[SEL]]
 ;
   %ext = sext i16 %x to i32
   %cmp = icmp sge i16 %x, 0
   %sel = select i1 %cmp, i32 %ext, i32 24
   ret i32 %sel

llvm/test/Transforms/CorrelatedValuePropagation/sext.ll

 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[FOR_COND:%.*]]
 ; CHECK:       for.cond:
 ; CHECK-NEXT:    [[A:%.*]] = phi i32 [ [[N:%.*]], [[ENTRY:%.*]] ], [ [[EXT:%.*]], [[FOR_BODY:%.*]] ]
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[A]], -1
 ; CHECK-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END:%.*]]
 ; CHECK:       for.body:
-; CHECK-NEXT:    [[EXT_WIDE1:%.*]] = zext i32 [[A]] to i64
-; CHECK-NEXT:    call void @use64(i64 [[EXT_WIDE1]])
-; CHECK-NEXT:    [[EXT]] = trunc i64 [[EXT_WIDE1]] to i32
+; CHECK-NEXT:    [[EXT_WIDE:%.*]] = zext was_sext i32 [[A]] to i64
+; CHECK-NEXT:    call void @use64(i64 [[EXT_WIDE]])
+; CHECK-NEXT:    [[EXT]] = trunc i64 [[EXT_WIDE]] to i32
 ; CHECK-NEXT:    br label [[FOR_COND]]
 ; CHECK:       for.end:
 ; CHECK-NEXT:    ret void
 ;
+; DEBUG-LABEL: @test1(
+; DEBUG-NEXT:  entry:
+; DEBUG-NEXT:    br label [[FOR_COND:%.*]], !dbg [[DBG16:![0-9]+]]
+; DEBUG:       for.cond:
+; DEBUG-NEXT:    [[A:%.*]] = phi i32 [ [[N:%.*]], [[ENTRY:%.*]] ], [ [[EXT:%.*]], [[FOR_BODY:%.*]] ], !dbg [[DBG17:![0-9]+]]
+; DEBUG-NEXT:    call void @llvm.dbg.value(metadata i32 [[A]], metadata [[META9:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17]]
+; DEBUG-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[A]], -1, !dbg [[DBG18:![0-9]+]]
+; DEBUG-NEXT:    call void @llvm.dbg.value(metadata i1 [[CMP]], metadata [[META11:![0-9]+]], metadata !DIExpression()), !dbg [[DBG18]]
+; DEBUG-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END:%.*]], !dbg [[DBG19:![0-9]+]]
+; DEBUG:       for.body:
+; DEBUG-NEXT:    [[EXT_WIDE:%.*]] = zext was_sext i32 [[A]] to i64, !dbg [[DBG20:![0-9]+]]
+; DEBUG-NEXT:    call void @llvm.dbg.value(metadata i64 [[EXT_WIDE]], metadata [[META13:![0-9]+]], metadata !DIExpression()), !dbg [[DBG20]]
+; DEBUG-NEXT:    call void @use64(i64 [[EXT_WIDE]]), !dbg [[DBG21:![0-9]+]]
+; DEBUG-NEXT:    [[EXT]] = trunc i64 [[EXT_WIDE]] to i32, !dbg [[DBG22:![0-9]+]]
+; DEBUG-NEXT:    call void @llvm.dbg.value(metadata i32 [[EXT]], metadata [[META15:![0-9]+]], metadata !DIExpression()), !dbg [[DBG22]]
+; DEBUG-NEXT:    br label [[FOR_COND]], !dbg [[DBG23:![0-9]+]]
+; DEBUG:       for.end:
+; DEBUG-NEXT:    ret void, !dbg [[DBG24:![0-9]+]]
+;
 entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.body, %entry
   %a = phi i32 [ %n, %entry ], [ %ext, %for.body ]
   %cmp = icmp sgt i32 %a, -1
   br i1 %cmp, label %for.body, label %for.end
 

 ; CHECK:       for.body:
 ; CHECK-NEXT:    [[EXT_WIDE:%.*]] = sext i32 [[A]] to i64
 ; CHECK-NEXT:    call void @use64(i64 [[EXT_WIDE]])
 ; CHECK-NEXT:    [[EXT]] = trunc i64 [[EXT_WIDE]] to i32
 ; CHECK-NEXT:    br label [[FOR_COND]]
 ; CHECK:       for.end:
 ; CHECK-NEXT:    ret void
 ;
+; DEBUG-LABEL: @test2(
+; DEBUG-NEXT:  entry:
+; DEBUG-NEXT:    br label [[FOR_COND:%.*]], !dbg [[DBG31:![0-9]+]]
+; DEBUG:       for.cond:
+; DEBUG-NEXT:    [[A:%.*]] = phi i32 [ [[N:%.*]], [[ENTRY:%.*]] ], [ [[EXT:%.*]], [[FOR_BODY:%.*]] ], !dbg [[DBG32:![0-9]+]]
+; DEBUG-NEXT:    call void @llvm.dbg.value(metadata i32 [[A]], metadata [[META27:![0-9]+]], metadata !DIExpression()), !dbg [[DBG32]]
+; DEBUG-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[A]], -2, !dbg [[DBG33:![0-9]+]]
+; DEBUG-NEXT:    call void @llvm.dbg.value(metadata i1 [[CMP]], metadata [[META28:![0-9]+]], metadata !DIExpression()), !dbg [[DBG33]]
+; DEBUG-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END:%.*]], !dbg [[DBG34:![0-9]+]]
+; DEBUG:       for.body:
+; DEBUG-NEXT:    [[EXT_WIDE:%.*]] = sext i32 [[A]] to i64, !dbg [[DBG35:![0-9]+]]
+; DEBUG-NEXT:    call void @llvm.dbg.value(metadata i64 [[EXT_WIDE]], metadata [[META29:![0-9]+]], metadata !DIExpression()), !dbg [[DBG35]]
+; DEBUG-NEXT:    call void @use64(i64 [[EXT_WIDE]]), !dbg [[DBG36:![0-9]+]]
+; DEBUG-NEXT:    [[EXT]] = trunc i64 [[EXT_WIDE]] to i32, !dbg [[DBG37:![0-9]+]]
+; DEBUG-NEXT:    call void @llvm.dbg.value(metadata i32 [[EXT]], metadata [[META30:![0-9]+]], metadata !DIExpression()), !dbg [[DBG37]]
+; DEBUG-NEXT:    br label [[FOR_COND]], !dbg [[DBG38:![0-9]+]]
+; DEBUG:       for.end:
+; DEBUG-NEXT:    ret void, !dbg [[DBG39:![0-9]+]]
+;
 entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.body, %entry
   %a = phi i32 [ %n, %entry ], [ %ext, %for.body ]
   %cmp = icmp sgt i32 %a, -2
   br i1 %cmp, label %for.body, label %for.end
 

 
 ;; Non looping test case.
 define void @test3(i32 %n) {
 ; CHECK-LABEL: @test3(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[N:%.*]], -1
 ; CHECK-NEXT:    br i1 [[CMP]], label [[BB:%.*]], label [[EXIT:%.*]]
 ; CHECK:       bb:
-; CHECK-NEXT:    [[EXT_WIDE1:%.*]] = zext i32 [[N]] to i64
-; CHECK-NEXT:    call void @use64(i64 [[EXT_WIDE1]])
-; CHECK-NEXT:    [[EXT:%.*]] = trunc i64 [[EXT_WIDE1]] to i32
+; CHECK-NEXT:    [[EXT_WIDE:%.*]] = zext was_sext i32 [[N]] to i64
+; CHECK-NEXT:    call void @use64(i64 [[EXT_WIDE]])
+; CHECK-NEXT:    [[EXT:%.*]] = trunc i64 [[EXT_WIDE]] to i32
 ; CHECK-NEXT:    br label [[EXIT]]
 ; CHECK:       exit:
 ; CHECK-NEXT:    ret void
 ;
+; DEBUG-LABEL: @test3(
+; DEBUG-NEXT:  entry:
+; DEBUG-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[N:%.*]], -1, !dbg [[DBG45:![0-9]+]]
+; DEBUG-NEXT:    call void @llvm.dbg.value(metadata i1 [[CMP]], metadata [[META42:![0-9]+]], metadata !DIExpression()), !dbg [[DBG45]]
+; DEBUG-NEXT:    br i1 [[CMP]], label [[BB:%.*]], label [[EXIT:%.*]], !dbg [[DBG46:![0-9]+]]
+; DEBUG:       bb:
+; DEBUG-NEXT:    [[EXT_WIDE:%.*]] = zext was_sext i32 [[N]] to i64, !dbg [[DBG47:![0-9]+]]
+; DEBUG-NEXT:    call void @llvm.dbg.value(metadata i64 [[EXT_WIDE]], metadata [[META43:![0-9]+]], metadata !DIExpression()), !dbg [[DBG47]]
+; DEBUG-NEXT:    call void @use64(i64 [[EXT_WIDE]]), !dbg [[DBG48:![0-9]+]]
+; DEBUG-NEXT:    [[EXT:%.*]] = trunc i64 [[EXT_WIDE]] to i32, !dbg [[DBG49:![0-9]+]]
+; DEBUG-NEXT:    call void @llvm.dbg.value(metadata i32 [[EXT]], metadata [[META44:![0-9]+]], metadata !DIExpression()), !dbg [[DBG49]]
+; DEBUG-NEXT:    br label [[EXIT]], !dbg [[DBG50:![0-9]+]]
+; DEBUG:       exit:
+; DEBUG-NEXT:    ret void, !dbg [[DBG51:![0-9]+]]
+;
 entry:
   %cmp = icmp sgt i32 %n, -1
   br i1 %cmp, label %bb, label %exit
 
 bb:
   %ext.wide = sext i32 %n to i64
   call void @use64(i64 %ext.wide)
   %ext = trunc i64 %ext.wide to i32

 ; CHECK:       bb:
 ; CHECK-NEXT:    [[EXT_WIDE:%.*]] = sext i32 [[N]] to i64
 ; CHECK-NEXT:    call void @use64(i64 [[EXT_WIDE]])
 ; CHECK-NEXT:    [[EXT:%.*]] = trunc i64 [[EXT_WIDE]] to i32
 ; CHECK-NEXT:    br label [[EXIT]]
 ; CHECK:       exit:
 ; CHECK-NEXT:    ret void
 ;
+; DEBUG-LABEL: @test4(
+; DEBUG-NEXT:  entry:
+; DEBUG-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[N:%.*]], -2, !dbg [[DBG57:![0-9]+]]
+; DEBUG-NEXT:    call void @llvm.dbg.value(metadata i1 [[CMP]], metadata [[META54:![0-9]+]], metadata !DIExpression()), !dbg [[DBG57]]
+; DEBUG-NEXT:    br i1 [[CMP]], label [[BB:%.*]], label [[EXIT:%.*]], !dbg [[DBG58:![0-9]+]]
+; DEBUG:       bb:
+; DEBUG-NEXT:    [[EXT_WIDE:%.*]] = sext i32 [[N]] to i64, !dbg [[DBG59:![0-9]+]]
+; DEBUG-NEXT:    call void @llvm.dbg.value(metadata i64 [[EXT_WIDE]], metadata [[META55:![0-9]+]], metadata !DIExpression()), !dbg [[DBG59]]
+; DEBUG-NEXT:    call void @use64(i64 [[EXT_WIDE]]), !dbg [[DBG60:![0-9]+]]
+; DEBUG-NEXT:    [[EXT:%.*]] = trunc i64 [[EXT_WIDE]] to i32, !dbg [[DBG61:![0-9]+]]
+; DEBUG-NEXT:    call void @llvm.dbg.value(metadata i32 [[EXT]], metadata [[META56:![0-9]+]], metadata !DIExpression()), !dbg [[DBG61]]
+; DEBUG-NEXT:    br label [[EXIT]], !dbg [[DBG62:![0-9]+]]
+; DEBUG:       exit:
+; DEBUG-NEXT:    ret void, !dbg [[DBG63:![0-9]+]]
+;
 entry:
   %cmp = icmp sgt i32 %n, -2
   br i1 %cmp, label %bb, label %exit
 
 bb:
   %ext.wide = sext i32 %n to i64
   call void @use64(i64 %ext.wide)
   %ext = trunc i64 %ext.wide to i32
   br label %exit
 
 exit:
   ret void
 }

llvm/test/Transforms/InstCombine/adjust-for-minmax.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
 
 ; Instcombine should recognize that this code can be adjusted to fit the canonical max/min pattern.
 
 ; No change
 
 define i32 @smax1(i32 %n) {
 ; CHECK-LABEL: @smax1(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0)
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[M:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0)
+; CHECK-NEXT:    ret i32 [[M]]
 ;
   %t = icmp sgt i32 %n, 0
   %m = select i1 %t, i32 %n, i32 0
   ret i32 %m
 }
 
 ; No change
 
 define i32 @smin1(i32 %n) {
 ; CHECK-LABEL: @smin1(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0)
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[M:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0)
+; CHECK-NEXT:    ret i32 [[M]]
 ;
   %t = icmp slt i32 %n, 0
   %m = select i1 %t, i32 %n, i32 0
   ret i32 %m
 }
 
 ; Canonicalize min/max.
 
 define i32 @smax2(i32 %n) {
 ; CHECK-LABEL: @smax2(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0)
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[M:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0)
+; CHECK-NEXT:    ret i32 [[M]]
 ;
   %t = icmp sge i32 %n, 1
   %m = select i1 %t, i32 %n, i32 0
   ret i32 %m
 }
 
 ; Canonicalize min/max.
 
 define i32 @smin2(i32 %n) {
 ; CHECK-LABEL: @smin2(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0)
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[M:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0)
+; CHECK-NEXT:    ret i32 [[M]]
 ;
   %t = icmp sle i32 %n, -1
   %m = select i1 %t, i32 %n, i32 0
   ret i32 %m
 }
 
 ; Canonicalize min/max.
 
 define i32 @smax3(i32 %n) {
 ; CHECK-LABEL: @smax3(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0)
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[M:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0)
+; CHECK-NEXT:    ret i32 [[M]]
 ;
   %t = icmp sgt i32 %n, -1
   %m = select i1 %t, i32 %n, i32 0
   ret i32 %m
 }
 
 ; Canonicalize min/max.
 
 define <2 x i32> @smax3_vec(<2 x i32> %n) {
 ; CHECK-LABEL: @smax3_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer)
-; CHECK-NEXT:    ret <2 x i32> [[TMP1]]
+; CHECK-NEXT:    [[M:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer)
+; CHECK-NEXT:    ret <2 x i32> [[M]]
 ;
   %t = icmp sgt <2 x i32> %n, <i32 -1, i32 -1>
   %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> zeroinitializer
   ret <2 x i32> %m
 }
 
 ; Canonicalize min/max.
 
 define i32 @smin3(i32 %n) {
 ; CHECK-LABEL: @smin3(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0)
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[M:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0)
+; CHECK-NEXT:    ret i32 [[M]]
 ;
   %t = icmp slt i32 %n, 1
   %m = select i1 %t, i32 %n, i32 0
   ret i32 %m
 }
 
 ; Canonicalize min/max.
 
 define <2 x i32> @smin3_vec(<2 x i32> %n) {
 ; CHECK-LABEL: @smin3_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer)
-; CHECK-NEXT:    ret <2 x i32> [[TMP1]]
+; CHECK-NEXT:    [[M:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer)
+; CHECK-NEXT:    ret <2 x i32> [[M]]
 ;
   %t = icmp slt <2 x i32> %n, <i32 1, i32 1>
   %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> zeroinitializer
   ret <2 x i32> %m
 }
 
 ; Canonicalize min/max.
 
 define i32 @umax3(i32 %n) {
 ; CHECK-LABEL: @umax3(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[N:%.*]], i32 5)
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[M:%.*]] = call i32 @llvm.umax.i32(i32 [[N:%.*]], i32 5)
+; CHECK-NEXT:    ret i32 [[M]]
 ;
   %t = icmp ugt i32 %n, 4
   %m = select i1 %t, i32 %n, i32 5
   ret i32 %m
 }
 
 ; Canonicalize min/max.
 
 define <2 x i32> @umax3_vec(<2 x i32> %n) {
 ; CHECK-LABEL: @umax3_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> <i32 5, i32 5>)
-; CHECK-NEXT:    ret <2 x i32> [[TMP1]]
+; CHECK-NEXT:    [[M:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> <i32 5, i32 5>)
+; CHECK-NEXT:    ret <2 x i32> [[M]]
 ;
   %t = icmp ugt <2 x i32> %n, <i32 4, i32 4>
   %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> <i32 5, i32 5>
   ret <2 x i32> %m
 }
 
 ; Canonicalize min/max.
 
 define i32 @umin3(i32 %n) {
 ; CHECK-LABEL: @umin3(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[N:%.*]], i32 6)
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[M:%.*]] = call i32 @llvm.umin.i32(i32 [[N:%.*]], i32 6)
+; CHECK-NEXT:    ret i32 [[M]]
 ;
   %t = icmp ult i32 %n, 7
   %m = select i1 %t, i32 %n, i32 6
   ret i32 %m
 }
 
 ; Canonicalize min/max.
 
 define <2 x i32> @umin3_vec(<2 x i32> %n) {
 ; CHECK-LABEL: @umin3_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> <i32 6, i32 6>)
-; CHECK-NEXT:    ret <2 x i32> [[TMP1]]
+; CHECK-NEXT:    [[M:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> <i32 6, i32 6>)
+; CHECK-NEXT:    ret <2 x i32> [[M]]
 ;
   %t = icmp ult <2 x i32> %n, <i32 7, i32 7>
   %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> <i32 6, i32 6>
   ret <2 x i32> %m
 }
 
 ; Canonicalize min/max.
 
 define i32 @smax4(i32 %n) {
 ; CHECK-LABEL: @smax4(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0)
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[M:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0)
+; CHECK-NEXT:    ret i32 [[M]]
 ;
   %t = icmp sge i32 %n, 0
   %m = select i1 %t, i32 %n, i32 0
   ret i32 %m
 }
 
 ; Canonicalize min/max.
 
 define <2 x i32> @smax4_vec(<2 x i32> %n) {
 ; CHECK-LABEL: @smax4_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer)
-; CHECK-NEXT:    ret <2 x i32> [[TMP1]]
+; CHECK-NEXT:    [[M:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer)
+; CHECK-NEXT:    ret <2 x i32> [[M]]
 ;
   %t = icmp sge <2 x i32> %n, zeroinitializer
   %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> zeroinitializer
   ret <2 x i32> %m
 }
 
 ; Canonicalize min/max.
 
 define i32 @smin4(i32 %n) {
 ; CHECK-LABEL: @smin4(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0)
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[M:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0)
+; CHECK-NEXT:    ret i32 [[M]]
 ;
   %t = icmp sle i32 %n, 0
   %m = select i1 %t, i32 %n, i32 0
   ret i32 %m
 }
 
 ; Canonicalize min/max.
 
 define <2 x i32> @smin4_vec(<2 x i32> %n) {
 ; CHECK-LABEL: @smin4_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer)
-; CHECK-NEXT:    ret <2 x i32> [[TMP1]]
+; CHECK-NEXT:    [[M:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer)
+; CHECK-NEXT:    ret <2 x i32> [[M]]
 ;
   %t = icmp sle <2 x i32> %n, zeroinitializer
   %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> zeroinitializer
   ret <2 x i32> %m
 }
 
 ; Canonicalize min/max.
 
 define i32 @umax4(i32 %n) {
 ; CHECK-LABEL: @umax4(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[N:%.*]], i32 8)
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[M:%.*]] = call i32 @llvm.umax.i32(i32 [[N:%.*]], i32 8)
+; CHECK-NEXT:    ret i32 [[M]]
 ;
   %t = icmp uge i32 %n, 8
   %m = select i1 %t, i32 %n, i32 8
   ret i32 %m
 }
 
 ; Canonicalize min/max.
 
 define <2 x i32> @umax4_vec(<2 x i32> %n) {
 ; CHECK-LABEL: @umax4_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> <i32 8, i32 8>)
-; CHECK-NEXT:    ret <2 x i32> [[TMP1]]
+; CHECK-NEXT:    [[M:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> <i32 8, i32 8>)
+; CHECK-NEXT:    ret <2 x i32> [[M]]
 ;
   %t = icmp uge <2 x i32> %n, <i32 8, i32 8>
   %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> <i32 8, i32 8>
   ret <2 x i32> %m
 }
 
 ; Canonicalize min/max.
 
 define i32 @umin4(i32 %n) {
 ; CHECK-LABEL: @umin4(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[N:%.*]], i32 9)
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[M:%.*]] = call i32 @llvm.umin.i32(i32 [[N:%.*]], i32 9)
+; CHECK-NEXT:    ret i32 [[M]]
 ;
   %t = icmp ule i32 %n, 9
   %m = select i1 %t, i32 %n, i32 9
   ret i32 %m
 }
 
 ; Canonicalize min/max.
 
 define <2 x i32> @umin4_vec(<2 x i32> %n) {
 ; CHECK-LABEL: @umin4_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> <i32 9, i32 9>)
-; CHECK-NEXT:    ret <2 x i32> [[TMP1]]
+; CHECK-NEXT:    [[M:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> <i32 9, i32 9>)
+; CHECK-NEXT:    ret <2 x i32> [[M]]
 ;
   %t = icmp ule <2 x i32> %n, <i32 9, i32 9>
   %m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> <i32 9, i32 9>
   ret <2 x i32> %m
 }
 
 define i64 @smax_sext(i32 %a) {
 ; CHECK-LABEL: @smax_sext(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 0)
-; CHECK-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
-; CHECK-NEXT:    ret i64 [[TMP2]]
+; CHECK-NEXT:    [[MAX:%.*]] = zext was_sext i32 [[TMP1]] to i64
+; CHECK-NEXT:    ret i64 [[MAX]]
 ;
   %a_ext = sext i32 %a to i64
   %cmp = icmp sgt i32 %a, -1
   %max = select i1 %cmp, i64 %a_ext, i64 0
   ret i64 %max
 }
 
 define <2 x i64> @smax_sext_vec(<2 x i32> %a) {
 ; CHECK-LABEL: @smax_sext_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[A:%.*]], <2 x i32> zeroinitializer)
-; CHECK-NEXT:    [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT:    ret <2 x i64> [[TMP2]]
+; CHECK-NEXT:    [[MAX:%.*]] = zext was_sext <2 x i32> [[TMP1]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[MAX]]
 ;
   %a_ext = sext <2 x i32> %a to <2 x i64>
   %cmp = icmp sgt <2 x i32> %a, <i32 -1, i32 -1>
   %max = select <2 x i1> %cmp, <2 x i64> %a_ext, <2 x i64> zeroinitializer
   ret <2 x i64> %max
 }
 
 define i64 @smin_sext(i32 %a) {
 ; CHECK-LABEL: @smin_sext(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[A:%.*]], i32 0)
-; CHECK-NEXT:    [[TMP2:%.*]] = sext i32 [[TMP1]] to i64
-; CHECK-NEXT:    ret i64 [[TMP2]]
+; CHECK-NEXT:    [[MIN:%.*]] = sext i32 [[TMP1]] to i64
+; CHECK-NEXT:    ret i64 [[MIN]]
 ;
   %a_ext = sext i32 %a to i64
   %cmp = icmp slt i32 %a, 1
   %min = select i1 %cmp, i64 %a_ext, i64 0
   ret i64 %min
 }
 
 define <2 x i64>@smin_sext_vec(<2 x i32> %a) {
 ; CHECK-LABEL: @smin_sext_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[A:%.*]], <2 x i32> zeroinitializer)
-; CHECK-NEXT:    [[TMP2:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT:    ret <2 x i64> [[TMP2]]
+; CHECK-NEXT:    [[MIN:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[MIN]]
 ;
   %a_ext = sext <2 x i32> %a to <2 x i64>
   %cmp = icmp slt <2 x i32> %a, <i32 1, i32 1>
   %min = select <2 x i1> %cmp, <2 x i64> %a_ext, <2 x i64> zeroinitializer
   ret <2 x i64> %min
 }
 
 define i64 @umax_sext(i32 %a) {
 ; CHECK-LABEL: @umax_sext(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[A:%.*]], i32 3)
-; CHECK-NEXT:    [[TMP2:%.*]] = sext i32 [[TMP1]] to i64
-; CHECK-NEXT:    ret i64 [[TMP2]]
+; CHECK-NEXT:    [[MAX:%.*]] = sext i32 [[TMP1]] to i64
+; CHECK-NEXT:    ret i64 [[MAX]]
 ;
   %a_ext = sext i32 %a to i64
   %cmp = icmp ugt i32 %a, 2
   %max = select i1 %cmp, i64 %a_ext, i64 3
   ret i64 %max
 }
 
 define <2 x i64> @umax_sext_vec(<2 x i32> %a) {
 ; CHECK-LABEL: @umax_sext_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[A:%.*]], <2 x i32> <i32 3, i32 3>)
-; CHECK-NEXT:    [[TMP2:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT:    ret <2 x i64> [[TMP2]]
+; CHECK-NEXT:    [[MAX:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[MAX]]
 ;
   %a_ext = sext <2 x i32> %a to <2 x i64>
   %cmp = icmp ugt <2 x i32> %a, <i32 2, i32 2>
   %max = select <2 x i1> %cmp, <2 x i64> %a_ext, <2 x i64> <i64 3, i64 3>
   ret <2 x i64> %max
 }
 
 define i64 @umin_sext(i32 %a) {
 ; CHECK-LABEL: @umin_sext(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[A:%.*]], i32 2)
-; CHECK-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
-; CHECK-NEXT:    ret i64 [[TMP2]]
+; CHECK-NEXT:    [[MIN:%.*]] = zext was_sext i32 [[TMP1]] to i64
+; CHECK-NEXT:    ret i64 [[MIN]]
 ;
   %a_ext = sext i32 %a to i64
   %cmp = icmp ult i32 %a, 3
   %min = select i1 %cmp, i64 %a_ext, i64 2
   ret i64 %min
 }
 
 define <2 x i64> @umin_sext_vec(<2 x i32> %a) {
 ; CHECK-LABEL: @umin_sext_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[A:%.*]], <2 x i32> <i32 2, i32 2>)
-; CHECK-NEXT:    [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT:    ret <2 x i64> [[TMP2]]
+; CHECK-NEXT:    [[MIN:%.*]] = zext was_sext <2 x i32> [[TMP1]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[MIN]]
 ;
   %a_ext = sext <2 x i32> %a to <2 x i64>
   %cmp = icmp ult <2 x i32> %a, <i32 3, i32 3>
   %min = select <2 x i1> %cmp, <2 x i64> %a_ext, <2 x i64> <i64 2, i64 2>
   ret <2 x i64> %min
 }
 
 define i64 @umax_sext2(i32 %a) {
 ; CHECK-LABEL: @umax_sext2(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[A:%.*]], i32 2)
-; CHECK-NEXT:    [[TMP2:%.*]] = sext i32 [[TMP1]] to i64
-; CHECK-NEXT:    ret i64 [[TMP2]]
+; CHECK-NEXT:    [[MIN:%.*]] = sext i32 [[TMP1]] to i64
+; CHECK-NEXT:    ret i64 [[MIN]]
 ;
   %a_ext = sext i32 %a to i64
   %cmp = icmp ult i32 %a, 3
   %min = select i1 %cmp, i64 2, i64 %a_ext
   ret i64 %min
 }
 
 define <2 x i64> @umax_sext2_vec(<2 x i32> %a) {
 ; CHECK-LABEL: @umax_sext2_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[A:%.*]], <2 x i32> <i32 2, i32 2>)
-; CHECK-NEXT:    [[TMP2:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT:    ret <2 x i64> [[TMP2]]
+; CHECK-NEXT:    [[MIN:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[MIN]]
 ;
   %a_ext = sext <2 x i32> %a to <2 x i64>
   %cmp = icmp ult <2 x i32> %a, <i32 3, i32 3>
   %min = select <2 x i1> %cmp, <2 x i64> <i64 2, i64 2>, <2 x i64> %a_ext
   ret <2 x i64> %min
 }
 
 define i64 @umin_sext2(i32 %a) {
 ; CHECK-LABEL: @umin_sext2(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[A:%.*]], i32 3)
-; CHECK-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
-; CHECK-NEXT:    ret i64 [[TMP2]]
+; CHECK-NEXT:    [[MIN:%.*]] = zext was_sext i32 [[TMP1]] to i64
+; CHECK-NEXT:    ret i64 [[MIN]]
 ;
   %a_ext = sext i32 %a to i64
   %cmp = icmp ugt i32 %a, 2
   %min = select i1 %cmp, i64 3, i64 %a_ext
   ret i64 %min
 }
 
 define <2 x i64> @umin_sext2_vec(<2 x i32> %a) {
 ; CHECK-LABEL: @umin_sext2_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[A:%.*]], <2 x i32> <i32 3, i32 3>)
-; CHECK-NEXT:    [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT:    ret <2 x i64> [[TMP2]]
+; CHECK-NEXT:    [[MIN:%.*]] = zext was_sext <2 x i32> [[TMP1]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[MIN]]
 ;
   %a_ext = sext <2 x i32> %a to <2 x i64>
   %cmp = icmp ugt <2 x i32> %a, <i32 2, i32 2>
   %min = select <2 x i1> %cmp, <2 x i64> <i64 3, i64 3>, <2 x i64> %a_ext
   ret <2 x i64> %min
 }
 
 define i64 @umax_zext(i32 %a) {
 ; CHECK-LABEL: @umax_zext(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[A:%.*]], i32 3)
-; CHECK-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
-; CHECK-NEXT:    ret i64 [[TMP2]]
+; CHECK-NEXT:    [[MAX:%.*]] = zext i32 [[TMP1]] to i64
+; CHECK-NEXT:    ret i64 [[MAX]]
 ;
   %a_ext = zext i32 %a to i64
   %cmp = icmp ugt i32 %a, 2
   %max = select i1 %cmp, i64 %a_ext, i64 3
   ret i64 %max
 }
 
 define <2 x i64> @umax_zext_vec(<2 x i32> %a) {
 ; CHECK-LABEL: @umax_zext_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[A:%.*]], <2 x i32> <i32 3, i32 3>)
-; CHECK-NEXT:    [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT:    ret <2 x i64> [[TMP2]]
+; CHECK-NEXT:    [[MAX:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[MAX]]
 ;
   %a_ext = zext <2 x i32> %a to <2 x i64>
   %cmp = icmp ugt <2 x i32> %a, <i32 2, i32 2>
   %max = select <2 x i1> %cmp, <2 x i64> %a_ext, <2 x i64> <i64 3, i64 3>
   ret <2 x i64> %max
 }
 
 define i64 @umin_zext(i32 %a) {
 ; CHECK-LABEL: @umin_zext(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[A:%.*]], i32 2)
-; CHECK-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
-; CHECK-NEXT:    ret i64 [[TMP2]]
+; CHECK-NEXT:    [[MIN:%.*]] = zext i32 [[TMP1]] to i64
+; CHECK-NEXT:    ret i64 [[MIN]]
 ;
   %a_ext = zext i32 %a to i64
   %cmp = icmp ult i32 %a, 3
   %min = select i1 %cmp, i64 %a_ext, i64 2
   ret i64 %min
 }
 
 define <2 x i64> @umin_zext_vec(<2 x i32> %a) {
 ; CHECK-LABEL: @umin_zext_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[A:%.*]], <2 x i32> <i32 2, i32 2>)
-; CHECK-NEXT:    [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT:    ret <2 x i64> [[TMP2]]
+; CHECK-NEXT:    [[MIN:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[MIN]]
 ;
   %a_ext = zext <2 x i32> %a to <2 x i64>
   %cmp = icmp ult <2 x i32> %a, <i32 3, i32 3>
   %min = select <2 x i1> %cmp, <2 x i64> %a_ext, <2 x i64> <i64 2, i64 2>
   ret <2 x i64> %min
 }
 
 ; Don't crash mishandling a pattern that can't be transformed.

llvm/test/Transforms/InstCombine/cast-mul-select.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
 ; RUN: opt -passes=debugify,instcombine -S < %s | FileCheck %s -check-prefix DBGINFO
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32"
 
 define i32 @mul(i32 %x, i32 %y) {
 ; CHECK-LABEL: @mul(
 ; CHECK-NEXT:    [[C:%.*]] = mul i32 [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    [[D:%.*]] = and i32 [[C]], 255
 ; CHECK-NEXT:    ret i32 [[D]]
+;
+; DBGINFO-LABEL: @mul(
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i32 [[X:%.*]], metadata [[META9:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_stack_value)), !dbg [[DBG15:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i32 [[Y:%.*]], metadata [[META11:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_stack_value)), !dbg [[DBG16:![0-9]+]]
+; DBGINFO-NEXT:    [[C:%.*]] = mul i32 [[X]], [[Y]], !dbg [[DBG17:![0-9]+]]
+; DBGINFO-NEXT:    [[D:%.*]] = and i32 [[C]], 255, !dbg [[DBG18:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i32 [[C]], metadata [[META12:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i32 [[D]], metadata [[META13:![0-9]+]], metadata !DIExpression()), !dbg [[DBG18]]
+; DBGINFO-NEXT:    ret i32 [[D]], !dbg [[DBG19:![0-9]+]]
+;
 
 ; Test that when zext is evaluated in different type
 ; we preserve the debug information in the resulting
 ; instruction.
-; DBGINFO-LABEL: @mul(
-; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i32 %x, {{.*}} !DIExpression(DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_stack_value))
-; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i32 %y, {{.*}} !DIExpression(DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_stack_value))
-; DBGINFO-NEXT:    [[C:%.*]] = mul i32 {{.*}}
-; DBGINFO-NEXT:    [[D:%.*]] = and i32 {{.*}}
-; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i32 [[C]]
-; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i32 [[D]]
 
   %A = trunc i32 %x to i8
   %B = trunc i32 %y to i8
   %C = mul i8 %A, %B
   %D = zext i8 %C to i32
   ret i32 %D
 }
 
 define i32 @select1(i1 %cond, i32 %x, i32 %y, i32 %z) {
 ; CHECK-LABEL: @select1(
 ; CHECK-NEXT:    [[D:%.*]] = add i32 [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    [[E:%.*]] = select i1 [[COND:%.*]], i32 [[Z:%.*]], i32 [[D]]
 ; CHECK-NEXT:    [[F:%.*]] = and i32 [[E]], 255
 ; CHECK-NEXT:    ret i32 [[F]]
 ;
+; DBGINFO-LABEL: @select1(
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i32 [[X:%.*]], metadata [[META22:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_stack_value)), !dbg [[DBG28:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i32 [[Y:%.*]], metadata [[META23:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_stack_value)), !dbg [[DBG29:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i32 [[Z:%.*]], metadata [[META24:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_stack_value)), !dbg [[DBG30:![0-9]+]]
+; DBGINFO-NEXT:    [[D:%.*]] = add i32 [[X]], [[Y]], !dbg [[DBG31:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata !DIArgList(i32 [[X]], i32 [[Y]]), metadata [[META25:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_LLVM_arg, 1, DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_plus, DW_OP_stack_value)), !dbg [[DBG31]]
+; DBGINFO-NEXT:    [[E:%.*]] = select i1 [[COND:%.*]], i32 [[Z]], i32 [[D]], !dbg [[DBG32:![0-9]+]]
+; DBGINFO-NEXT:    [[F:%.*]] = and i32 [[E]], 255, !dbg [[DBG33:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i32 [[E]], metadata [[META26:![0-9]+]], metadata !DIExpression()), !dbg [[DBG32]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i32 [[F]], metadata [[META27:![0-9]+]], metadata !DIExpression()), !dbg [[DBG33]]
+; DBGINFO-NEXT:    ret i32 [[F]], !dbg [[DBG34:![0-9]+]]
+;
   %A = trunc i32 %x to i8
   %B = trunc i32 %y to i8
   %C = trunc i32 %z to i8
   %D = add i8 %A, %B
   %E = select i1 %cond, i8 %C, i8 %D
   %F = zext i8 %E to i32
   ret i32 %F
 }
 
 define i8 @select2(i1 %cond, i8 %x, i8 %y, i8 %z) {
 ; CHECK-LABEL: @select2(
 ; CHECK-NEXT:    [[D:%.*]] = add i8 [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    [[E:%.*]] = select i1 [[COND:%.*]], i8 [[Z:%.*]], i8 [[D]]
 ; CHECK-NEXT:    ret i8 [[E]]
 ;
+; DBGINFO-LABEL: @select2(
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i8 [[X:%.*]], metadata [[META37:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_stack_value)), !dbg [[DBG43:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i8 [[Y:%.*]], metadata [[META38:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_stack_value)), !dbg [[DBG44:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i8 [[Z:%.*]], metadata [[META39:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_stack_value)), !dbg [[DBG45:![0-9]+]]
+; DBGINFO-NEXT:    [[D:%.*]] = add i8 [[X]], [[Y]], !dbg [[DBG46:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata !DIArgList(i8 [[X]], i8 [[Y]]), metadata [[META40:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_LLVM_arg, 1, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_plus, DW_OP_stack_value)), !dbg [[DBG46]]
+; DBGINFO-NEXT:    [[E:%.*]] = select i1 [[COND:%.*]], i8 [[Z]], i8 [[D]], !dbg [[DBG47:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i32 poison, metadata [[META41:![0-9]+]], metadata !DIExpression()), !dbg [[DBG47]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i8 [[E]], metadata [[META42:![0-9]+]], metadata !DIExpression()), !dbg [[DBG48:![0-9]+]]
+; DBGINFO-NEXT:    ret i8 [[E]], !dbg [[DBG49:![0-9]+]]
+;
   %A = zext i8 %x to i32
   %B = zext i8 %y to i32
   %C = zext i8 %z to i32
   %D = add i32 %A, %B
   %E = select i1 %cond, i32 %C, i32 %D
   %F = trunc i32 %E to i8
   ret i8 %F
 }
 
 ; The next 3 tests could be handled in instcombine, but evaluating values
 ; with multiple uses may be very slow. Let some other pass deal with it.
 
 define i32 @eval_trunc_multi_use_in_one_inst(i32 %x) {
 ; CHECK-LABEL: @eval_trunc_multi_use_in_one_inst(
 ; CHECK-NEXT:    [[Z:%.*]] = zext i32 [[X:%.*]] to i64
 ; CHECK-NEXT:    [[A:%.*]] = add nuw nsw i64 [[Z]], 15
 ; CHECK-NEXT:    [[M:%.*]] = mul i64 [[A]], [[A]]
 ; CHECK-NEXT:    [[T:%.*]] = trunc i64 [[M]] to i32
 ; CHECK-NEXT:    ret i32 [[T]]
 ;
+; DBGINFO-LABEL: @eval_trunc_multi_use_in_one_inst(
+; DBGINFO-NEXT:    [[Z:%.*]] = zext i32 [[X:%.*]] to i64, !dbg [[DBG57:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i64 [[Z]], metadata [[META52:![0-9]+]], metadata !DIExpression()), !dbg [[DBG57]]
+; DBGINFO-NEXT:    [[A:%.*]] = add nuw nsw i64 [[Z]], 15, !dbg [[DBG58:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i64 [[A]], metadata [[META54:![0-9]+]], metadata !DIExpression()), !dbg [[DBG58]]
+; DBGINFO-NEXT:    [[M:%.*]] = mul i64 [[A]], [[A]], !dbg [[DBG59:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i64 [[M]], metadata [[META55:![0-9]+]], metadata !DIExpression()), !dbg [[DBG59]]
+; DBGINFO-NEXT:    [[T:%.*]] = trunc i64 [[M]] to i32, !dbg [[DBG60:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i32 [[T]], metadata [[META56:![0-9]+]], metadata !DIExpression()), !dbg [[DBG60]]
+; DBGINFO-NEXT:    ret i32 [[T]], !dbg [[DBG61:![0-9]+]]
+;
   %z = zext i32 %x to i64
   %a = add nsw nuw i64 %z, 15
   %m = mul i64 %a, %a
   %t = trunc i64 %m to i32
   ret i32 %t
 }
 
 define i32 @eval_zext_multi_use_in_one_inst(i32 %x) {
 ; CHECK-LABEL: @eval_zext_multi_use_in_one_inst(
 ; CHECK-NEXT:    [[T:%.*]] = trunc i32 [[X:%.*]] to i16
 ; CHECK-NEXT:    [[A:%.*]] = and i16 [[T]], 5
 ; CHECK-NEXT:    [[M:%.*]] = mul nuw nsw i16 [[A]], [[A]]
 ; CHECK-NEXT:    [[R:%.*]] = zext i16 [[M]] to i32
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
+; DBGINFO-LABEL: @eval_zext_multi_use_in_one_inst(
+; DBGINFO-NEXT:    [[T:%.*]] = trunc i32 [[X:%.*]] to i16, !dbg [[DBG69:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i16 [[T]], metadata [[META64:![0-9]+]], metadata !DIExpression()), !dbg [[DBG69]]
+; DBGINFO-NEXT:    [[A:%.*]] = and i16 [[T]], 5, !dbg [[DBG70:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i16 [[A]], metadata [[META66:![0-9]+]], metadata !DIExpression()), !dbg [[DBG70]]
+; DBGINFO-NEXT:    [[M:%.*]] = mul nuw nsw i16 [[A]], [[A]], !dbg [[DBG71:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i16 [[M]], metadata [[META67:![0-9]+]], metadata !DIExpression()), !dbg [[DBG71]]
+; DBGINFO-NEXT:    [[R:%.*]] = zext i16 [[M]] to i32, !dbg [[DBG72:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i32 [[R]], metadata [[META68:![0-9]+]], metadata !DIExpression()), !dbg [[DBG72]]
+; DBGINFO-NEXT:    ret i32 [[R]], !dbg [[DBG73:![0-9]+]]
+;
   %t = trunc i32 %x to i16
   %a = and i16 %t, 5
   %m = mul nuw nsw i16 %a, %a
   %r = zext i16 %m to i32
   ret i32 %r
 }
 
 define i32 @eval_sext_multi_use_in_one_inst(i32 %x) {
 ; CHECK-LABEL: @eval_sext_multi_use_in_one_inst(
 ; CHECK-NEXT:    [[T:%.*]] = trunc i32 [[X:%.*]] to i16
 ; CHECK-NEXT:    [[A:%.*]] = and i16 [[T]], 14
 ; CHECK-NEXT:    [[M:%.*]] = mul nuw nsw i16 [[A]], [[A]]
 ; CHECK-NEXT:    [[O:%.*]] = or i16 [[M]], -32768
 ; CHECK-NEXT:    [[R:%.*]] = sext i16 [[O]] to i32
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
+; DBGINFO-LABEL: @eval_sext_multi_use_in_one_inst(
+; DBGINFO-NEXT:    [[T:%.*]] = trunc i32 [[X:%.*]] to i16, !dbg [[DBG81:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i16 [[T]], metadata [[META76:![0-9]+]], metadata !DIExpression()), !dbg [[DBG81]]
+; DBGINFO-NEXT:    [[A:%.*]] = and i16 [[T]], 14, !dbg [[DBG82:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i16 [[A]], metadata [[META77:![0-9]+]], metadata !DIExpression()), !dbg [[DBG82]]
+; DBGINFO-NEXT:    [[M:%.*]] = mul nuw nsw i16 [[A]], [[A]], !dbg [[DBG83:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i16 [[M]], metadata [[META78:![0-9]+]], metadata !DIExpression()), !dbg [[DBG83]]
+; DBGINFO-NEXT:    [[O:%.*]] = or i16 [[M]], -32768, !dbg [[DBG84:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i16 [[O]], metadata [[META79:![0-9]+]], metadata !DIExpression()), !dbg [[DBG84]]
+; DBGINFO-NEXT:    [[R:%.*]] = sext i16 [[O]] to i32, !dbg [[DBG85:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i32 [[R]], metadata [[META80:![0-9]+]], metadata !DIExpression()), !dbg [[DBG85]]
+; DBGINFO-NEXT:    ret i32 [[R]], !dbg [[DBG86:![0-9]+]]
+;
   %t = trunc i32 %x to i16
   %a = and i16 %t, 14
   %m = mul nuw nsw i16 %a, %a
   %o = or i16 %m, 32768
   %r = sext i16 %o to i32
   ret i32 %r
 }
 

 ; CHECK-NEXT:    ]
 ; CHECK:       for.body3:
 ; CHECK-NEXT:    switch i3 [[V2:%.*]], label [[EXIT]] [
 ; CHECK-NEXT:    i3 0, label [[FOR_END]]
 ; CHECK-NEXT:    i3 -1, label [[FOR_END]]
 ; CHECK-NEXT:    ]
 ; CHECK:       for.end:
 ; CHECK-NEXT:    [[H:%.*]] = phi i8 [ [[SPEC_SELECT]], [[FOR_BODY3_US]] ], [ [[SPEC_SELECT]], [[FOR_BODY3_US]] ], [ 0, [[FOR_BODY3]] ], [ 0, [[FOR_BODY3]] ]
-; CHECK-NEXT:    [[CONV:%.*]] = zext i8 [[H]] to i32
+; CHECK-NEXT:    [[CONV:%.*]] = zext was_sext i8 [[H]] to i32
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[CONV]], [[A:%.*]]
 ; CHECK-NEXT:    br i1 [[CMP]], label [[EXIT]], label [[EXIT2:%.*]]
 ; CHECK:       exit2:
 ; CHECK-NEXT:    unreachable
 ; CHECK:       exit:
 ; CHECK-NEXT:    unreachable
 ;
+; DBGINFO-LABEL: @PR36225(
+; DBGINFO-NEXT:  entry:
+; DBGINFO-NEXT:    br label [[WHILE_BODY:%.*]], !dbg [[DBG94:![0-9]+]]
+; DBGINFO:       while.body:
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i1 poison, metadata [[META89:![0-9]+]], metadata !DIExpression()), !dbg [[DBG95:![0-9]+]]
+; DBGINFO-NEXT:    br i1 [[C1:%.*]], label [[FOR_BODY3_US:%.*]], label [[FOR_BODY3:%.*]], !dbg [[DBG96:![0-9]+]]
+; DBGINFO:       for.body3.us:
+; DBGINFO-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[B:%.*]], 0, !dbg [[DBG95]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i1 [[TOBOOL]], metadata [[META89]], metadata !DIExpression()), !dbg [[DBG95]]
+; DBGINFO-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[TOBOOL]], i8 0, i8 4, !dbg [[DBG97:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i8 [[SPEC_SELECT]], metadata [[META90:![0-9]+]], metadata !DIExpression()), !dbg [[DBG97]]
+; DBGINFO-NEXT:    switch i3 [[V1:%.*]], label [[EXIT:%.*]] [
+; DBGINFO-NEXT:    i3 0, label [[FOR_END:%.*]]
+; DBGINFO-NEXT:    i3 -1, label [[FOR_END]]
+; DBGINFO-NEXT:    ], !dbg [[DBG98:![0-9]+]]
+; DBGINFO:       for.body3:
+; DBGINFO-NEXT:    switch i3 [[V2:%.*]], label [[EXIT]] [
+; DBGINFO-NEXT:    i3 0, label [[FOR_END]]
+; DBGINFO-NEXT:    i3 -1, label [[FOR_END]]
+; DBGINFO-NEXT:    ], !dbg [[DBG99:![0-9]+]]
+; DBGINFO:       for.end:
+; DBGINFO-NEXT:    [[H:%.*]] = phi i8 [ [[SPEC_SELECT]], [[FOR_BODY3_US]] ], [ [[SPEC_SELECT]], [[FOR_BODY3_US]] ], [ 0, [[FOR_BODY3]] ], [ 0, [[FOR_BODY3]] ], !dbg [[DBG100:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i8 [[H]], metadata [[META91:![0-9]+]], metadata !DIExpression()), !dbg [[DBG100]]
+; DBGINFO-NEXT:    [[CONV:%.*]] = zext was_sext i8 [[H]] to i32, !dbg [[DBG101:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i32 [[CONV]], metadata [[META92:![0-9]+]], metadata !DIExpression()), !dbg [[DBG101]]
+; DBGINFO-NEXT:    [[CMP:%.*]] = icmp slt i32 [[CONV]], [[A:%.*]], !dbg [[DBG102:![0-9]+]]
+; DBGINFO-NEXT:    call void @llvm.dbg.value(metadata i1 [[CMP]], metadata [[META93:![0-9]+]], metadata !DIExpression()), !dbg [[DBG102]]
+; DBGINFO-NEXT:    br i1 [[CMP]], label [[EXIT]], label [[EXIT2:%.*]], !dbg [[DBG103:![0-9]+]]
+; DBGINFO:       exit2:
+; DBGINFO-NEXT:    unreachable, !dbg [[DBG104:![0-9]+]]
+; DBGINFO:       exit:
+; DBGINFO-NEXT:    unreachable, !dbg [[DBG105:![0-9]+]]
+;
 entry:
   br label %while.body
 
 while.body:
   %tobool = icmp eq i32 %b, 0
   br i1 %c1, label %for.body3.us, label %for.body3
 
 for.body3.us:

llvm/test/Transforms/InstCombine/gep-sext.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-pc-win32"
 
 declare void @use(i32) readonly
 
 ; We prefer to canonicalize the machine width gep indices early
 define void @test(ptr %p, i32 %index) {
-; CHECK-LABEL: @test
-; CHECK-NEXT: %1 = sext i32 %index to i64
-; CHECK-NEXT: %addr = getelementptr i32, ptr %p, i64 %1
+; CHECK-LABEL: @test(
+; CHECK-NEXT:    [[TMP1:%.*]] = sext i32 [[INDEX:%.*]] to i64
+; CHECK-NEXT:    [[ADDR:%.*]] = getelementptr i32, ptr [[P:%.*]], i64 [[TMP1]]
+; CHECK-NEXT:    [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4
+; CHECK-NEXT:    call void @use(i32 [[VAL]])
+; CHECK-NEXT:    ret void
+;
   %addr = getelementptr i32, ptr %p, i32 %index
   %val = load i32, ptr %addr
   call void @use(i32 %val)
   ret void
 }
 ; If they've already been canonicalized via zext, that's fine
 define void @test2(ptr %p, i32 %index) {
-; CHECK-LABEL: @test2
-; CHECK-NEXT: %i = zext i32 %index to i64
-; CHECK-NEXT: %addr = getelementptr i32, ptr %p, i64 %i
+; CHECK-LABEL: @test2(
+; CHECK-NEXT:    [[I:%.*]] = zext i32 [[INDEX:%.*]] to i64
+; CHECK-NEXT:    [[ADDR:%.*]] = getelementptr i32, ptr [[P:%.*]], i64 [[I]]
+; CHECK-NEXT:    [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4
+; CHECK-NEXT:    call void @use(i32 [[VAL]])
+; CHECK-NEXT:    ret void
+;
   %i = zext i32 %index to i64
   %addr = getelementptr i32, ptr %p, i64 %i
   %val = load i32, ptr %addr
   call void @use(i32 %val)
   ret void
 }
 ; If we can use a zext, we prefer that.  This requires
 ; knowing that the index is positive.
 define void @test3(ptr %p, i32 %index) {
-; CHECK-LABEL: @test3
-; CHECK:   zext
-; CHECK-NOT: sext
+; CHECK-LABEL: @test3(
+; CHECK-NEXT:    [[ADDR_BEGIN:%.*]] = getelementptr i32, ptr [[P:%.*]], i64 40
+; CHECK-NEXT:    [[ADDR_FIXED:%.*]] = getelementptr i32, ptr [[P]], i64 88
+; CHECK-NEXT:    [[VAL_FIXED:%.*]] = load i32, ptr [[ADDR_FIXED]], align 4, !range [[RNG0:![0-9]+]]
+; CHECK-NEXT:    [[TMP1:%.*]] = zext was_sext i32 [[VAL_FIXED]] to i64
+; CHECK-NEXT:    [[ADDR:%.*]] = getelementptr i32, ptr [[ADDR_BEGIN]], i64 [[TMP1]]
+; CHECK-NEXT:    [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4
+; CHECK-NEXT:    call void @use(i32 [[VAL]])
+; CHECK-NEXT:    ret void
+;
   %addr_begin = getelementptr i32, ptr %p, i64 40
   %addr_fixed = getelementptr i32, ptr %addr_begin, i64 48
   %val_fixed = load i32, ptr %addr_fixed, !range !0
   %addr = getelementptr i32, ptr %addr_begin, i32 %val_fixed
   %val = load i32, ptr %addr
   call void @use(i32 %val)
   ret void
 }
 ; Replace sext with zext where possible
 define void @test4(ptr %p, i32 %index) {
-; CHECK-LABEL: @test4
-; CHECK:   zext
-; CHECK-NOT: sext
+; CHECK-LABEL: @test4(
+; CHECK-NEXT:    [[ADDR_BEGIN:%.*]] = getelementptr i32, ptr [[P:%.*]], i64 40
+; CHECK-NEXT:    [[ADDR_FIXED:%.*]] = getelementptr i32, ptr [[P]], i64 88
+; CHECK-NEXT:    [[VAL_FIXED:%.*]] = load i32, ptr [[ADDR_FIXED]], align 4, !range [[RNG0]]
+; CHECK-NEXT:    [[I:%.*]] = zext was_sext i32 [[VAL_FIXED]] to i64
+; CHECK-NEXT:    [[ADDR:%.*]] = getelementptr i32, ptr [[ADDR_BEGIN]], i64 [[I]]
+; CHECK-NEXT:    [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4
+; CHECK-NEXT:    call void @use(i32 [[VAL]])
+; CHECK-NEXT:    ret void
+;
   %addr_begin = getelementptr i32, ptr %p, i64 40
   %addr_fixed = getelementptr i32, ptr %addr_begin, i64 48
   %val_fixed = load i32, ptr %addr_fixed, !range !0
   %i = sext i32 %val_fixed to i64
   %addr = getelementptr i32, ptr %addr_begin, i64 %i
   %val = load i32, ptr %addr
   call void @use(i32 %val)
   ret void
 }
 
 ;;  !range !0
 !0 = !{i32 0, i32 2147483647}
 
 
 

llvm/test/Transforms/InstCombine/icmp-ext-ext.ll

;
   %b = sext i8 %y to i32
   %c = icmp eq i32 %a, %b
   ret i1 %c
 }
 
 define i1 @zext_sext_sle_known_nonneg_op0_narrow(i8 %x, i16 %y) {
 ; CHECK-LABEL: @zext_sext_sle_known_nonneg_op0_narrow(
 ; CHECK-NEXT:    [[N:%.*]] = and i8 [[X:%.*]], 12
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[N]] to i16
+; CHECK-NEXT:    [[TMP1:%.*]] = zext was_sext i8 [[N]] to i16
 ; CHECK-NEXT:    [[C:%.*]] = icmp sle i16 [[TMP1]], [[Y:%.*]]
 ; CHECK-NEXT:    ret i1 [[C]]
 ;
   %n = and i8 %x, 12
   %a = zext i8 %n to i32
   %b = sext i16 %y to i32
   %c = icmp sle i32 %a, %b
   ret i1 %c
;
   %b = zext <2 x i8> %n to <2 x i32>
   %c = icmp sge <2 x i32> %a, %b
   ret <2 x i1> %c
 }
 
 define i1 @sext_zext_uge_known_nonneg_op0_wide(i16 %x, i8 %y) {
 ; CHECK-LABEL: @sext_zext_uge_known_nonneg_op0_wide(
 ; CHECK-NEXT:    [[N:%.*]] = and i8 [[Y:%.*]], 12
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[N]] to i16
+; CHECK-NEXT:    [[TMP1:%.*]] = zext was_sext i8 [[N]] to i16
 ; CHECK-NEXT:    [[C:%.*]] = icmp ule i16 [[TMP1]], [[X:%.*]]
 ; CHECK-NEXT:    ret i1 [[C]]
 ;
   %a = sext i16 %x to i32
   %n = and i8 %y, 12
   %b = zext i8 %n to i32
   %c = icmp uge i32 %a, %b
   ret i1 %c
 }

llvm/test/Transforms/InstCombine/load-cmp.ll

;
   %P = getelementptr inbounds [10 x i16], ptr @G16, i32 0, i32 %X
   %Q = load i16, ptr %P
   %R = icmp sle i16 %Q, 73
   ret i1 %R
 }
 
 define i1 @test4_i16(i16 %X) {
 ; CHECK-LABEL: @test4_i16(
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[X:%.*]] to i32
+; CHECK-NEXT:    [[TMP1:%.*]] = zext was_sext i16 [[X:%.*]] to i32
 ; CHECK-NEXT:    [[TMP2:%.*]] = lshr i32 933, [[TMP1]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP2]], 1
 ; CHECK-NEXT:    [[R:%.*]] = icmp ne i32 [[TMP3]], 0
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %P = getelementptr inbounds [10 x i16], ptr @G16, i32 0, i16 %X
   %Q = load i16, ptr %P
   %R = icmp sle i16 %Q, 73
;
   %Q = load double, ptr %P
   %R = fcmp olt double %Q, 0.0
   ret i1 %R
 }
 
 define i1 @test8(i32 %X) {
 ; CHECK-LABEL: @test8(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], -2
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 8
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[S:%.*]] = icmp eq i32 [[TMP1]], 8
+; CHECK-NEXT:    ret i1 [[S]]
 ;
   %P = getelementptr inbounds [10 x i16], ptr @G16, i32 0, i32 %X
   %Q = load i16, ptr %P
   %R = and i16 %Q, 3
   %S = icmp eq i16 %R, 0
   ret i1 %S
 }
 
 @GA = internal constant [4 x { i32, i32 } ] [
   { i32, i32 } { i32 1, i32 0 },
   { i32, i32 } { i32 2, i32 1 },
   { i32, i32 } { i32 3, i32 1 },
   { i32, i32 } { i32 4, i32 0 }
 ]
 
 define i1 @test9(i32 %X) {
 ; CHECK-LABEL: @test9(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -1
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 2
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = icmp ult i32 [[TMP1]], 2
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %P = getelementptr inbounds [4 x { i32, i32 } ], ptr @GA, i32 0, i32 %X, i32 1
   %Q = load i32, ptr %P
   %R = icmp eq i32 %Q, 1
   ret i1 %R
 }
 
 define i1 @test10_struct(i32 %x) {

llvm/test/Transforms/InstCombine/lshr.ll

;
   %sext = sext <2 x i6> %x to <2 x i8>
   %hibit = lshr <2 x i8> %sext, <i8 2, i8 2>
   ret <2 x i8> %hibit
 }
 
 define i18 @fake_sext(i3 %x) {
 ; CHECK-LABEL: @fake_sext(
 ; CHECK-NEXT:    [[TMP1:%.*]] = lshr i3 [[X:%.*]], 2
-; CHECK-NEXT:    [[SH:%.*]] = zext i3 [[TMP1]] to i18
+; CHECK-NEXT:    [[SH:%.*]] = zext was_sext i3 [[TMP1]] to i18
 ; CHECK-NEXT:    ret i18 [[SH]]
 ;
   %sext = sext i3 %x to i18
   %sh = lshr i18 %sext, 17
   ret i18 %sh
 }
 
 ; Avoid the transform if it would change the shift from a legal to illegal type.
 
 define i32 @fake_sext_but_should_not_change_type(i3 %x) {
 ; CHECK-LABEL: @fake_sext_but_should_not_change_type(
 ; CHECK-NEXT:    [[SEXT:%.*]] = sext i3 [[X:%.*]] to i32
 ; CHECK-NEXT:    [[SH:%.*]] = lshr i32 [[SEXT]], 31
 ; CHECK-NEXT:    ret i32 [[SH]]
 ;
   %sext = sext i3 %x to i32
   %sh = lshr i32 %sext, 31
   ret i32 %sh
 }
 
 define <2 x i8> @fake_sext_splat(<2 x i3> %x) {
 ; CHECK-LABEL: @fake_sext_splat(
 ; CHECK-NEXT:    [[TMP1:%.*]] = lshr <2 x i3> [[X:%.*]], <i3 2, i3 2>
-; CHECK-NEXT:    [[SH:%.*]] = zext <2 x i3> [[TMP1]] to <2 x i8>
+; CHECK-NEXT:    [[SH:%.*]] = zext was_sext <2 x i3> [[TMP1]] to <2 x i8>
 ; CHECK-NEXT:    ret <2 x i8> [[SH]]
 ;
   %sext = sext <2 x i3> %x to <2 x i8>
   %sh = lshr <2 x i8> %sext, <i8 7, i8 7>
   ret <2 x i8> %sh
 }
 
 ; Use a narrow shift: lshr (zext iM X to iN), C --> zext (lshr X, C) to iN

llvm/test/Transforms/InstCombine/memcpy-from-global.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
 @C.0.1248 = internal constant [128 x float] [ float -1.000000e+00, float -1.000000e+00, float -1.000000e+00, float 0.000000e+00, float -1.000000e+00, float -1.000000e+00, float 0.000000e+00, float -1.000000e+00, float -1.000000e+00, float -1.000000e+00, float 0.000000e+00, float 1.000000e+00, float -1.000000e+00, float -1.000000e+00, float 1.000000e+00, float 0.000000e+00, float -1.000000e+00, float 0.000000e+00, float -1.000000e+00, float -1.000000e+00, float -1.000000e+00, float 0.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00, float 0.000000e+00, float 1.000000e+00, float -1.000000e+00, float -1.000000e+00, float 0.000000e+00, float 1.000000e+00, float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00, float 0.000000e+00, float -1.000000e+00, float 1.000000e+00, float 0.000000e+00, float -1.000000e+00, float -1.000000e+00, float 1.000000e+00, float 0.000000e+00, float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0.000000e+00, float 0.000000e+00, float -1.000000e+00, float -1.000000e+00, float -1.000000e+00, float 0.000000e+00, float -1.000000e+00, float -1.000000e+00, float 1.000000e+00, float 0.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00, float 0.000000e+00, float -1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float -1.000000e+00, float -1.000000e+00, float 0.000000e+00, float 1.000000e+00, float -1.000000e+00, float 0.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00, float 0.000000e+00, float 1.000000e+00, float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float 0.000000e+00, float 1.000000e+00, float 0.000000e+00, float -1.000000e+00, float -1.000000e+00, float 1.000000e+00, float 0.000000e+00, float -1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0.000000e+00, float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float 0.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float -1.000000e+00, float 0.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0.000000e+00, float -1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00, float -1.000000e+00, float -1.000000e+00, float 0.000000e+00, float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float 0.000000e+00, float 1.000000e+00, float 1.000000e+00, float -1.000000e+00, float 0.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00 ], align 32    ; <ptr> [#uses=1]
 
 define float @test1(i32 %hash, float %x, float %y, float %z, float %w) {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP3:%.*]] = shl i32 [[HASH:%.*]], 2
 ; CHECK-NEXT:    [[TMP5:%.*]] = and i32 [[TMP3]], 124
-; CHECK-NEXT:    [[TMP0:%.*]] = zext i32 [[TMP5]] to i64
+; CHECK-NEXT:    [[TMP0:%.*]] = zext was_sext i32 [[TMP5]] to i64
 ; CHECK-NEXT:    [[TMP753:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP0]]
 ; CHECK-NEXT:    [[TMP9:%.*]] = load float, ptr [[TMP753]], align 16
 ; CHECK-NEXT:    [[TMP11:%.*]] = fmul float [[TMP9]], [[X:%.*]]
 ; CHECK-NEXT:    [[TMP13:%.*]] = fadd float [[TMP11]], 0.000000e+00
 ; CHECK-NEXT:    [[TMP17_SUM52:%.*]] = or i32 [[TMP5]], 1
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP17_SUM52]] to i64
+; CHECK-NEXT:    [[TMP1:%.*]] = zext was_sext i32 [[TMP17_SUM52]] to i64
 ; CHECK-NEXT:    [[TMP1851:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP1]]
 ; CHECK-NEXT:    [[TMP19:%.*]] = load float, ptr [[TMP1851]], align 4
 ; CHECK-NEXT:    [[TMP21:%.*]] = fmul float [[TMP19]], [[Y:%.*]]
 ; CHECK-NEXT:    [[TMP23:%.*]] = fadd float [[TMP21]], [[TMP13]]
 ; CHECK-NEXT:    [[TMP27_SUM50:%.*]] = or i32 [[TMP5]], 2
-; CHECK-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP27_SUM50]] to i64
+; CHECK-NEXT:    [[TMP2:%.*]] = zext was_sext i32 [[TMP27_SUM50]] to i64
 ; CHECK-NEXT:    [[TMP2849:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP2]]
 ; CHECK-NEXT:    [[TMP29:%.*]] = load float, ptr [[TMP2849]], align 8
 ; CHECK-NEXT:    [[TMP31:%.*]] = fmul float [[TMP29]], [[Z:%.*]]
 ; CHECK-NEXT:    [[TMP33:%.*]] = fadd float [[TMP31]], [[TMP23]]
 ; CHECK-NEXT:    [[TMP37_SUM48:%.*]] = or i32 [[TMP5]], 3
-; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP37_SUM48]] to i64
+; CHECK-NEXT:    [[TMP3:%.*]] = zext was_sext i32 [[TMP37_SUM48]] to i64
 ; CHECK-NEXT:    [[TMP3847:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP3]]
 ; CHECK-NEXT:    [[TMP39:%.*]] = load float, ptr [[TMP3847]], align 4
 ; CHECK-NEXT:    [[TMP41:%.*]] = fmul float [[TMP39]], [[W:%.*]]
 ; CHECK-NEXT:    [[TMP43:%.*]] = fadd float [[TMP41]], [[TMP33]]
 ; CHECK-NEXT:    ret float [[TMP43]]
 ;
 entry:
   %lookupTable = alloca [128 x float], align 16    ; <ptr> [#uses=5]

llvm/test/Transforms/InstCombine/minmax-intrinsics.ll

;
   call void @use(i8 %zy)
   %m = call i8 @llvm.umin.i8(i8 %zx, i8 %zy)
   ret i8 %m
 }
 
 define i8 @smax_sext_constant(i5 %x) {
 ; CHECK-LABEL: @smax_sext_constant(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i5 @llvm.smax.i5(i5 [[X:%.*]], i5 7)
-; CHECK-NEXT:    [[M:%.*]] = zext i5 [[TMP1]] to i8
+; CHECK-NEXT:    [[M:%.*]] = zext was_sext i5 [[TMP1]] to i8
 ; CHECK-NEXT:    ret i8 [[M]]
 ;
   %e = sext i5 %x to i8
   %m = call i8 @llvm.smax.i8(i8 %e, i8 7)
   ret i8 %m
 }
 
 ; simplifies
;
   %e = zext i5 %x to i8
   %m = call i8 @llvm.umax.i8(i8 %e, i8 126)
   ret i8 %m
 }
 
 define i8 @umin_sext_constant(i5 %x) {
 ; CHECK-LABEL: @umin_sext_constant(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i5 @llvm.umin.i5(i5 [[X:%.*]], i5 7)
-; CHECK-NEXT:    [[M:%.*]] = zext i5 [[TMP1]] to i8
+; CHECK-NEXT:    [[M:%.*]] = zext was_sext i5 [[TMP1]] to i8
 ; CHECK-NEXT:    ret i8 [[M]]
 ;
   %e = sext i5 %x to i8
   %m = call i8 @llvm.umin.i8(i8 %e, i8 7)
   ret i8 %m
 }
 
 ; negative test

 }
 
 define i8 @not_smax_of_nots(i8 %x, i8 %y) {
 ; CHECK-LABEL: @not_smax_of_nots(
 ; CHECK-NEXT:    [[NOTX:%.*]] = xor i8 [[X:%.*]], -1
 ; CHECK-NEXT:    call void @use(i8 [[NOTX]])
 ; CHECK-NEXT:    [[NOTY:%.*]] = xor i8 [[Y:%.*]], -1
 ; CHECK-NEXT:    call void @use(i8 [[NOTY]])
-; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.smin.i8(i8 [[X]], i8 [[Y]])
-; CHECK-NEXT:    ret i8 [[TMP1]]
+; CHECK-NEXT:    [[NOTM:%.*]] = call i8 @llvm.smin.i8(i8 [[X]], i8 [[Y]])
+; CHECK-NEXT:    ret i8 [[NOTM]]
 ;
   %notx = xor i8 %x, -1
   call void @use(i8 %notx)
   %noty = xor i8 %y, -1
   call void @use(i8 %noty)
   %m = call i8 @llvm.smax.i8(i8 %notx, i8 %noty)
   %notm = xor i8 %m, -1
   ret i8 %notm
;
   ret i8 %notm
 }
 
 define i8 @not_umax_of_not(i8 %x, i8 %y) {
 ; CHECK-LABEL: @not_umax_of_not(
 ; CHECK-NEXT:    [[NOTX:%.*]] = xor i8 [[X:%.*]], -1
 ; CHECK-NEXT:    call void @use(i8 [[NOTX]])
 ; CHECK-NEXT:    [[TMP1:%.*]] = xor i8 [[Y:%.*]], -1
-; CHECK-NEXT:    [[TMP2:%.*]] = call i8 @llvm.umin.i8(i8 [[X]], i8 [[TMP1]])
-; CHECK-NEXT:    ret i8 [[TMP2]]
+; CHECK-NEXT:    [[NOTM:%.*]] = call i8 @llvm.umin.i8(i8 [[X]], i8 [[TMP1]])
+; CHECK-NEXT:    ret i8 [[NOTM]]
 ;
   %notx = xor i8 %x, -1
   call void @use(i8 %notx)
   %m = call i8 @llvm.umax.i8(i8 %notx, i8 %y)
   %notm = xor i8 %m, -1
   ret i8 %notm
 }
 
;
   %notm = xor i8 %m, -1
   ret i8 %notm
 }
 
 define i8 @not_umin_of_not_constant_op(i8 %x) {
 ; CHECK-LABEL: @not_umin_of_not_constant_op(
 ; CHECK-NEXT:    [[NOTX:%.*]] = xor i8 [[X:%.*]], -1
 ; CHECK-NEXT:    call void @use(i8 [[NOTX]])
-; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.umax.i8(i8 [[X]], i8 -43)
-; CHECK-NEXT:    ret i8 [[TMP1]]
+; CHECK-NEXT:    [[NOTM:%.*]] = call i8 @llvm.umax.i8(i8 [[X]], i8 -43)
+; CHECK-NEXT:    ret i8 [[NOTM]]
 ;
   %notx = xor i8 %x, -1
   call void @use(i8 %notx)
   %m = call i8 @llvm.umin.i8(i8 %notx, i8 42)
   %notm = xor i8 %m, -1
   ret i8 %notm
 }
 
 define i8 @smax_negation(i8 %x, i8 %y) {
 ; CHECK-LABEL: @smax_negation(
 ; CHECK-NEXT:    [[S1:%.*]] = sub i8 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[S1]], i1 false)
-; CHECK-NEXT:    ret i8 [[TMP1]]
+; CHECK-NEXT:    [[R:%.*]] = call i8 @llvm.abs.i8(i8 [[S1]], i1 false)
+; CHECK-NEXT:    ret i8 [[R]]
 ;
   %s1 = sub i8 %x, %y
   %s2 = sub i8 %y, %x
   %r = call i8 @llvm.smax.i8(i8 %s1, i8 %s2)
   ret i8 %r
 }
 
 define i8 @smax_negation_nsw(i8 %x, i8 %y) {
 ; CHECK-LABEL: @smax_negation_nsw(
 ; CHECK-NEXT:    [[S1:%.*]] = sub nsw i8 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[S1]], i1 true)
-; CHECK-NEXT:    ret i8 [[TMP1]]
+; CHECK-NEXT:    [[R:%.*]] = call i8 @llvm.abs.i8(i8 [[S1]], i1 true)
+; CHECK-NEXT:    ret i8 [[R]]
 ;
   %s1 = sub nsw i8 %x, %y
   %s2 = sub nsw i8 %y, %x
   %r = call i8 @llvm.smax.i8(i8 %s1, i8 %s2)
   ret i8 %r
 }
 
 define i8 @smax_negation_not_nsw(i8 %x, i8 %y) {
 ; CHECK-LABEL: @smax_negation_not_nsw(
 ; CHECK-NEXT:    [[S1:%.*]] = sub nsw i8 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[S1]], i1 false)
-; CHECK-NEXT:    ret i8 [[TMP1]]
+; CHECK-NEXT:    [[R:%.*]] = call i8 @llvm.abs.i8(i8 [[S1]], i1 false)
+; CHECK-NEXT:    ret i8 [[R]]
 ;
   %s1 = sub nsw i8 %x, %y
   %s2 = sub nuw i8 %y, %x
   %r = call i8 @llvm.smax.i8(i8 %s1, i8 %s2)
   ret i8 %r
 }
 
 define <3 x i8> @smax_negation_vec(<3 x i8> %x) {
 ; CHECK-LABEL: @smax_negation_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = call <3 x i8> @llvm.abs.v3i8(<3 x i8> [[X:%.*]], i1 false)
-; CHECK-NEXT:    ret <3 x i8> [[TMP1]]
+; CHECK-NEXT:    [[R:%.*]] = call <3 x i8> @llvm.abs.v3i8(<3 x i8> [[X:%.*]], i1 false)
+; CHECK-NEXT:    ret <3 x i8> [[R]]
 ;
   %s = sub <3 x i8> <i8 0, i8 undef, i8 0>, %x
   %r = call <3 x i8> @llvm.smax.v3i8(<3 x i8> %x, <3 x i8> %s)
   ret <3 x i8> %r
 }
 
 define i8 @smin_negation(i8 %x, i8 %y) {
 ; CHECK-LABEL: @smin_negation(
;
   %s1 = sub nsw i8 %x, %y
   %s2 = sub nsw i8 %y, %x
   %r = call i8 @llvm.umax.i8(i8 %s1, i8 %s2)
   ret i8 %r
 }
 
 define i8 @umin_negation(i8 %x) {
 ; CHECK-LABEL: @umin_negation(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 true)
-; CHECK-NEXT:    ret i8 [[TMP1]]
+; CHECK-NEXT:    [[R:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i8 [[R]]
 ;
   %s = sub nsw i8 0, %x
   %r = call i8 @llvm.umin.i8(i8 %s, i8 %x)
   ret i8 %r
 }
 
 define i8 @smax_negation_uses(i8 %x, i8 %y) {
 ; CHECK-LABEL: @smax_negation_uses(
 ; CHECK-NEXT:    [[S2:%.*]] = sub i8 [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    call void @use(i8 [[S2]])
-; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[S2]], i1 false)
-; CHECK-NEXT:    ret i8 [[TMP1]]
+; CHECK-NEXT:    [[R:%.*]] = call i8 @llvm.abs.i8(i8 [[S2]], i1 false)
+; CHECK-NEXT:    ret i8 [[R]]
 ;
   %s1 = sub i8 %x, %y
   %s2 = sub i8 %y, %x
   call void @use(i8 %s2)
   %r = call i8 @llvm.smax.i8(i8 %s1, i8 %s2)
   ret i8 %r
 }
 

 ; CHECK-LABEL: @freeToInvert(
 ; CHECK-NEXT:    [[NX:%.*]] = xor i8 [[X:%.*]], -1
 ; CHECK-NEXT:    [[NY:%.*]] = xor i8 [[Y:%.*]], -1
 ; CHECK-NEXT:    [[NZ:%.*]] = xor i8 [[Z:%.*]], -1
 ; CHECK-NEXT:    call void @use(i8 [[NX]])
 ; CHECK-NEXT:    call void @use(i8 [[NY]])
 ; CHECK-NEXT:    call void @use(i8 [[NZ]])
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.umin.i8(i8 [[X]], i8 [[Y]])
-; CHECK-NEXT:    [[TMP2:%.*]] = call i8 @llvm.smax.i8(i8 [[TMP1]], i8 [[Z]])
-; CHECK-NEXT:    ret i8 [[TMP2]]
+; CHECK-NEXT:    [[NOT:%.*]] = call i8 @llvm.smax.i8(i8 [[TMP1]], i8 [[Z]])
+; CHECK-NEXT:    ret i8 [[NOT]]
 ;
   %nx = xor i8 %x, -1
   %ny = xor i8 %y, -1
   %nz = xor i8 %z, -1
   call void @use(i8 %nx)
   call void @use(i8 %ny)
   call void @use(i8 %nz)
   %m1 = call i8 @llvm.umax.i8(i8 %nx, i8 %ny)
   %m2 = call i8 @llvm.smin.i8(i8 %m1, i8 %nz)
   %not = xor i8 %m2, -1
   ret i8 %not
 }
 
 define i8 @freeToInvert_use1(i8 %x, i8 %y, i8 %z) {
 ; CHECK-LABEL: @freeToInvert_use1(
 ; CHECK-NEXT:    [[NX:%.*]] = xor i8 [[X:%.*]], -1
 ; CHECK-NEXT:    [[NY:%.*]] = xor i8 [[Y:%.*]], -1
 ; CHECK-NEXT:    [[NZ:%.*]] = xor i8 [[Z:%.*]], -1
 ; CHECK-NEXT:    call void @use(i8 [[NX]])
 ; CHECK-NEXT:    call void @use(i8 [[NY]])
 ; CHECK-NEXT:    call void @use(i8 [[NZ]])
 ; CHECK-NEXT:    [[M1:%.*]] = call i8 @llvm.umax.i8(i8 [[NX]], i8 [[NY]])
 ; CHECK-NEXT:    call void @use(i8 [[M1]])
 ; CHECK-NEXT:    [[TMP1:%.*]] = xor i8 [[M1]], -1
-; CHECK-NEXT:    [[TMP2:%.*]] = call i8 @llvm.smax.i8(i8 [[Z]], i8 [[TMP1]])
-; CHECK-NEXT:    ret i8 [[TMP2]]
+; CHECK-NEXT:    [[NOT:%.*]] = call i8 @llvm.smax.i8(i8 [[Z]], i8 [[TMP1]])
+; CHECK-NEXT:    ret i8 [[NOT]]
 ;
   %nx = xor i8 %x, -1
   %ny = xor i8 %y, -1
   %nz = xor i8 %z, -1
   call void @use(i8 %nx)
   call void @use(i8 %ny)
   call void @use(i8 %nz)
   %m1 = call i8 @llvm.umax.i8(i8 %nx, i8 %ny)

 ; CHECK-NEXT:    [[NZ:%.*]] = xor i8 [[Z:%.*]], -1
 ; CHECK-NEXT:    [[NW:%.*]] = xor i8 [[W:%.*]], -1
 ; CHECK-NEXT:    call void @use(i8 [[NX]])
 ; CHECK-NEXT:    call void @use(i8 [[NY]])
 ; CHECK-NEXT:    call void @use(i8 [[NZ]])
 ; CHECK-NEXT:    call void @use(i8 [[NW]])
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.umin.i8(i8 [[X]], i8 [[Y]])
 ; CHECK-NEXT:    [[TMP2:%.*]] = call i8 @llvm.smin.i8(i8 [[W]], i8 [[Z]])
-; CHECK-NEXT:    [[TMP3:%.*]] = call i8 @llvm.smax.i8(i8 [[TMP1]], i8 [[TMP2]])
-; CHECK-NEXT:    ret i8 [[TMP3]]
+; CHECK-NEXT:    [[NOT:%.*]] = call i8 @llvm.smax.i8(i8 [[TMP1]], i8 [[TMP2]])
+; CHECK-NEXT:    ret i8 [[NOT]]
 ;
   %nx = xor i8 %x, -1
   %ny = xor i8 %y, -1
   %nz = xor i8 %z, -1
   %nw = xor i8 %w, -1
   call void @use(i8 %nx)
   call void @use(i8 %ny)
   call void @use(i8 %nz)

llvm/test/Transforms/InstCombine/mul-inseltpoison.ll

;
   call void @use32(i32 %zy)
   %r = mul i32 %zx, %zy
   ret i32 %r
 }
 
 define <3 x i32> @mul_bools_sext(<3 x i1> %x, <3 x i1> %y) {
 ; CHECK-LABEL: @mul_bools_sext(
 ; CHECK-NEXT:    [[MULBOOL:%.*]] = and <3 x i1> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = zext <3 x i1> [[MULBOOL]] to <3 x i32>
+; CHECK-NEXT:    [[R:%.*]] = zext was_sext <3 x i1> [[MULBOOL]] to <3 x i32>
 ; CHECK-NEXT:    ret <3 x i32> [[R]]
 ;
   %sx = sext <3 x i1> %x to <3 x i32>
   %sy = sext <3 x i1> %y to <3 x i32>
   %r = mul <3 x i32> %sx, %sy
   ret <3 x i32> %r
 }
 
 define i32 @mul_bools_sext_use1(i1 %x, i1 %y) {
 ; CHECK-LABEL: @mul_bools_sext_use1(
 ; CHECK-NEXT:    [[SY:%.*]] = sext i1 [[Y:%.*]] to i32
 ; CHECK-NEXT:    call void @use32(i32 [[SY]])
 ; CHECK-NEXT:    [[MULBOOL:%.*]] = and i1 [[X:%.*]], [[Y]]
-; CHECK-NEXT:    [[R:%.*]] = zext i1 [[MULBOOL]] to i32
+; CHECK-NEXT:    [[R:%.*]] = zext was_sext i1 [[MULBOOL]] to i32
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %sx = sext i1 %x to i32
   %sy = sext i1 %y to i32
   call void @use32(i32 %sy)
   %r = mul i32 %sx, %sy
   ret i32 %r
 }
 
 define i32 @mul_bools_sext_use2(i1 %x, i1 %y) {
 ; CHECK-LABEL: @mul_bools_sext_use2(
 ; CHECK-NEXT:    [[SY:%.*]] = sext i1 [[Y:%.*]] to i32
 ; CHECK-NEXT:    call void @use32(i32 [[SY]])
 ; CHECK-NEXT:    [[MULBOOL:%.*]] = and i1 [[Y]], [[X:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = zext i1 [[MULBOOL]] to i32
+; CHECK-NEXT:    [[R:%.*]] = zext was_sext i1 [[MULBOOL]] to i32
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %sx = sext i1 %x to i32
   %sy = sext i1 %y to i32
   call void @use32(i32 %sy)
   %r = mul i32 %sy, %sx
   ret i32 %r
 }
;
   %B8 = sub i64 0, %v1
   %B4 = mul i64 %B8, %L1
   ret i64 %B4
 }
 
 define i32 @negate_if_true(i32 %x, i1 %cond) {
 ; CHECK-LABEL: @negate_if_true(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 0, [[X:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[X]]
+; CHECK-NEXT:    ret i32 [[R]]
 ;
   %sel = select i1 %cond, i32 -1, i32 1
   %r = mul i32 %sel, %x
   ret i32 %r
 }
 
 define i32 @negate_if_false(i32 %x, i1 %cond) {
 ; CHECK-LABEL: @negate_if_false(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 0, [[X:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[COND:%.*]], i32 [[X]], i32 [[TMP1]]
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[COND:%.*]], i32 [[X]], i32 [[TMP1]]
+; CHECK-NEXT:    ret i32 [[R]]
 ;
   %sel = select i1 %cond, i32 1, i32 -1
   %r = mul i32 %sel, %x
   ret i32 %r
 }
 
 define i32 @negate_if_true_nsw(i32 %x, i1 %cond) {
 ; CHECK-LABEL: @negate_if_true_nsw(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub nsw i32 0, [[X:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[X]]
+; CHECK-NEXT:    ret i32 [[R]]
 ;
   %sel = select i1 %cond, i32 -1, i32 1
   %r = mul nsw i32 %sel, %x
   ret i32 %r
 }
 
 define i32 @negate_if_true_nuw(i32 %x, i1 %cond) {
 ; CHECK-LABEL: @negate_if_true_nuw(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub nsw i32 0, [[X:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[X]]
+; CHECK-NEXT:    ret i32 [[R]]
 ;
   %sel = select i1 %cond, i32 -1, i32 1
   %r = mul nuw i32 %sel, %x
   ret i32 %r
 }
 
 define i32 @negate_if_false_nsw(i32 %x, i1 %cond) {
 ; CHECK-LABEL: @negate_if_false_nsw(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub nsw i32 0, [[X:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[COND:%.*]], i32 [[X]], i32 [[TMP1]]
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[COND:%.*]], i32 [[X]], i32 [[TMP1]]
+; CHECK-NEXT:    ret i32 [[R]]
 ;
   %sel = select i1 %cond, i32 1, i32 -1
   %r = mul nsw i32 %sel, %x
   ret i32 %r
 }
 
 define i32 @negate_if_false_nuw(i32 %x, i1 %cond) {
 ; CHECK-LABEL: @negate_if_false_nuw(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub nsw i32 0, [[X:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[COND:%.*]], i32 [[X]], i32 [[TMP1]]
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[COND:%.*]], i32 [[X]], i32 [[TMP1]]
+; CHECK-NEXT:    ret i32 [[R]]
 ;
   %sel = select i1 %cond, i32 1, i32 -1
   %r = mul nuw i32 %sel, %x
   ret i32 %r
 }
 
 define <2 x i8> @negate_if_true_commute(<2 x i8> %px, i1 %cond) {
 ; CHECK-LABEL: @negate_if_true_commute(
 ; CHECK-NEXT:    [[X:%.*]] = sdiv <2 x i8> <i8 42, i8 42>, [[PX:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub nsw <2 x i8> zeroinitializer, [[X]]
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[COND:%.*]], <2 x i8> [[TMP1]], <2 x i8> [[X]]
-; CHECK-NEXT:    ret <2 x i8> [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[COND:%.*]], <2 x i8> [[TMP1]], <2 x i8> [[X]]
+; CHECK-NEXT:    ret <2 x i8> [[R]]
 ;
   %x = sdiv <2 x i8> <i8 42, i8 42>, %px  ; thwart complexity-based canonicalization
   %sel = select i1 %cond, <2 x i8> <i8 -1, i8 -1>, <2 x i8> <i8 1, i8 1>
   %r = mul <2 x i8> %x, %sel
   ret <2 x i8> %r
 }
 
 define <2 x i8> @negate_if_false_commute(<2 x i8> %px, <2 x i1> %cond) {
 ; CHECK-LABEL: @negate_if_false_commute(
 ; CHECK-NEXT:    [[X:%.*]] = sdiv <2 x i8> <i8 42, i8 5>, [[PX:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub <2 x i8> zeroinitializer, [[X]]
-; CHECK-NEXT:    [[TMP2:%.*]] = select <2 x i1> [[COND:%.*]], <2 x i8> [[X]], <2 x i8> [[TMP1]]
-; CHECK-NEXT:    ret <2 x i8> [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[COND:%.*]], <2 x i8> [[X]], <2 x i8> [[TMP1]]
+; CHECK-NEXT:    ret <2 x i8> [[R]]
 ;
   %x = sdiv <2 x i8> <i8 42, i8 5>, %px  ; thwart complexity-based canonicalization
   %sel = select <2 x i1> %cond, <2 x i8> <i8 1, i8 undef>, <2 x i8> <i8 -1, i8 -1>
   %r = mul <2 x i8> %x, %sel
   ret <2 x i8> %r
 }
 
 ; Negative test

llvm/test/Transforms/InstCombine/mul.ll

;
   call void @use32(i32 %zy)
   %r = mul i32 %zx, %zy
   ret i32 %r
 }
 
 define <3 x i32> @mul_bools_sext(<3 x i1> %x, <3 x i1> %y) {
 ; CHECK-LABEL: @mul_bools_sext(
 ; CHECK-NEXT:    [[MULBOOL:%.*]] = and <3 x i1> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = zext <3 x i1> [[MULBOOL]] to <3 x i32>
+; CHECK-NEXT:    [[R:%.*]] = zext was_sext <3 x i1> [[MULBOOL]] to <3 x i32>
 ; CHECK-NEXT:    ret <3 x i32> [[R]]
 ;
   %sx = sext <3 x i1> %x to <3 x i32>
   %sy = sext <3 x i1> %y to <3 x i32>
   %r = mul <3 x i32> %sx, %sy
   ret <3 x i32> %r
 }
 
 define i32 @mul_bools_sext_use1(i1 %x, i1 %y) {
 ; CHECK-LABEL: @mul_bools_sext_use1(
 ; CHECK-NEXT:    [[SY:%.*]] = sext i1 [[Y:%.*]] to i32
 ; CHECK-NEXT:    call void @use32(i32 [[SY]])
 ; CHECK-NEXT:    [[MULBOOL:%.*]] = and i1 [[X:%.*]], [[Y]]
-; CHECK-NEXT:    [[R:%.*]] = zext i1 [[MULBOOL]] to i32
+; CHECK-NEXT:    [[R:%.*]] = zext was_sext i1 [[MULBOOL]] to i32
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %sx = sext i1 %x to i32
   %sy = sext i1 %y to i32
   call void @use32(i32 %sy)
   %r = mul i32 %sx, %sy
   ret i32 %r
 }
 
 define i32 @mul_bools_sext_use2(i1 %x, i1 %y) {
 ; CHECK-LABEL: @mul_bools_sext_use2(
 ; CHECK-NEXT:    [[SY:%.*]] = sext i1 [[Y:%.*]] to i32
 ; CHECK-NEXT:    call void @use32(i32 [[SY]])
 ; CHECK-NEXT:    [[MULBOOL:%.*]] = and i1 [[Y]], [[X:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = zext i1 [[MULBOOL]] to i32
+; CHECK-NEXT:    [[R:%.*]] = zext was_sext i1 [[MULBOOL]] to i32
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %sx = sext i1 %x to i32
   %sy = sext i1 %y to i32
   call void @use32(i32 %sy)
   %r = mul i32 %sy, %sx
   ret i32 %r
 }
;
   call void @use32(i32 %sy)
   %r = mul i32 %sy, %sx
   ret i32 %r
 }
 
 define i32 @mul_bools_sext_one_use_per_op(i1 %x, i1 %y) {
 ; CHECK-LABEL: @mul_bools_sext_one_use_per_op(
 ; CHECK-NEXT:    [[MULBOOL:%.*]] = and i1 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = zext i1 [[MULBOOL]] to i32
+; CHECK-NEXT:    [[R:%.*]] = zext was_sext i1 [[MULBOOL]] to i32
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %sx = sext i1 %x to i32
   %sy = sext i1 %y to i32
   %r = mul i32 %sx, %sy
   ret i32 %r
 }
 
 define i32 @mul_bool_sext_one_user(i1 %x) {
 ; CHECK-LABEL: @mul_bool_sext_one_user(
-; CHECK-NEXT:    [[R:%.*]] = zext i1 [[X:%.*]] to i32
+; CHECK-NEXT:    [[R:%.*]] = zext was_sext i1 [[X:%.*]] to i32
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %sx = sext i1 %x to i32
   %r = mul i32 %sx, %sx
   ret i32 %r
 }
 
 define i32 @mul_bools_zext_one_use_per_op(i1 %x, i1 %y) {
;
   %r = mul i32 %sx, %sx
   ret i32 %r
 }
 
 define i32 @mul_bool_sext_one_extra_user(i1 %x) {
 ; CHECK-LABEL: @mul_bool_sext_one_extra_user(
 ; CHECK-NEXT:    [[SX:%.*]] = sext i1 [[X:%.*]] to i32
 ; CHECK-NEXT:    call void @use32(i32 [[SX]])
-; CHECK-NEXT:    [[R:%.*]] = zext i1 [[X]] to i32
+; CHECK-NEXT:    [[R:%.*]] = zext was_sext i1 [[X]] to i32
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %sx = sext i1 %x to i32
   call void @use32(i32 %sx)
   %r = mul i32 %sx, %sx
   ret i32 %r
 }
 
;
   %B8 = sub i64 0, %v1
   %B4 = mul i64 %B8, %L1
   ret i64 %B4
 }
 
 define i32 @negate_if_true(i32 %x, i1 %cond) {
 ; CHECK-LABEL: @negate_if_true(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 0, [[X:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[X]]
+; CHECK-NEXT:    ret i32 [[R]]
 ;
   %sel = select i1 %cond, i32 -1, i32 1
   %r = mul i32 %sel, %x
   ret i32 %r
 }
 
 define i32 @negate_if_false(i32 %x, i1 %cond) {
 ; CHECK-LABEL: @negate_if_false(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 0, [[X:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[COND:%.*]], i32 [[X]], i32 [[TMP1]]
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[COND:%.*]], i32 [[X]], i32 [[TMP1]]
+; CHECK-NEXT:    ret i32 [[R]]
 ;
   %sel = select i1 %cond, i32 1, i32 -1
   %r = mul i32 %sel, %x
   ret i32 %r
 }
 
 define <2 x i8> @negate_if_true_commute(<2 x i8> %px, i1 %cond) {
 ; CHECK-LABEL: @negate_if_true_commute(
 ; CHECK-NEXT:    [[X:%.*]] = sdiv <2 x i8> <i8 42, i8 42>, [[PX:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub nsw <2 x i8> zeroinitializer, [[X]]
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[COND:%.*]], <2 x i8> [[TMP1]], <2 x i8> [[X]]
-; CHECK-NEXT:    ret <2 x i8> [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[COND:%.*]], <2 x i8> [[TMP1]], <2 x i8> [[X]]
+; CHECK-NEXT:    ret <2 x i8> [[R]]
 ;
   %x = sdiv <2 x i8> <i8 42, i8 42>, %px  ; thwart complexity-based canonicalization
   %sel = select i1 %cond, <2 x i8> <i8 -1, i8 -1>, <2 x i8> <i8 1, i8 1>
   %r = mul <2 x i8> %x, %sel
   ret <2 x i8> %r
 }
 
 define <2 x i8> @negate_if_false_commute(<2 x i8> %px, <2 x i1> %cond) {
 ; CHECK-LABEL: @negate_if_false_commute(
 ; CHECK-NEXT:    [[X:%.*]] = sdiv <2 x i8> <i8 42, i8 5>, [[PX:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub <2 x i8> zeroinitializer, [[X]]
-; CHECK-NEXT:    [[TMP2:%.*]] = select <2 x i1> [[COND:%.*]], <2 x i8> [[X]], <2 x i8> [[TMP1]]
-; CHECK-NEXT:    ret <2 x i8> [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[COND:%.*]], <2 x i8> [[X]], <2 x i8> [[TMP1]]
+; CHECK-NEXT:    ret <2 x i8> [[R]]
 ;
   %x = sdiv <2 x i8> <i8 42, i8 5>, %px  ; thwart complexity-based canonicalization
   %sel = select <2 x i1> %cond, <2 x i8> <i8 1, i8 undef>, <2 x i8> <i8 -1, i8 -1>
   %r = mul <2 x i8> %x, %sel
   ret <2 x i8> %r
 }
 
 ; Negative test

llvm/test/Transforms/InstCombine/narrow-math.ll

;
   %E = sext i32 %C to i64
   call void @use(i64 %E)
   %F = add i64 %D, %E
   ret i64 %F
 }
 
 define i64 @test1(i32 %V) {
 ; CHECK-LABEL: @test1(
-; CHECK-NEXT:    [[CALL1:%.*]] = call i32 @callee(), [[RNG0:!range !.*]]
-; CHECK-NEXT:    [[CALL2:%.*]] = call i32 @callee(), [[RNG0]]
+; CHECK-NEXT:    [[CALL1:%.*]] = call i32 @callee(), !range [[RNG0:![0-9]+]]
+; CHECK-NEXT:    [[CALL2:%.*]] = call i32 @callee(), !range [[RNG0]]
 ; CHECK-NEXT:    [[NARROW:%.*]] = add nuw nsw i32 [[CALL1]], [[CALL2]]
 ; CHECK-NEXT:    [[ADD:%.*]] = zext i32 [[NARROW]] to i64
 ; CHECK-NEXT:    ret i64 [[ADD]]
 ;
   %call1 = call i32 @callee(), !range !0
   %call2 = call i32 @callee(), !range !0
   %zext1 = sext i32 %call1 to i64
   %zext2 = sext i32 %call2 to i64
   %add = add i64 %zext1, %zext2
   ret i64 %add
 }
 
 define i64 @test2(i32 %V) {
 ; CHECK-LABEL: @test2(
-; CHECK-NEXT:    [[CALL1:%.*]] = call i32 @callee(), [[RNG0]]
-; CHECK-NEXT:    [[CALL2:%.*]] = call i32 @callee(), [[RNG0]]
+; CHECK-NEXT:    [[CALL1:%.*]] = call i32 @callee(), !range [[RNG0]]
+; CHECK-NEXT:    [[CALL2:%.*]] = call i32 @callee(), !range [[RNG0]]
 ; CHECK-NEXT:    [[ADD:%.*]] = add nuw nsw i32 [[CALL1]], [[CALL2]]
-; CHECK-NEXT:    [[ZEXT:%.*]] = zext i32 [[ADD]] to i64
+; CHECK-NEXT:    [[ZEXT:%.*]] = zext was_sext i32 [[ADD]] to i64
 ; CHECK-NEXT:    ret i64 [[ZEXT]]
 ;
   %call1 = call i32 @callee(), !range !0
   %call2 = call i32 @callee(), !range !0
   %add = add i32 %call1, %call2
   %zext = sext i32 %add to i64
   ret i64 %zext
 }
 
 define i64 @test3(i32 %V) {
 ; CHECK-LABEL: @test3(
-; CHECK-NEXT:    [[CALL1:%.*]] = call i32 @callee(), [[RNG0]]
-; CHECK-NEXT:    [[CALL2:%.*]] = call i32 @callee(), [[RNG0]]
+; CHECK-NEXT:    [[CALL1:%.*]] = call i32 @callee(), !range [[RNG0]]
+; CHECK-NEXT:    [[CALL2:%.*]] = call i32 @callee(), !range [[RNG0]]
 ; CHECK-NEXT:    [[NARROW:%.*]] = mul nuw nsw i32 [[CALL1]], [[CALL2]]
 ; CHECK-NEXT:    [[ADD:%.*]] = zext i32 [[NARROW]] to i64
 ; CHECK-NEXT:    ret i64 [[ADD]]
 ;
   %call1 = call i32 @callee(), !range !0
   %call2 = call i32 @callee(), !range !0
   %zext1 = sext i32 %call1 to i64
   %zext2 = sext i32 %call2 to i64
   %add = mul i64 %zext1, %zext2
   ret i64 %add
 }
 
 define i64 @test4(i32 %V) {
 ; CHECK-LABEL: @test4(
-; CHECK-NEXT:    [[CALL1:%.*]] = call i32 @callee(), [[RNG0]]
-; CHECK-NEXT:    [[CALL2:%.*]] = call i32 @callee(), [[RNG0]]
+; CHECK-NEXT:    [[CALL1:%.*]] = call i32 @callee(), !range [[RNG0]]
+; CHECK-NEXT:    [[CALL2:%.*]] = call i32 @callee(), !range [[RNG0]]
 ; CHECK-NEXT:    [[ADD:%.*]] = mul nuw nsw i32 [[CALL1]], [[CALL2]]
-; CHECK-NEXT:    [[ZEXT:%.*]] = zext i32 [[ADD]] to i64
+; CHECK-NEXT:    [[ZEXT:%.*]] = zext was_sext i32 [[ADD]] to i64
 ; CHECK-NEXT:    ret i64 [[ZEXT]]
 ;
   %call1 = call i32 @callee(), !range !0
   %call2 = call i32 @callee(), !range !0
   %add = mul i32 %call1, %call2
   %zext = sext i32 %add to i64
   ret i64 %zext
 }
;
   %lshr = lshr <2 x i32> %V, <i32 16, i32 16>
   %zext = zext <2 x i32> %lshr to <2 x i64>
   %mul = mul <2 x i64> %zext, <i64 65535, i64 2>
   ret <2 x i64> %mul
 }
 
 define i64 @test11(i32 %V) {
 ; CHECK-LABEL: @test11(
-; CHECK-NEXT:    [[CALL1:%.*]] = call i32 @callee(), [[RNG1:!range !.*]]
-; CHECK-NEXT:    [[CALL2:%.*]] = call i32 @callee(), [[RNG1]]
+; CHECK-NEXT:    [[CALL1:%.*]] = call i32 @callee(), !range [[RNG1:![0-9]+]]
+; CHECK-NEXT:    [[CALL2:%.*]] = call i32 @callee(), !range [[RNG1]]
 ; CHECK-NEXT:    [[NARROW:%.*]] = add nsw i32 [[CALL1]], [[CALL2]]
 ; CHECK-NEXT:    [[ADD:%.*]] = sext i32 [[NARROW]] to i64
 ; CHECK-NEXT:    ret i64 [[ADD]]
 ;
   %call1 = call i32 @callee(), !range !1
   %call2 = call i32 @callee(), !range !1
   %sext1 = sext i32 %call1 to i64
   %sext2 = sext i32 %call2 to i64
   %add = add i64 %sext1, %sext2
   ret i64 %add
 }
 
 define i64 @test12(i32 %V) {
 ; CHECK-LABEL: @test12(
-; CHECK-NEXT:    [[CALL1:%.*]] = call i32 @callee(), [[RNG1]]
-; CHECK-NEXT:    [[CALL2:%.*]] = call i32 @callee(), [[RNG1]]
+; CHECK-NEXT:    [[CALL1:%.*]] = call i32 @callee(), !range [[RNG1]]
+; CHECK-NEXT:    [[CALL2:%.*]] = call i32 @callee(), !range [[RNG1]]
 ; CHECK-NEXT:    [[NARROW:%.*]] = mul nsw i32 [[CALL1]], [[CALL2]]
-; CHECK-NEXT:    [[ADD:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT:    [[ADD:%.*]] = zext was_sext i32 [[NARROW]] to i64
 ; CHECK-NEXT:    ret i64 [[ADD]]
 ;
   %call1 = call i32 @callee(), !range !1
   %call2 = call i32 @callee(), !range !1
   %sext1 = sext i32 %call1 to i64
   %sext2 = sext i32 %call2 to i64
   %add = mul i64 %sext1, %sext2
   ret i64 %add
 }
 
 define i64 @test13(i32 %V) {
 ; CHECK-LABEL: @test13(
-; CHECK-NEXT:    [[CALL1:%.*]] = call i32 @callee(), [[RNG2:!range !.*]]
-; CHECK-NEXT:    [[CALL2:%.*]] = call i32 @callee(), [[RNG3:!range !.*]]
+; CHECK-NEXT:    [[CALL1:%.*]] = call i32 @callee(), !range [[RNG2:![0-9]+]]
+; CHECK-NEXT:    [[CALL2:%.*]] = call i32 @callee(), !range [[RNG3:![0-9]+]]
 ; CHECK-NEXT:    [[NARROW:%.*]] = sub nsw i32 [[CALL1]], [[CALL2]]
 ; CHECK-NEXT:    [[SUB:%.*]] = sext i32 [[NARROW]] to i64
 ; CHECK-NEXT:    ret i64 [[SUB]]
 ;
   %call1 = call i32 @callee(), !range !2
   %call2 = call i32 @callee(), !range !3
   %sext1 = sext i32 %call1 to i64
   %sext2 = sext i32 %call2 to i64
   %sub = sub i64 %sext1, %sext2
   ret i64 %sub
 }
 
 define i64 @test14(i32 %V) {
 ; CHECK-LABEL: @test14(
-; CHECK-NEXT:    [[CALL1:%.*]] = call i32 @callee(), [[RNG2]]
-; CHECK-NEXT:    [[CALL2:%.*]] = call i32 @callee(), [[RNG0]]
+; CHECK-NEXT:    [[CALL1:%.*]] = call i32 @callee(), !range [[RNG2]]
+; CHECK-NEXT:    [[CALL2:%.*]] = call i32 @callee(), !range [[RNG0]]
 ; CHECK-NEXT:    [[NARROW:%.*]] = sub nuw nsw i32 [[CALL1]], [[CALL2]]
 ; CHECK-NEXT:    [[SUB:%.*]] = zext i32 [[NARROW]] to i64
 ; CHECK-NEXT:    ret i64 [[SUB]]
 ;
   %call1 = call i32 @callee(), !range !2
   %call2 = call i32 @callee(), !range !0
   %zext1 = zext i32 %call1 to i64
   %zext2 = zext i32 %call2 to i64
;
   %sub = sub <2 x i64> <i64 4294967294, i64 4294967294>, %zext
   ret <2 x i64> %sub
 }
 
 ; Negative test. Both have the same range so we can't guarantee the subtract
 ; won't wrap.
 define i64 @test17(i32 %V) {
 ; CHECK-LABEL: @test17(
-; CHECK-NEXT:    [[CALL1:%.*]] = call i32 @callee(), [[RNG0]]
-; CHECK-NEXT:    [[CALL2:%.*]] = call i32 @callee(), [[RNG0]]
+; CHECK-NEXT:    [[CALL1:%.*]] = call i32 @callee(), !range [[RNG0]]
+; CHECK-NEXT:    [[CALL2:%.*]] = call i32 @callee(), !range [[RNG0]]
 ; CHECK-NEXT:    [[SEXT1:%.*]] = zext i32 [[CALL1]] to i64
 ; CHECK-NEXT:    [[SEXT2:%.*]] = zext i32 [[CALL2]] to i64
 ; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i64 [[SEXT1]], [[SEXT2]]
 ; CHECK-NEXT:    ret i64 [[SUB]]
 ;
   %call1 = call i32 @callee(), !range !0
   %call2 = call i32 @callee(), !range !0
   %sext1 = zext i32 %call1 to i64
   %sext2 = zext i32 %call2 to i64
   %sub = sub i64 %sext1, %sext2
   ret i64 %sub
 }
 
 ; Negative test. LHS is large positive 32-bit number. Range of callee can
 ; cause overflow.
 define i64 @test18(i32 %V) {
 ; CHECK-LABEL: @test18(
-; CHECK-NEXT:    [[CALL1:%.*]] = call i32 @callee(), [[RNG1]]
+; CHECK-NEXT:    [[CALL1:%.*]] = call i32 @callee(), !range [[RNG1]]
 ; CHECK-NEXT:    [[SEXT1:%.*]] = sext i32 [[CALL1]] to i64
 ; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i64 2147481648, [[SEXT1]]
 ; CHECK-NEXT:    ret i64 [[SUB]]
 ;
   %call1 = call i32 @callee(), !range !1
   %sext1 = sext i32 %call1 to i64
   %sub = sub i64 2147481648, %sext1
   ret i64 %sub
 }
 
 ; Negative test. LHS is large negative 32-bit number. Range of callee can
 ; cause overflow.
 define i64 @test19(i32 %V) {
 ; CHECK-LABEL: @test19(
-; CHECK-NEXT:    [[CALL1:%.*]] = call i32 @callee(), [[RNG0]]
-; CHECK-NEXT:    [[SEXT1:%.*]] = zext i32 [[CALL1]] to i64
+; CHECK-NEXT:    [[CALL1:%.*]] = call i32 @callee(), !range [[RNG0]]
+; CHECK-NEXT:    [[SEXT1:%.*]] = zext was_sext i32 [[CALL1]] to i64
 ; CHECK-NEXT:    [[SUB:%.*]] = sub nuw nsw i64 -2147481648, [[SEXT1]]
 ; CHECK-NEXT:    ret i64 [[SUB]]
 ;
   %call1 = call i32 @callee(), !range !0
   %sext1 = sext i32 %call1 to i64
   %sub = sub i64 -2147481648, %sext1
   ret i64 %sub
 }
 
 !0 = !{ i32 0, i32 2000 }
 !1 = !{ i32 -2000, i32 0 }
 !2 = !{ i32 -512, i32 -255 }
 !3 = !{ i32 -128, i32 0 }

llvm/test/Transforms/InstCombine/select_meta.ll

;
   %5 = sub nsw i32 %0, %1
   select i1 %3, i32 %4, i32 %5, !prof !1
   ret i32 %6
 }
 
 define i64 @test43(i32 %a) nounwind {
 ; CHECK-LABEL: @test43(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 0)
-; CHECK-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
-; CHECK-NEXT:    ret i64 [[TMP2]]
+; CHECK-NEXT:    [[MAX:%.*]] = zext was_sext i32 [[TMP1]] to i64
+; CHECK-NEXT:    ret i64 [[MAX]]
 ;
   %a_ext = sext i32 %a to i64
   %is_a_nonnegative = icmp sgt i32 %a, -1
   %max = select i1 %is_a_nonnegative, i64 %a_ext, i64 0, !prof !1
   ret i64 %max
 }
 
 define <2 x i32> @scalar_select_of_vectors_sext(<2 x i1> %cca, i1 %ccb) {
;
   %sub16 = sub nsw <2 x i32> zeroinitializer, %cond
   %cond18 = select <2 x i1> %cmp1, <2 x i32> %cond, <2 x i32> %sub16, !prof !2
   ret <2 x i32> %cond18
 }
 
 ; SMAX(SMAX(x, y), x) -> SMAX(x, y)
 define i32 @test30(i32 %x, i32 %y) {
 ; CHECK-LABEL: @test30(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[COND:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
+; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp sgt i32 %x, %y
   %cond = select i1 %cmp, i32 %x, i32 %y, !prof !1
   %cmp5 = icmp sgt i32 %cond, %x
   %retval = select i1 %cmp5, i32 %cond, i32 %x, !prof !2
   ret i32 %retval
 }
 
 ; SMAX(SMAX(75, X), 36) -> SMAX(X, 75)
 define i32 @test70(i32 %x) {
 ; CHECK-LABEL: @test70(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 75)
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[COND:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 75)
+; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp slt i32 %x, 75
   %cond = select i1 %cmp, i32 75, i32 %x, !prof !1
   %cmp3 = icmp slt i32 %cond, 36
   %retval = select i1 %cmp3, i32 36, i32 %cond, !prof !2
   ret i32 %retval
 }
 
 ; Swap predicate / metadata order
 ; SMIN(SMIN(X, 92), 11) -> SMIN(X, 11)
 define i32 @test72(i32 %x) {
 ; CHECK-LABEL: @test72(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 11)
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[RETVAL:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 11)
+; CHECK-NEXT:    ret i32 [[RETVAL]]
 ;
   %cmp = icmp sgt i32 %x, 92
   %cond = select i1 %cmp, i32 92, i32 %x, !prof !1
   %cmp3 = icmp sgt i32 %cond, 11
   %retval = select i1 %cmp3, i32 11, i32 %cond, !prof !2
   ret i32 %retval
 }
 
 ; Swap predicate / metadata order
 ; SMAX(SMAX(X, 36), 75) -> SMAX(X, 75)
 define i32 @test74(i32 %x) {
 ; CHECK-LABEL: @test74(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 36)
-; CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.umax.i32(i32 [[TMP1]], i32 75)
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[COND:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 36)
+; CHECK-NEXT:    [[RETVAL:%.*]] = call i32 @llvm.umax.i32(i32 [[COND]], i32 75)
+; CHECK-NEXT:    ret i32 [[RETVAL]]
 ;
   %cmp = icmp slt i32 %x, 36
   %cond = select i1 %cmp, i32 36, i32 %x, !prof !1
   %cmp3 = icmp slt i32 %cond, 75
   %retval = select i1 %cmp3, i32 75, i32 %cond, !prof !2
   ret i32 %retval
 }
 
 ; The xor is moved after the select. The metadata remains the same because the select operands are not swapped only inverted.
 define i32 @smin1(i32 %x) {
 ; CHECK-LABEL: @smin1(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 0)
-; CHECK-NEXT:    [[TMP2:%.*]] = xor i32 [[TMP1]], -1
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[SEL:%.*]] = xor i32 [[TMP1]], -1
+; CHECK-NEXT:    ret i32 [[SEL]]
 ;
   %not_x = xor i32 %x, -1
   %cmp = icmp sgt i32 %x, 0
   %sel = select i1 %cmp, i32 %not_x, i32 -1, !prof !1
   ret i32 %sel
 }
 
 ; The compare should change, and the metadata is swapped because the select operands are swapped and inverted.
 define i32 @smin2(i32 %x) {
 ; CHECK-LABEL: @smin2(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 0)
-; CHECK-NEXT:    [[TMP2:%.*]] = xor i32 [[TMP1]], -1
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[SEL:%.*]] = xor i32 [[TMP1]], -1
+; CHECK-NEXT:    ret i32 [[SEL]]
 ;
   %not_x = xor i32 %x, -1
   %cmp = icmp slt i32 %x, 0
   %sel = select i1 %cmp, i32 -1, i32 %not_x, !prof !1
   ret i32 %sel
 }
 
 ; The xor is moved after the select. The metadata remains the same because the select operands are not swapped only inverted.
 define i32 @smax1(i32 %x) {
 ; CHECK-LABEL: @smax1(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 0)
-; CHECK-NEXT:    [[TMP2:%.*]] = xor i32 [[TMP1]], -1
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[SEL:%.*]] = xor i32 [[TMP1]], -1
+; CHECK-NEXT:    ret i32 [[SEL]]
 ;
   %not_x = xor i32 %x, -1
   %cmp = icmp slt i32 %x, 0
   %sel = select i1 %cmp, i32 %not_x, i32 -1, !prof !1
   ret i32 %sel
 }
 
 ; The compare should change, and the metadata is swapped because the select operands are swapped and inverted.
 define i32 @smax2(i32 %x) {
 ; CHECK-LABEL: @smax2(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 0)
-; CHECK-NEXT:    [[TMP2:%.*]] = xor i32 [[TMP1]], -1
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[SEL:%.*]] = xor i32 [[TMP1]], -1
+; CHECK-NEXT:    ret i32 [[SEL]]
 ;
   %not_x = xor i32 %x, -1
   %cmp = icmp sgt i32 %x, 0
   %sel = select i1 %cmp, i32 -1, i32 %not_x, !prof !1
   ret i32 %sel
 }
 
 ; The compare should change, but the metadata remains the same because the select operands are not swapped.
 define i32 @umin1(i32 %x) {
 ; CHECK-LABEL: @umin1(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[X:%.*]], i32 -2147483648)
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[SEL:%.*]] = call i32 @llvm.umin.i32(i32 [[X:%.*]], i32 -2147483648)
+; CHECK-NEXT:    ret i32 [[SEL]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sel = select i1 %cmp, i32 %x, i32 -2147483648, !prof !1
   ret i32 %sel
 }
 
 ; The compare should change, and the metadata is swapped because the select operands are swapped.
 define i32 @umin2(i32 %x) {
 ; CHECK-LABEL: @umin2(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[X:%.*]], i32 2147483647)
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[SEL:%.*]] = call i32 @llvm.umin.i32(i32 [[X:%.*]], i32 2147483647)
+; CHECK-NEXT:    ret i32 [[SEL]]
 ;
   %cmp = icmp slt i32 %x, 0
   %sel = select i1 %cmp, i32 2147483647, i32 %x, !prof !1
   ret i32 %sel
 }
 
 ; The compare should change, but the metadata remains the same because the select operands are not swapped.
 define i32 @umax1(i32 %x) {
 ; CHECK-LABEL: @umax1(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[X:%.*]], i32 2147483647)
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[SEL:%.*]] = call i32 @llvm.umax.i32(i32 [[X:%.*]], i32 2147483647)
+; CHECK-NEXT:    ret i32 [[SEL]]
 ;
   %cmp = icmp slt i32 %x, 0
   %sel = select i1 %cmp, i32 %x, i32 2147483647, !prof !1
   ret i32 %sel
 }
 
 ; The compare should change, and the metadata is swapped because the select operands are swapped.
 define i32 @umax2(i32 %x) {
 ; CHECK-LABEL: @umax2(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[X:%.*]], i32 -2147483648)
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[SEL:%.*]] = call i32 @llvm.umax.i32(i32 [[X:%.*]], i32 -2147483648)
+; CHECK-NEXT:    ret i32 [[SEL]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sel = select i1 %cmp, i32 -2147483648, i32 %x, !prof !1
   ret i32 %sel
 }
 
 ; The condition is inverted, and the select ops are swapped. The metadata should be swapped.
 

llvm/test/Transforms/InstCombine/sext.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 
 declare i32 @llvm.ctpop.i32(i32)
 declare i32 @llvm.ctlz.i32(i32, i1)
 declare i32 @llvm.cttz.i32(i32, i1)
 declare void @use(i8)
 declare void @use_vec(<2 x i5>)
 
 define i64 @test1(i32 %x) {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:    [[T:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0:![0-9]+]]
-; CHECK-NEXT:    [[S:%.*]] = zext i32 [[T]] to i64
+; CHECK-NEXT:    [[S:%.*]] = zext was_sext i32 [[T]] to i64
 ; CHECK-NEXT:    ret i64 [[S]]
 ;
   %t = call i32 @llvm.ctpop.i32(i32 %x)
   %s = sext i32 %t to i64
   ret i64 %s
 }
 
 define i64 @test2(i32 %x) {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:    [[T:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0]]
-; CHECK-NEXT:    [[S:%.*]] = zext i32 [[T]] to i64
+; CHECK-NEXT:    [[S:%.*]] = zext was_sext i32 [[T]] to i64
 ; CHECK-NEXT:    ret i64 [[S]]
 ;
   %t = call i32 @llvm.ctlz.i32(i32 %x, i1 true)
   %s = sext i32 %t to i64
   ret i64 %s
 }
 
 define i64 @test3(i32 %x) {
 ; CHECK-LABEL: @test3(
 ; CHECK-NEXT:    [[T:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0]]
-; CHECK-NEXT:    [[S:%.*]] = zext i32 [[T]] to i64
+; CHECK-NEXT:    [[S:%.*]] = zext was_sext i32 [[T]] to i64
 ; CHECK-NEXT:    ret i64 [[S]]
 ;
   %t = call i32 @llvm.cttz.i32(i32 %x, i1 true)
   %s = sext i32 %t to i64
   ret i64 %s
 }
 
 define i64 @test4(i32 %x) {
 ; CHECK-LABEL: @test4(
 ; CHECK-NEXT:    [[T:%.*]] = udiv i32 [[X:%.*]], 3
-; CHECK-NEXT:    [[S:%.*]] = zext i32 [[T]] to i64
+; CHECK-NEXT:    [[S:%.*]] = zext was_sext i32 [[T]] to i64
 ; CHECK-NEXT:    ret i64 [[S]]
 ;
   %t = udiv i32 %x, 3
   %s = sext i32 %t to i64
   ret i64 %s
 }
 
 define i64 @test5(i32 %x) {
 ; CHECK-LABEL: @test5(
 ; CHECK-NEXT:    [[T:%.*]] = urem i32 [[X:%.*]], 30000
-; CHECK-NEXT:    [[S:%.*]] = zext i32 [[T]] to i64
+; CHECK-NEXT:    [[S:%.*]] = zext was_sext i32 [[T]] to i64
 ; CHECK-NEXT:    ret i64 [[S]]
 ;
   %t = urem i32 %x, 30000
   %s = sext i32 %t to i64
   ret i64 %s
 }
 
 define i64 @test6(i32 %x) {
 ; CHECK-LABEL: @test6(
 ; CHECK-NEXT:    [[U:%.*]] = lshr i32 [[X:%.*]], 3
 ; CHECK-NEXT:    [[T:%.*]] = mul nuw nsw i32 [[U]], 3
-; CHECK-NEXT:    [[S:%.*]] = zext i32 [[T]] to i64
+; CHECK-NEXT:    [[S:%.*]] = zext was_sext i32 [[T]] to i64
 ; CHECK-NEXT:    ret i64 [[S]]
 ;
   %u = lshr i32 %x, 3
   %t = mul i32 %u, 3
   %s = sext i32 %t to i64
   ret i64 %s
 }
 
 define i64 @test7(i32 %x) {
 ; CHECK-LABEL: @test7(
 ; CHECK-NEXT:    [[T:%.*]] = and i32 [[X:%.*]], 511
 ; CHECK-NEXT:    [[U:%.*]] = sub nuw nsw i32 20000, [[T]]
-; CHECK-NEXT:    [[S:%.*]] = zext i32 [[U]] to i64
+; CHECK-NEXT:    [[S:%.*]] = zext was_sext i32 [[U]] to i64
 ; CHECK-NEXT:    ret i64 [[S]]
 ;
   %t = and i32 %x, 511
   %u = sub i32 20000, %t
   %s = sext i32 %u to i64
   ret i64 %s
 }
 

 ;
   %c1 = sext i1 %x to i32
   %c2 = sub i32 0, %c1
   ret i32 %c2
 }
 
 define i32 @test18(i16 %x) {
 ; CHECK-LABEL: @test18(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i16 @llvm.smax.i16(i16 [[X:%.*]], i16 0)
-; CHECK-NEXT:    [[EXT:%.*]] = zext i16 [[TMP1]] to i32
+; CHECK-NEXT:    [[SEL:%.*]] = call i16 @llvm.smax.i16(i16 [[X:%.*]], i16 0)
+; CHECK-NEXT:    [[EXT:%.*]] = zext was_sext i16 [[SEL]] to i32
 ; CHECK-NEXT:    ret i32 [[EXT]]
 ;
   %cmp = icmp slt i16 %x, 0
   %sel = select i1 %cmp, i16 0, i16 %x
   %ext = sext i16 %sel to i32
   ret i32 %ext
 }
 

llvm/test/Transforms/InstCombine/shift-by-signext.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
 
 ; If we have a shift by sign-extended value, we can replace sign-extension
 ; with zero-extension.
 
 define i32 @t0_shl(i32 %x, i8 %shamt) {
 ; CHECK-LABEL: @t0_shl(
-; CHECK-NEXT:    [[SHAMT_WIDE1:%.*]] = zext i8 [[SHAMT:%.*]] to i32
+; CHECK-NEXT:    [[SHAMT_WIDE1:%.*]] = zext was_sext i8 [[SHAMT:%.*]] to i32
 ; CHECK-NEXT:    [[R:%.*]] = shl i32 [[X:%.*]], [[SHAMT_WIDE1]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %shamt_wide = sext i8 %shamt to i32
   %r = shl i32 %x, %shamt_wide
   ret i32 %r
 }
 define i32 @t1_lshr(i32 %x, i8 %shamt) {
 ; CHECK-LABEL: @t1_lshr(
-; CHECK-NEXT:    [[SHAMT_WIDE1:%.*]] = zext i8 [[SHAMT:%.*]] to i32
+; CHECK-NEXT:    [[SHAMT_WIDE1:%.*]] = zext was_sext i8 [[SHAMT:%.*]] to i32
 ; CHECK-NEXT:    [[R:%.*]] = lshr i32 [[X:%.*]], [[SHAMT_WIDE1]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %shamt_wide = sext i8 %shamt to i32
   %r = lshr i32 %x, %shamt_wide
   ret i32 %r
 }
 define i32 @t2_ashr(i32 %x, i8 %shamt) {
 ; CHECK-LABEL: @t2_ashr(
-; CHECK-NEXT:    [[SHAMT_WIDE1:%.*]] = zext i8 [[SHAMT:%.*]] to i32
+; CHECK-NEXT:    [[SHAMT_WIDE1:%.*]] = zext was_sext i8 [[SHAMT:%.*]] to i32
 ; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X:%.*]], [[SHAMT_WIDE1]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %shamt_wide = sext i8 %shamt to i32
   %r = ashr i32 %x, %shamt_wide
   ret i32 %r
 }
 
 define <2 x i32> @t3_vec_shl(<2 x i32> %x, <2 x i8> %shamt) {
 ; CHECK-LABEL: @t3_vec_shl(
-; CHECK-NEXT:    [[SHAMT_WIDE1:%.*]] = zext <2 x i8> [[SHAMT:%.*]] to <2 x i32>
+; CHECK-NEXT:    [[SHAMT_WIDE1:%.*]] = zext was_sext <2 x i8> [[SHAMT:%.*]] to <2 x i32>
 ; CHECK-NEXT:    [[R:%.*]] = shl <2 x i32> [[X:%.*]], [[SHAMT_WIDE1]]
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
   %shamt_wide = sext <2 x i8> %shamt to <2 x i32>
   %r = shl <2 x i32> %x, %shamt_wide
   ret <2 x i32> %r
 }
 define <2 x i32> @t4_vec_lshr(<2 x i32> %x, <2 x i8> %shamt) {
 ; CHECK-LABEL: @t4_vec_lshr(
-; CHECK-NEXT:    [[SHAMT_WIDE1:%.*]] = zext <2 x i8> [[SHAMT:%.*]] to <2 x i32>
+; CHECK-NEXT:    [[SHAMT_WIDE1:%.*]] = zext was_sext <2 x i8> [[SHAMT:%.*]] to <2 x i32>
 ; CHECK-NEXT:    [[R:%.*]] = lshr <2 x i32> [[X:%.*]], [[SHAMT_WIDE1]]
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
   %shamt_wide = sext <2 x i8> %shamt to <2 x i32>
   %r = lshr <2 x i32> %x, %shamt_wide
   ret <2 x i32> %r
 }
 define <2 x i32> @t5_vec_ashr(<2 x i32> %x, <2 x i8> %shamt) {
 ; CHECK-LABEL: @t5_vec_ashr(
-; CHECK-NEXT:    [[SHAMT_WIDE1:%.*]] = zext <2 x i8> [[SHAMT:%.*]] to <2 x i32>
+; CHECK-NEXT:    [[SHAMT_WIDE1:%.*]] = zext was_sext <2 x i8> [[SHAMT:%.*]] to <2 x i32>
 ; CHECK-NEXT:    [[R:%.*]] = ashr <2 x i32> [[X:%.*]], [[SHAMT_WIDE1]]
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
   %shamt_wide = sext <2 x i8> %shamt to <2 x i32>
   %r = ashr <2 x i32> %x, %shamt_wide
   ret <2 x i32> %r
 }
 

llvm/test/Transforms/InstCombine/udiv-simplify.ll

 
 ; The udiv instructions shouldn't be optimized away, and the
 ; sext instructions should be optimized to zext.
 
 define i64 @test1_PR2274(i32 %x, i32 %g) nounwind {
 ; CHECK-LABEL: @test1_PR2274(
 ; CHECK-NEXT:    [[Y:%.*]] = lshr i32 [[X:%.*]], 30
 ; CHECK-NEXT:    [[R:%.*]] = udiv i32 [[Y]], [[G:%.*]]
-; CHECK-NEXT:    [[Z:%.*]] = zext i32 [[R]] to i64
+; CHECK-NEXT:    [[Z:%.*]] = zext was_sext i32 [[R]] to i64
 ; CHECK-NEXT:    ret i64 [[Z]]
 ;
   %y = lshr i32 %x, 30
   %r = udiv i32 %y, %g
   %z = sext i32 %r to i64
   ret i64 %z
 }
 define i64 @test2_PR2274(i32 %x, i32 %v) nounwind {
 ; CHECK-LABEL: @test2_PR2274(
 ; CHECK-NEXT:    [[Y:%.*]] = lshr i32 [[X:%.*]], 31
 ; CHECK-NEXT:    [[R:%.*]] = udiv i32 [[Y]], [[V:%.*]]
-; CHECK-NEXT:    [[Z:%.*]] = zext i32 [[R]] to i64
+; CHECK-NEXT:    [[Z:%.*]] = zext was_sext i32 [[R]] to i64
 ; CHECK-NEXT:    ret i64 [[Z]]
 ;
   %y = lshr i32 %x, 31
   %r = udiv i32 %y, %v
   %z = sext i32 %r to i64
   ret i64 %z
 }
 

llvm/test/Transforms/InstCombine/wcslen-1.ll

 ;
   %str_l = call i64 @wcslen(ptr %str_p)
   %ne_null = icmp ne i64 %str_l, 0
   ret i1 %ne_null
 }
 
 define i64 @test_simplify9(i1 %x) {
 ; CHECK-LABEL: @test_simplify9(
-; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[X:%.*]], i64 5, i64 6
-; CHECK-NEXT:    ret i64 [[TMP1]]
+; CHECK-NEXT:    [[L:%.*]] = select i1 [[X:%.*]], i64 5, i64 6
+; CHECK-NEXT:    ret i64 [[L]]
 ;
   %s = select i1 %x, ptr @hello, ptr @longer
   %l = call i64 @wcslen(ptr %s)
   ret i64 %l
 }
 
 ; Check the case that should be simplified to a sub instruction.
 ; wcslen(@hello + x) --> 5 - x
 
 define i64 @test_simplify10(i32 %x) {
 ; CHECK-LABEL: @test_simplify10(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sext i32 [[X:%.*]] to i64
-; CHECK-NEXT:    [[TMP2:%.*]] = sub nsw i64 5, [[TMP1]]
-; CHECK-NEXT:    ret i64 [[TMP2]]
+; CHECK-NEXT:    [[HELLO_L:%.*]] = sub nsw i64 5, [[TMP1]]
+; CHECK-NEXT:    ret i64 [[HELLO_L]]
 ;
   %hello_p = getelementptr inbounds [6 x i32], ptr @hello, i32 0, i32 %x
   %hello_l = call i64 @wcslen(ptr %hello_p)
   ret i64 %hello_l
 }
 
 ; wcslen(@null_hello_mid + (x & 7)) --> 9 - (x & 7)
 
 define i64 @test_simplify11(i32 %x) {
 ; CHECK-LABEL: @test_simplify11(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 7
 ; CHECK-NEXT:    [[NARROW:%.*]] = sub nuw nsw i32 9, [[AND]]
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i32 [[NARROW]] to i64
-; CHECK-NEXT:    ret i64 [[TMP1]]
+; CHECK-NEXT:    [[HELLO_L:%.*]] = zext i32 [[NARROW]] to i64
+; CHECK-NEXT:    ret i64 [[HELLO_L]]
 ;
   %and = and i32 %x, 7
   %hello_p = getelementptr inbounds [13 x i32], ptr @null_hello_mid, i32 0, i32 %and
   %hello_l = call i64 @wcslen(ptr %hello_p)
   ret i64 %hello_l
 }
 
 ; Check cases that shouldn't be simplified.
;
   ret i64 %hello_l
 }
 
 ; wcslen(@null_hello_mid + (x & 15)) should not be simplified to a sub instruction.
 
 define i64 @test_no_simplify3(i32 %x) {
 ; CHECK-LABEL: @test_no_simplify3(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 15
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i32 [[AND]] to i64
+; CHECK-NEXT:    [[TMP1:%.*]] = zext was_sext i32 [[AND]] to i64
 ; CHECK-NEXT:    [[HELLO_P:%.*]] = getelementptr inbounds [13 x i32], ptr @null_hello_mid, i64 0, i64 [[TMP1]]
 ; CHECK-NEXT:    [[HELLO_L:%.*]] = call i64 @wcslen(ptr nonnull [[HELLO_P]])
 ; CHECK-NEXT:    ret i64 [[HELLO_L]]
 ;
   %and = and i32 %x, 15
   %hello_p = getelementptr inbounds [13 x i32], ptr @null_hello_mid, i32 0, i32 %and
   %hello_l = call i64 @wcslen(ptr %hello_p)
   ret i64 %hello_l
 }
 
 define i64 @test_no_simplify3_no_null_opt(i32 %x) #0 {
 ; CHECK-LABEL: @test_no_simplify3_no_null_opt(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 15
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i32 [[AND]] to i64
+; CHECK-NEXT:    [[TMP1:%.*]] = zext was_sext i32 [[AND]] to i64
 ; CHECK-NEXT:    [[HELLO_P:%.*]] = getelementptr inbounds [13 x i32], ptr @null_hello_mid, i64 0, i64 [[TMP1]]
 ; CHECK-NEXT:    [[HELLO_L:%.*]] = call i64 @wcslen(ptr [[HELLO_P]])
 ; CHECK-NEXT:    ret i64 [[HELLO_L]]
 ;
   %and = and i32 %x, 15
   %hello_p = getelementptr inbounds [13 x i32], ptr @null_hello_mid, i32 0, i32 %and
   %hello_l = call i64 @wcslen(ptr %hello_p)
   ret i64 %hello_l
;
   ret i64 %len
 }
 
 ; Should not crash on this, and no optimization expected (idea is to get into
 ; llvm::getConstantDataArrayInfo looking for an array with 32-bit elements but
 ; with an offset that isn't a multiple of the element size).
 define i64 @no_fold_wcslen_1() {
 ; CHECK-LABEL: @no_fold_wcslen_1(
-; CHECK-NEXT:    %len = tail call i64 @wcslen(ptr nonnull getelementptr inbounds ([15 x i8], ptr @ws, i64 0, i64 3))
-; CHECK-NEXT:    ret i64 %len
+; CHECK-NEXT:    [[LEN:%.*]] = tail call i64 @wcslen(ptr nonnull getelementptr inbounds ([15 x i8], ptr @ws, i64 0, i64 3))
+; CHECK-NEXT:    ret i64 [[LEN]]
 ;
   %p = getelementptr [15 x i8], ptr @ws, i64 0, i64 3
   %len = tail call i64 @wcslen(ptr %p)
   ret i64 %len
 }
 
 @s8 = constant [10 x i8] [i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0]
 
 ; Should not crash on this, and no optimization expected (idea is to get into
 ; llvm::getConstantDataArrayInfo looking for an array with 32-bit elements but
 ; with an offset that isn't a multiple of the element size).
 define i64 @no_fold_wcslen_2() {
 ; CHECK-LABEL: @no_fold_wcslen_2(
-; CHECK-NEXT:    %len = tail call i64 @wcslen(ptr nonnull getelementptr inbounds ([10 x i8], ptr @s8, i64 0, i64 3))
-; CHECK-NEXT:    ret i64 %len
+; CHECK-NEXT:    [[LEN:%.*]] = tail call i64 @wcslen(ptr nonnull getelementptr inbounds ([10 x i8], ptr @s8, i64 0, i64 3))
+; CHECK-NEXT:    ret i64 [[LEN]]
 ;
   %p = getelementptr [10 x i8], ptr @s8, i64 0, i64 3
   %len = tail call i64 @wcslen(ptr %p)
   ret i64 %len
 }
 
 attributes #0 = { null_pointer_is_valid }

llvm/test/Transforms/InstCombine/wcslen-3.ll

 ;
   %str_l = call i64 @wcslen(ptr %str_p)
   %ne_null = icmp ne i64 %str_l, 0
   ret i1 %ne_null
 }
 
 define i64 @test_simplify9(i1 %x) {
 ; CHECK-LABEL: @test_simplify9(
-; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[X:%.*]], i64 5, i64 6
-; CHECK-NEXT:    ret i64 [[TMP1]]
+; CHECK-NEXT:    [[L:%.*]] = select i1 [[X:%.*]], i64 5, i64 6
+; CHECK-NEXT:    ret i64 [[L]]
 ;
   %s = select i1 %x, ptr @hello, ptr @longer
   %l = call i64 @wcslen(ptr %s)
   ret i64 %l
 }
 
 ; Check the case that should be simplified to a sub instruction.
 ; wcslen(@hello + x) --> 5 - x
 
 define i64 @test_simplify10(i16 %x) {
 ; CHECK-LABEL: @test_simplify10(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sext i16 [[X:%.*]] to i64
-; CHECK-NEXT:    [[TMP2:%.*]] = sub nsw i64 5, [[TMP1]]
-; CHECK-NEXT:    ret i64 [[TMP2]]
+; CHECK-NEXT:    [[HELLO_L:%.*]] = sub nsw i64 5, [[TMP1]]
+; CHECK-NEXT:    ret i64 [[HELLO_L]]
 ;
   %hello_p = getelementptr inbounds [6 x i16], ptr @hello, i16 0, i16 %x
   %hello_l = call i64 @wcslen(ptr %hello_p)
   ret i64 %hello_l
 }
 
 ; wcslen(@null_hello_mid + (x & 7)) --> 9 - (x & 7)
 
 define i64 @test_simplify11(i16 %x) {
 ; CHECK-LABEL: @test_simplify11(
 ; CHECK-NEXT:    [[AND:%.*]] = and i16 [[X:%.*]], 7
 ; CHECK-NEXT:    [[NARROW:%.*]] = sub nuw nsw i16 9, [[AND]]
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[NARROW]] to i64
-; CHECK-NEXT:    ret i64 [[TMP1]]
+; CHECK-NEXT:    [[HELLO_L:%.*]] = zext i16 [[NARROW]] to i64
+; CHECK-NEXT:    ret i64 [[HELLO_L]]
 ;
   %and = and i16 %x, 7
   %hello_p = getelementptr inbounds [13 x i16], ptr @null_hello_mid, i16 0, i16 %and
   %hello_l = call i64 @wcslen(ptr %hello_p)
   ret i64 %hello_l
 }
 
 ; Check cases that shouldn't be simplified.
;
   ret i64 %hello_l
 }
 
 ; wcslen(@null_hello_mid + (x & 15)) should not be simplified to a sub instruction.
 
 define i64 @test_no_simplify3(i16 %x) {
 ; CHECK-LABEL: @test_no_simplify3(
 ; CHECK-NEXT:    [[AND:%.*]] = and i16 [[X:%.*]], 15
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[AND]] to i64
+; CHECK-NEXT:    [[TMP1:%.*]] = zext was_sext i16 [[AND]] to i64
 ; CHECK-NEXT:    [[HELLO_P:%.*]] = getelementptr inbounds [13 x i16], ptr @null_hello_mid, i64 0, i64 [[TMP1]]
 ; CHECK-NEXT:    [[HELLO_L:%.*]] = call i64 @wcslen(ptr nonnull [[HELLO_P]])
 ; CHECK-NEXT:    ret i64 [[HELLO_L]]
 ;
   %and = and i16 %x, 15
   %hello_p = getelementptr inbounds [13 x i16], ptr @null_hello_mid, i16 0, i16 %and
   %hello_l = call i64 @wcslen(ptr %hello_p)
   ret i64 %hello_l

llvm/test/Transforms/LoopVectorize/induction.ll

 ; IND-NEXT:    br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]]
 ; IND:       scalar.ph:
 ; IND-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
 ; IND-NEXT:    [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP15]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ]
 ; IND-NEXT:    br label [[FOR_BODY:%.*]]
 ; IND:       for.body:
 ; IND-NEXT:    [[I:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[I_NEXT:%.*]], [[IF_END:%.*]] ]
 ; IND-NEXT:    [[SUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[VAR4:%.*]], [[IF_END]] ]
-; IND-NEXT:    [[TMP16:%.*]] = zext i32 [[I]] to i64
+; IND-NEXT:    [[TMP16:%.*]] = zext was_sext i32 [[I]] to i64
 ; IND-NEXT:    [[VAR0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP16]]
 ; IND-NEXT:    [[VAR1:%.*]] = load i32, ptr [[VAR0]], align 4
 ; IND-NEXT:    br i1 [[C]], label [[IF_THEN:%.*]], label [[IF_END]]
 ; IND:       if.then:
 ; IND-NEXT:    [[VAR2:%.*]] = udiv i32 [[VAR1]], [[I]]
 ; IND-NEXT:    br label [[IF_END]]
 ; IND:       if.end:
 ; IND-NEXT:    [[VAR3:%.*]] = phi i32 [ [[VAR2]], [[IF_THEN]] ], [ [[VAR1]], [[FOR_BODY]] ]

 ; UNROLL-NEXT:    br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]]
 ; UNROLL:       scalar.ph:
 ; UNROLL-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
 ; UNROLL-NEXT:    [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP29]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ]
 ; UNROLL-NEXT:    br label [[FOR_BODY:%.*]]
 ; UNROLL:       for.body:
 ; UNROLL-NEXT:    [[I:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[I_NEXT:%.*]], [[IF_END:%.*]] ]
 ; UNROLL-NEXT:    [[SUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[VAR4:%.*]], [[IF_END]] ]
-; UNROLL-NEXT:    [[TMP30:%.*]] = zext i32 [[I]] to i64
+; UNROLL-NEXT:    [[TMP30:%.*]] = zext was_sext i32 [[I]] to i64
 ; UNROLL-NEXT:    [[VAR0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP30]]
 ; UNROLL-NEXT:    [[VAR1:%.*]] = load i32, ptr [[VAR0]], align 4
 ; UNROLL-NEXT:    br i1 [[C]], label [[IF_THEN:%.*]], label [[IF_END]]
 ; UNROLL:       if.then:
 ; UNROLL-NEXT:    [[VAR2:%.*]] = udiv i32 [[VAR1]], [[I]]
 ; UNROLL-NEXT:    br label [[IF_END]]
 ; UNROLL:       if.end:
 ; UNROLL-NEXT:    [[VAR3:%.*]] = phi i32 [ [[VAR2]], [[IF_THEN]] ], [ [[VAR1]], [[FOR_BODY]] ]

 ; INTERLEAVE-NEXT:    br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]]
 ; INTERLEAVE:       scalar.ph:
 ; INTERLEAVE-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
 ; INTERLEAVE-NEXT:    [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP49]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ]
 ; INTERLEAVE-NEXT:    br label [[FOR_BODY:%.*]]
 ; INTERLEAVE:       for.body:
 ; INTERLEAVE-NEXT:    [[I:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[I_NEXT:%.*]], [[IF_END:%.*]] ]
 ; INTERLEAVE-NEXT:    [[SUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[VAR4:%.*]], [[IF_END]] ]
-; INTERLEAVE-NEXT:    [[TMP50:%.*]] = zext i32 [[I]] to i64
+; INTERLEAVE-NEXT:    [[TMP50:%.*]] = zext was_sext i32 [[I]] to i64
 ; INTERLEAVE-NEXT:    [[VAR0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP50]]
 ; INTERLEAVE-NEXT:    [[VAR1:%.*]] = load i32, ptr [[VAR0]], align 4
 ; INTERLEAVE-NEXT:    br i1 [[C]], label [[IF_THEN:%.*]], label [[IF_END]]
 ; INTERLEAVE:       if.then:
 ; INTERLEAVE-NEXT:    [[VAR2:%.*]] = udiv i32 [[VAR1]], [[I]]
 ; INTERLEAVE-NEXT:    br label [[IF_END]]
 ; INTERLEAVE:       if.end:
 ; INTERLEAVE-NEXT:    [[VAR3:%.*]] = phi i32 [ [[VAR2]], [[IF_THEN]] ], [ [[VAR1]], [[FOR_BODY]] ]

llvm/test/Transforms/PhaseOrdering/lto-licm.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -passes='lto<O3>'               -S < %s  | FileCheck %s
 
 define void @hoist_fdiv(ptr %a, float %b) {
 ; CHECK-LABEL: @hoist_fdiv(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[FOR_COND:%.*]]
 ; CHECK:       for.cond:
 ; CHECK-NEXT:    [[I_0:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_INC:%.*]] ]
 ; CHECK-NEXT:    [[CMP_NOT:%.*]] = icmp eq i32 [[I_0]], 1024
 ; CHECK-NEXT:    br i1 [[CMP_NOT]], label [[FOR_END:%.*]], label [[FOR_INC]]
 ; CHECK:       for.inc:
-; CHECK-NEXT:    [[IDXPROM:%.*]] = zext i32 [[I_0]] to i64
+; CHECK-NEXT:    [[IDXPROM:%.*]] = zext was_sext i32 [[I_0]] to i64
 ; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A:%.*]], i64 [[IDXPROM]]
 ; CHECK-NEXT:    [[TMP0:%.*]] = load float, ptr [[ARRAYIDX]], align 4
 ; CHECK-NEXT:    [[TMP1:%.*]] = fdiv fast float [[TMP0]], [[B:%.*]]
 ; CHECK-NEXT:    store float [[TMP1]], ptr [[ARRAYIDX]], align 4
 ; CHECK-NEXT:    [[INC]] = add nuw nsw i32 [[I_0]], 1
 ; CHECK-NEXT:    br label [[FOR_COND]]
 ; CHECK:       for.end:
 ; CHECK-NEXT:    ret void

llvm/test/Transforms/SCCP/ip-ranges-casts.ll

;
   %call.2 = tail call i1 @f.zext(i32 300, i32 900)
   %res = and i1 %call.1, %call.2
   ret i1 %res
 }
 
 ; x = [100, 301)
 define internal i1 @f.sext(i32 %x, i32 %y) {
 ; CHECK-LABEL: @f.sext(
-; CHECK-NEXT:    [[T_1:%.*]] = zext i32 [[X:%.*]] to i64
+; CHECK-NEXT:    [[T_1:%.*]] = zext was_sext i32 [[X:%.*]] to i64
 ; CHECK-NEXT:    [[C_2:%.*]] = icmp sgt i64 [[T_1]], 299
 ; CHECK-NEXT:    [[C_4:%.*]] = icmp slt i64 [[T_1]], 101
 ; CHECK-NEXT:    [[RES_1:%.*]] = add i1 false, [[C_2]]
 ; CHECK-NEXT:    [[RES_2:%.*]] = add i1 [[RES_1]], false
 ; CHECK-NEXT:    [[RES_3:%.*]] = add i1 [[RES_2]], [[C_4]]
 ; CHECK-NEXT:    [[T_2:%.*]] = sext i32 [[Y:%.*]] to i64
 ; CHECK-NEXT:    [[C_6:%.*]] = icmp sgt i64 [[T_2]], 899
 ; CHECK-NEXT:    [[C_8:%.*]] = icmp slt i64 [[T_2]], -119
entry:
   %rem = srem <8 x i16> <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>, %vecinit7
   %0 = bitcast <8 x i16> %rem to i128
   %1 = trunc i128 %0 to i16
   ret i16 %1
 }
 
 define internal i64 @f.sext_to_zext(i32 %t) {
 ; CHECK-LABEL: @f.sext_to_zext(
-; CHECK-NEXT:    [[A:%.*]] = zext i32 [[T:%.*]] to i64
+; CHECK-NEXT:    [[A:%.*]] = zext was_sext i32 [[T:%.*]] to i64
 ; CHECK-NEXT:    ret i64 [[A]]
 ;
   %a = sext i32 %t to i64
   ret i64 %a
 }
 
 define i64 @caller.sext_to_zext(i32 %i) {
 ; CHECK-LABEL: @caller.sext_to_zext(

llvm/test/Transforms/SCCP/ip-ranges-sext.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -passes=ipsccp -S %s -o -| FileCheck %s
 
 define i64 @test1(i32 %x) {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:    [[C:%.*]] = icmp sgt i32 [[X:%.*]], 0
 ; CHECK-NEXT:    br i1 [[C]], label [[TRUE:%.*]], label [[FALSE:%.*]]
 ; CHECK:       true:
-; CHECK-NEXT:    [[EXT_1:%.*]] = zext i32 [[X]] to i64
+; CHECK-NEXT:    [[EXT_1:%.*]] = zext was_sext i32 [[X]] to i64
 ; CHECK-NEXT:    ret i64 [[EXT_1]]
 ; CHECK:       false:
 ; CHECK-NEXT:    [[EXT_2:%.*]] = sext i32 [[X]] to i64
 ; CHECK-NEXT:    ret i64 [[EXT_2]]
 ;
   %c = icmp sgt i32 %x, 0
   br i1 %c, label %true, label %false
 
 true:
   %ext.1 = sext i32 %x to i64
   ret i64 %ext.1
 
 false:
   %ext.2 = sext i32 %x to i64
   ret i64 %ext.2
 }
 
 define i64 @test2(i32 %x) {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:    [[C:%.*]] = icmp sge i32 [[X:%.*]], 0
 ; CHECK-NEXT:    br i1 [[C]], label [[TRUE:%.*]], label [[FALSE:%.*]]
 ; CHECK:       true:
-; CHECK-NEXT:    [[EXT_1:%.*]] = zext i32 [[X]] to i64
+; CHECK-NEXT:    [[EXT_1:%.*]] = zext was_sext i32 [[X]] to i64
 ; CHECK-NEXT:    ret i64 [[EXT_1]]
 ; CHECK:       false:
 ; CHECK-NEXT:    [[EXT_2:%.*]] = sext i32 [[X]] to i64
 ; CHECK-NEXT:    ret i64 [[EXT_2]]
 ;
   %c = icmp sge i32 %x, 0
   br i1 %c, label %true, label %false
 
exit:
   %p = phi i32 [ 0, %true.1 ], [ 1, %true.2], [ undef, %false ]
   %ext = sext i32 %p to i64
   ret i64 %ext
 }
 
 define i64 @test5(i32 %x) {
 ; CHECK-LABEL: @test5(
 ; CHECK-NEXT:    [[P:%.*]] = and i32 [[X:%.*]], 15
-; CHECK-NEXT:    [[EXT:%.*]] = zext i32 [[P]] to i64
+; CHECK-NEXT:    [[EXT:%.*]] = zext was_sext i32 [[P]] to i64
 ; CHECK-NEXT:    ret i64 [[EXT]]
 ;
   %p = and i32 %x, 15
   %ext = sext i32 %p to i64
   ret i64 %ext
 }
 
 ; sext is constant folded before sext -> zext conversion.
 define i64 @test6(i32 %x) {
 ; CHECK-LABEL: @test6(
 ; CHECK-NEXT:    ret i64 10
 ;
   %ext = sext i32 10 to i64
   ret i64 %ext
 }
 
 ; sext that can be converted to zext feeds another sext.
 define i64 @test7(i16 %x) {
 ; CHECK-LABEL: @test7(
 ; CHECK-NEXT:    [[P:%.*]] = and i16 [[X:%.*]], 15
-; CHECK-NEXT:    [[EXT_1:%.*]] = zext i16 [[P]] to i32
+; CHECK-NEXT:    [[EXT_1:%.*]] = zext was_sext i16 [[P]] to i32
 ; CHECK-NEXT:    [[EXT_2:%.*]] = sext i32 [[EXT_1]] to i64
 ; CHECK-NEXT:    ret i64 [[EXT_2]]
 ;
   %p = and i16 %x, 15
   %ext.1 = sext i16 %p to i32
   %ext.2 = sext i32 %ext.1 to i64
   ret i64 %ext.2
 }

llvm/test/Transforms/SCCP/ranges-sext.ll

exit:
   %p.fr = freeze i32 %p
   %ext = sext i32 %p.fr to i64
   ret i64 %ext
 }
 
 define i64 @test2(i32 %x) {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:    [[P:%.*]] = and i32 [[X:%.*]], 15
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i32 [[P]] to i64
-; CHECK-NEXT:    ret i64 [[TMP1]]
+; CHECK-NEXT:    [[EXT:%.*]] = zext was_sext i32 [[P]] to i64
+; CHECK-NEXT:    ret i64 [[EXT]]
 ;
   %p = and i32 %x, 15
   %ext = sext i32 %p to i64
   ret i64 %ext
 }
 
 define i64 @test3(i1 %c.1, i1 %c.2) {
 ; CHECK-LABEL: @test3(
 ; CHECK-NEXT:    br i1 [[C_1:%.*]], label [[TRUE_1:%.*]], label [[FALSE:%.*]]
 ; CHECK:       true.1:
 ; CHECK-NEXT:    br i1 [[C_2:%.*]], label [[TRUE_2:%.*]], label [[EXIT:%.*]]
 ; CHECK:       true.2:
 ; CHECK-NEXT:    br label [[EXIT]]
 ; CHECK:       false:
 ; CHECK-NEXT:    br label [[EXIT]]
 ; CHECK:       exit:
 ; CHECK-NEXT:    [[P:%.*]] = phi i32 [ 0, [[TRUE_1]] ], [ 1, [[TRUE_2]] ], [ 3, [[FALSE]] ]
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i32 [[P]] to i64
-; CHECK-NEXT:    ret i64 [[TMP1]]
+; CHECK-NEXT:    [[EXT:%.*]] = zext was_sext i32 [[P]] to i64
+; CHECK-NEXT:    ret i64 [[EXT]]
 ;
   br i1 %c.1, label %true.1, label %false
 
 true.1:
   br i1 %c.2, label %true.2, label %exit
 
 true.2:
   br label %exit

llvm/test/Transforms/SCCP/widening.ll

 ; SCCP:       bb3:
 ; SCCP-NEXT:    unreachable
 ; SCCP:       bb4:
 ; SCCP-NEXT:    [[TMP5:%.*]] = add i64 [[TMP2]], 3
 ; SCCP-NEXT:    [[TMP6:%.*]] = and i64 [[TMP5]], 3
 ; SCCP-NEXT:    [[TMP7:%.*]] = sub i64 3, [[TMP6]]
 ; SCCP-NEXT:    [[TMP8:%.*]] = shl i64 [[TMP7]], 1
 ; SCCP-NEXT:    [[TMP9:%.*]] = trunc i64 [[TMP8]] to i32
-; SCCP-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
+; SCCP-NEXT:    [[TMP10:%.*]] = zext was_sext i32 [[TMP9]] to i64
 ; SCCP-NEXT:    br label [[BB11:%.*]]
 ; SCCP:       bb11:
 ; SCCP-NEXT:    [[TMP12:%.*]] = phi i64 [ [[TMP10]], [[BB4]] ], [ [[TMP17:%.*]], [[BB18:%.*]] ]
 ; SCCP-NEXT:    br label [[BB13:%.*]]
 ; SCCP:       bb13:
 ; SCCP-NEXT:    [[C_1:%.*]] = icmp eq i64 [[TMP12]], 6
 ; SCCP-NEXT:    br i1 [[C_1]], label [[BB15:%.*]], label [[BB16:%.*]]
 ; SCCP:       bb15:

 ; IPSCCP:       bb3:
 ; IPSCCP-NEXT:    unreachable
 ; IPSCCP:       bb4:
 ; IPSCCP-NEXT:    [[TMP5:%.*]] = add i64 [[TMP2]], 3
 ; IPSCCP-NEXT:    [[TMP6:%.*]] = and i64 [[TMP5]], 3
 ; IPSCCP-NEXT:    [[TMP7:%.*]] = sub i64 3, [[TMP6]]
 ; IPSCCP-NEXT:    [[TMP8:%.*]] = shl i64 [[TMP7]], 1
 ; IPSCCP-NEXT:    [[TMP9:%.*]] = trunc i64 [[TMP8]] to i32
-; IPSCCP-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
+; IPSCCP-NEXT:    [[TMP10:%.*]] = zext was_sext i32 [[TMP9]] to i64
 ; IPSCCP-NEXT:    br label [[BB11:%.*]]
 ; IPSCCP:       bb11:
 ; IPSCCP-NEXT:    [[TMP12:%.*]] = phi i64 [ [[TMP10]], [[BB4]] ], [ [[TMP17:%.*]], [[BB18:%.*]] ]
 ; IPSCCP-NEXT:    br label [[BB13:%.*]]
 ; IPSCCP:       bb13:
 ; IPSCCP-NEXT:    [[C_1:%.*]] = icmp eq i64 [[TMP12]], 6
 ; IPSCCP-NEXT:    br i1 [[C_1]], label [[BB15:%.*]], label [[BB16:%.*]]
 ; IPSCCP:       bb15: