mkazantsev (Max Kazantsev)
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Jan 23 2017, 8:11 PM (34 w, 5 d)

Recent Activity

Fri, Sep 15

mkazantsev updated the diff for D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors.

Fixed one more case with PRE, updated tests accordingly.

Fri, Sep 15, 8:18 PM
mkazantsev added inline comments to D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors.
Fri, Sep 15, 8:17 PM
mkazantsev added inline comments to D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors.
Fri, Sep 15, 4:08 AM

Wed, Sep 13

mkazantsev added inline comments to D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors.
Wed, Sep 13, 8:04 PM
mkazantsev added inline comments to D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors.
Wed, Sep 13, 8:03 PM
mkazantsev updated the diff for D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors.

Nits.

Wed, Sep 13, 9:11 AM
mkazantsev updated the diff for D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors.

Factored the filling of implicit control flow map out of main iteration loop.

Wed, Sep 13, 1:08 AM

Tue, Sep 12

mkazantsev updated the diff for D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors.
Tue, Sep 12, 9:52 PM
mkazantsev updated the diff for D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors.

Added some tests, changed commit message.

Tue, Sep 12, 9:50 PM
mkazantsev added a reviewer for D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors: efriedma.
Tue, Sep 12, 8:42 PM

Mon, Sep 11

mkazantsev updated the diff for D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors.
Mon, Sep 11, 11:08 PM
mkazantsev updated the diff for D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors.

Reused isGuaranteedToTransferExecutionToSuccessor, added some clarifying comments. In this version of patch, we explicitly allow hoisting across volatile loads/stores. Given the discussion here, we might want to modify isGuaranteedToTransferExecutionToSuccessor so that it returns true for volatile loads/stores. Once the ongoing discussion on volatiles comes to some conclusion, this part can be reworked.

Mon, Sep 11, 11:04 PM
mkazantsev added inline comments to D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors.
Mon, Sep 11, 10:02 PM
mkazantsev added inline comments to D37569: Rework loop predication pass.
Mon, Sep 11, 5:21 AM
mkazantsev updated the diff for D37679: [IRCE][NFC] Introduce parameters for making lightweight IRCE.
Mon, Sep 11, 3:14 AM
mkazantsev created D37679: [IRCE][NFC] Introduce parameters for making lightweight IRCE.
Mon, Sep 11, 3:14 AM
mkazantsev added inline comments to D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors.
Mon, Sep 11, 12:12 AM

Fri, Sep 8

mkazantsev committed rL312783: Re-enable "[IRCE] Identify loops with latch comparison against current IV value".
Re-enable "[IRCE] Identify loops with latch comparison against current IV value"
Fri, Sep 8, 3:16 AM
mkazantsev closed D36215: [IRCE] Identify loops with latch comparison against current IV value by committing rL312783: Re-enable "[IRCE] Identify loops with latch comparison against current IV value".
Fri, Sep 8, 3:16 AM
mkazantsev updated the diff for D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors.

Cleaning between iterations now.

Fri, Sep 8, 1:57 AM
mkazantsev planned changes to D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors.

Need to clean guard set between iterations, not one time in the end.

Fri, Sep 8, 1:57 AM
mkazantsev added a comment to D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors.

The expected size of set of blocks with guards is actually small, so cleaning should be cheap. Could you please approve the patch for merge?

Fri, Sep 8, 1:46 AM
mkazantsev updated the diff for D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors.

Actually we don't even need OrderedInstructions to do that. It's enough to maintain a set of blocks where we have ever seen the guards. We iterate through blocks in reverse postorder which guarantees us that if a block has one predecessor it will be visited before the block. We also traverse block instructions in direct order. Using this, we just mark a block as having a guard when we meet one and know for sure that:

Fri, Sep 8, 1:21 AM

Thu, Sep 7

mkazantsev updated the diff for D36215: [IRCE] Identify loops with latch comparison against current IV value.

Fixed buggy tests & code, added a new test.

Thu, Sep 7, 11:04 PM
mkazantsev reopened D36215: [IRCE] Identify loops with latch comparison against current IV value.

This one was reverted due to found bug, I'm working on fix.

Thu, Sep 7, 9:39 PM
mkazantsev committed rL312775: diff --git a/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp….
diff --git a/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp…
Thu, Sep 7, 9:30 PM

Wed, Sep 6

mkazantsev planned changes to D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors.

Thanks for the detailed clarification! I will do that.

Wed, Sep 6, 10:45 PM
mkazantsev updated the diff for D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors.
  1. Removed assumes-related stuff.
  2. Added a motivating test and comment.
  3. Daniel, I didn't get what you mean under using ordered instructions to do this stuff. OrderedInstructions can only answer if a particular guard dominates our load. It will still take linear time to gather the guards, and for them we know for sure that they dominate the load and don't basically need to ask anything from OrderdeInstructions. I used any_of to speed the things up, but don't see any way to reduce complexity.
Wed, Sep 6, 2:25 AM

Tue, Sep 5

mkazantsev added a comment to D37463: Fix miscompile in LoopSink pass.

I need to read what C++ specification says about this particular issue, but basically LLVM is not only used to compile C++. This situation can be illegal in other languages (again, need to dig more through specifications). My proposal is to add an option that prohibits this transform and set it to false by default, with abitily to turn it off for languages where it is prohibited.

Tue, Sep 5, 10:52 PM
mkazantsev added a comment to D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors.

Hi Daniel,

Tue, Sep 5, 8:12 PM
mkazantsev updated the diff for D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors.

Fixed formatting.

Tue, Sep 5, 3:12 AM
mkazantsev created D37460: [GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors.
Tue, Sep 5, 3:08 AM

Fri, Sep 1

mkazantsev accepted D37265: [SCEV] Ensure ScalarEvolution::createAddRecFromPHIWithCastsImpl properly handles out of range truncations of the start and accum values.

LGTM with nits: use isa for boolean type checks, not dyn_cast.

Fri, Sep 1, 3:05 PM

Thu, Aug 31

mkazantsev added inline comments to D37265: [SCEV] Ensure ScalarEvolution::createAddRecFromPHIWithCastsImpl properly handles out of range truncations of the start and accum values.
Thu, Aug 31, 9:57 PM
mkazantsev added inline comments to D37265: [SCEV] Ensure ScalarEvolution::createAddRecFromPHIWithCastsImpl properly handles out of range truncations of the start and accum values.
Thu, Aug 31, 9:53 PM
mkazantsev added inline comments to D37265: [SCEV] Ensure ScalarEvolution::createAddRecFromPHIWithCastsImpl properly handles out of range truncations of the start and accum values.
Thu, Aug 31, 9:51 PM
mkazantsev requested changes to D37265: [SCEV] Ensure ScalarEvolution::createAddRecFromPHIWithCastsImpl properly handles out of range truncations of the start and accum values.

Code part looks ok for me (with comments addressed). I propose you to add a C++ unit test.

Thu, Aug 31, 9:42 PM
mkazantsev committed rL312221: [IRCE] Identify loops with latch comparison against current IV value.
[IRCE] Identify loops with latch comparison against current IV value
Thu, Aug 31, 12:05 AM
mkazantsev closed D36215: [IRCE] Identify loops with latch comparison against current IV value by committing rL312221: [IRCE] Identify loops with latch comparison against current IV value.
Thu, Aug 31, 12:05 AM

Wed, Aug 30

mkazantsev committed rL312215: [IRCE][NFC] Rename IndVarNext to IndVarBase.
[IRCE][NFC] Rename IndVarNext to IndVarBase
Wed, Aug 30, 10:59 PM
mkazantsev closed D36509: [IRCE][NFC] Rename IndVarNext to IndVarBase by committing rL312215: [IRCE][NFC] Rename IndVarNext to IndVarBase.
Wed, Aug 30, 10:59 PM
mkazantsev requested changes to D37265: [SCEV] Ensure ScalarEvolution::createAddRecFromPHIWithCastsImpl properly handles out of range truncations of the start and accum values.
Wed, Aug 30, 10:22 PM

Tue, Aug 29

mkazantsev committed rL311986: [LSR] Fix Shadow IV in case of integer overflow.
[LSR] Fix Shadow IV in case of integer overflow
Tue, Aug 29, 12:33 AM
mkazantsev closed D37209: [LSR] Fix Shadow IV in case of integer overflow by committing rL311986: [LSR] Fix Shadow IV in case of integer overflow.
Tue, Aug 29, 12:33 AM

Mon, Aug 28

mkazantsev updated the diff for D37209: [LSR] Fix Shadow IV in case of integer overflow.

Rebased, moved tests to existing test file, fixed the wrap check,

Mon, Aug 28, 11:33 PM
mkazantsev committed rL311982: [NFC] Fix indents in test.
[NFC] Fix indents in test
Mon, Aug 28, 10:34 PM
mkazantsev committed rL311980: [NFC] Refactor ShadowIV test to use FileCheck.
[NFC] Refactor ShadowIV test to use FileCheck
Mon, Aug 28, 10:24 PM
mkazantsev added inline comments to D37209: [LSR] Fix Shadow IV in case of integer overflow.
Mon, Aug 28, 10:24 PM
mkazantsev added inline comments to D37209: [LSR] Fix Shadow IV in case of integer overflow.
Mon, Aug 28, 9:44 PM
mkazantsev added inline comments to D37209: [LSR] Fix Shadow IV in case of integer overflow.
Mon, Aug 28, 8:39 PM
mkazantsev created D37209: [LSR] Fix Shadow IV in case of integer overflow.
Mon, Aug 28, 4:20 AM
mkazantsev updated the diff for D36215: [IRCE] Identify loops with latch comparison against current IV value.

Oh. My bad. Re-uploaded version with context.

Mon, Aug 28, 1:10 AM

Aug 23 2017

mkazantsev updated the diff for D36215: [IRCE] Identify loops with latch comparison against current IV value.

Added some clarifying comments & tests.

Aug 23 2017, 3:18 AM
mkazantsev added inline comments to D36215: [IRCE] Identify loops with latch comparison against current IV value.
Aug 23 2017, 2:55 AM

Aug 18 2017

mkazantsev committed rL311205: [IRCE] Fix buggy behavior in Clamp.
[IRCE] Fix buggy behavior in Clamp
Aug 18 2017, 3:52 PM
mkazantsev closed D36873: [IRCE] Fix buggy behavior in Clamp by committing rL311205: [IRCE] Fix buggy behavior in Clamp.
Aug 18 2017, 3:52 PM
mkazantsev added inline comments to D36873: [IRCE] Fix buggy behavior in Clamp.
Aug 18 2017, 6:25 AM
mkazantsev updated the diff for D36873: [IRCE] Fix buggy behavior in Clamp.

Renamed test's blocks.

Aug 18 2017, 6:25 AM
mkazantsev added inline comments to D36215: [IRCE] Identify loops with latch comparison against current IV value.
Aug 18 2017, 5:48 AM
mkazantsev created D36873: [IRCE] Fix buggy behavior in Clamp.
Aug 18 2017, 5:39 AM

Aug 14 2017

mkazantsev updated the diff for D36215: [IRCE] Identify loops with latch comparison against current IV value.

Fixed the problem with incorrect end value in changeIterationSpaceEnd, updated tests wrt this change.

Aug 14 2017, 11:54 PM

Aug 9 2017

mkazantsev planned changes to D36215: [IRCE] Identify loops with latch comparison against current IV value.

One more (rare) failure was found on internal testing. Need to investigate it. Also need to extend the test base.

Aug 9 2017, 11:03 PM
mkazantsev updated the diff for D36215: [IRCE] Identify loops with latch comparison against current IV value.
Aug 9 2017, 4:07 AM
mkazantsev added a dependent revision for D36509: [IRCE][NFC] Rename IndVarNext to IndVarBase: D36215: [IRCE] Identify loops with latch comparison against current IV value.
Aug 9 2017, 4:04 AM
mkazantsev updated the diff for D36215: [IRCE] Identify loops with latch comparison against current IV value.

Split into two parts (NFC rename and new logic) to make it easier to review.

Aug 9 2017, 4:04 AM
mkazantsev added a dependency for D36215: [IRCE] Identify loops with latch comparison against current IV value: D36509: [IRCE][NFC] Rename IndVarNext to IndVarBase.
Aug 9 2017, 4:04 AM
mkazantsev created D36509: [IRCE][NFC] Rename IndVarNext to IndVarBase.
Aug 9 2017, 4:01 AM

Aug 8 2017

mkazantsev added a comment to D36215: [IRCE] Identify loops with latch comparison against current IV value.

Ping

Aug 8 2017, 8:59 PM

Aug 7 2017

mkazantsev added inline comments to D36073: [CGP] Extends the scope of optimizeMemoryInst optimization.
Aug 7 2017, 12:18 AM
mkazantsev added inline comments to D36073: [CGP] Extends the scope of optimizeMemoryInst optimization.
Aug 7 2017, 12:18 AM

Aug 6 2017

mkazantsev updated the diff for D36215: [IRCE] Identify loops with latch comparison against current IV value.

Fixed the bug that was found on internal testing, extended tests.

Aug 6 2017, 11:26 PM

Aug 4 2017

mkazantsev committed rL310034: Do not declare a variable which is used only in assert. NFC.
Do not declare a variable which is used only in assert. NFC
Aug 4 2017, 12:42 AM
mkazantsev committed rL310032: [IRCE] Handle loops with step different from 1/-1.
[IRCE] Handle loops with step different from 1/-1
Aug 4 2017, 12:02 AM
mkazantsev closed D35539: [IRCE] Handle loops with step different from 1/-1 by committing rL310032: [IRCE] Handle loops with step different from 1/-1.
Aug 4 2017, 12:02 AM

Aug 3 2017

mkazantsev committed rL310029: Avoid comparison between signed and unsigned in SCEVExitLimitForget tests.
Avoid comparison between signed and unsigned in SCEVExitLimitForget tests
Aug 3 2017, 11:04 PM
mkazantsev committed rL310027: [IRCE] Recognize loops with unsigned latch conditions.
[IRCE] Recognize loops with unsigned latch conditions
Aug 3 2017, 10:41 PM
mkazantsev closed D35302: [IRCE] Recognize loops with unsigned latch conditions by committing rL310027: [IRCE] Recognize loops with unsigned latch conditions.
Aug 3 2017, 10:41 PM
mkazantsev committed rL310023: Fix SCEVExitLimitForget tests to make Sanitizer happy.
Fix SCEVExitLimitForget tests to make Sanitizer happy
Aug 3 2017, 10:07 PM
mkazantsev added inline comments to D35302: [IRCE] Recognize loops with unsigned latch conditions.
Aug 3 2017, 4:23 AM
mkazantsev updated the diff for D35302: [IRCE] Recognize loops with unsigned latch conditions.

Addressed nits, reworked tests so that now they check the structure of transformed loop, not only the fact that the transformation has happened.

Aug 3 2017, 4:20 AM
mkazantsev committed rL309929: Removed unused variabled from unit test.
Removed unused variabled from unit test
Aug 3 2017, 2:26 AM
mkazantsev committed rL309925: [SCEV] Re-enable "Cache results of computeExitLimit".
[SCEV] Re-enable "Cache results of computeExitLimit"
Aug 3 2017, 1:42 AM
mkazantsev closed D36087: [SCEV] Re-enable "Cache results of computeExitLimit" by committing rL309925: [SCEV] Re-enable "Cache results of computeExitLimit".
Aug 3 2017, 1:42 AM

Aug 2 2017

mkazantsev updated the diff for D36087: [SCEV] Re-enable "Cache results of computeExitLimit".
Aug 2 2017, 11:18 PM
mkazantsev planned changes to D36215: [IRCE] Identify loops with latch comparison against current IV value.

Our internal testing has detected some bugs with this patch, so I will fix them and re-submit the fixed version.

Aug 2 2017, 9:46 PM
mkazantsev added a comment to D35989: [SCEV][NFC] Introduces expression sizes estimation.

Seems that I've missed the comment here.

Aug 2 2017, 7:40 PM
mkazantsev added a dependent revision for D35539: [IRCE] Handle loops with step different from 1/-1: D36215: [IRCE] Identify loops with latch comparison against current IV value.
Aug 2 2017, 4:17 AM
mkazantsev added a dependency for D36215: [IRCE] Identify loops with latch comparison against current IV value: D35539: [IRCE] Handle loops with step different from 1/-1.
Aug 2 2017, 4:17 AM
mkazantsev created D36215: [IRCE] Identify loops with latch comparison against current IV value.
Aug 2 2017, 4:17 AM

Aug 1 2017

mkazantsev updated the diff for D35539: [IRCE] Handle loops with step different from 1/-1.

Rebased after underlying patch update, added comments.

Aug 1 2017, 4:53 AM
mkazantsev added inline comments to D35302: [IRCE] Recognize loops with unsigned latch conditions.
Aug 1 2017, 3:43 AM
mkazantsev updated the diff for D35302: [IRCE] Recognize loops with unsigned latch conditions.

Reworked tests, made some refactoring, addressed TODOs.

Aug 1 2017, 3:35 AM
mkazantsev committed rL309670: [NFC] Remove obsolete profiling data from eq_ne test.
[NFC] Remove obsolete profiling data from eq_ne test
Aug 1 2017, 3:14 AM

Jul 31 2017

mkazantsev added inline comments to D35539: [IRCE] Handle loops with step different from 1/-1.
Jul 31 2017, 11:50 PM
mkazantsev committed rL309663: [IRCE][NFC] Add another assert that AddRecExpr's step is not zero.
[IRCE][NFC] Add another assert that AddRecExpr's step is not zero
Jul 31 2017, 11:50 PM
mkazantsev committed rL309661: [IRCE][NFC] Add assert that AddRecExpr's step is not zero.
[IRCE][NFC] Add assert that AddRecExpr's step is not zero
Jul 31 2017, 11:28 PM
mkazantsev updated the diff for D36087: [SCEV] Re-enable "Cache results of computeExitLimit".

Now we don't throw away the exit limit for sake of a more optimistic future estimation every time we calculate getBackedgeTakenInfo. It doesn't look like estimation of Exit Limit for a particular exit block may be improved from what we have there.

Jul 31 2017, 7:47 AM
mkazantsev planned changes to D36087: [SCEV] Re-enable "Cache results of computeExitLimit".

Needs update to pass its own test within reasonable time.

Jul 31 2017, 7:18 AM
mkazantsev added a comment to D36087: [SCEV] Re-enable "Cache results of computeExitLimit".

I just realized that the attached IR test takes unreasonably long time with this fix, what makes the entire patch pointless.

Jul 31 2017, 6:42 AM
mkazantsev created D36087: [SCEV] Re-enable "Cache results of computeExitLimit".
Jul 31 2017, 6:17 AM