[LV] Ignore the option prefer-predicate-over-epilogue for target unspported mask

[Allen]

Summary

If don't specified a target default, the option -prefer-predicate-over-epilogue will be ignored.
then, we can add option -enable-masked-interleaved-mem-accesses to get same behavior as before the changes.

Fixes https://github.com/llvm/llvm-project/issues/63977.

[david-arm]

llvm/lib/Target/ARM/ARMTargetTransformInfo.h

311

Maybe I'm missing something, but this feels like quite a huge change that isn't described in the subject line or in the commit message? Currently for RISCV and ARM backends this always returns false.

Enabling this by default for two different targets could cause performance regressions, and I'm not sure this is what you actually want?

[dmgreen]

I'm not sure I understand what this is trying to do, but yes, I'm pretty sure enableMaskedInterleavedAccessVectorization should not be enabled for MVE.

[Allen]

llvm/lib/Target/ARM/ARMTargetTransformInfo.h

311

The motivation is described in issue 63977. When the -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue option is added, the common non-mask loop vector is still enabled, now https://gcc.godbolt.org/z/3z7e3rh1T

• option -march=armv8.2-a -O3 can vectorize
• option -march=armv8.2-a -O3 -mllvm -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue cannot vectorize

llvm/lib/Target/ARM/ARMTargetTransformInfo.h

public:
 
   bool maybeLoweredToCall(Instruction &I);
   bool isLoweredToCall(const Function *F);
   bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE,
                                 AssumptionCache &AC,
                                 TargetLibraryInfo *LibInfo,
                                 HardwareLoopInfo &HWLoopInfo);
   bool preferPredicateOverEpilogue(TailFoldingInfo *TFI);
+  bool enableMaskedInterleavedAccessVectorization() const {
+    return ST->hasMVEIntegerOps();
+  }
   void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
                                TTI::UnrollingPreferences &UP,
                                OptimizationRemarkEmitter *ORE);
 
   TailFoldingStyle
   getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) const;
 
   void getPeelingPreferences(Loop *L, ScalarEvolution &SE,

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

public:
   InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
                                       const APInt &Imm, Type *Ty,
                                       TTI::TargetCostKind CostKind);
 
   TargetTransformInfo::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
 
   bool shouldExpandReduction(const IntrinsicInst *II) const;
   bool supportsScalableVectors() const { return ST->hasVInstructions(); }
+  bool enableMaskedInterleavedAccessVectorization() const {
+    return ST->hasVInstructions();
+  }
   bool enableOrderedReductions() const { return true; }
   bool enableScalableVectorization() const { return ST->hasVInstructions(); }
   TailFoldingStyle
   getPreferredTailFoldingStyle(bool IVUpdateMayOverflow) const {
     return ST->hasVInstructions() ? TailFoldingStyle::Data
                                   : TailFoldingStyle::DataWithoutLaneMask;
   }
   std::optional<unsigned> getMaxVScale() const;

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

if (F->hasOptSize() || (llvm::shouldOptimizeForSize(L->getHeader(), PSI, BFI,
     return CM_ScalarEpilogueNotAllowedOptSize;
 
   // 2) If set, obey the directives
   if (PreferPredicateOverEpilogue.getNumOccurrences()) {
     switch (PreferPredicateOverEpilogue) {
     case PreferPredicateTy::ScalarEpilogue:
       return CM_ScalarEpilogueAllowed;
     case PreferPredicateTy::PredicateElseScalarEpilogue:
+      if (useMaskedInterleavedAccesses(*TTI))
         return CM_ScalarEpilogueNotNeededUsePredicate;
+      else
+        return CM_ScalarEpilogueAllowed;
     case PreferPredicateTy::PredicateOrDontVectorize:
       return CM_ScalarEpilogueNotAllowedUsePredicate;
     };
   }
 
   // 3) If set, obey the hints
   switch (Hints.getPredicate()) {
   case LoopVectorizeHints::FK_Enabled:

llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes=loop-vectorize,dce,instcombine -force-vector-interleave=1 -force-vector-width=4 -prefer-inloop-reductions -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -S | FileCheck %s
+; RUN: opt < %s -passes=loop-vectorize,dce,instcombine -force-vector-interleave=1 -force-vector-width=4 -prefer-inloop-reductions -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -enable-masked-interleaved-mem-accesses -S | FileCheck %s
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 
 define i32 @reduction_sum_single(ptr noalias nocapture %A) {
 ; CHECK-LABEL: @reduction_sum_single(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
 ; CHECK:       vector.ph:

llvm/test/Transforms/LoopVectorize/reduction-predselect.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes=loop-vectorize,dce,instcombine -force-vector-width=4 -force-vector-interleave=1 -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -prefer-predicated-reduction-select -S | FileCheck %s
+; RUN: opt < %s -passes=loop-vectorize,dce,instcombine -force-vector-width=4 -force-vector-interleave=1 -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -prefer-predicated-reduction-select -enable-masked-interleaved-mem-accesses -S | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
 
 define i32 @reduction_sum_single(ptr noalias nocapture %A) {
 ; CHECK-LABEL: @reduction_sum_single(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
 ; CHECK:       vector.ph: