[SelectionDAG][TargetLowering]Add support for nuw/nsw on KnownBits::shl

[liaolucy]

Summary

1. Use KnownBits::shl() in SimplifyDemandedBits()
2. Add flags for KnownBits::shl in computeKnownBits()

Similar to e1aa91b36325

[craig.topper]

Tests?

[liaolucy]

Add testcase for riscv.
The testcase is copied from instcombine.
Without this patch:
https://godbolt.org/z/M1nxxf163

[RKSimon]

llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll

197

please can you precommit this test with current trunk codegen and then rebase this patch to show the diff

[liaolucy]

llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll

197

Thanks for the review. In fact, I found not only good testcase, but also bad ones.
Regarding the bad testcase, no solution has been found for the time being.
I'll come back to this patch later when I find a solution. Thanks again.

[RKSimon]

Needs better test coverage

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

case ISD::STRICT_FSETCCS: {
     unsigned OpNo = Op->isStrictFPOpcode() ? 1 : 0;
     // If we know the result of a setcc has the top bits zero, use this info.
     if (TLI->getBooleanContents(Op.getOperand(OpNo).getValueType()) ==
             TargetLowering::ZeroOrOneBooleanContent &&
         BitWidth > 1)
       Known.Zero.setBitsFrom(1);
     break;
   }
-  case ISD::SHL:
+  case ISD::SHL: {
     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
-    Known = KnownBits::shl(Known, Known2);
+    SDNodeFlags Flags = Op.getNode()->getFlags();
+    Known = KnownBits::shl(Known, Known2, Flags.hasNoUnsignedWrap(),
+                           Flags.hasNoSignedWrap());
 
     // Minimum shift low bits are known zero.
     if (const APInt *ShMinAmt =
             getValidMinimumShiftAmountConstant(Op, DemandedElts))
       Known.Zero.setLowBits(ShMinAmt->getZExtValue());
     break;
+  }
   case ISD::SRL:
     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
     Known = KnownBits::lshr(Known, Known2);
 
     // Minimum shift high bits are known zero.
     if (const APInt *ShMinAmt =
             getValidMinimumShiftAmountConstant(Op, DemandedElts))

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

if (const APInt *SA =
         }
       }
 
       APInt InDemandedMask = DemandedBits.lshr(ShAmt);
       if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
                                Depth + 1))
         return true;
       assert(!Known.hasConflict() && "Bits known to be one AND zero?");
-      Known.Zero <<= ShAmt;
-      Known.One <<= ShAmt;
-      // low bits known zero.
-      Known.Zero.setLowBits(ShAmt);
+      SDNodeFlags Flags = Op.getNode()->getFlags();
+      Known =
+          KnownBits::shl(Known, KnownBits::makeConstant(APInt(BitWidth, ShAmt)),
+                         Flags.hasNoUnsignedWrap(), Flags.hasNoSignedWrap());
 
       // Attempt to avoid multi-use ops if we don't need anything from them.
       if (!InDemandedMask.isAllOnes() || !DemandedElts.isAllOnes()) {
         SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
             Op0, InDemandedMask, DemandedElts, TLO.DAG, Depth + 1);
         if (DemandedOp0) {
           SDValue NewOp = TLO.DAG.getNode(ISD::SHL, dl, VT, DemandedOp0, Op1);
           return TLO.CombineTo(Op, NewOp);

llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll

 ; CHECK-NEXT:    slli a0, a0, 48
 ; CHECK-NEXT:    srli a0, a0, 48
 ; CHECK-NEXT:    ret
 entry:
   %and = and i32 %x, 65280
   %or = or i32 %and, 255
   ret i32 %or
 }
+
+
+define i32 @test_shl_nuw__nsw_is_safe(i32 %x) {
+; CHECK-LABEL: test_shl_nuw__nsw_is_safe:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    ret
+  %1 = or i32 %x, -83886080
+  %2 = icmp eq i32 %1, -83886079
+  %3 = shl nuw i32 %1, 2
+  %4 = select i1 %2, i32 -335544316, i32 %3
+  %5 = mul i32 %4, %1
+  %6 = mul i32 %5, %3
+  ret i32 %6
+}