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Differential D153899

[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
ClosedPublic

Authored by reames on Jun 27 2023, 10:59 AM.

Details

Reviewers
craig.topper
asb
frasercrmck
luke
kito-cheng
Commits
rG92b5a3405de9: [RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
Summary

This change continues with the line of work discussed in https://discourse.llvm.org/t/riscv-transition-in-vector-pseudo-structure-policy-variants/71295. In D153155, we started removing the legacy distinction between unsuffixed (TA) and _TU pseudos. This patch continues that effort for the unary instruction families.

The change consists of a few interacting pieces:

  • Adding a vector policy operand to VPseudoUnaryNoMaskTU.
  • Then using VPseudoUnaryNoMaskTU for all cases where VPseudoUnaryNoMask was previously used and deleting the unsuffixed form.
  • Then renaming VPseudoUnaryNoMaskTU to VPseudoUnaryNoMask, and adjusting the RISCVMaskedPseudo table to use the combined pseudo.
  • Fixing up two places in C++ code which manually construct VMV_V_* instructions.

Normally, I'd try to factor this into a couple of changes, but in this case, the table structure is tried to naming and thus we can't really separate the otherwise NFC bits.

As before, we see codegen changes (some improvements and some regressions) due to scheduling differences caused by the extra implicit_def instructions.

Diff Detail

Event Timeline

reames created this revision.Jun 27 2023, 10:59 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 27 2023, 10:59 AM
Herald added subscribers: jobnoorman, VincentWu, vkmr and 26 others. · View Herald Transcript
reames requested review of this revision.Jun 27 2023, 10:59 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 27 2023, 10:59 AM
Herald added subscribers: wangpc, eopXD, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B241545: Diff 535055.Jun 27 2023, 12:38 PM
craig.topper added inline comments.Jun 27 2023, 12:57 PM
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
3422

While you're here, can you fix this typo. MMV->VMV

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
784

What happened here?

reames added inline comments.Jun 27 2023, 1:08 PM
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
3422

Fixed in 49428ba.

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
784

It looks my hand update to the MIR was wrong. The undef form is post register allocation, I should have used an implicit_def instruction here. Same problem in vsetvli-insert.mir.

Thanks for catching this.

reames updated this revision to Diff 535544.Jun 28 2023, 3:01 PM

Address review comment

craig.topper accepted this revision.Jun 28 2023, 3:23 PM

LGTM

This revision is now accepted and ready to land.Jun 28 2023, 3:23 PM
Harbormaster completed remote builds in B241905: Diff 535544.Jun 28 2023, 4:44 PM
This revision was landed with ongoing or failed builds.Jun 29 2023, 7:34 AM
Closed by commit rG92b5a3405de9: [RISCV] Remove legacy TA/TU pseudo distinction for unary instructions (authored by reames). · Explain Why
This revision was automatically updated to reflect the committed changes.
reames added a commit: rG92b5a3405de9: [RISCV] Remove legacy TA/TU pseudo distinction for unary instructions.

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Diff 535790

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Show First 20 Lines • Show All 3,413 Lines • ▼ Show 20 Lines for (unsigned Idx = 1; Idx < True->getNumValues(); ++Idx)
ReplaceUses(True.getValue(Idx), SDValue(Result, Idx)); ReplaceUses(True.getValue(Idx), SDValue(Result, Idx));
// Try to transform Result to unmasked intrinsic. // Try to transform Result to unmasked intrinsic.
doPeepholeMaskedRVV(Result); doPeepholeMaskedRVV(Result);
return true; return true;
} }
// Transform (VMERGE_VVM_<LMUL>_TU false, false, true, allones, vl, sew) to // Transform (VMERGE_VVM_<LMUL>_TU false, false, true, allones, vl, sew) to
// (VMV_V_V_<LMUL>_TU false, true, vl, sew). It may decrease uses of VMSET. // (VMV_V_V_<LMUL>_TU false, true, vl, sew). It may decrease uses of VMSET.
craig.topperUnsubmitted
Not Done
ReplyInline Actions

While you're here, can you fix this typo. MMV->VMV

craig.topper: While you're here, can you fix this typo. `MMV`->`VMV`
reamesAuthorUnsubmitted
Done
ReplyInline Actions

Fixed in 49428ba.

reames: Fixed in 49428ba.
bool RISCVDAGToDAGISel::performVMergeToVMv(SDNode *N) { bool RISCVDAGToDAGISel::performVMergeToVMv(SDNode *N) {
#define CASE_VMERGE_TO_VMV(lmul) \ #define CASE_VMERGE_TO_VMV(lmul) \
case RISCV::PseudoVMERGE_VVM_##lmul##_TU: \ case RISCV::PseudoVMERGE_VVM_##lmul##_TU: \
NewOpc = RISCV::PseudoVMV_V_V_##lmul##_TU; \ NewOpc = RISCV::PseudoVMV_V_V_##lmul; \
break; break;
unsigned NewOpc; unsigned NewOpc;
switch (N->getMachineOpcode()) { switch (N->getMachineOpcode()) {
default: default:
llvm_unreachable("Expected VMERGE_VVM_<LMUL>_TU instruction."); llvm_unreachable("Expected VMERGE_VVM_<LMUL>_TU instruction.");
CASE_VMERGE_TO_VMV(MF8) CASE_VMERGE_TO_VMV(MF8)
CASE_VMERGE_TO_VMV(MF4) CASE_VMERGE_TO_VMV(MF4)
CASE_VMERGE_TO_VMV(MF2) CASE_VMERGE_TO_VMV(MF2)
CASE_VMERGE_TO_VMV(M1) CASE_VMERGE_TO_VMV(M1)
CASE_VMERGE_TO_VMV(M2) CASE_VMERGE_TO_VMV(M2)
CASE_VMERGE_TO_VMV(M4) CASE_VMERGE_TO_VMV(M4)
CASE_VMERGE_TO_VMV(M8) CASE_VMERGE_TO_VMV(M8)
} }
if (!usesAllOnesMask(N, /* MaskOpIdx */ 3)) if (!usesAllOnesMask(N, /* MaskOpIdx */ 3))
return false; return false;
SDLoc DL(N);
SDValue PolicyOp =
CurDAG->getTargetConstant(/*TUMU*/ 0, DL, Subtarget->getXLenVT());
SDNode *Result = CurDAG->getMachineNode( SDNode *Result = CurDAG->getMachineNode(
NewOpc, SDLoc(N), N->getValueType(0), NewOpc, DL, N->getValueType(0),
{N->getOperand(1), N->getOperand(2), N->getOperand(4), N->getOperand(5)}); {N->getOperand(1), N->getOperand(2), N->getOperand(4), N->getOperand(5),
PolicyOp});
ReplaceUses(N, Result); ReplaceUses(N, Result);
return true; return true;
} }
bool RISCVDAGToDAGISel::doPeepholeMergeVVMFold() { bool RISCVDAGToDAGISel::doPeepholeMergeVVMFold() {
bool MadeChange = false; bool MadeChange = false;
SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end(); SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
▲ Show 20 Lines • Show All 44 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Show First 20 Lines • Show All 447 Lines • ▼ Show 20 Lines if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
if (DefMBBI->getOpcode() == VIOpc) { if (DefMBBI->getOpcode() == VIOpc) {
UseVMV_V_I = true; UseVMV_V_I = true;
Opc = VIOpc; Opc = VIOpc;
} }
} }
if (NF == 1) { if (NF == 1) {
auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg); auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg);
if (UseVMV_V_V)
MIB.addReg(DstReg, RegState::Undef);
if (UseVMV_V_I) if (UseVMV_V_I)
MIB = MIB.add(DefMBBI->getOperand(1)); MIB = MIB.add(DefMBBI->getOperand(2));
else else
MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc)); MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc));
if (UseVMV_V_V) { if (UseVMV_V_V) {
const MCInstrDesc &Desc = DefMBBI->getDesc(); const MCInstrDesc &Desc = DefMBBI->getDesc();
MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL
MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
MIB.addImm(0); // tu, mu
MIB.addReg(RISCV::VL, RegState::Implicit); MIB.addReg(RISCV::VL, RegState::Implicit);
MIB.addReg(RISCV::VTYPE, RegState::Implicit); MIB.addReg(RISCV::VTYPE, RegState::Implicit);
} }
} else { } else {
int I = 0, End = NF, Incr = 1; int I = 0, End = NF, Incr = 1;
unsigned SrcEncoding = TRI->getEncodingValue(SrcReg); unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
unsigned DstEncoding = TRI->getEncodingValue(DstReg); unsigned DstEncoding = TRI->getEncodingValue(DstReg);
unsigned LMulVal; unsigned LMulVal;
bool Fractional; bool Fractional;
std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul); std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul);
assert(!Fractional && "It is impossible be fractional lmul here."); assert(!Fractional && "It is impossible be fractional lmul here.");
if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) { if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) {
I = NF - 1; I = NF - 1;
End = -1; End = -1;
Incr = -1; Incr = -1;
} }
for (; I != End; I += Incr) { for (; I != End; I += Incr) {
auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), auto MIB = BuildMI(MBB, MBBI, DL, get(Opc),
TRI->getSubReg(DstReg, SubRegIdx + I)); TRI->getSubReg(DstReg, SubRegIdx + I));
if (UseVMV_V_V)
MIB.addReg(TRI->getSubReg(DstReg, SubRegIdx + I),
RegState::Undef);
if (UseVMV_V_I) if (UseVMV_V_I)
MIB = MIB.add(DefMBBI->getOperand(1)); MIB = MIB.add(DefMBBI->getOperand(2));
else else
MIB = MIB.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I), MIB = MIB.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I),
getKillRegState(KillSrc)); getKillRegState(KillSrc));
if (UseVMV_V_V) { if (UseVMV_V_V) {
const MCInstrDesc &Desc = DefMBBI->getDesc(); const MCInstrDesc &Desc = DefMBBI->getDesc();
MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL
MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
MIB.addImm(0); // tu, mu
MIB.addReg(RISCV::VL, RegState::Implicit); MIB.addReg(RISCV::VL, RegState::Implicit);
MIB.addReg(RISCV::VTYPE, RegState::Implicit); MIB.addReg(RISCV::VTYPE, RegState::Implicit);
} }
} }
} }
} else { } else {
BuildMI(MBB, MBBI, DL, get(Opc), DstReg) BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
.addReg(SrcReg, getKillRegState(KillSrc)) .addReg(SrcReg, getKillRegState(KillSrc))
▲ Show 20 Lines • Show All 2,286 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,024 Lines • ▼ Show 20 Linesclass VPseudoNullaryPseudoM<string BaseInst>
let HasSEWOp = 1; let HasSEWOp = 1;
// BaseInstr is not used in RISCVExpandPseudoInsts pass. // BaseInstr is not used in RISCVExpandPseudoInsts pass.
// Just fill a corresponding real v-inst to pass tablegen check. // Just fill a corresponding real v-inst to pass tablegen check.
let BaseInstr = !cast<Instruction>(BaseInst); let BaseInstr = !cast<Instruction>(BaseInst);
} }
class VPseudoUnaryNoMask<DAGOperand RetClass, DAGOperand OpClass, class VPseudoUnaryNoMask<DAGOperand RetClass, DAGOperand OpClass,
string Constraint = ""> : string Constraint = ""> :
Pseudo<(outs RetClass:$rd), Pseudo<(outs RetClass:$rd),
(ins OpClass:$rs2, AVL:$vl, ixlenimm:$sew), []>, (ins RetClass:$merge, OpClass:$rs2, AVL:$vl, ixlenimm:$sew,
RISCVVPseudo { ixlenimm:$policy), []>,
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = Constraint;
let HasVLOp = 1;
let HasSEWOp = 1;
}
class VPseudoUnaryNoMaskTU<DAGOperand RetClass, DAGOperand OpClass,
string Constraint = ""> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$merge, OpClass:$rs2, AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo { RISCVVPseudo {
let mayLoad = 0; let mayLoad = 0;
let mayStore = 0; let mayStore = 0;
let hasSideEffects = 0; let hasSideEffects = 0;
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret; let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1; let HasVLOp = 1;
let HasSEWOp = 1; let HasSEWOp = 1;
let HasVecPolicyOp = 1;
} }
class VPseudoUnaryMask<VReg RetClass, VReg OpClass, string Constraint = ""> : class VPseudoUnaryMask<VReg RetClass, VReg OpClass, string Constraint = ""> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2, (ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
RISCVVPseudo { RISCVVPseudo {
let mayLoad = 0; let mayLoad = 0;
▲ Show 20 Lines • Show All 890 Lines • ▼ Show 20 Linesmulticlass VPseudoVIOT_M {
defvar constraint = "@earlyclobber $rd"; defvar constraint = "@earlyclobber $rd";
foreach m = MxList in { foreach m = MxList in {
defvar mx = m.MX; defvar mx = m.MX;
defvar WriteVMIotV_MX = !cast<SchedWrite>("WriteVMIotV_" # mx); defvar WriteVMIotV_MX = !cast<SchedWrite>("WriteVMIotV_" # mx);
defvar ReadVMIotV_MX = !cast<SchedRead>("ReadVMIotV_" # mx); defvar ReadVMIotV_MX = !cast<SchedRead>("ReadVMIotV_" # mx);
let VLMul = m.value in { let VLMul = m.value in {
def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, VR, constraint>, def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, VR, constraint>,
Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>; Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>;
def "_" # m.MX # "_TU" : VPseudoUnaryNoMaskTU<m.vrclass, VR, constraint>,
Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>;
def "_" # m.MX # "_MASK" : VPseudoUnaryMask<m.vrclass, VR, constraint>, def "_" # m.MX # "_MASK" : VPseudoUnaryMask<m.vrclass, VR, constraint>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>, RISCVMaskedPseudo</*MaskOpIdx*/ 2,
/*HasTU*/ false,
/*IsCombined*/true>,
Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>; Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>;
} }
} }
} }
multiclass VPseudoVCPR_V { multiclass VPseudoVCPR_V {
foreach m = MxList in { foreach m = MxList in {
defvar mx = m.MX; defvar mx = m.MX;
▲ Show 20 Lines • Show All 350 Lines • ▼ Show 20 Lines let VLMul = m.value in {
let VLMul = m.value in { let VLMul = m.value in {
def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.vrclass>, def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
Sched<[WriteVIMovV_MX, ReadVIMovV_MX]>; Sched<[WriteVIMovV_MX, ReadVIMovV_MX]>;
def "_X_" # mx : VPseudoUnaryNoMask<m.vrclass, GPR>, def "_X_" # mx : VPseudoUnaryNoMask<m.vrclass, GPR>,
Sched<[WriteVIMovX_MX, ReadVIMovX_MX]>; Sched<[WriteVIMovX_MX, ReadVIMovX_MX]>;
def "_I_" # mx : VPseudoUnaryNoMask<m.vrclass, simm5>, def "_I_" # mx : VPseudoUnaryNoMask<m.vrclass, simm5>,
Sched<[WriteVIMovI_MX]>; Sched<[WriteVIMovI_MX]>;
def "_V_" # mx # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.vrclass>,
Sched<[WriteVIMovV_MX, ReadVIMovV_MX]>;
def "_X_" # mx # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, GPR>,
Sched<[WriteVIMovX_MX, ReadVIMovX_MX]>;
def "_I_" # mx # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, simm5>,
Sched<[WriteVIMovI_MX]>;
} }
} }
} }
} }
multiclass VPseudoVMV_F { multiclass VPseudoVMV_F {
foreach f = FPList in { foreach f = FPList in {
foreach m = f.MxList in { foreach m = f.MxList in {
defvar mx = m.MX; defvar mx = m.MX;
defvar WriteVFMovV_MX = !cast<SchedWrite>("WriteVFMovV_" # mx); defvar WriteVFMovV_MX = !cast<SchedWrite>("WriteVFMovV_" # mx);
defvar ReadVFMovF_MX = !cast<SchedRead>("ReadVFMovF_" # mx); defvar ReadVFMovF_MX = !cast<SchedRead>("ReadVFMovF_" # mx);
let VLMul = m.value in { let VLMul = m.value in {
def "_" # f.FX # "_" # mx : def "_" # f.FX # "_" # mx :
VPseudoUnaryNoMask<m.vrclass, f.fprclass>, VPseudoUnaryNoMask<m.vrclass, f.fprclass>,
Sched<[WriteVFMovV_MX, ReadVFMovF_MX]>; Sched<[WriteVFMovV_MX, ReadVFMovF_MX]>;
def "_" # f.FX # "_" # mx # "_TU":
VPseudoUnaryNoMaskTU<m.vrclass, f.fprclass>,
Sched<[WriteVFMovV_MX, ReadVFMovF_MX]>;
} }
} }
} }
} }
multiclass VPseudoVCLS_V { multiclass VPseudoVCLS_V {
foreach m = MxListF in { foreach m = MxListF in {
defvar mx = m.MX; defvar mx = m.MX;
defvar WriteVFClassV_MX = !cast<SchedWrite>("WriteVFClassV_" # mx); defvar WriteVFClassV_MX = !cast<SchedWrite>("WriteVFClassV_" # mx);
defvar ReadVFClassV_MX = !cast<SchedRead>("ReadVFClassV_" # mx); defvar ReadVFClassV_MX = !cast<SchedRead>("ReadVFClassV_" # mx);
let VLMul = m.value in { let VLMul = m.value in {
def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.vrclass>, def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
Sched<[WriteVFClassV_MX, ReadVFClassV_MX, ReadVMask]>; Sched<[WriteVFClassV_MX, ReadVFClassV_MX, ReadVMask]>;
def "_V_" # mx # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.vrclass>,
Sched<[WriteVFClassV_MX, ReadVFClassV_MX, ReadVMask]>;
def "_V_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>, def "_V_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>, RISCVMaskedPseudo</*MaskOpIdx*/ 2,
/*HasTU*/ false,
/*IsCombined*/true>,
Sched<[WriteVFClassV_MX, ReadVFClassV_MX, ReadVMask]>; Sched<[WriteVFClassV_MX, ReadVFClassV_MX, ReadVMask]>;
} }
} }
} }
multiclass VPseudoVSQR_V { multiclass VPseudoVSQR_V {
foreach m = MxListF in { foreach m = MxListF in {
defvar mx = m.MX; defvar mx = m.MX;
defvar sews = SchedSEWSet<m.MX, /*isF*/ 1>.val; defvar sews = SchedSEWSet<m.MX, /*isF*/ 1>.val;
let VLMul = m.value in let VLMul = m.value in
foreach e = sews in { foreach e = sews in {
defvar suffix = "_" # mx # "_E" # e; defvar suffix = "_" # mx # "_E" # e;
defvar WriteVFSqrtV_MX_E = !cast<SchedWrite>("WriteVFSqrtV" # suffix); defvar WriteVFSqrtV_MX_E = !cast<SchedWrite>("WriteVFSqrtV" # suffix);
defvar ReadVFSqrtV_MX_E = !cast<SchedRead>("ReadVFSqrtV" # suffix); defvar ReadVFSqrtV_MX_E = !cast<SchedRead>("ReadVFSqrtV" # suffix);
def "_V" # suffix : VPseudoUnaryNoMask<m.vrclass, m.vrclass>, def "_V" # suffix : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E, Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
ReadVMask]>; ReadVMask]>;
def "_V" # suffix # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.vrclass>,
Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
ReadVMask]>;
def "_V" # suffix # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>, def "_V" # suffix # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>, RISCVMaskedPseudo</*MaskOpIdx*/ 2,
/*HasTU*/ false,
/*IsCombined*/true>,
Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E, Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
ReadVMask]>; ReadVMask]>;
} }
} }
} }
multiclass VPseudoVRCP_V { multiclass VPseudoVRCP_V {
foreach m = MxListF in { foreach m = MxListF in {
defvar mx = m.MX; defvar mx = m.MX;
defvar WriteVFRecpV_MX = !cast<SchedWrite>("WriteVFRecpV_" # mx); defvar WriteVFRecpV_MX = !cast<SchedWrite>("WriteVFRecpV_" # mx);
defvar ReadVFRecpV_MX = !cast<SchedRead>("ReadVFRecpV_" # mx); defvar ReadVFRecpV_MX = !cast<SchedRead>("ReadVFRecpV_" # mx);
let VLMul = m.value in { let VLMul = m.value in {
def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.vrclass>, def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>; Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>;
def "_V_" # mx # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.vrclass>,
Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>;
def "_V_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>, def "_V_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>, RISCVMaskedPseudo</*MaskOpIdx*/ 2,
/*HasTU*/ false,
/*IsCombined*/true>,
Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>; Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>;
} }
} }
} }
multiclass PseudoVEXT_VF2 { multiclass PseudoVEXT_VF2 {
defvar constraints = "@earlyclobber $rd"; defvar constraints = "@earlyclobber $rd";
foreach m = MxListVF2 in foreach m = MxListVF2 in
{ {
defvar mx = m.MX; defvar mx = m.MX;
defvar WriteVExtV_MX = !cast<SchedWrite>("WriteVExtV_" # mx); defvar WriteVExtV_MX = !cast<SchedWrite>("WriteVExtV_" # mx);
defvar ReadVExtV_MX = !cast<SchedRead>("ReadVExtV_" # mx); defvar ReadVExtV_MX = !cast<SchedRead>("ReadVExtV_" # mx);
let VLMul = m.value in { let VLMul = m.value in {
def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f2vrclass, constraints>, def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f2vrclass, constraints>,
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>; Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
def "_" # mx # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.f2vrclass, constraints>,
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
def "_" # mx # "_MASK" : def "_" # mx # "_MASK" :
VPseudoUnaryMask<m.vrclass, m.f2vrclass, constraints>, VPseudoUnaryMask<m.vrclass, m.f2vrclass, constraints>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>, RISCVMaskedPseudo</*MaskOpIdx*/ 2, /*HasTU*/ false, /*IsCombined*/true>,
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>; Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
} }
} }
} }
multiclass PseudoVEXT_VF4 { multiclass PseudoVEXT_VF4 {
defvar constraints = "@earlyclobber $rd"; defvar constraints = "@earlyclobber $rd";
foreach m = MxListVF4 in foreach m = MxListVF4 in
{ {
defvar mx = m.MX; defvar mx = m.MX;
defvar WriteVExtV_MX = !cast<SchedWrite>("WriteVExtV_" # mx); defvar WriteVExtV_MX = !cast<SchedWrite>("WriteVExtV_" # mx);
defvar ReadVExtV_MX = !cast<SchedRead>("ReadVExtV_" # mx); defvar ReadVExtV_MX = !cast<SchedRead>("ReadVExtV_" # mx);
let VLMul = m.value in { let VLMul = m.value in {
def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f4vrclass, constraints>, def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f4vrclass, constraints>,
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>; Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
def "_" # mx # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.f4vrclass, constraints>,
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
def "_" # mx # "_MASK" : def "_" # mx # "_MASK" :
VPseudoUnaryMask<m.vrclass, m.f4vrclass, constraints>, VPseudoUnaryMask<m.vrclass, m.f4vrclass, constraints>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>, RISCVMaskedPseudo</*MaskOpIdx*/ 2, /*HasTU*/ false, /*IsCombined*/true>,
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>; Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
} }
} }
} }
multiclass PseudoVEXT_VF8 { multiclass PseudoVEXT_VF8 {
defvar constraints = "@earlyclobber $rd"; defvar constraints = "@earlyclobber $rd";
foreach m = MxListVF8 in foreach m = MxListVF8 in
{ {
defvar mx = m.MX; defvar mx = m.MX;
defvar WriteVExtV_MX = !cast<SchedWrite>("WriteVExtV_" # mx); defvar WriteVExtV_MX = !cast<SchedWrite>("WriteVExtV_" # mx);
defvar ReadVExtV_MX = !cast<SchedRead>("ReadVExtV_" # mx); defvar ReadVExtV_MX = !cast<SchedRead>("ReadVExtV_" # mx);
let VLMul = m.value in { let VLMul = m.value in {
def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f8vrclass, constraints>, def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f8vrclass, constraints>,
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>; Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
def "_" # mx # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.f8vrclass, constraints>,
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
def "_" # mx # "_MASK" : def "_" # mx # "_MASK" :
VPseudoUnaryMask<m.vrclass, m.f8vrclass, constraints>, VPseudoUnaryMask<m.vrclass, m.f8vrclass, constraints>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>, RISCVMaskedPseudo</*MaskOpIdx*/ 2, /*HasTU*/ false, /*IsCombined*/true>,
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>; Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
} }
} }
} }
// The destination EEW is 1 since "For the purposes of register group overlap // The destination EEW is 1 since "For the purposes of register group overlap
// constraints, mask elements have EEW=1." // constraints, mask elements have EEW=1."
// The source EEW is 8, 16, 32, or 64. // The source EEW is 8, 16, 32, or 64.
▲ Show 20 Lines • Show All 1,061 Lines • ▼ Show 20 Lines
} }
multiclass VPseudoConversion<VReg RetClass, multiclass VPseudoConversion<VReg RetClass,
VReg Op1Class, VReg Op1Class,
LMULInfo MInfo, LMULInfo MInfo,
string Constraint = ""> { string Constraint = ""> {
let VLMul = MInfo.value in { let VLMul = MInfo.value in {
def "_" # MInfo.MX : VPseudoUnaryNoMask<RetClass, Op1Class, Constraint>; def "_" # MInfo.MX : VPseudoUnaryNoMask<RetClass, Op1Class, Constraint>;
def "_" # MInfo.MX # "_TU": VPseudoUnaryNoMaskTU<RetClass, Op1Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask<RetClass, Op1Class, def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask<RetClass, Op1Class,
Constraint>, Constraint>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>; RISCVMaskedPseudo</*MaskOpIdx*/ 2,
/*HasTU*/ false,
/*IsCombined*/true>;
} }
} }
multiclass VPseudoConversionRM<VReg RetClass, multiclass VPseudoConversionRM<VReg RetClass,
VReg Op1Class, VReg Op1Class,
LMULInfo MInfo, LMULInfo MInfo,
string Constraint = ""> { string Constraint = ""> {
let VLMul = MInfo.value in { let VLMul = MInfo.value in {
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class VPatUnaryNoMask<string intrinsic_name, class VPatUnaryNoMask<string intrinsic_name,
string inst, string inst,
string kind, string kind,
ValueType result_type, ValueType result_type,
ValueType op2_type, ValueType op2_type,
int log2sew, int log2sew,
LMULInfo vlmul, LMULInfo vlmul,
VReg op2_reg_class,
bit isSEWAware = 0> :
Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
(result_type undef),
(op2_type op2_reg_class:$rs2),
VLOpFrag)),
(!cast<Instruction>(
!if(isSEWAware,
inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew),
inst#"_"#kind#"_"#vlmul.MX))
(op2_type op2_reg_class:$rs2),
GPR:$vl, log2sew)>;
class VPatUnaryNoMaskTU<string intrinsic_name,
string inst,
string kind,
ValueType result_type,
ValueType op2_type,
int log2sew,
LMULInfo vlmul,
VReg result_reg_class, VReg result_reg_class,
VReg op2_reg_class, VReg op2_reg_class,
bit isSEWAware = 0> : bit isSEWAware = 0> :
Pat<(result_type (!cast<Intrinsic>(intrinsic_name) Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
(result_type result_reg_class:$merge), (result_type result_reg_class:$merge),
(op2_type op2_reg_class:$rs2), (op2_type op2_reg_class:$rs2),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>( (!cast<Instruction>(
!if(isSEWAware, !if(isSEWAware,
inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_TU", inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew),
inst#"_"#kind#"_"#vlmul.MX#"_TU")) inst#"_"#kind#"_"#vlmul.MX))
(result_type result_reg_class:$merge), (result_type result_reg_class:$merge),
(op2_type op2_reg_class:$rs2), (op2_type op2_reg_class:$rs2),
GPR:$vl, log2sew)>; GPR:$vl, log2sew, TU_MU)>;
class VPatUnaryMask<string intrinsic_name, class VPatUnaryMask<string intrinsic_name,
string inst, string inst,
string kind, string kind,
ValueType result_type, ValueType result_type,
ValueType op2_type, ValueType op2_type,
ValueType mask_type, ValueType mask_type,
int log2sew, int log2sew,
Show All 16 Lines
class VPatMaskUnaryNoMask<string intrinsic_name, class VPatMaskUnaryNoMask<string intrinsic_name,
string inst, string inst,
MTypeInfo mti> : MTypeInfo mti> :
Pat<(mti.Mask (!cast<Intrinsic>(intrinsic_name) Pat<(mti.Mask (!cast<Intrinsic>(intrinsic_name)
(mti.Mask VR:$rs2), (mti.Mask VR:$rs2),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(inst#"_M_"#mti.BX) (!cast<Instruction>(inst#"_M_"#mti.BX)
(mti.Mask (IMPLICIT_DEF)),
(mti.Mask VR:$rs2), (mti.Mask VR:$rs2),
GPR:$vl, mti.Log2SEW)>; GPR:$vl, mti.Log2SEW, TU_MU)>;
class VPatMaskUnaryMask<string intrinsic_name, class VPatMaskUnaryMask<string intrinsic_name,
string inst, string inst,
MTypeInfo mti> : MTypeInfo mti> :
Pat<(mti.Mask (!cast<Intrinsic>(intrinsic_name#"_mask") Pat<(mti.Mask (!cast<Intrinsic>(intrinsic_name#"_mask")
(mti.Mask VR:$merge), (mti.Mask VR:$merge),
(mti.Mask VR:$rs2), (mti.Mask VR:$rs2),
(mti.Mask V0), (mti.Mask V0),
▲ Show 20 Lines • Show All 460 Lines • ▼ Show 20 Linesmulticlass VPatUnaryM_M<string intrinsic,
} }
} }
multiclass VPatUnaryV_M<string intrinsic, string instruction> multiclass VPatUnaryV_M<string intrinsic, string instruction>
{ {
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
let Predicates = GetVTypePredicates<vti>.Predicates in { let Predicates = GetVTypePredicates<vti>.Predicates in {
def : VPatUnaryNoMask<intrinsic, instruction, "M", vti.Vector, vti.Mask, def : VPatUnaryNoMask<intrinsic, instruction, "M", vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, VR>;
def : VPatUnaryNoMaskTU<intrinsic, instruction, "M", vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass,VR>; vti.Log2SEW, vti.LMul, vti.RegClass, VR>;
def : VPatUnaryMask<intrinsic, instruction, "M", vti.Vector, vti.Mask, def : VPatUnaryMask<intrinsic, instruction, "M", vti.Vector, vti.Mask,
vti.Mask, vti.Log2SEW, vti.LMul, vti.RegClass, VR>; vti.Mask, vti.Log2SEW, vti.LMul, vti.RegClass, VR>;
} }
} }
} }
multiclass VPatUnaryV_VF<string intrinsic, string instruction, string suffix, multiclass VPatUnaryV_VF<string intrinsic, string instruction, string suffix,
list<VTypeInfoToFraction> fractionList> list<VTypeInfoToFraction> fractionList>
{ {
foreach vtiTofti = fractionList in foreach vtiTofti = fractionList in
{ {
defvar vti = vtiTofti.Vti; defvar vti = vtiTofti.Vti;
defvar fti = vtiTofti.Fti; defvar fti = vtiTofti.Fti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<fti>.Predicates) in { GetVTypePredicates<fti>.Predicates) in {
def : VPatUnaryNoMask<intrinsic, instruction, suffix, def : VPatUnaryNoMask<intrinsic, instruction, suffix,
vti.Vector, fti.Vector, vti.Vector, fti.Vector,
vti.Log2SEW, vti.LMul, fti.RegClass>;
def : VPatUnaryNoMaskTU<intrinsic, instruction, suffix,
vti.Vector, fti.Vector,
vti.Log2SEW, vti.LMul, vti.RegClass, fti.RegClass>; vti.Log2SEW, vti.LMul, vti.RegClass, fti.RegClass>;
def : VPatUnaryMask<intrinsic, instruction, suffix, def : VPatUnaryMask<intrinsic, instruction, suffix,
vti.Vector, fti.Vector, vti.Mask, vti.Vector, fti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass, fti.RegClass>; vti.Log2SEW, vti.LMul, vti.RegClass, fti.RegClass>;
} }
} }
} }
multiclass VPatUnaryV_V<string intrinsic, string instruction, multiclass VPatUnaryV_V<string intrinsic, string instruction,
list<VTypeInfo> vtilist, bit isSEWAware = 0> { list<VTypeInfo> vtilist, bit isSEWAware = 0> {
foreach vti = vtilist in { foreach vti = vtilist in {
let Predicates = GetVTypePredicates<vti>.Predicates in { let Predicates = GetVTypePredicates<vti>.Predicates in {
def : VPatUnaryNoMask<intrinsic, instruction, "V", def : VPatUnaryNoMask<intrinsic, instruction, "V",
vti.Vector, vti.Vector, vti.Log2SEW, vti.Vector, vti.Vector, vti.Log2SEW,
vti.LMul, vti.RegClass, isSEWAware>;
def : VPatUnaryNoMaskTU<intrinsic, instruction, "V",
vti.Vector, vti.Vector, vti.Log2SEW,
vti.LMul, vti.RegClass, vti.RegClass, isSEWAware>; vti.LMul, vti.RegClass, vti.RegClass, isSEWAware>;
def : VPatUnaryMask<intrinsic, instruction, "V", def : VPatUnaryMask<intrinsic, instruction, "V",
vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
vti.LMul, vti.RegClass, vti.RegClass, isSEWAware>; vti.LMul, vti.RegClass, vti.RegClass, isSEWAware>;
} }
} }
} }
multiclass VPatNullaryV<string intrinsic, string instruction> multiclass VPatNullaryV<string intrinsic, string instruction>
▲ Show 20 Lines • Show All 186 Lines • ▼ Show 20 Linesmulticlass VPatConversionTA<string intrinsic,
ValueType op1_type, ValueType op1_type,
ValueType mask_type, ValueType mask_type,
int sew, int sew,
LMULInfo vlmul, LMULInfo vlmul,
VReg result_reg_class, VReg result_reg_class,
VReg op1_reg_class> VReg op1_reg_class>
{ {
def : VPatUnaryNoMask<intrinsic, inst, kind, result_type, op1_type, def : VPatUnaryNoMask<intrinsic, inst, kind, result_type, op1_type,
sew, vlmul, op1_reg_class>;
def : VPatUnaryNoMaskTU<intrinsic, inst, kind, result_type, op1_type,
sew, vlmul, result_reg_class, op1_reg_class>; sew, vlmul, result_reg_class, op1_reg_class>;
def : VPatUnaryMask<intrinsic, inst, kind, result_type, op1_type, def : VPatUnaryMask<intrinsic, inst, kind, result_type, op1_type,
mask_type, sew, vlmul, result_reg_class, op1_reg_class>; mask_type, sew, vlmul, result_reg_class, op1_reg_class>;
} }
multiclass VPatBinaryV_VV<string intrinsic, string instruction, multiclass VPatBinaryV_VV<string intrinsic, string instruction,
list<VTypeInfo> vtilist, bit isSEWAware = 0> { list<VTypeInfo> vtilist, bit isSEWAware = 0> {
foreach vti = vtilist in foreach vti = vtilist in
let Predicates = GetVTypePredicates<vti>.Predicates in let Predicates = GetVTypePredicates<vti>.Predicates in
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//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm : VPatBinaryV_VM_XM_IM<"int_riscv_vmerge", "PseudoVMERGE">; defm : VPatBinaryV_VM_XM_IM<"int_riscv_vmerge", "PseudoVMERGE">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 11.16. Vector Integer Move Instructions // 11.16. Vector Integer Move Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
foreach vti = AllVectors in { foreach vti = AllVectors in {
let Predicates = GetVTypePredicates<vti>.Predicates in { let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(vti.Vector (int_riscv_vmv_v_v (vti.Vector undef),
(vti.Vector vti.RegClass:$rs1),
VLOpFrag)),
(!cast<Instruction>("PseudoVMV_V_V_"#vti.LMul.MX)
$rs1, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Vector (int_riscv_vmv_v_v (vti.Vector vti.RegClass:$passthru), def : Pat<(vti.Vector (int_riscv_vmv_v_v (vti.Vector vti.RegClass:$passthru),
(vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs1),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVMV_V_V_"#vti.LMul.MX#"_TU") (!cast<Instruction>("PseudoVMV_V_V_"#vti.LMul.MX)
$passthru, $rs1, GPR:$vl, vti.Log2SEW)>; $passthru, $rs1, GPR:$vl, vti.Log2SEW, TU_MU)>;
// vmv.v.x/vmv.v.i are handled in RISCInstrVInstrInfoVVLPatterns.td // vmv.v.x/vmv.v.i are handled in RISCInstrVInstrInfoVVLPatterns.td
} }
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 12. Vector Fixed-Point Arithmetic Instructions // 12. Vector Fixed-Point Arithmetic Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
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llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Show First 20 Lines • Show All 310 Lines • ▼ Show 20 Linesmulticlass VPatExtendSDNode_V<list<SDNode> ops, string inst_name, string suffix,
foreach vtiTofti = fraction_list in { foreach vtiTofti = fraction_list in {
defvar vti = vtiTofti.Vti; defvar vti = vtiTofti.Vti;
defvar fti = vtiTofti.Fti; defvar fti = vtiTofti.Fti;
foreach op = ops in foreach op = ops in
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<fti>.Predicates) in GetVTypePredicates<fti>.Predicates) in
def : Pat<(vti.Vector (op (fti.Vector fti.RegClass:$rs2))), def : Pat<(vti.Vector (op (fti.Vector fti.RegClass:$rs2))),
(!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX) (!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX)
fti.RegClass:$rs2, fti.AVL, vti.Log2SEW)>; (vti.Vector (IMPLICIT_DEF)),
fti.RegClass:$rs2, fti.AVL, vti.Log2SEW, TU_MU)>;
} }
} }
multiclass VPatConvertI2FPSDNode_V<SDPatternOperator vop, multiclass VPatConvertI2FPSDNode_V<SDPatternOperator vop,
string instruction_name> { string instruction_name> {
foreach fvti = AllFloatVectors in { foreach fvti = AllFloatVectors in {
defvar ivti = GetIntVTypeInfo<fvti>.Vti; defvar ivti = GetIntVTypeInfo<fvti>.Vti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<ivti>.Predicates) in GetVTypePredicates<ivti>.Predicates) in
def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1))), def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1))),
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX) (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
ivti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>; (fvti.Vector (IMPLICIT_DEF)),
ivti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW, TU_MU)>;
} }
} }
multiclass VPatConvertFP2ISDNode_V<SDPatternOperator vop, multiclass VPatConvertFP2ISDNode_V<SDPatternOperator vop,
string instruction_name> { string instruction_name> {
foreach fvti = AllFloatVectors in { foreach fvti = AllFloatVectors in {
defvar ivti = GetIntVTypeInfo<fvti>.Vti; defvar ivti = GetIntVTypeInfo<fvti>.Vti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<ivti>.Predicates) in GetVTypePredicates<ivti>.Predicates) in
def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1))), def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1))),
(!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX) (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX)
fvti.RegClass:$rs1, ivti.AVL, ivti.Log2SEW)>; (ivti.Vector (IMPLICIT_DEF)),
fvti.RegClass:$rs1, ivti.AVL, ivti.Log2SEW, TU_MU)>;
} }
} }
multiclass VPatWConvertI2FPSDNode_V<SDPatternOperator vop, multiclass VPatWConvertI2FPSDNode_V<SDPatternOperator vop,
string instruction_name> { string instruction_name> {
foreach vtiToWti = AllWidenableIntToFloatVectors in { foreach vtiToWti = AllWidenableIntToFloatVectors in {
defvar ivti = vtiToWti.Vti; defvar ivti = vtiToWti.Vti;
defvar fwti = vtiToWti.Wti; defvar fwti = vtiToWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<ivti>.Predicates, let Predicates = !listconcat(GetVTypePredicates<ivti>.Predicates,
GetVTypePredicates<fwti>.Predicates) in GetVTypePredicates<fwti>.Predicates) in
def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1))), def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1))),
(!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX) (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX)
ivti.RegClass:$rs1, ivti.AVL, ivti.Log2SEW)>; (fwti.Vector (IMPLICIT_DEF)),
ivti.RegClass:$rs1, ivti.AVL, ivti.Log2SEW, TU_MU)>;
} }
} }
multiclass VPatWConvertFP2ISDNode_V<SDPatternOperator vop, multiclass VPatWConvertFP2ISDNode_V<SDPatternOperator vop,
string instruction_name> { string instruction_name> {
foreach fvtiToFWti = AllWidenableFloatVectors in { foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti; defvar fvti = fvtiToFWti.Vti;
defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<iwti>.Predicates) in GetVTypePredicates<iwti>.Predicates) in
def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1))), def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1))),
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX) (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
fvti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>; (iwti.Vector (IMPLICIT_DEF)),
fvti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW, TU_MU)>;
} }
} }
multiclass VPatNConvertI2FPSDNode_W<SDPatternOperator vop, multiclass VPatNConvertI2FPSDNode_W<SDPatternOperator vop,
string instruction_name> { string instruction_name> {
foreach fvtiToFWti = AllWidenableFloatVectors in { foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti; defvar fvti = fvtiToFWti.Vti;
defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<iwti>.Predicates) in GetVTypePredicates<iwti>.Predicates) in
def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1))), def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1))),
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX) (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
iwti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>; (fvti.Vector (IMPLICIT_DEF)),
iwti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW, TU_MU)>;
} }
} }
multiclass VPatNConvertFP2ISDNode_W<SDPatternOperator vop, multiclass VPatNConvertFP2ISDNode_W<SDPatternOperator vop,
string instruction_name> { string instruction_name> {
foreach vtiToWti = AllWidenableIntToFloatVectors in { foreach vtiToWti = AllWidenableIntToFloatVectors in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar fwti = vtiToWti.Wti; defvar fwti = vtiToWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<fwti>.Predicates) in GetVTypePredicates<fwti>.Predicates) in
def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1))), def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1))),
(!cast<Instruction>(instruction_name#"_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_"#vti.LMul.MX)
fwti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>; (vti.Vector (IMPLICIT_DEF)),
fwti.RegClass:$rs1, vti.AVL, vti.Log2SEW, TU_MU)>;
} }
} }
multiclass VPatWidenBinarySDNode_VV_VX<SDNode op, PatFrags extop1, PatFrags extop2, multiclass VPatWidenBinarySDNode_VV_VX<SDNode op, PatFrags extop1, PatFrags extop2,
string instruction_name> { string instruction_name> {
foreach vtiToWti = AllWidenableIntVectors in { foreach vtiToWti = AllWidenableIntVectors in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti; defvar wti = vtiToWti.Wti;
▲ Show 20 Lines • Show All 630 Lines • ▼ Show 20 Lines
defm : VPatWidenFPMulSacSDNode_VV_VF<"PseudoVFWMSAC">; defm : VPatWidenFPMulSacSDNode_VV_VF<"PseudoVFWMSAC">;
defm : VPatWidenFPNegMulSacSDNode_VV_VF<"PseudoVFWNMSAC">; defm : VPatWidenFPNegMulSacSDNode_VV_VF<"PseudoVFWNMSAC">;
foreach vti = AllFloatVectors in { foreach vti = AllFloatVectors in {
let Predicates = GetVTypePredicates<vti>.Predicates in { let Predicates = GetVTypePredicates<vti>.Predicates in {
// 13.8. Vector Floating-Point Square-Root Instruction // 13.8. Vector Floating-Point Square-Root Instruction
def : Pat<(any_fsqrt (vti.Vector vti.RegClass:$rs2)), def : Pat<(any_fsqrt (vti.Vector vti.RegClass:$rs2)),
(!cast<Instruction>("PseudoVFSQRT_V_"# vti.LMul.MX#"_E"#vti.SEW) (!cast<Instruction>("PseudoVFSQRT_V_"# vti.LMul.MX#"_E"#vti.SEW)
vti.RegClass:$rs2, vti.AVL, vti.Log2SEW)>; (vti.Vector (IMPLICIT_DEF)),
vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TU_MU)>;
// 13.12. Vector Floating-Point Sign-Injection Instructions // 13.12. Vector Floating-Point Sign-Injection Instructions
def : Pat<(fabs (vti.Vector vti.RegClass:$rs)), def : Pat<(fabs (vti.Vector vti.RegClass:$rs)),
(!cast<Instruction>("PseudoVFSGNJX_VV_"# vti.LMul.MX) (!cast<Instruction>("PseudoVFSGNJX_VV_"# vti.LMul.MX)
vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW)>; vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW)>;
// Handle fneg with VFSGNJN using the same input for both operands. // Handle fneg with VFSGNJN using the same input for both operands.
def : Pat<(fneg (vti.Vector vti.RegClass:$rs)), def : Pat<(fneg (vti.Vector vti.RegClass:$rs)),
(!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX) (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX)
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
defm : VPatNConvertI2FPSDNode_W<any_uint_to_fp, "PseudoVFNCVT_F_XU_W">; defm : VPatNConvertI2FPSDNode_W<any_uint_to_fp, "PseudoVFNCVT_F_XU_W">;
foreach fvtiToFWti = AllWidenableFloatVectors in { foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti; defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti; defvar fwti = fvtiToFWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates, let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<fwti>.Predicates) in GetVTypePredicates<fwti>.Predicates) in
def : Pat<(fvti.Vector (fpround (fwti.Vector fwti.RegClass:$rs1))), def : Pat<(fvti.Vector (fpround (fwti.Vector fwti.RegClass:$rs1))),
(!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX) (!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX)
fwti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>; (fvti.Vector (IMPLICIT_DEF)),
fwti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW, TU_MU)>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Vector Splats // Vector Splats
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
foreach fvti = AllFloatVectors in { foreach fvti = AllFloatVectors in {
let Predicates = GetVTypePredicates<fvti>.Predicates in { let Predicates = GetVTypePredicates<fvti>.Predicates in {
def : Pat<(fvti.Vector (SplatFPOp fvti.ScalarRegClass:$rs1)), def : Pat<(fvti.Vector (SplatFPOp fvti.ScalarRegClass:$rs1)),
(!cast<Instruction>("PseudoVFMV_V_"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) (!cast<Instruction>("PseudoVFMV_V_"#fvti.ScalarSuffix#"_"#fvti.LMul.MX)
(fvti.Vector (IMPLICIT_DEF)),
(fvti.Scalar fvti.ScalarRegClass:$rs1), (fvti.Scalar fvti.ScalarRegClass:$rs1),
fvti.AVL, fvti.Log2SEW)>; fvti.AVL, fvti.Log2SEW, TU_MU)>;
def : Pat<(fvti.Vector (SplatFPOp (fvti.Scalar fpimm0))), def : Pat<(fvti.Vector (SplatFPOp (fvti.Scalar fpimm0))),
(!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX) (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX)
0, fvti.AVL, fvti.Log2SEW)>; (fvti.Vector (IMPLICIT_DEF)),
0, fvti.AVL, fvti.Log2SEW, TU_MU)>;
} }
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Vector Element Extracts // Vector Element Extracts
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
foreach vti = AllFloatVectors in { foreach vti = AllFloatVectors in {
defvar vmv_f_s_inst = !cast<Instruction>(!strconcat("PseudoVFMV_", defvar vmv_f_s_inst = !cast<Instruction>(!strconcat("PseudoVFMV_",
Show All 9 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Show First 20 Lines • Show All 1,782 Lines • ▼ Show 20 Lines def : Pat<(vti.Vector (riscv_vp_merge_vl (vti.Mask V0),
vti.RegClass:$rs2, vti.RegClass:$rs2, simm5:$rs1, vti.RegClass:$rs2, vti.RegClass:$rs2, simm5:$rs1,
(vti.Mask V0), GPR:$vl, vti.Log2SEW)>; (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
} }
} }
// 11.16. Vector Integer Move Instructions // 11.16. Vector Integer Move Instructions
foreach vti = AllVectors in { foreach vti = AllVectors in {
let Predicates = GetVTypePredicates<vti>.Predicates in { let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(vti.Vector (riscv_vmv_v_v_vl (vti.Vector undef),
vti.RegClass:$rs2, VLOpFrag)),
(!cast<Instruction>("PseudoVMV_V_V_"#vti.LMul.MX)
vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Vector (riscv_vmv_v_v_vl vti.RegClass:$passthru, def : Pat<(vti.Vector (riscv_vmv_v_v_vl vti.RegClass:$passthru,
vti.RegClass:$rs2, VLOpFrag)), vti.RegClass:$rs2, VLOpFrag)),
(!cast<Instruction>("PseudoVMV_V_V_"#vti.LMul.MX#"_TU") (!cast<Instruction>("PseudoVMV_V_V_"#vti.LMul.MX)
vti.RegClass:$passthru, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; vti.RegClass:$passthru, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>;
} }
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
def : Pat<(vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), GPR:$rs2, VLOpFrag)),
(!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX)
GPR:$rs2, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.RegClass:$passthru, GPR:$rs2, VLOpFrag)), def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.RegClass:$passthru, GPR:$rs2, VLOpFrag)),
(!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX#"_TU") (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX)
vti.RegClass:$passthru, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; vti.RegClass:$passthru, GPR:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>;
defvar ImmPat = !cast<ComplexPattern>("sew"#vti.SEW#"simm5"); defvar ImmPat = !cast<ComplexPattern>("sew"#vti.SEW#"simm5");
def : Pat<(vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), (ImmPat simm5:$imm5),
VLOpFrag)),
(!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX)
simm5:$imm5, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.RegClass:$passthru, (ImmPat simm5:$imm5), def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.RegClass:$passthru, (ImmPat simm5:$imm5),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX#"_TU") (!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX)
vti.RegClass:$passthru, simm5:$imm5, GPR:$vl, vti.Log2SEW)>; vti.RegClass:$passthru, simm5:$imm5, GPR:$vl, vti.Log2SEW, TU_MU)>;
} }
} }
// 12. Vector Fixed-Point Arithmetic Instructions // 12. Vector Fixed-Point Arithmetic Instructions
// 12.1. Vector Single-Width Saturating Add and Subtract // 12.1. Vector Single-Width Saturating Add and Subtract
defm : VPatBinaryVL_VV_VX_VI<riscv_saddsat_vl, "PseudoVSADD">; defm : VPatBinaryVL_VV_VX_VI<riscv_saddsat_vl, "PseudoVSADD">;
defm : VPatBinaryVL_VV_VX_VI<riscv_uaddsat_vl, "PseudoVSADDU">; defm : VPatBinaryVL_VV_VX_VI<riscv_uaddsat_vl, "PseudoVSADDU">;
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines def : Pat<(any_riscv_vfround_noexcept_vl (vti.Vector vti.RegClass:$rs1),
(!cast<Instruction>("PseudoVFROUND_NOEXCEPT_V_" # vti.LMul.MX #"_MASK") (!cast<Instruction>("PseudoVFROUND_NOEXCEPT_V_" # vti.LMul.MX #"_MASK")
(vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1,
(vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>; (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>;
// 14.14. Vector Floating-Point Classify Instruction // 14.14. Vector Floating-Point Classify Instruction
def : Pat<(riscv_fclass_vl (vti.Vector vti.RegClass:$rs2), def : Pat<(riscv_fclass_vl (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag), (vti.Mask true_mask), VLOpFrag),
(!cast<Instruction>("PseudoVFCLASS_V_"# vti.LMul.MX) (!cast<Instruction>("PseudoVFCLASS_V_"# vti.LMul.MX)
vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>;
} }
} }
foreach fvti = AllFloatVectors in { foreach fvti = AllFloatVectors in {
// Floating-point vselects: // Floating-point vselects:
// 11.15. Vector Integer Merge Instructions // 11.15. Vector Integer Merge Instructions
// 13.15. Vector Floating-Point Merge Instruction // 13.15. Vector Floating-Point Merge Instruction
let Predicates = GetVTypePredicates<fvti>.Predicates in { let Predicates = GetVTypePredicates<fvti>.Predicates in {
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines def : Pat<(fvti.Vector (riscv_vp_merge_vl (fvti.Mask V0),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX#"_TU") (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX#"_TU")
fvti.RegClass:$rs2, fvti.RegClass:$rs2, 0, (fvti.Mask V0), fvti.RegClass:$rs2, fvti.RegClass:$rs2, 0, (fvti.Mask V0),
GPR:$vl, fvti.Log2SEW)>; GPR:$vl, fvti.Log2SEW)>;
// 13.16. Vector Floating-Point Move Instruction // 13.16. Vector Floating-Point Move Instruction
// If we're splatting fpimm0, use vmv.v.x vd, x0. // If we're splatting fpimm0, use vmv.v.x vd, x0.
def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl
(fvti.Vector undef), (fvti.Scalar (fpimm0)), VLOpFrag)),
(!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX)
0, GPR:$vl, fvti.Log2SEW)>;
def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl
fvti.Vector:$passthru, (fvti.Scalar (fpimm0)), VLOpFrag)), fvti.Vector:$passthru, (fvti.Scalar (fpimm0)), VLOpFrag)),
(!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX#"_TU") (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX)
$passthru, 0, GPR:$vl, fvti.Log2SEW)>; $passthru, 0, GPR:$vl, fvti.Log2SEW, TU_MU)>;
def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl
(fvti.Vector undef), (fvti.Scalar (SelectFPImm (XLenVT GPR:$imm))), VLOpFrag)),
(!cast<Instruction>("PseudoVMV_V_X_"#fvti.LMul.MX)
GPR:$imm, GPR:$vl, fvti.Log2SEW)>;
def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl
fvti.Vector:$passthru, (fvti.Scalar (SelectFPImm (XLenVT GPR:$imm))), VLOpFrag)), fvti.Vector:$passthru, (fvti.Scalar (SelectFPImm (XLenVT GPR:$imm))), VLOpFrag)),
(!cast<Instruction>("PseudoVMV_V_X_"#fvti.LMul.MX#"_TU") (!cast<Instruction>("PseudoVMV_V_X_"#fvti.LMul.MX)
$passthru, GPR:$imm, GPR:$vl, fvti.Log2SEW)>; $passthru, GPR:$imm, GPR:$vl, fvti.Log2SEW, TU_MU)>;
def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl
(fvti.Vector undef), (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)),
(!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" #
fvti.LMul.MX)
(fvti.Scalar fvti.ScalarRegClass:$rs2),
GPR:$vl, fvti.Log2SEW)>;
def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl
fvti.Vector:$passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)), fvti.Vector:$passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)),
(!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" # (!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" #
fvti.LMul.MX # "_TU") fvti.LMul.MX)
$passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), $passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2),
GPR:$vl, fvti.Log2SEW)>; GPR:$vl, fvti.Log2SEW, TU_MU)>;
} }
} }
// 13.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions // 13.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions
defm : VPatConvertFP2IVL_V<riscv_vfcvt_xu_f_vl, "PseudoVFCVT_XU_F_V">; defm : VPatConvertFP2IVL_V<riscv_vfcvt_xu_f_vl, "PseudoVFCVT_XU_F_V">;
defm : VPatConvertFP2IVL_V<riscv_vfcvt_x_f_vl, "PseudoVFCVT_X_F_V">; defm : VPatConvertFP2IVL_V<riscv_vfcvt_x_f_vl, "PseudoVFCVT_X_F_V">;
defm : VPatConvertFP2I_RM_VL_V<riscv_vfcvt_rm_xu_f_vl, "PseudoVFCVT_RM_XU_F_V">; defm : VPatConvertFP2I_RM_VL_V<riscv_vfcvt_rm_xu_f_vl, "PseudoVFCVT_RM_XU_F_V">;
defm : VPatConvertFP2I_RM_VL_V<any_riscv_vfcvt_rm_x_f_vl, "PseudoVFCVT_RM_X_F_V">; defm : VPatConvertFP2I_RM_VL_V<any_riscv_vfcvt_rm_x_f_vl, "PseudoVFCVT_RM_X_F_V">;
▲ Show 20 Lines • Show All 446 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/calling-conv-vector-on-stack.ll

Show All 11 Lines
; CHECK-NEXT: sd s1, 72(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 72(sp) # 8-byte Folded Spill
; CHECK-NEXT: addi s0, sp, 96 ; CHECK-NEXT: addi s0, sp, 96
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: sub sp, sp, a0 ; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: andi sp, sp, -64 ; CHECK-NEXT: andi sp, sp, -64
; CHECK-NEXT: mv s1, sp ; CHECK-NEXT: mv s1, sp
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: addi a0, s1, 64 ; CHECK-NEXT: addi a0, s1, 64
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: sd a0, 0(sp) ; CHECK-NEXT: sd a0, 0(sp)
; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: li a1, 0
; CHECK-NEXT: li a2, 0 ; CHECK-NEXT: li a2, 0
; CHECK-NEXT: li a3, 0 ; CHECK-NEXT: li a3, 0
; CHECK-NEXT: li a4, 0 ; CHECK-NEXT: li a4, 0
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: li a6, 0 ; CHECK-NEXT: li a6, 0
; CHECK-NEXT: li a7, 0 ; CHECK-NEXT: li a7, 0
Show All 15 Lines

llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Linesbody: |
; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $x8, 0 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $x8, 0
; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -272 ; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -272
; CHECK-NEXT: $x10 = frame-setup PseudoReadVLENB ; CHECK-NEXT: $x10 = frame-setup PseudoReadVLENB
; CHECK-NEXT: $x11 = frame-setup ADDI killed $x0, 52 ; CHECK-NEXT: $x11 = frame-setup ADDI killed $x0, 52
; CHECK-NEXT: $x10 = frame-setup MUL killed $x10, killed $x11 ; CHECK-NEXT: $x10 = frame-setup MUL killed $x10, killed $x11
; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x10 ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x10
; CHECK-NEXT: $x2 = frame-setup ANDI $x2, -128 ; CHECK-NEXT: $x2 = frame-setup ANDI $x2, -128
; CHECK-NEXT: dead renamable $x15 = PseudoVSETIVLI 1, 72 /* e16, m1, ta, mu */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead renamable $x15 = PseudoVSETIVLI 1, 72 /* e16, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: renamable $v25 = PseudoVMV_V_X_M1 killed renamable $x12, $noreg, 4 /* e16 */, implicit $vl, implicit $vtype ; CHECK-NEXT: renamable $v25 = PseudoVMV_V_X_M1 undef $v25, killed renamable $x12, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: $x10 = PseudoReadVLENB ; CHECK-NEXT: $x10 = PseudoReadVLENB
; CHECK-NEXT: $x11 = ADDI killed $x0, 50 ; CHECK-NEXT: $x11 = ADDI killed $x0, 50
; CHECK-NEXT: $x10 = MUL killed $x10, killed $x11 ; CHECK-NEXT: $x10 = MUL killed $x10, killed $x11
; CHECK-NEXT: $x10 = ADD $x2, killed $x10 ; CHECK-NEXT: $x10 = ADD $x2, killed $x10
; CHECK-NEXT: $x10 = ADDI killed $x10, 2047 ; CHECK-NEXT: $x10 = ADDI killed $x10, 2047
; CHECK-NEXT: $x10 = ADDI killed $x10, 161 ; CHECK-NEXT: $x10 = ADDI killed $x10, 161
; CHECK-NEXT: VS1R_V killed renamable $v25, killed $x10 :: (store unknown-size into %stack.1, align 8) ; CHECK-NEXT: VS1R_V killed renamable $v25, killed $x10 :: (store unknown-size into %stack.1, align 8)
; CHECK-NEXT: renamable $x1 = ADDI $x0, 255 ; CHECK-NEXT: renamable $x1 = ADDI $x0, 255
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Linesbody: |
; CHECK-NEXT: $x27 = LD $x2, 1936 :: (load (s64) from %stack.14) ; CHECK-NEXT: $x27 = LD $x2, 1936 :: (load (s64) from %stack.14)
; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 2032 ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 2032
; CHECK-NEXT: PseudoRET ; CHECK-NEXT: PseudoRET
bb.0: bb.0:
successors: %bb.1, %bb.2 successors: %bb.1, %bb.2
liveins: $x12 liveins: $x12
dead renamable $x15 = PseudoVSETIVLI 1, 72, implicit-def $vl, implicit-def $vtype dead renamable $x15 = PseudoVSETIVLI 1, 72, implicit-def $vl, implicit-def $vtype
renamable $v25 = PseudoVMV_V_X_M1 killed renamable $x12, $noreg, 4, implicit $vl, implicit $vtype renamable $v25 = PseudoVMV_V_X_M1 undef $v25, killed renamable $x12, $noreg, 4, 0, implicit $vl, implicit $vtype
VS1R_V killed renamable $v25, %stack.1 :: (store unknown-size into %stack.1, align 8) VS1R_V killed renamable $v25, %stack.1 :: (store unknown-size into %stack.1, align 8)
renamable $x1 = ADDI $x0, 255 renamable $x1 = ADDI $x0, 255
renamable $x5 = nuw ADDI %stack.0, 256 renamable $x5 = nuw ADDI %stack.0, 256
renamable $x6 = ADDI %stack.0, 384 renamable $x6 = ADDI %stack.0, 384
renamable $x7 = nuw ADDI %stack.0, 512 renamable $x7 = nuw ADDI %stack.0, 512
renamable $x10 = ADDI $x0, 128 renamable $x10 = ADDI $x0, 128
renamable $x12 = nuw ADDI %stack.0, 128 renamable $x12 = nuw ADDI %stack.0, 128
renamable $x14 = COPY $x0 renamable $x14 = COPY $x0
Show All 38 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-transpose.ll

Show All 36 Lines
} }
define <16 x i8> @trn1.v16i8(<16 x i8> %v0, <16 x i8> %v1) { define <16 x i8> @trn1.v16i8(<16 x i8> %v0, <16 x i8> %v1) {
; RV32-LABEL: trn1.v16i8: ; RV32-LABEL: trn1.v16i8:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vid.v v11 ; RV32-NEXT: vid.v v11
; RV32-NEXT: vrgather.vv v10, v8, v11 ; RV32-NEXT: vrgather.vv v10, v8, v11
; RV32-NEXT: vadd.vi v8, v11, -1
; RV32-NEXT: lui a0, 11 ; RV32-NEXT: lui a0, 11
; RV32-NEXT: addi a0, a0, -1366 ; RV32-NEXT: addi a0, a0, -1366
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a0 ; RV32-NEXT: vmv.v.x v0, a0
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV32-NEXT: vadd.vi v8, v11, -1
; RV32-NEXT: vrgather.vv v10, v9, v8, v0.t ; RV32-NEXT: vrgather.vv v10, v9, v8, v0.t
; RV32-NEXT: vmv.v.v v8, v10 ; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: trn1.v16i8: ; RV64-LABEL: trn1.v16i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vid.v v11 ; RV64-NEXT: vid.v v11
; RV64-NEXT: vrgather.vv v10, v8, v11 ; RV64-NEXT: vrgather.vv v10, v8, v11
; RV64-NEXT: vadd.vi v8, v11, -1
; RV64-NEXT: lui a0, 11 ; RV64-NEXT: lui a0, 11
; RV64-NEXT: addiw a0, a0, -1366 ; RV64-NEXT: addiw a0, a0, -1366
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vmv.v.x v0, a0 ; RV64-NEXT: vmv.v.x v0, a0
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64-NEXT: vadd.vi v8, v11, -1
; RV64-NEXT: vrgather.vv v10, v9, v8, v0.t ; RV64-NEXT: vrgather.vv v10, v9, v8, v0.t
; RV64-NEXT: vmv.v.v v8, v10 ; RV64-NEXT: vmv.v.v v8, v10
; RV64-NEXT: ret ; RV64-NEXT: ret
%tmp0 = shufflevector <16 x i8> %v0, <16 x i8> %v1, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30> %tmp0 = shufflevector <16 x i8> %v0, <16 x i8> %v1, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
ret <16 x i8> %tmp0 ret <16 x i8> %tmp0
} }
define <16 x i8> @trn2.v16i8(<16 x i8> %v0, <16 x i8> %v1) { define <16 x i8> @trn2.v16i8(<16 x i8> %v0, <16 x i8> %v1) {
▲ Show 20 Lines • Show All 308 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll

Show First 20 Lines • Show All 1,390 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsrl.vx v10, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v10, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v11, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v11, v8, a2, v0.t
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v11, v11, a3, v0.t ; RV32-NEXT: vand.vx v11, v11, a3, v0.t
; RV32-NEXT: vor.vv v10, v11, v10, v0.t ; RV32-NEXT: vor.vv v10, v11, v10, v0.t
; RV32-NEXT: vsrl.vi v11, v8, 8, v0.t ; RV32-NEXT: vsrl.vi v11, v8, 8, v0.t
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.i v12, 0 ; RV32-NEXT: vmv.v.i v12, 0
; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: lui a4, 1044480 ; RV32-NEXT: lui a4, 1044480
; RV32-NEXT: vmerge.vxm v12, v12, a4, v0 ; RV32-NEXT: vmerge.vxm v12, v12, a4, v0
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vmv1r.v v0, v9 ; RV32-NEXT: vmv1r.v v0, v9
; RV32-NEXT: vand.vv v11, v11, v12, v0.t ; RV32-NEXT: vand.vv v11, v11, v12, v0.t
; RV32-NEXT: vsrl.vi v13, v8, 24, v0.t ; RV32-NEXT: vsrl.vi v13, v8, 24, v0.t
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v13, v13, a4, v0.t ; RV32-NEXT: vand.vx v13, v13, a4, v0.t
▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v9, v8, a1 ; RV32-NEXT: vsrl.vx v9, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v10, v8, a2 ; RV32-NEXT: vsrl.vx v10, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v10, v10, a3 ; RV32-NEXT: vand.vx v10, v10, a3
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v10, v9
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.i v10, 0 ; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: lui a4, 1044480 ; RV32-NEXT: lui a4, 1044480
; RV32-NEXT: vmerge.vxm v10, v10, a4, v0 ; RV32-NEXT: vmerge.vxm v10, v10, a4, v0
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vsrl.vi v11, v8, 8 ; RV32-NEXT: vsrl.vi v11, v8, 8
; RV32-NEXT: vand.vv v11, v11, v10 ; RV32-NEXT: vand.vv v11, v11, v10
; RV32-NEXT: vsrl.vi v12, v8, 24 ; RV32-NEXT: vsrl.vi v12, v8, 24
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v12, v12, a4 ; RV32-NEXT: vand.vx v12, v12, a4
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsrl.vx v12, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v12, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v14, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v14, v8, a2, v0.t
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v14, v14, a3, v0.t ; RV32-NEXT: vand.vx v14, v14, a3, v0.t
; RV32-NEXT: vor.vv v12, v14, v12, v0.t ; RV32-NEXT: vor.vv v12, v14, v12, v0.t
; RV32-NEXT: vsrl.vi v14, v8, 8, v0.t ; RV32-NEXT: vsrl.vi v14, v8, 24, v0.t
; RV32-NEXT: li a4, 85 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v14, v14, a4, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
; RV32-NEXT: li a5, 85
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.x v0, a4 ; RV32-NEXT: vmv.v.x v0, a5
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v18, 0
; RV32-NEXT: lui a4, 1044480 ; RV32-NEXT: lui a5, 1044480
; RV32-NEXT: vmerge.vxm v16, v16, a4, v0 ; RV32-NEXT: vmerge.vxm v18, v18, a5, v0
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vmv1r.v v0, v10 ; RV32-NEXT: vmv1r.v v0, v10
; RV32-NEXT: vand.vv v14, v14, v16, v0.t ; RV32-NEXT: vand.vv v16, v16, v18, v0.t
; RV32-NEXT: vsrl.vi v18, v8, 24, v0.t ; RV32-NEXT: vor.vv v14, v16, v14, v0.t
; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v18, v18, a4, v0.t
; RV32-NEXT: vor.vv v14, v14, v18, v0.t
; RV32-NEXT: vor.vv v12, v14, v12, v0.t ; RV32-NEXT: vor.vv v12, v14, v12, v0.t
; RV32-NEXT: vsll.vx v14, v8, a1, v0.t ; RV32-NEXT: vsll.vx v14, v8, a1, v0.t
; RV32-NEXT: vand.vx v18, v8, a3, v0.t ; RV32-NEXT: vand.vx v16, v8, a3, v0.t
; RV32-NEXT: vsll.vx v18, v18, a2, v0.t ; RV32-NEXT: vsll.vx v16, v16, a2, v0.t
; RV32-NEXT: vor.vv v14, v14, v18, v0.t ; RV32-NEXT: vor.vv v14, v14, v16, v0.t
; RV32-NEXT: vand.vx v18, v8, a4, v0.t ; RV32-NEXT: vand.vx v16, v8, a4, v0.t
; RV32-NEXT: vsll.vi v18, v18, 24, v0.t ; RV32-NEXT: vsll.vi v16, v16, 24, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vv v8, v8, v18, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t ; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
; RV32-NEXT: vor.vv v8, v18, v8, v0.t ; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: vor.vv v8, v14, v8, v0.t ; RV32-NEXT: vor.vv v8, v14, v8, v0.t
; RV32-NEXT: vor.vv v8, v8, v12, v0.t ; RV32-NEXT: vor.vv v8, v8, v12, v0.t
; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t ; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t
; RV32-NEXT: lui a1, 61681 ; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241 ; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.x v14, a1 ; RV32-NEXT: vmv.v.x v14, a1
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsrl.vx v10, v8, a1 ; RV32-NEXT: vsrl.vx v10, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v12, v8, a2 ; RV32-NEXT: vsrl.vx v12, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v12, v12, a3 ; RV32-NEXT: vand.vx v12, v12, a3
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vsrl.vi v12, v8, 8
; RV32-NEXT: li a4, 85 ; RV32-NEXT: li a4, 85
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.x v0, a4 ; RV32-NEXT: vmv.v.x v0, a4
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.i v12, 0 ; RV32-NEXT: vmv.v.i v14, 0
; RV32-NEXT: lui a4, 1044480 ; RV32-NEXT: lui a4, 1044480
; RV32-NEXT: vmerge.vxm v12, v12, a4, v0 ; RV32-NEXT: vmerge.vxm v14, v14, a4, v0
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsrl.vi v14, v8, 8 ; RV32-NEXT: vand.vv v12, v12, v14
; RV32-NEXT: vand.vv v14, v14, v12
; RV32-NEXT: vsrl.vi v16, v8, 24 ; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v16, v16, a4 ; RV32-NEXT: vand.vx v16, v16, a4
; RV32-NEXT: vor.vv v14, v14, v16 ; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vor.vv v10, v14, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vsll.vx v14, v8, a1 ; RV32-NEXT: vsll.vx v12, v8, a1
; RV32-NEXT: vand.vx v16, v8, a3 ; RV32-NEXT: vand.vx v16, v8, a3
; RV32-NEXT: vsll.vx v16, v16, a2 ; RV32-NEXT: vsll.vx v16, v16, a2
; RV32-NEXT: vor.vv v14, v14, v16 ; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vand.vv v12, v8, v12 ; RV32-NEXT: vand.vx v16, v8, a4
; RV32-NEXT: vsll.vi v12, v12, 8 ; RV32-NEXT: vsll.vi v16, v16, 24
; RV32-NEXT: vand.vx v8, v8, a4 ; RV32-NEXT: vand.vv v8, v8, v14
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v14, v8 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vsrl.vi v10, v8, 4 ; RV32-NEXT: vsrl.vi v10, v8, 4
; RV32-NEXT: lui a1, 61681 ; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241 ; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.x v12, a1 ; RV32-NEXT: vmv.v.x v12, a1
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v10, v10, v12 ; RV32-NEXT: vand.vv v10, v10, v12
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v20, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v20, v8, a2, v0.t
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v20, v20, a3, v0.t ; RV32-NEXT: vand.vx v20, v20, a3, v0.t
; RV32-NEXT: vor.vv v20, v20, v16, v0.t ; RV32-NEXT: vor.vv v16, v20, v16, v0.t
; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t ; RV32-NEXT: vsrl.vi v20, v8, 24, v0.t
; RV32-NEXT: lui a4, 5 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: addi a4, a4, 1365 ; RV32-NEXT: vand.vx v24, v20, a4, v0.t
; RV32-NEXT: vsrl.vi v28, v8, 8, v0.t
; RV32-NEXT: lui a5, 5
; RV32-NEXT: addi a5, a5, 1365
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a4 ; RV32-NEXT: vmv.v.x v0, a5
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v20, 0
; RV32-NEXT: lui a4, 1044480 ; RV32-NEXT: lui a5, 1044480
; RV32-NEXT: vmerge.vxm v16, v16, a4, v0 ; RV32-NEXT: vmerge.vxm v20, v20, a5, v0
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: vand.vv v24, v24, v16, v0.t ; RV32-NEXT: vand.vv v28, v28, v20, v0.t
; RV32-NEXT: vsrl.vi v28, v8, 24, v0.t ; RV32-NEXT: vor.vv v24, v28, v24, v0.t
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: vor.vv v16, v24, v16, v0.t
; RV32-NEXT: vand.vx v28, v28, a4, v0.t
; RV32-NEXT: vor.vv v24, v24, v28, v0.t
; RV32-NEXT: vor.vv v20, v24, v20, v0.t
; RV32-NEXT: vsll.vx v24, v8, a1, v0.t ; RV32-NEXT: vsll.vx v24, v8, a1, v0.t
; RV32-NEXT: vand.vx v28, v8, a3, v0.t ; RV32-NEXT: vand.vx v28, v8, a3, v0.t
; RV32-NEXT: vsll.vx v28, v28, a2, v0.t ; RV32-NEXT: vsll.vx v28, v28, a2, v0.t
; RV32-NEXT: vor.vv v24, v24, v28, v0.t ; RV32-NEXT: vor.vv v24, v24, v28, v0.t
; RV32-NEXT: vand.vx v28, v8, a4, v0.t ; RV32-NEXT: vand.vx v28, v8, a4, v0.t
; RV32-NEXT: vsll.vi v28, v28, 24, v0.t ; RV32-NEXT: vsll.vi v28, v28, 24, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vv v8, v8, v20, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t ; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
; RV32-NEXT: vor.vv v8, v28, v8, v0.t ; RV32-NEXT: vor.vv v8, v28, v8, v0.t
; RV32-NEXT: vor.vv v8, v24, v8, v0.t ; RV32-NEXT: vor.vv v8, v24, v8, v0.t
; RV32-NEXT: vor.vv v8, v8, v20, v0.t ; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: lui a1, 61681 ; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241 ; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vmv.v.x v20, a1 ; RV32-NEXT: vmv.v.x v20, a1
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vand.vv v16, v16, v20, v0.t ; RV32-NEXT: vand.vv v16, v16, v20, v0.t
; RV32-NEXT: vand.vv v8, v8, v20, v0.t ; RV32-NEXT: vand.vv v8, v8, v20, v0.t
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsrl.vx v12, v8, a1 ; RV32-NEXT: vsrl.vx v12, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v16, v8, a2 ; RV32-NEXT: vsrl.vx v16, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v16, v16, a3 ; RV32-NEXT: vand.vx v16, v16, a3
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vsrl.vi v20, v8, 8
; RV32-NEXT: lui a4, 5 ; RV32-NEXT: lui a4, 5
; RV32-NEXT: addi a4, a4, 1365 ; RV32-NEXT: addi a4, a4, 1365
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a4 ; RV32-NEXT: vmv.v.x v0, a4
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: lui a4, 1044480 ; RV32-NEXT: lui a4, 1044480
; RV32-NEXT: vmerge.vxm v16, v16, a4, v0 ; RV32-NEXT: vmerge.vxm v16, v16, a4, v0
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsrl.vi v20, v8, 8
; RV32-NEXT: vand.vv v20, v20, v16 ; RV32-NEXT: vand.vv v20, v20, v16
; RV32-NEXT: vsrl.vi v24, v8, 24 ; RV32-NEXT: vsrl.vi v24, v8, 24
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v24, v24, a4 ; RV32-NEXT: vand.vx v24, v24, a4
; RV32-NEXT: vor.vv v20, v20, v24 ; RV32-NEXT: vor.vv v20, v20, v24
; RV32-NEXT: vor.vv v12, v20, v12 ; RV32-NEXT: vor.vv v12, v20, v12
; RV32-NEXT: vsll.vx v20, v8, a1 ; RV32-NEXT: vsll.vx v20, v8, a1
; RV32-NEXT: vand.vx v24, v8, a3 ; RV32-NEXT: vand.vx v24, v8, a3
; RV32-NEXT: vsll.vx v24, v24, a2 ; RV32-NEXT: vsll.vx v24, v24, a2
; RV32-NEXT: vor.vv v20, v20, v24 ; RV32-NEXT: vor.vv v20, v20, v24
; RV32-NEXT: vand.vv v16, v8, v16 ; RV32-NEXT: vand.vx v24, v8, a4
; RV32-NEXT: vsll.vi v16, v16, 8 ; RV32-NEXT: vsll.vi v24, v24, 24
; RV32-NEXT: vand.vx v8, v8, a4 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: vor.vv v8, v20, v8 ; RV32-NEXT: vor.vv v8, v20, v8
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: vsrl.vi v12, v8, 4 ; RV32-NEXT: vsrl.vi v12, v8, 4
; RV32-NEXT: lui a1, 61681 ; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241 ; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vmv.v.x v16, a1 ; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
declare <15 x i64> @llvm.vp.bitreverse.v15i64(<15 x i64>, <15 x i1>, i32) declare <15 x i64> @llvm.vp.bitreverse.v15i64(<15 x i64>, <15 x i1>, i32)
define <15 x i64> @vp_bitreverse_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) { define <15 x i64> @vp_bitreverse_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_bitreverse_v15i64: ; RV32-LABEL: vp_bitreverse_v15i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a2, 24 ; RV32-NEXT: slli a1, a1, 5
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
; RV32-NEXT: vmv1r.v v1, v0 ; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: li a3, 56 ; RV32-NEXT: li a3, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsll.vx v24, v8, a3, v0.t ; RV32-NEXT: vsrl.vx v16, v8, a3, v0.t
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: li a4, 40
; RV32-NEXT: slli a1, a1, 4 ; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV32-NEXT: lui a1, 16 ; RV32-NEXT: lui a1, 16
; RV32-NEXT: addi a4, a1, -256 ; RV32-NEXT: addi a5, a1, -256
; RV32-NEXT: vand.vx v24, v8, a4, v0.t ; RV32-NEXT: vand.vx v24, v24, a5, v0.t
; RV32-NEXT: li a5, 40
; RV32-NEXT: vsll.vx v24, v24, a5, v0.t
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v16, v0.t ; RV32-NEXT: vor.vv v24, v24, v16, v0.t
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 4 ; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
; RV32-NEXT: lui a6, 4080 ; RV32-NEXT: lui a6, 4080
; RV32-NEXT: vand.vx v24, v8, a6, v0.t ; RV32-NEXT: vand.vx v24, v24, a6, v0.t
; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
; RV32-NEXT: addi a2, sp, 16
; RV32-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: lui a2, 349525 ; RV32-NEXT: lui a2, 349525
; RV32-NEXT: addi a2, a2, 1365 ; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: vmv.v.i v24, 0 ; RV32-NEXT: vmv.v.i v24, 0
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: lui a7, 1044480 ; RV32-NEXT: lui a7, 1044480
; RV32-NEXT: vmv.v.x v0, a2 ; RV32-NEXT: vmv.v.x v0, a2
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vmerge.vxm v24, v24, a7, v0 ; RV32-NEXT: vmerge.vxm v16, v24, a7, v0
; RV32-NEXT: addi a7, sp, 16 ; RV32-NEXT: csrr a7, vlenb
; RV32-NEXT: vs8r.v v24, (a7) # Unknown-size Folded Spill ; RV32-NEXT: li t0, 24
; RV32-NEXT: mul a7, a7, t0
; RV32-NEXT: add a7, sp, a7
; RV32-NEXT: addi a7, a7, 16
; RV32-NEXT: vs8r.v v16, (a7) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: vand.vv v16, v8, v24, v0.t ; RV32-NEXT: addi a7, sp, 16
; RV32-NEXT: vsll.vi v16, v16, 8, v0.t ; RV32-NEXT: vl8r.v v24, (a7) # Unknown-size Folded Reload
; RV32-NEXT: csrr a7, vlenb
; RV32-NEXT: li t0, 24
; RV32-NEXT: mul a7, a7, t0
; RV32-NEXT: add a7, sp, a7
; RV32-NEXT: addi a7, a7, 16
; RV32-NEXT: vl8r.v v16, (a7) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: csrr a7, vlenb ; RV32-NEXT: csrr a7, vlenb
; RV32-NEXT: slli a7, a7, 3 ; RV32-NEXT: slli a7, a7, 3
; RV32-NEXT: add a7, sp, a7 ; RV32-NEXT: add a7, sp, a7
; RV32-NEXT: addi a7, a7, 16 ; RV32-NEXT: addi a7, a7, 16
; RV32-NEXT: vl8r.v v24, (a7) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a7) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: csrr a7, vlenb ; RV32-NEXT: csrr a7, vlenb
; RV32-NEXT: slli a7, a7, 4 ; RV32-NEXT: slli a7, a7, 4
; RV32-NEXT: add a7, sp, a7 ; RV32-NEXT: add a7, sp, a7
; RV32-NEXT: addi a7, a7, 16 ; RV32-NEXT: addi a7, a7, 16
; RV32-NEXT: vl8r.v v24, (a7) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a7) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v16, v0.t ; RV32-NEXT: vor.vv v24, v16, v24, v0.t
; RV32-NEXT: csrr a7, vlenb ; RV32-NEXT: csrr a7, vlenb
; RV32-NEXT: slli a7, a7, 4 ; RV32-NEXT: slli a7, a7, 4
; RV32-NEXT: add a7, sp, a7 ; RV32-NEXT: add a7, sp, a7
; RV32-NEXT: addi a7, a7, 16 ; RV32-NEXT: addi a7, a7, 16
; RV32-NEXT: vs8r.v v24, (a7) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a7) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vx v24, v8, a3, v0.t ; RV32-NEXT: vsll.vx v16, v8, a3, v0.t
; RV32-NEXT: vand.vx v24, v8, a5, v0.t
; RV32-NEXT: vsll.vx v24, v24, a4, v0.t
; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: vand.vx v24, v8, a6, v0.t
; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3 ; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vx v24, v8, a5, v0.t
; RV32-NEXT: vand.vx v16, v24, a4, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3 ; RV32-NEXT: li a4, 24
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v16, v24, v0.t ; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3 ; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
; RV32-NEXT: addi a3, sp, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v24, v16, v24, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV32-NEXT: vand.vx v8, v8, a6, v0.t
; RV32-NEXT: vor.vv v8, v24, v8, v0.t ; RV32-NEXT: vor.vv v8, v24, v8, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v24, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v24, v8, v0.t ; RV32-NEXT: vor.vv v24, v8, v24, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: vsrl.vi v16, v24, 4, v0.t
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v8, v8, 4, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: lui a3, 61681 ; RV32-NEXT: lui a3, 61681
; RV32-NEXT: addi a3, a3, -241 ; RV32-NEXT: addi a3, a3, -241
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a3 ; RV32-NEXT: vmv.v.x v8, a3
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v24, v24, v8, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v24, v8, v0.t ; RV32-NEXT: vand.vv v8, v24, v8, v0.t
; RV32-NEXT: vsll.vi v8, v8, 4, v0.t ; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: vor.vv v24, v16, v8, v0.t
; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: vsrl.vi v16, v24, 2, v0.t
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v24, v8, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: lui a3, 209715 ; RV32-NEXT: lui a3, 209715
; RV32-NEXT: addi a3, a3, 819 ; RV32-NEXT: addi a3, a3, 819
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a3 ; RV32-NEXT: vmv.v.x v8, a3
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v24, v24, v8, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v24, v8, v0.t ; RV32-NEXT: vand.vv v8, v24, v8, v0.t
; RV32-NEXT: vsll.vi v8, v8, 2, v0.t ; RV32-NEXT: vsll.vi v8, v8, 2, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: vor.vv v24, v16, v8, v0.t
; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: vsrl.vi v16, v24, 1, v0.t
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v24, v8, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a2 ; RV32-NEXT: vmv.v.x v8, a2
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v24, v24, v8, v0.t
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v24, v8, v0.t ; RV32-NEXT: vand.vv v8, v24, v8, v0.t
; RV32-NEXT: vsll.vi v8, v8, 1, v0.t ; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8, v0.t ; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 24 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bitreverse_v15i64: ; RV64-LABEL: vp_bitreverse_v15i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
; RV32-LABEL: vp_bitreverse_v15i64_unmasked: ; RV32-LABEL: vp_bitreverse_v15i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: vand.vx v24, v8, a2
; RV32-NEXT: li a3, 40
; RV32-NEXT: vsll.vx v24, v24, a3
; RV32-NEXT: vor.vv v16, v16, v24
; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v16, v8, a4
; RV32-NEXT: vsll.vi v24, v16, 24
; RV32-NEXT: li a5, 32
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: lui a2, 349525 ; RV32-NEXT: lui a6, 349525
; RV32-NEXT: addi a2, a2, 1365 ; RV32-NEXT: addi a6, a6, 1365
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: vmv.v.x v0, a2 ; RV32-NEXT: lui a7, 1044480
; RV32-NEXT: lui a3, 1044480 ; RV32-NEXT: vmv.v.x v0, a6
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: vmerge.vxm v16, v16, a3, v0 ; RV32-NEXT: vmerge.vxm v16, v16, a7, v0
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v24, v8, 8 ; RV32-NEXT: vand.vv v0, v8, v16
; RV32-NEXT: vand.vv v24, v24, v16 ; RV32-NEXT: vsll.vi v0, v0, 8
; RV32-NEXT: vsrl.vi v0, v8, 24
; RV32-NEXT: lui a3, 4080
; RV32-NEXT: vand.vx v0, v0, a3
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: li a4, 56
; RV32-NEXT: li a5, 40
; RV32-NEXT: vsrl.vx v0, v8, a5
; RV32-NEXT: lui a6, 16
; RV32-NEXT: addi a6, a6, -256
; RV32-NEXT: vand.vx v0, v0, a6
; RV32-NEXT: vsrl.vx v24, v8, a4
; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: addi a7, sp, 16 ; RV32-NEXT: addi a7, sp, 16
; RV32-NEXT: vl8r.v v0, (a7) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v0, (a7) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v0, v24 ; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: vand.vv v16, v8, v16 ; RV32-NEXT: vs8r.v v24, (a7) # Unknown-size Folded Spill
; RV32-NEXT: vsll.vi v16, v16, 8 ; RV32-NEXT: vsrl.vx v0, v8, a3
; RV32-NEXT: vand.vx v0, v8, a3 ; RV32-NEXT: vand.vx v0, v0, a2
; RV32-NEXT: vsll.vi v0, v0, 24 ; RV32-NEXT: vsrl.vx v24, v8, a1
; RV32-NEXT: vor.vv v16, v0, v16 ; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: vsll.vx v0, v8, a4 ; RV32-NEXT: vsrl.vi v0, v8, 8
; RV32-NEXT: vand.vx v8, v8, a6 ; RV32-NEXT: vand.vv v16, v0, v16
; RV32-NEXT: vsll.vx v8, v8, a5 ; RV32-NEXT: vsrl.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v0, v8 ; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v8, v24 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 4 ; RV32-NEXT: vsrl.vi v16, v8, 4
; RV32-NEXT: lui a3, 61681 ; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a3, a3, -241 ; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a3 ; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vsll.vi v8, v8, 4 ; RV32-NEXT: vsll.vi v8, v8, 4
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 2 ; RV32-NEXT: vsrl.vi v16, v8, 2
; RV32-NEXT: lui a3, 209715 ; RV32-NEXT: lui a1, 209715
; RV32-NEXT: addi a3, a3, 819 ; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a3 ; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vsll.vi v8, v8, 2 ; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 1 ; RV32-NEXT: vsrl.vi v16, v8, 1
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a2 ; RV32-NEXT: vmv.v.x v24, a6
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vadd.vv v8, v8, v8 ; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
declare <16 x i64> @llvm.vp.bitreverse.v16i64(<16 x i64>, <16 x i1>, i32) declare <16 x i64> @llvm.vp.bitreverse.v16i64(<16 x i64>, <16 x i1>, i32)
define <16 x i64> @vp_bitreverse_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @vp_bitreverse_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_bitreverse_v16i64: ; RV32-LABEL: vp_bitreverse_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a2, 24 ; RV32-NEXT: slli a1, a1, 5
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
; RV32-NEXT: vmv1r.v v1, v0 ; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: li a3, 56 ; RV32-NEXT: li a3, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsll.vx v24, v8, a3, v0.t ; RV32-NEXT: vsrl.vx v16, v8, a3, v0.t
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: li a4, 40
; RV32-NEXT: slli a1, a1, 4 ; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV32-NEXT: lui a1, 16 ; RV32-NEXT: lui a1, 16
; RV32-NEXT: addi a4, a1, -256 ; RV32-NEXT: addi a5, a1, -256
; RV32-NEXT: vand.vx v24, v8, a4, v0.t ; RV32-NEXT: vand.vx v24, v24, a5, v0.t
; RV32-NEXT: li a5, 40
; RV32-NEXT: vsll.vx v24, v24, a5, v0.t
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v16, v0.t ; RV32-NEXT: vor.vv v24, v24, v16, v0.t
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 4 ; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
; RV32-NEXT: lui a6, 4080 ; RV32-NEXT: lui a6, 4080
; RV32-NEXT: vand.vx v24, v8, a6, v0.t ; RV32-NEXT: vand.vx v24, v24, a6, v0.t
; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
; RV32-NEXT: addi a2, sp, 16
; RV32-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: lui a2, 349525 ; RV32-NEXT: lui a2, 349525
; RV32-NEXT: addi a2, a2, 1365 ; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: vmv.v.i v24, 0 ; RV32-NEXT: vmv.v.i v24, 0
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: lui a7, 1044480 ; RV32-NEXT: lui a7, 1044480
; RV32-NEXT: vmv.v.x v0, a2 ; RV32-NEXT: vmv.v.x v0, a2
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vmerge.vxm v24, v24, a7, v0 ; RV32-NEXT: vmerge.vxm v16, v24, a7, v0
; RV32-NEXT: addi a7, sp, 16 ; RV32-NEXT: csrr a7, vlenb
; RV32-NEXT: vs8r.v v24, (a7) # Unknown-size Folded Spill ; RV32-NEXT: li t0, 24
; RV32-NEXT: mul a7, a7, t0
; RV32-NEXT: add a7, sp, a7
; RV32-NEXT: addi a7, a7, 16
; RV32-NEXT: vs8r.v v16, (a7) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: vand.vv v16, v8, v24, v0.t ; RV32-NEXT: addi a7, sp, 16
; RV32-NEXT: vsll.vi v16, v16, 8, v0.t ; RV32-NEXT: vl8r.v v24, (a7) # Unknown-size Folded Reload
; RV32-NEXT: csrr a7, vlenb
; RV32-NEXT: li t0, 24
; RV32-NEXT: mul a7, a7, t0
; RV32-NEXT: add a7, sp, a7
; RV32-NEXT: addi a7, a7, 16
; RV32-NEXT: vl8r.v v16, (a7) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: csrr a7, vlenb ; RV32-NEXT: csrr a7, vlenb
; RV32-NEXT: slli a7, a7, 3 ; RV32-NEXT: slli a7, a7, 3
; RV32-NEXT: add a7, sp, a7 ; RV32-NEXT: add a7, sp, a7
; RV32-NEXT: addi a7, a7, 16 ; RV32-NEXT: addi a7, a7, 16
; RV32-NEXT: vl8r.v v24, (a7) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a7) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: csrr a7, vlenb ; RV32-NEXT: csrr a7, vlenb
; RV32-NEXT: slli a7, a7, 4 ; RV32-NEXT: slli a7, a7, 4
; RV32-NEXT: add a7, sp, a7 ; RV32-NEXT: add a7, sp, a7
; RV32-NEXT: addi a7, a7, 16 ; RV32-NEXT: addi a7, a7, 16
; RV32-NEXT: vl8r.v v24, (a7) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a7) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v16, v0.t ; RV32-NEXT: vor.vv v24, v16, v24, v0.t
; RV32-NEXT: csrr a7, vlenb ; RV32-NEXT: csrr a7, vlenb
; RV32-NEXT: slli a7, a7, 4 ; RV32-NEXT: slli a7, a7, 4
; RV32-NEXT: add a7, sp, a7 ; RV32-NEXT: add a7, sp, a7
; RV32-NEXT: addi a7, a7, 16 ; RV32-NEXT: addi a7, a7, 16
; RV32-NEXT: vs8r.v v24, (a7) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a7) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vx v24, v8, a3, v0.t ; RV32-NEXT: vsll.vx v16, v8, a3, v0.t
; RV32-NEXT: vand.vx v24, v8, a5, v0.t
; RV32-NEXT: vsll.vx v24, v24, a4, v0.t
; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: vand.vx v24, v8, a6, v0.t
; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3 ; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vx v24, v8, a5, v0.t
; RV32-NEXT: vand.vx v16, v24, a4, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3 ; RV32-NEXT: li a4, 24
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v16, v24, v0.t ; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3 ; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
; RV32-NEXT: addi a3, sp, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v24, v16, v24, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV32-NEXT: vand.vx v8, v8, a6, v0.t
; RV32-NEXT: vor.vv v8, v24, v8, v0.t ; RV32-NEXT: vor.vv v8, v24, v8, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v24, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v24, v8, v0.t ; RV32-NEXT: vor.vv v24, v8, v24, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: vsrl.vi v16, v24, 4, v0.t
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v8, v8, 4, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: lui a3, 61681 ; RV32-NEXT: lui a3, 61681
; RV32-NEXT: addi a3, a3, -241 ; RV32-NEXT: addi a3, a3, -241
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a3 ; RV32-NEXT: vmv.v.x v8, a3
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v24, v24, v8, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v24, v8, v0.t ; RV32-NEXT: vand.vv v8, v24, v8, v0.t
; RV32-NEXT: vsll.vi v8, v8, 4, v0.t ; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: vor.vv v24, v16, v8, v0.t
; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: vsrl.vi v16, v24, 2, v0.t
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v24, v8, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: lui a3, 209715 ; RV32-NEXT: lui a3, 209715
; RV32-NEXT: addi a3, a3, 819 ; RV32-NEXT: addi a3, a3, 819
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a3 ; RV32-NEXT: vmv.v.x v8, a3
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v24, v24, v8, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v24, v8, v0.t ; RV32-NEXT: vand.vv v8, v24, v8, v0.t
; RV32-NEXT: vsll.vi v8, v8, 2, v0.t ; RV32-NEXT: vsll.vi v8, v8, 2, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: vor.vv v24, v16, v8, v0.t
; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: vsrl.vi v16, v24, 1, v0.t
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v24, v8, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a2 ; RV32-NEXT: vmv.v.x v8, a2
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v24, v24, v8, v0.t
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v24, v8, v0.t ; RV32-NEXT: vand.vv v8, v24, v8, v0.t
; RV32-NEXT: vsll.vi v8, v8, 1, v0.t ; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8, v0.t ; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 24 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bitreverse_v16i64: ; RV64-LABEL: vp_bitreverse_v16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
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; RV32-LABEL: vp_bitreverse_v16i64_unmasked: ; RV32-LABEL: vp_bitreverse_v16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: vand.vx v24, v8, a2
; RV32-NEXT: li a3, 40
; RV32-NEXT: vsll.vx v24, v24, a3
; RV32-NEXT: vor.vv v16, v16, v24
; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v16, v8, a4
; RV32-NEXT: vsll.vi v24, v16, 24
; RV32-NEXT: li a5, 32
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: lui a2, 349525 ; RV32-NEXT: lui a6, 349525
; RV32-NEXT: addi a2, a2, 1365 ; RV32-NEXT: addi a6, a6, 1365
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: vmv.v.x v0, a2 ; RV32-NEXT: lui a7, 1044480
; RV32-NEXT: lui a3, 1044480 ; RV32-NEXT: vmv.v.x v0, a6
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: vmerge.vxm v16, v16, a3, v0 ; RV32-NEXT: vmerge.vxm v16, v16, a7, v0
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v24, v8, 8 ; RV32-NEXT: vand.vv v0, v8, v16
; RV32-NEXT: vand.vv v24, v24, v16 ; RV32-NEXT: vsll.vi v0, v0, 8
; RV32-NEXT: vsrl.vi v0, v8, 24
; RV32-NEXT: lui a3, 4080
; RV32-NEXT: vand.vx v0, v0, a3
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: li a4, 56
; RV32-NEXT: li a5, 40
; RV32-NEXT: vsrl.vx v0, v8, a5
; RV32-NEXT: lui a6, 16
; RV32-NEXT: addi a6, a6, -256
; RV32-NEXT: vand.vx v0, v0, a6
; RV32-NEXT: vsrl.vx v24, v8, a4
; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: addi a7, sp, 16 ; RV32-NEXT: addi a7, sp, 16
; RV32-NEXT: vl8r.v v0, (a7) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v0, (a7) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v0, v24 ; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: vand.vv v16, v8, v16 ; RV32-NEXT: vs8r.v v24, (a7) # Unknown-size Folded Spill
; RV32-NEXT: vsll.vi v16, v16, 8 ; RV32-NEXT: vsrl.vx v0, v8, a3
; RV32-NEXT: vand.vx v0, v8, a3 ; RV32-NEXT: vand.vx v0, v0, a2
; RV32-NEXT: vsll.vi v0, v0, 24 ; RV32-NEXT: vsrl.vx v24, v8, a1
; RV32-NEXT: vor.vv v16, v0, v16 ; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: vsll.vx v0, v8, a4 ; RV32-NEXT: vsrl.vi v0, v8, 8
; RV32-NEXT: vand.vx v8, v8, a6 ; RV32-NEXT: vand.vv v16, v0, v16
; RV32-NEXT: vsll.vx v8, v8, a5 ; RV32-NEXT: vsrl.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v0, v8 ; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v8, v24 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 4 ; RV32-NEXT: vsrl.vi v16, v8, 4
; RV32-NEXT: lui a3, 61681 ; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a3, a3, -241 ; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a3 ; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vsll.vi v8, v8, 4 ; RV32-NEXT: vsll.vi v8, v8, 4
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 2 ; RV32-NEXT: vsrl.vi v16, v8, 2
; RV32-NEXT: lui a3, 209715 ; RV32-NEXT: lui a1, 209715
; RV32-NEXT: addi a3, a3, 819 ; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a3 ; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vsll.vi v8, v8, 2 ; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 1 ; RV32-NEXT: vsrl.vi v16, v8, 1
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a2 ; RV32-NEXT: vmv.v.x v24, a6
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vadd.vv v8, v8, v8 ; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
▲ Show 20 Lines • Show All 365 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll

Show First 20 Lines • Show All 159 Lines • ▼ Show 20 Lines
} }
declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>) declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>)
define void @bitreverse_v2i64(ptr %x, ptr %y) { define void @bitreverse_v2i64(ptr %x, ptr %y) {
; RV32-LABEL: bitreverse_v2i64: ; RV32-LABEL: bitreverse_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.i v9, 0 ; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: lui a1, 1044480
; RV32-NEXT: vmerge.vxm v9, v9, a1, v0 ; RV32-NEXT: vmerge.vxm v9, v9, a1, v0
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vsrl.vi v10, v8, 8 ; RV32-NEXT: vsrl.vi v10, v8, 8
; RV32-NEXT: vand.vv v10, v10, v9 ; RV32-NEXT: vand.vv v10, v10, v9
; RV32-NEXT: vsrl.vi v11, v8, 24 ; RV32-NEXT: vsrl.vi v11, v8, 24
; RV32-NEXT: lui a1, 4080 ; RV32-NEXT: lui a1, 4080
; RV32-NEXT: vand.vx v11, v11, a1 ; RV32-NEXT: vand.vx v11, v11, a1
▲ Show 20 Lines • Show All 512 Lines • ▼ Show 20 Lines
} }
declare <8 x i32> @llvm.bitreverse.v8i32(<8 x i32>) declare <8 x i32> @llvm.bitreverse.v8i32(<8 x i32>)
define void @bitreverse_v4i64(ptr %x, ptr %y) { define void @bitreverse_v4i64(ptr %x, ptr %y) {
; LMULMAX2-RV32-LABEL: bitreverse_v4i64: ; LMULMAX2-RV32-LABEL: bitreverse_v4i64:
; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32-NEXT: li a1, 85 ; LMULMAX2-RV32-NEXT: li a1, 56
; LMULMAX2-RV32-NEXT: vsrl.vx v10, v8, a1
; LMULMAX2-RV32-NEXT: li a2, 40
; LMULMAX2-RV32-NEXT: vsrl.vx v12, v8, a2
; LMULMAX2-RV32-NEXT: lui a3, 16
; LMULMAX2-RV32-NEXT: addi a3, a3, -256
; LMULMAX2-RV32-NEXT: vand.vx v12, v12, a3
; LMULMAX2-RV32-NEXT: vor.vv v10, v12, v10
; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 24
; LMULMAX2-RV32-NEXT: lui a4, 4080
; LMULMAX2-RV32-NEXT: vand.vx v12, v12, a4
; LMULMAX2-RV32-NEXT: li a5, 85
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v0, a1 ; LMULMAX2-RV32-NEXT: vmv.v.x v0, a5
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.i v10, 0 ; LMULMAX2-RV32-NEXT: vmv.v.i v14, 0
; LMULMAX2-RV32-NEXT: lui a1, 1044480 ; LMULMAX2-RV32-NEXT: lui a5, 1044480
; LMULMAX2-RV32-NEXT: vmerge.vxm v10, v10, a1, v0 ; LMULMAX2-RV32-NEXT: vmerge.vxm v14, v14, a5, v0
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 8 ; LMULMAX2-RV32-NEXT: vsrl.vi v16, v8, 8
; LMULMAX2-RV32-NEXT: vand.vv v12, v12, v10 ; LMULMAX2-RV32-NEXT: vand.vv v16, v16, v14
; LMULMAX2-RV32-NEXT: vsrl.vi v14, v8, 24 ; LMULMAX2-RV32-NEXT: vor.vv v12, v16, v12
; LMULMAX2-RV32-NEXT: lui a1, 4080 ; LMULMAX2-RV32-NEXT: vor.vv v10, v12, v10
; LMULMAX2-RV32-NEXT: vand.vx v14, v14, a1 ; LMULMAX2-RV32-NEXT: vsll.vx v12, v8, a1
; LMULMAX2-RV32-NEXT: vor.vv v12, v12, v14 ; LMULMAX2-RV32-NEXT: vand.vx v16, v8, a3
; LMULMAX2-RV32-NEXT: li a2, 56 ; LMULMAX2-RV32-NEXT: vsll.vx v16, v16, a2
; LMULMAX2-RV32-NEXT: vsrl.vx v14, v8, a2 ; LMULMAX2-RV32-NEXT: vor.vv v12, v12, v16
; LMULMAX2-RV32-NEXT: li a3, 40 ; LMULMAX2-RV32-NEXT: vand.vx v16, v8, a4
; LMULMAX2-RV32-NEXT: vsrl.vx v16, v8, a3 ; LMULMAX2-RV32-NEXT: vsll.vi v16, v16, 24
; LMULMAX2-RV32-NEXT: lui a4, 16 ; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v14
; LMULMAX2-RV32-NEXT: addi a4, a4, -256 ; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 8
; LMULMAX2-RV32-NEXT: vand.vx v16, v16, a4 ; LMULMAX2-RV32-NEXT: vor.vv v8, v16, v8
; LMULMAX2-RV32-NEXT: vor.vv v14, v16, v14 ; LMULMAX2-RV32-NEXT: vor.vv v8, v12, v8
; LMULMAX2-RV32-NEXT: vor.vv v12, v12, v14
; LMULMAX2-RV32-NEXT: vand.vv v10, v8, v10
; LMULMAX2-RV32-NEXT: vsll.vi v10, v10, 8
; LMULMAX2-RV32-NEXT: vand.vx v14, v8, a1
; LMULMAX2-RV32-NEXT: vsll.vi v14, v14, 24
; LMULMAX2-RV32-NEXT: vor.vv v10, v14, v10
; LMULMAX2-RV32-NEXT: vsll.vx v14, v8, a2
; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a4
; LMULMAX2-RV32-NEXT: vsll.vx v8, v8, a3
; LMULMAX2-RV32-NEXT: vor.vv v8, v14, v8
; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v12
; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 4
; LMULMAX2-RV32-NEXT: lui a1, 61681 ; LMULMAX2-RV32-NEXT: lui a1, 61681
; LMULMAX2-RV32-NEXT: addi a1, a1, -241 ; LMULMAX2-RV32-NEXT: addi a1, a1, -241
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v12, a1 ; LMULMAX2-RV32-NEXT: vmv.v.x v12, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32-NEXT: vand.vv v10, v10, v12 ; LMULMAX2-RV32-NEXT: vand.vv v10, v10, v12
; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v12 ; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v12
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; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: bitreverse_v4i64: ; LMULMAX1-RV32-LABEL: bitreverse_v4i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a1, a0, 16 ; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle64.v v10, (a1) ; LMULMAX1-RV32-NEXT: vle64.v v10, (a1)
; LMULMAX1-RV32-NEXT: vmv.v.i v0, 5
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.i v9, 0 ; LMULMAX1-RV32-NEXT: vmv.v.i v9, 0
; LMULMAX1-RV32-NEXT: vmv.v.i v0, 5
; LMULMAX1-RV32-NEXT: lui a2, 1044480 ; LMULMAX1-RV32-NEXT: lui a2, 1044480
; LMULMAX1-RV32-NEXT: vmerge.vxm v9, v9, a2, v0 ; LMULMAX1-RV32-NEXT: vmerge.vxm v9, v9, a2, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v10, 8 ; LMULMAX1-RV32-NEXT: vsrl.vi v11, v10, 8
; LMULMAX1-RV32-NEXT: vand.vv v11, v11, v9 ; LMULMAX1-RV32-NEXT: vand.vv v11, v11, v9
; LMULMAX1-RV32-NEXT: vsrl.vi v12, v10, 24 ; LMULMAX1-RV32-NEXT: vsrl.vi v12, v10, 24
; LMULMAX1-RV32-NEXT: lui a2, 4080 ; LMULMAX1-RV32-NEXT: lui a2, 4080
; LMULMAX1-RV32-NEXT: vand.vx v12, v12, a2 ; LMULMAX1-RV32-NEXT: vand.vx v12, v12, a2
▲ Show 20 Lines • Show All 198 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll

Show First 20 Lines • Show All 430 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsrl.vx v10, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v10, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v11, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v11, v8, a2, v0.t
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v11, v11, a3, v0.t ; RV32-NEXT: vand.vx v11, v11, a3, v0.t
; RV32-NEXT: vor.vv v10, v11, v10, v0.t ; RV32-NEXT: vor.vv v10, v11, v10, v0.t
; RV32-NEXT: vsrl.vi v11, v8, 8, v0.t ; RV32-NEXT: vsrl.vi v11, v8, 8, v0.t
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.i v12, 0 ; RV32-NEXT: vmv.v.i v12, 0
; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: lui a4, 1044480 ; RV32-NEXT: lui a4, 1044480
; RV32-NEXT: vmerge.vxm v12, v12, a4, v0 ; RV32-NEXT: vmerge.vxm v12, v12, a4, v0
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vmv1r.v v0, v9 ; RV32-NEXT: vmv1r.v v0, v9
; RV32-NEXT: vand.vv v11, v11, v12, v0.t ; RV32-NEXT: vand.vv v11, v11, v12, v0.t
; RV32-NEXT: vsrl.vi v13, v8, 24, v0.t ; RV32-NEXT: vsrl.vi v13, v8, 24, v0.t
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: lui a0, 4080
; RV32-NEXT: vand.vx v13, v13, a0, v0.t ; RV32-NEXT: vand.vx v13, v13, a0, v0.t
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v9, v8, a1 ; RV32-NEXT: vsrl.vx v9, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v10, v8, a2 ; RV32-NEXT: vsrl.vx v10, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v10, v10, a3 ; RV32-NEXT: vand.vx v10, v10, a3
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v10, v9
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.i v10, 0 ; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: lui a4, 1044480 ; RV32-NEXT: lui a4, 1044480
; RV32-NEXT: vmerge.vxm v10, v10, a4, v0 ; RV32-NEXT: vmerge.vxm v10, v10, a4, v0
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vsrl.vi v11, v8, 8 ; RV32-NEXT: vsrl.vi v11, v8, 8
; RV32-NEXT: vand.vv v11, v11, v10 ; RV32-NEXT: vand.vv v11, v11, v10
; RV32-NEXT: vsrl.vi v12, v8, 24 ; RV32-NEXT: vsrl.vi v12, v8, 24
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: lui a0, 4080
; RV32-NEXT: vand.vx v12, v12, a0 ; RV32-NEXT: vand.vx v12, v12, a0
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsrl.vx v12, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v12, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v14, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v14, v8, a2, v0.t
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v14, v14, a3, v0.t ; RV32-NEXT: vand.vx v14, v14, a3, v0.t
; RV32-NEXT: vor.vv v12, v14, v12, v0.t ; RV32-NEXT: vor.vv v12, v14, v12, v0.t
; RV32-NEXT: vsrl.vi v14, v8, 8, v0.t ; RV32-NEXT: vsrl.vi v14, v8, 24, v0.t
; RV32-NEXT: li a4, 85 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v14, v14, a4, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
; RV32-NEXT: li a5, 85
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.x v0, a4 ; RV32-NEXT: vmv.v.x v0, a5
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v18, 0
; RV32-NEXT: lui a4, 1044480 ; RV32-NEXT: lui a5, 1044480
; RV32-NEXT: vmerge.vxm v16, v16, a4, v0 ; RV32-NEXT: vmerge.vxm v18, v18, a5, v0
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vmv1r.v v0, v10 ; RV32-NEXT: vmv1r.v v0, v10
; RV32-NEXT: vand.vv v14, v14, v16, v0.t ; RV32-NEXT: vand.vv v16, v16, v18, v0.t
; RV32-NEXT: vsrl.vi v18, v8, 24, v0.t ; RV32-NEXT: vor.vv v14, v16, v14, v0.t
; RV32-NEXT: lui a0, 4080
; RV32-NEXT: vand.vx v18, v18, a0, v0.t
; RV32-NEXT: vor.vv v14, v14, v18, v0.t
; RV32-NEXT: vor.vv v12, v14, v12, v0.t ; RV32-NEXT: vor.vv v12, v14, v12, v0.t
; RV32-NEXT: vsll.vx v14, v8, a1, v0.t ; RV32-NEXT: vsll.vx v14, v8, a1, v0.t
; RV32-NEXT: vand.vx v18, v8, a3, v0.t ; RV32-NEXT: vand.vx v16, v8, a3, v0.t
; RV32-NEXT: vsll.vx v18, v18, a2, v0.t ; RV32-NEXT: vsll.vx v16, v16, a2, v0.t
; RV32-NEXT: vor.vv v14, v14, v18, v0.t ; RV32-NEXT: vor.vv v14, v14, v16, v0.t
; RV32-NEXT: vand.vx v18, v8, a0, v0.t ; RV32-NEXT: vand.vx v16, v8, a4, v0.t
; RV32-NEXT: vsll.vi v18, v18, 24, v0.t ; RV32-NEXT: vsll.vi v16, v16, 24, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vv v8, v8, v18, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t ; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
; RV32-NEXT: vor.vv v8, v18, v8, v0.t ; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: vor.vv v8, v14, v8, v0.t ; RV32-NEXT: vor.vv v8, v14, v8, v0.t
; RV32-NEXT: vor.vv v8, v8, v12, v0.t ; RV32-NEXT: vor.vv v8, v8, v12, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_v4i64: ; RV64-LABEL: vp_bswap_v4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
Show All 36 Lines
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsrl.vx v10, v8, a1 ; RV32-NEXT: vsrl.vx v10, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v12, v8, a2 ; RV32-NEXT: vsrl.vx v12, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v12, v12, a3 ; RV32-NEXT: vand.vx v12, v12, a3
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vsrl.vi v12, v8, 8
; RV32-NEXT: li a4, 85 ; RV32-NEXT: li a4, 85
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.x v0, a4 ; RV32-NEXT: vmv.v.x v0, a4
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.i v12, 0 ; RV32-NEXT: vmv.v.i v14, 0
; RV32-NEXT: lui a4, 1044480 ; RV32-NEXT: lui a4, 1044480
; RV32-NEXT: vmerge.vxm v12, v12, a4, v0 ; RV32-NEXT: vmerge.vxm v14, v14, a4, v0
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsrl.vi v14, v8, 8 ; RV32-NEXT: vand.vv v12, v12, v14
; RV32-NEXT: vand.vv v14, v14, v12
; RV32-NEXT: vsrl.vi v16, v8, 24 ; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: lui a0, 4080
; RV32-NEXT: vand.vx v16, v16, a0 ; RV32-NEXT: vand.vx v16, v16, a0
; RV32-NEXT: vor.vv v14, v14, v16 ; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vor.vv v10, v14, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vsll.vx v14, v8, a1 ; RV32-NEXT: vsll.vx v12, v8, a1
; RV32-NEXT: vand.vx v16, v8, a3 ; RV32-NEXT: vand.vx v16, v8, a3
; RV32-NEXT: vsll.vx v16, v16, a2 ; RV32-NEXT: vsll.vx v16, v16, a2
; RV32-NEXT: vor.vv v14, v14, v16 ; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vand.vv v12, v8, v12 ; RV32-NEXT: vand.vx v16, v8, a0
; RV32-NEXT: vsll.vi v12, v12, 8 ; RV32-NEXT: vsll.vi v16, v16, 24
; RV32-NEXT: vand.vx v8, v8, a0 ; RV32-NEXT: vand.vv v8, v8, v14
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v14, v8 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_v4i64_unmasked: ; RV64-LABEL: vp_bswap_v4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV64-NEXT: vand.vx v10, v8, a1 ; RV64-NEXT: vand.vx v10, v8, a1
Show All 39 Lines
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v20, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v20, v8, a2, v0.t
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v20, v20, a3, v0.t ; RV32-NEXT: vand.vx v20, v20, a3, v0.t
; RV32-NEXT: vor.vv v20, v20, v16, v0.t ; RV32-NEXT: vor.vv v16, v20, v16, v0.t
; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t ; RV32-NEXT: vsrl.vi v20, v8, 24, v0.t
; RV32-NEXT: lui a4, 5 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: addi a4, a4, 1365 ; RV32-NEXT: vand.vx v24, v20, a4, v0.t
; RV32-NEXT: vsrl.vi v28, v8, 8, v0.t
; RV32-NEXT: lui a5, 5
; RV32-NEXT: addi a5, a5, 1365
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a4 ; RV32-NEXT: vmv.v.x v0, a5
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v20, 0
; RV32-NEXT: lui a4, 1044480 ; RV32-NEXT: lui a5, 1044480
; RV32-NEXT: vmerge.vxm v16, v16, a4, v0 ; RV32-NEXT: vmerge.vxm v20, v20, a5, v0
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: vand.vv v24, v24, v16, v0.t ; RV32-NEXT: vand.vv v28, v28, v20, v0.t
; RV32-NEXT: vsrl.vi v28, v8, 24, v0.t ; RV32-NEXT: vor.vv v24, v28, v24, v0.t
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: vor.vv v16, v24, v16, v0.t
; RV32-NEXT: vand.vx v28, v28, a0, v0.t
; RV32-NEXT: vor.vv v24, v24, v28, v0.t
; RV32-NEXT: vor.vv v20, v24, v20, v0.t
; RV32-NEXT: vsll.vx v24, v8, a1, v0.t ; RV32-NEXT: vsll.vx v24, v8, a1, v0.t
; RV32-NEXT: vand.vx v28, v8, a3, v0.t ; RV32-NEXT: vand.vx v28, v8, a3, v0.t
; RV32-NEXT: vsll.vx v28, v28, a2, v0.t ; RV32-NEXT: vsll.vx v28, v28, a2, v0.t
; RV32-NEXT: vor.vv v24, v24, v28, v0.t ; RV32-NEXT: vor.vv v24, v24, v28, v0.t
; RV32-NEXT: vand.vx v28, v8, a0, v0.t ; RV32-NEXT: vand.vx v28, v8, a4, v0.t
; RV32-NEXT: vsll.vi v28, v28, 24, v0.t ; RV32-NEXT: vsll.vi v28, v28, 24, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vv v8, v8, v20, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t ; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
; RV32-NEXT: vor.vv v8, v28, v8, v0.t ; RV32-NEXT: vor.vv v8, v28, v8, v0.t
; RV32-NEXT: vor.vv v8, v24, v8, v0.t ; RV32-NEXT: vor.vv v8, v24, v8, v0.t
; RV32-NEXT: vor.vv v8, v8, v20, v0.t ; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_v8i64: ; RV64-LABEL: vp_bswap_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV64-NEXT: vand.vx v12, v8, a1, v0.t ; RV64-NEXT: vand.vx v12, v8, a1, v0.t
; RV64-NEXT: vsll.vi v12, v12, 24, v0.t ; RV64-NEXT: vsll.vi v12, v12, 24, v0.t
Show All 34 Lines
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsrl.vx v12, v8, a1 ; RV32-NEXT: vsrl.vx v12, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v16, v8, a2 ; RV32-NEXT: vsrl.vx v16, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v16, v16, a3 ; RV32-NEXT: vand.vx v16, v16, a3
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vsrl.vi v20, v8, 8
; RV32-NEXT: lui a4, 5 ; RV32-NEXT: lui a4, 5
; RV32-NEXT: addi a4, a4, 1365 ; RV32-NEXT: addi a4, a4, 1365
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a4 ; RV32-NEXT: vmv.v.x v0, a4
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: lui a4, 1044480 ; RV32-NEXT: lui a4, 1044480
; RV32-NEXT: vmerge.vxm v16, v16, a4, v0 ; RV32-NEXT: vmerge.vxm v16, v16, a4, v0
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsrl.vi v20, v8, 8
; RV32-NEXT: vand.vv v20, v20, v16 ; RV32-NEXT: vand.vv v20, v20, v16
; RV32-NEXT: vsrl.vi v24, v8, 24 ; RV32-NEXT: vsrl.vi v24, v8, 24
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: lui a0, 4080
; RV32-NEXT: vand.vx v24, v24, a0 ; RV32-NEXT: vand.vx v24, v24, a0
; RV32-NEXT: vor.vv v20, v20, v24 ; RV32-NEXT: vor.vv v20, v20, v24
; RV32-NEXT: vor.vv v12, v20, v12 ; RV32-NEXT: vor.vv v12, v20, v12
; RV32-NEXT: vsll.vx v20, v8, a1 ; RV32-NEXT: vsll.vx v20, v8, a1
; RV32-NEXT: vand.vx v24, v8, a3 ; RV32-NEXT: vand.vx v24, v8, a3
; RV32-NEXT: vsll.vx v24, v24, a2 ; RV32-NEXT: vsll.vx v24, v24, a2
; RV32-NEXT: vor.vv v20, v20, v24 ; RV32-NEXT: vor.vv v20, v20, v24
; RV32-NEXT: vand.vv v16, v8, v16 ; RV32-NEXT: vand.vx v24, v8, a0
; RV32-NEXT: vsll.vi v16, v16, 8 ; RV32-NEXT: vsll.vi v24, v24, 24
; RV32-NEXT: vand.vx v8, v8, a0 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: vor.vv v8, v20, v8 ; RV32-NEXT: vor.vv v8, v20, v8
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_v8i64_unmasked: ; RV64-LABEL: vp_bswap_v8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
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declare <15 x i64> @llvm.vp.bswap.v15i64(<15 x i64>, <15 x i1>, i32) declare <15 x i64> @llvm.vp.bswap.v15i64(<15 x i64>, <15 x i1>, i32)
define <15 x i64> @vp_bswap_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) { define <15 x i64> @vp_bswap_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_bswap_v15i64: ; RV32-LABEL: vp_bswap_v15i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a2, 24 ; RV32-NEXT: slli a1, a1, 5
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
; RV32-NEXT: vmv1r.v v1, v0 ; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsll.vx v24, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: li a2, 40
; RV32-NEXT: slli a2, a2, 4 ; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t
; RV32-NEXT: add a2, sp, a2 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a2, a2, 16 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill ; RV32-NEXT: vand.vx v24, v24, a3, v0.t
; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: vand.vx v24, v8, a2, v0.t
; RV32-NEXT: li a3, 40
; RV32-NEXT: vsll.vx v24, v24, a3, v0.t
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 3
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v24, (a4) # Unknown-size Folded Reload
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 3
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v16, v0.t ; RV32-NEXT: vor.vv v24, v24, v16, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 4 ; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v24, v8, a4, v0.t ; RV32-NEXT: vand.vx v24, v24, a4, v0.t
; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
; RV32-NEXT: csrr a5, vlenb ; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: slli a5, a5, 3 ; RV32-NEXT: slli a5, a5, 3
; RV32-NEXT: add a5, sp, a5 ; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16 ; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vs8r.v v24, (a5) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a5) # Unknown-size Folded Spill
; RV32-NEXT: li a5, 32 ; RV32-NEXT: li a5, 32
; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
; RV32-NEXT: addi a6, sp, 16
; RV32-NEXT: vs8r.v v24, (a6) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: lui a6, 349525 ; RV32-NEXT: lui a6, 349525
; RV32-NEXT: addi a6, a6, 1365 ; RV32-NEXT: addi a6, a6, 1365
; RV32-NEXT: vmv.v.i v24, 0 ; RV32-NEXT: vmv.v.i v24, 0
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: lui a7, 1044480 ; RV32-NEXT: lui a7, 1044480
; RV32-NEXT: vmv.v.x v0, a6 ; RV32-NEXT: vmv.v.x v0, a6
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: vmerge.vxm v24, v24, a7, v0 ; RV32-NEXT: vmerge.vxm v16, v24, a7, v0
; RV32-NEXT: addi a5, sp, 16 ; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: vs8r.v v24, (a5) # Unknown-size Folded Spill ; RV32-NEXT: li a6, 24
; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: vand.vv v16, v8, v24, v0.t ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vsll.vi v16, v16, 8, v0.t ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a5, 24
; RV32-NEXT: mul a0, a0, a5
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v16, v0.t ; RV32-NEXT: vor.vv v24, v16, v24, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vx v24, v8, a1, v0.t ; RV32-NEXT: vsll.vx v16, v8, a1, v0.t
; RV32-NEXT: vand.vx v24, v8, a3, v0.t
; RV32-NEXT: vsll.vx v24, v24, a2, v0.t
; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: vand.vx v24, v8, a4, v0.t
; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vx v24, v8, a3, v0.t
; RV32-NEXT: vand.vx v16, v24, a2, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: li a1, 24
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v16, v24, v0.t ; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v24, v16, v24, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV32-NEXT: vand.vx v8, v8, a4, v0.t
; RV32-NEXT: vor.vv v8, v24, v8, v0.t ; RV32-NEXT: vor.vv v8, v24, v8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v24, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8, v0.t ; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 24 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_v15i64: ; RV64-LABEL: vp_bswap_v15i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; RV32-LABEL: vp_bswap_v15i64_unmasked: ; RV32-LABEL: vp_bswap_v15i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: vand.vx v24, v8, a2
; RV32-NEXT: li a3, 40
; RV32-NEXT: vsll.vx v24, v24, a3
; RV32-NEXT: vor.vv v16, v16, v24
; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v16, v8, a4
; RV32-NEXT: vsll.vi v24, v16, 24
; RV32-NEXT: li a5, 32
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: lui a2, 349525 ; RV32-NEXT: lui a6, 349525
; RV32-NEXT: addi a2, a2, 1365 ; RV32-NEXT: addi a6, a6, 1365
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: vmv.v.x v0, a2 ; RV32-NEXT: lui a7, 1044480
; RV32-NEXT: lui a2, 1044480 ; RV32-NEXT: vmv.v.x v0, a6
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: vmerge.vxm v16, v16, a2, v0 ; RV32-NEXT: vmerge.vxm v16, v16, a7, v0
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v24, v8, 8 ; RV32-NEXT: vand.vv v0, v8, v16
; RV32-NEXT: vand.vv v24, v24, v16 ; RV32-NEXT: vsll.vi v0, v0, 8
; RV32-NEXT: vsrl.vi v0, v8, 24
; RV32-NEXT: lui a0, 4080
; RV32-NEXT: vand.vx v0, v0, a0
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: addi a1, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill ; RV32-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload
; RV32-NEXT: li a1, 56
; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v0, v8, a2
; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v0, v0, a3
; RV32-NEXT: vsrl.vx v24, v8, a1
; RV32-NEXT: vor.vv v24, v0, v24 ; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vl8r.v v0, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vsrl.vx v0, v8, a3
; RV32-NEXT: vand.vx v0, v0, a2
; RV32-NEXT: vsrl.vx v24, v8, a1
; RV32-NEXT: vor.vv v24, v0, v24 ; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: vand.vv v16, v8, v16 ; RV32-NEXT: vsrl.vi v0, v8, 8
; RV32-NEXT: vsll.vi v16, v16, 8 ; RV32-NEXT: vand.vv v16, v0, v16
; RV32-NEXT: vand.vx v0, v8, a0 ; RV32-NEXT: vsrl.vi v8, v8, 24
; RV32-NEXT: vsll.vi v0, v0, 24 ; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vor.vv v16, v0, v16 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vsll.vx v0, v8, a1
; RV32-NEXT: vand.vx v8, v8, a3
; RV32-NEXT: vsll.vx v8, v8, a2
; RV32-NEXT: vor.vv v8, v0, v8
; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vor.vv v8, v8, v24 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_v15i64_unmasked: ; RV64-LABEL: vp_bswap_v15i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
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declare <16 x i64> @llvm.vp.bswap.v16i64(<16 x i64>, <16 x i1>, i32) declare <16 x i64> @llvm.vp.bswap.v16i64(<16 x i64>, <16 x i1>, i32)
define <16 x i64> @vp_bswap_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @vp_bswap_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_bswap_v16i64: ; RV32-LABEL: vp_bswap_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a2, 24 ; RV32-NEXT: slli a1, a1, 5
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
; RV32-NEXT: vmv1r.v v1, v0 ; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsll.vx v24, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: li a2, 40
; RV32-NEXT: slli a2, a2, 4 ; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t
; RV32-NEXT: add a2, sp, a2 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a2, a2, 16 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill ; RV32-NEXT: vand.vx v24, v24, a3, v0.t
; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: vand.vx v24, v8, a2, v0.t
; RV32-NEXT: li a3, 40
; RV32-NEXT: vsll.vx v24, v24, a3, v0.t
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 3
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v24, (a4) # Unknown-size Folded Reload
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 3
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v16, v0.t ; RV32-NEXT: vor.vv v24, v24, v16, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 4 ; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v24, v8, a4, v0.t ; RV32-NEXT: vand.vx v24, v24, a4, v0.t
; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
; RV32-NEXT: csrr a5, vlenb ; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: slli a5, a5, 3 ; RV32-NEXT: slli a5, a5, 3
; RV32-NEXT: add a5, sp, a5 ; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16 ; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vs8r.v v24, (a5) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a5) # Unknown-size Folded Spill
; RV32-NEXT: li a5, 32 ; RV32-NEXT: li a5, 32
; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
; RV32-NEXT: addi a6, sp, 16
; RV32-NEXT: vs8r.v v24, (a6) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: lui a6, 349525 ; RV32-NEXT: lui a6, 349525
; RV32-NEXT: addi a6, a6, 1365 ; RV32-NEXT: addi a6, a6, 1365
; RV32-NEXT: vmv.v.i v24, 0 ; RV32-NEXT: vmv.v.i v24, 0
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: lui a7, 1044480 ; RV32-NEXT: lui a7, 1044480
; RV32-NEXT: vmv.v.x v0, a6 ; RV32-NEXT: vmv.v.x v0, a6
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: vmerge.vxm v24, v24, a7, v0 ; RV32-NEXT: vmerge.vxm v16, v24, a7, v0
; RV32-NEXT: addi a5, sp, 16 ; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: vs8r.v v24, (a5) # Unknown-size Folded Spill ; RV32-NEXT: li a6, 24
; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: vand.vv v16, v8, v24, v0.t ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vsll.vi v16, v16, 8, v0.t ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a5, 24
; RV32-NEXT: mul a0, a0, a5
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v16, v0.t ; RV32-NEXT: vor.vv v24, v16, v24, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vx v24, v8, a1, v0.t ; RV32-NEXT: vsll.vx v16, v8, a1, v0.t
; RV32-NEXT: vand.vx v24, v8, a3, v0.t
; RV32-NEXT: vsll.vx v24, v24, a2, v0.t
; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: vand.vx v24, v8, a4, v0.t
; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vx v24, v8, a3, v0.t
; RV32-NEXT: vand.vx v16, v24, a2, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: li a1, 24
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v16, v24, v0.t ; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v24, v16, v24, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV32-NEXT: vand.vx v8, v8, a4, v0.t
; RV32-NEXT: vor.vv v8, v24, v8, v0.t ; RV32-NEXT: vor.vv v8, v24, v8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v24, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8, v0.t ; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 24 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_v16i64: ; RV64-LABEL: vp_bswap_v16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
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; RV32-LABEL: vp_bswap_v16i64_unmasked: ; RV32-LABEL: vp_bswap_v16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: vand.vx v24, v8, a2
; RV32-NEXT: li a3, 40
; RV32-NEXT: vsll.vx v24, v24, a3
; RV32-NEXT: vor.vv v16, v16, v24
; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v16, v8, a4
; RV32-NEXT: vsll.vi v24, v16, 24
; RV32-NEXT: li a5, 32
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: lui a2, 349525 ; RV32-NEXT: lui a6, 349525
; RV32-NEXT: addi a2, a2, 1365 ; RV32-NEXT: addi a6, a6, 1365
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: vmv.v.x v0, a2 ; RV32-NEXT: lui a7, 1044480
; RV32-NEXT: lui a2, 1044480 ; RV32-NEXT: vmv.v.x v0, a6
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: vmerge.vxm v16, v16, a2, v0 ; RV32-NEXT: vmerge.vxm v16, v16, a7, v0
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v24, v8, 8 ; RV32-NEXT: vand.vv v0, v8, v16
; RV32-NEXT: vand.vv v24, v24, v16 ; RV32-NEXT: vsll.vi v0, v0, 8
; RV32-NEXT: vsrl.vi v0, v8, 24
; RV32-NEXT: lui a0, 4080
; RV32-NEXT: vand.vx v0, v0, a0
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: addi a1, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill ; RV32-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload
; RV32-NEXT: li a1, 56
; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v0, v8, a2
; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v0, v0, a3
; RV32-NEXT: vsrl.vx v24, v8, a1
; RV32-NEXT: vor.vv v24, v0, v24 ; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vl8r.v v0, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vsrl.vx v0, v8, a3
; RV32-NEXT: vand.vx v0, v0, a2
; RV32-NEXT: vsrl.vx v24, v8, a1
; RV32-NEXT: vor.vv v24, v0, v24 ; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: vand.vv v16, v8, v16 ; RV32-NEXT: vsrl.vi v0, v8, 8
; RV32-NEXT: vsll.vi v16, v16, 8 ; RV32-NEXT: vand.vv v16, v0, v16
; RV32-NEXT: vand.vx v0, v8, a0 ; RV32-NEXT: vsrl.vi v8, v8, 24
; RV32-NEXT: vsll.vi v0, v0, 24 ; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vor.vv v16, v0, v16 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vsll.vx v0, v8, a1
; RV32-NEXT: vand.vx v8, v8, a3
; RV32-NEXT: vsll.vx v8, v8, a2
; RV32-NEXT: vor.vv v8, v0, v8
; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vor.vv v8, v8, v24 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_v16i64_unmasked: ; RV64-LABEL: vp_bswap_v16i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll

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} }
declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)
define void @bswap_v2i64(ptr %x, ptr %y) { define void @bswap_v2i64(ptr %x, ptr %y) {
; RV32-LABEL: bswap_v2i64: ; RV32-LABEL: bswap_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.i v9, 0 ; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: lui a1, 1044480
; RV32-NEXT: vmerge.vxm v9, v9, a1, v0 ; RV32-NEXT: vmerge.vxm v9, v9, a1, v0
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vsrl.vi v10, v8, 8 ; RV32-NEXT: vsrl.vi v10, v8, 8
; RV32-NEXT: vand.vv v10, v10, v9 ; RV32-NEXT: vand.vv v10, v10, v9
; RV32-NEXT: vsrl.vi v11, v8, 24 ; RV32-NEXT: vsrl.vi v11, v8, 24
; RV32-NEXT: lui a1, 4080 ; RV32-NEXT: lui a1, 4080
; RV32-NEXT: vand.vx v11, v11, a1 ; RV32-NEXT: vand.vx v11, v11, a1
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} }
declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>) declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>)
define void @bswap_v4i64(ptr %x, ptr %y) { define void @bswap_v4i64(ptr %x, ptr %y) {
; LMULMAX2-RV32-LABEL: bswap_v4i64: ; LMULMAX2-RV32-LABEL: bswap_v4i64:
; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32-NEXT: li a1, 85 ; LMULMAX2-RV32-NEXT: li a1, 56
; LMULMAX2-RV32-NEXT: vsrl.vx v10, v8, a1
; LMULMAX2-RV32-NEXT: li a2, 40
; LMULMAX2-RV32-NEXT: vsrl.vx v12, v8, a2
; LMULMAX2-RV32-NEXT: lui a3, 16
; LMULMAX2-RV32-NEXT: addi a3, a3, -256
; LMULMAX2-RV32-NEXT: vand.vx v12, v12, a3
; LMULMAX2-RV32-NEXT: vor.vv v10, v12, v10
; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 24
; LMULMAX2-RV32-NEXT: lui a4, 4080
; LMULMAX2-RV32-NEXT: vand.vx v12, v12, a4
; LMULMAX2-RV32-NEXT: li a5, 85
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v0, a1 ; LMULMAX2-RV32-NEXT: vmv.v.x v0, a5
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.i v10, 0 ; LMULMAX2-RV32-NEXT: vmv.v.i v14, 0
; LMULMAX2-RV32-NEXT: lui a1, 1044480 ; LMULMAX2-RV32-NEXT: lui a5, 1044480
; LMULMAX2-RV32-NEXT: vmerge.vxm v10, v10, a1, v0 ; LMULMAX2-RV32-NEXT: vmerge.vxm v14, v14, a5, v0
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 8 ; LMULMAX2-RV32-NEXT: vsrl.vi v16, v8, 8
; LMULMAX2-RV32-NEXT: vand.vv v12, v12, v10 ; LMULMAX2-RV32-NEXT: vand.vv v16, v16, v14
; LMULMAX2-RV32-NEXT: vsrl.vi v14, v8, 24 ; LMULMAX2-RV32-NEXT: vor.vv v12, v16, v12
; LMULMAX2-RV32-NEXT: lui a1, 4080 ; LMULMAX2-RV32-NEXT: vor.vv v10, v12, v10
; LMULMAX2-RV32-NEXT: vand.vx v14, v14, a1 ; LMULMAX2-RV32-NEXT: vsll.vx v12, v8, a1
; LMULMAX2-RV32-NEXT: vor.vv v12, v12, v14 ; LMULMAX2-RV32-NEXT: vand.vx v16, v8, a3
; LMULMAX2-RV32-NEXT: li a2, 56 ; LMULMAX2-RV32-NEXT: vsll.vx v16, v16, a2
; LMULMAX2-RV32-NEXT: vsrl.vx v14, v8, a2 ; LMULMAX2-RV32-NEXT: vor.vv v12, v12, v16
; LMULMAX2-RV32-NEXT: li a3, 40 ; LMULMAX2-RV32-NEXT: vand.vx v16, v8, a4
; LMULMAX2-RV32-NEXT: vsrl.vx v16, v8, a3 ; LMULMAX2-RV32-NEXT: vsll.vi v16, v16, 24
; LMULMAX2-RV32-NEXT: lui a4, 16 ; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v14
; LMULMAX2-RV32-NEXT: addi a4, a4, -256 ; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 8
; LMULMAX2-RV32-NEXT: vand.vx v16, v16, a4 ; LMULMAX2-RV32-NEXT: vor.vv v8, v16, v8
; LMULMAX2-RV32-NEXT: vor.vv v14, v16, v14 ; LMULMAX2-RV32-NEXT: vor.vv v8, v12, v8
; LMULMAX2-RV32-NEXT: vor.vv v12, v12, v14
; LMULMAX2-RV32-NEXT: vand.vv v10, v8, v10
; LMULMAX2-RV32-NEXT: vsll.vi v10, v10, 8
; LMULMAX2-RV32-NEXT: vand.vx v14, v8, a1
; LMULMAX2-RV32-NEXT: vsll.vi v14, v14, 24
; LMULMAX2-RV32-NEXT: vor.vv v10, v14, v10
; LMULMAX2-RV32-NEXT: vsll.vx v14, v8, a2
; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a4
; LMULMAX2-RV32-NEXT: vsll.vx v8, v8, a3
; LMULMAX2-RV32-NEXT: vor.vv v8, v14, v8
; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v12
; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret ; LMULMAX2-RV32-NEXT: ret
; ;
; LMULMAX2-RV64-LABEL: bswap_v4i64: ; LMULMAX2-RV64-LABEL: bswap_v4i64:
; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64-NEXT: li a1, 56 ; LMULMAX2-RV64-NEXT: li a1, 56
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; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: bswap_v4i64: ; LMULMAX1-RV32-LABEL: bswap_v4i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a1, a0, 16 ; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle64.v v9, (a1) ; LMULMAX1-RV32-NEXT: vle64.v v9, (a1)
; LMULMAX1-RV32-NEXT: vmv.v.i v0, 5
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.i v10, 0 ; LMULMAX1-RV32-NEXT: vmv.v.i v10, 0
; LMULMAX1-RV32-NEXT: vmv.v.i v0, 5
; LMULMAX1-RV32-NEXT: lui a2, 1044480 ; LMULMAX1-RV32-NEXT: lui a2, 1044480
; LMULMAX1-RV32-NEXT: vmerge.vxm v10, v10, a2, v0 ; LMULMAX1-RV32-NEXT: vmerge.vxm v10, v10, a2, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 8 ; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 8
; LMULMAX1-RV32-NEXT: vand.vv v11, v11, v10 ; LMULMAX1-RV32-NEXT: vand.vv v11, v11, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v12, v9, 24 ; LMULMAX1-RV32-NEXT: vsrl.vi v12, v9, 24
; LMULMAX1-RV32-NEXT: lui a2, 4080 ; LMULMAX1-RV32-NEXT: lui a2, 4080
; LMULMAX1-RV32-NEXT: vand.vx v12, v12, a2 ; LMULMAX1-RV32-NEXT: vand.vx v12, v12, a2
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll

Show First 20 Lines • Show All 406 Lines • ▼ Show 20 Lines
; LMULMAX4-NEXT: .cfi_def_cfa_offset 256 ; LMULMAX4-NEXT: .cfi_def_cfa_offset 256
; LMULMAX4-NEXT: sd ra, 248(sp) # 8-byte Folded Spill ; LMULMAX4-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
; LMULMAX4-NEXT: sd s0, 240(sp) # 8-byte Folded Spill ; LMULMAX4-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
; LMULMAX4-NEXT: .cfi_offset ra, -8 ; LMULMAX4-NEXT: .cfi_offset ra, -8
; LMULMAX4-NEXT: .cfi_offset s0, -16 ; LMULMAX4-NEXT: .cfi_offset s0, -16
; LMULMAX4-NEXT: addi s0, sp, 256 ; LMULMAX4-NEXT: addi s0, sp, 256
; LMULMAX4-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX4-NEXT: .cfi_def_cfa s0, 0
; LMULMAX4-NEXT: andi sp, sp, -128 ; LMULMAX4-NEXT: andi sp, sp, -128
; LMULMAX4-NEXT: addi a0, sp, 64
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; LMULMAX4-NEXT: vmv.v.i v8, 0 ; LMULMAX4-NEXT: vmv.v.i v8, 0
; LMULMAX4-NEXT: addi a0, sp, 64
; LMULMAX4-NEXT: vse32.v v8, (a0) ; LMULMAX4-NEXT: vse32.v v8, (a0)
; LMULMAX4-NEXT: mv a0, sp ; LMULMAX4-NEXT: mv a0, sp
; LMULMAX4-NEXT: li a1, 1 ; LMULMAX4-NEXT: li a1, 1
; LMULMAX4-NEXT: li a2, 2 ; LMULMAX4-NEXT: li a2, 2
; LMULMAX4-NEXT: li a3, 3 ; LMULMAX4-NEXT: li a3, 3
; LMULMAX4-NEXT: li a4, 4 ; LMULMAX4-NEXT: li a4, 4
; LMULMAX4-NEXT: li a5, 5 ; LMULMAX4-NEXT: li a5, 5
; LMULMAX4-NEXT: li a6, 6 ; LMULMAX4-NEXT: li a6, 6
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; LMULMAX4-NEXT: addi sp, sp, -160 ; LMULMAX4-NEXT: addi sp, sp, -160
; LMULMAX4-NEXT: .cfi_def_cfa_offset 160 ; LMULMAX4-NEXT: .cfi_def_cfa_offset 160
; LMULMAX4-NEXT: sd ra, 152(sp) # 8-byte Folded Spill ; LMULMAX4-NEXT: sd ra, 152(sp) # 8-byte Folded Spill
; LMULMAX4-NEXT: .cfi_offset ra, -8 ; LMULMAX4-NEXT: .cfi_offset ra, -8
; LMULMAX4-NEXT: li a0, 1 ; LMULMAX4-NEXT: li a0, 1
; LMULMAX4-NEXT: sd a0, 136(sp) ; LMULMAX4-NEXT: sd a0, 136(sp)
; LMULMAX4-NEXT: li a0, 13 ; LMULMAX4-NEXT: li a0, 13
; LMULMAX4-NEXT: sd a0, 0(sp) ; LMULMAX4-NEXT: sd a0, 0(sp)
; LMULMAX4-NEXT: addi a0, sp, 72
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; LMULMAX4-NEXT: vmv.v.i v8, 0 ; LMULMAX4-NEXT: vmv.v.i v8, 0
; LMULMAX4-NEXT: addi a0, sp, 72
; LMULMAX4-NEXT: vse32.v v8, (a0) ; LMULMAX4-NEXT: vse32.v v8, (a0)
; LMULMAX4-NEXT: addi a0, sp, 8 ; LMULMAX4-NEXT: addi a0, sp, 8
; LMULMAX4-NEXT: li a1, 1 ; LMULMAX4-NEXT: li a1, 1
; LMULMAX4-NEXT: li a2, 2 ; LMULMAX4-NEXT: li a2, 2
; LMULMAX4-NEXT: li a3, 3 ; LMULMAX4-NEXT: li a3, 3
; LMULMAX4-NEXT: li a4, 4 ; LMULMAX4-NEXT: li a4, 4
; LMULMAX4-NEXT: li a5, 5 ; LMULMAX4-NEXT: li a5, 5
; LMULMAX4-NEXT: li a6, 6 ; LMULMAX4-NEXT: li a6, 6
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll

Show First 20 Lines • Show All 1,612 Lines • ▼ Show 20 Lines
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <15 x i64> @llvm.vp.ctpop.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl) %v = call <15 x i64> @llvm.vp.ctpop.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl)
ret <15 x i64> %v ret <15 x i64> %v
} }
define <15 x i64> @vp_ctpop_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) { define <15 x i64> @vp_ctpop_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctpop_v15i64_unmasked: ; RV32-LABEL: vp_ctpop_v15i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 1
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1 ; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vsrl.vi v24, v8, 1
; RV32-NEXT: vand.vv v16, v24, v16
; RV32-NEXT: vsub.vv v8, v8, v16 ; RV32-NEXT: vsub.vv v8, v8, v16
; RV32-NEXT: lui a1, 209715 ; RV32-NEXT: lui a1, 209715
; RV32-NEXT: addi a1, a1, 819 ; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v16, a1 ; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v24, v8, v16 ; RV32-NEXT: vand.vv v24, v8, v16
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
▲ Show 20 Lines • Show All 133 Lines • ▼ Show 20 Lines
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <16 x i64> @llvm.vp.ctpop.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl) %v = call <16 x i64> @llvm.vp.ctpop.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
define <16 x i64> @vp_ctpop_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { define <16 x i64> @vp_ctpop_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctpop_v16i64_unmasked: ; RV32-LABEL: vp_ctpop_v16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 1
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1 ; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vsrl.vi v24, v8, 1
; RV32-NEXT: vand.vv v16, v24, v16
; RV32-NEXT: vsub.vv v8, v8, v16 ; RV32-NEXT: vsub.vv v8, v8, v16
; RV32-NEXT: lui a1, 209715 ; RV32-NEXT: lui a1, 209715
; RV32-NEXT: addi a1, a1, 819 ; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v16, a1 ; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v24, v8, v16 ; RV32-NEXT: vand.vv v24, v8, v16
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x38, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 56 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x38, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 56 * vlenb
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a2, 48 ; RV32-NEXT: li a2, 48
; RV32-NEXT: mul a1, a1, a2 ; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: li a2, 16
; RV32-NEXT: vslidedown.vi v24, v0, 2 ; RV32-NEXT: vslidedown.vi v24, v0, 2
; RV32-NEXT: mv a1, a0 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: bltu a0, a2, .LBB34_2 ; RV32-NEXT: addi a2, a1, 1365
; RV32-NEXT: # %bb.1: ; RV32-NEXT: li a1, 32
; RV32-NEXT: li a1, 16 ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: .LBB34_2: ; RV32-NEXT: li a3, 16
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vmv.v.x v16, a2
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV32-NEXT: lui a2, 349525
; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: li a3, 32
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 40
; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vmv.v.x v8, a2
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: li a4, 24
; RV32-NEXT: mul a2, a2, a4
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: li a4, 40
; RV32-NEXT: mul a2, a2, a4
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload
; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 5
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV32-NEXT: lui a2, 209715
; RV32-NEXT: addi a2, a2, 819
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a2
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: li a4, 40 ; RV32-NEXT: li a4, 40
; RV32-NEXT: mul a2, a2, a4 ; RV32-NEXT: mul a2, a2, a4
; RV32-NEXT: add a2, sp, a2 ; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16 ; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 5
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl8r.v v16, (a2) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 4
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: mv a2, a0
; RV32-NEXT: slli a2, a2, 5 ; RV32-NEXT: bltu a0, a3, .LBB34_2
; RV32-NEXT: add a2, sp, a2 ; RV32-NEXT: # %bb.1:
; RV32-NEXT: addi a2, a2, 16 ; RV32-NEXT: li a2, 16
; RV32-NEXT: vl8r.v v16, (a2) # Unknown-size Folded Reload ; RV32-NEXT: .LBB34_2:
; RV32-NEXT: vsrl.vi v16, v16, 2, v0.t ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 5
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: li a4, 40
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v8, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a2, a2, 4 ; RV32-NEXT: slli a3, a3, 5
; RV32-NEXT: add a2, sp, a2 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a2, a2, 16 ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vadd.vv v16, v8, v16, v0.t ; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v8, v16, 4, v0.t ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: vadd.vv v16, v16, v8, v0.t ; RV32-NEXT: li a4, 24
; RV32-NEXT: lui a2, 61681 ; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: addi a2, a2, -241 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vmv.v.x v8, a2 ; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: lui a3, 209715
; RV32-NEXT: slli a2, a2, 5 ; RV32-NEXT: addi a3, a3, 819
; RV32-NEXT: add a2, sp, a2 ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: addi a2, a2, 16 ; RV32-NEXT: vmv.v.x v16, a3
; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: slli a3, a3, 5
; RV32-NEXT: vand.vv v8, v16, v8, v0.t ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: lui a2, 4112 ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: addi a2, a2, 257 ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmv.v.x v16, a2 ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: li a4, 24
; RV32-NEXT: slli a2, a2, 3 ; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a2, sp, a2 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a2, a2, 16 ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; RV32-NEXT: vl8r.v v8, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: li a4, 24
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v8, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v16, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: lui a3, 61681
; RV32-NEXT: addi a3, a3, -241
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v16, a3
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: li a4, 24
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: lui a3, 4112
; RV32-NEXT: addi a3, a3, 257
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v16, a3
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmul.vv v8, v8, v16, v0.t ; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 4 ; RV32-NEXT: slli a2, a2, 4
; RV32-NEXT: add a2, sp, a2 ; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16 ; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV32-NEXT: addi a2, a0, -16 ; RV32-NEXT: addi a2, a0, -16
; RV32-NEXT: sltu a0, a0, a2 ; RV32-NEXT: sltu a0, a0, a2
; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a2 ; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v24 ; RV32-NEXT: vmv1r.v v0, v24
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a2, 48 ; RV32-NEXT: li a2, 48
; RV32-NEXT: mul a0, a0, a2 ; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a2, 24 ; RV32-NEXT: li a2, 40
; RV32-NEXT: mul a0, a0, a2 ; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v16, v8, v0.t ; RV32-NEXT: vand.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a2, 48 ; RV32-NEXT: li a2, 48
; RV32-NEXT: mul a0, a0, a2 ; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsub.vv v8, v16, v8, v0.t ; RV32-NEXT: vsub.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a2, 40 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v8, v16, v0.t ; RV32-NEXT: vand.vv v16, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a2, 48 ; RV32-NEXT: li a2, 48
; RV32-NEXT: mul a0, a0, a2 ; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a2, 40 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a2, 48 ; RV32-NEXT: li a2, 48
; RV32-NEXT: mul a0, a0, a2 ; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vadd.vv v8, v16, v8, v0.t ; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t ; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: li a2, 24
; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
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; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.ctpop.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl) %v = call <32 x i64> @llvm.vp.ctpop.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }
define <32 x i64> @vp_ctpop_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { define <32 x i64> @vp_ctpop_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctpop_v32i64_unmasked: ; RV32-LABEL: vp_ctpop_v32i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: addi a2, a1, 1365
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: li a1, 32
; RV32-NEXT: li a2, 40 ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: mul a1, a1, a2 ; RV32-NEXT: li a3, 16
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: vmv.v.x v0, a2
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb ; RV32-NEXT: mv a2, a0
; RV32-NEXT: li a2, 16 ; RV32-NEXT: bltu a0, a3, .LBB35_2
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 5
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV32-NEXT: mv a1, a0
; RV32-NEXT: bltu a0, a2, .LBB35_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a1, 16 ; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB35_2: ; RV32-NEXT: .LBB35_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: vsrl.vi v16, v8, 1 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: lui a2, 349525 ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: addi a2, a2, 1365 ; RV32-NEXT: slli a3, a3, 5
; RV32-NEXT: li a3, 32 ; RV32-NEXT: sub sp, sp, a3
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
; RV32-NEXT: vmv.v.x v24, a2 ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: vsrl.vi v24, v8, 1
; RV32-NEXT: li a4, 24 ; RV32-NEXT: vand.vv v24, v24, v0
; RV32-NEXT: mul a2, a2, a4 ; RV32-NEXT: vsub.vv v8, v8, v24
; RV32-NEXT: add a2, sp, a2 ; RV32-NEXT: lui a3, 209715
; RV32-NEXT: addi a2, a2, 16 ; RV32-NEXT: addi a3, a3, 819
; RV32-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: li a5, 24
; RV32-NEXT: vsub.vv v8, v8, v16 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: lui a2, 209715 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a2, a2, 819 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vs8r.v v0, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vmv.v.x v0, a2 ; RV32-NEXT: vmv.v.x v0, a3
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v8, v0 ; RV32-NEXT: vand.vv v24, v8, v0
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v0 ; RV32-NEXT: vand.vv v8, v8, v0
; RV32-NEXT: vadd.vv v8, v16, v8 ; RV32-NEXT: vadd.vv v8, v24, v8
; RV32-NEXT: vsrl.vi v16, v8, 4 ; RV32-NEXT: vsrl.vi v24, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v16 ; RV32-NEXT: vadd.vv v8, v8, v24
; RV32-NEXT: lui a2, 61681 ; RV32-NEXT: lui a3, 61681
; RV32-NEXT: addi a2, a2, -241 ; RV32-NEXT: addi a3, a3, -241
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v16, a2 ; RV32-NEXT: vmv.v.x v24, a3
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a2, a2, 4 ; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a2, sp, a2 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a2, a2, 16 ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vand.vv v24, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: lui a2, 4112 ; RV32-NEXT: lui a3, 4112
; RV32-NEXT: addi a2, a2, 257 ; RV32-NEXT: addi a3, a3, 257
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a2 ; RV32-NEXT: vmv.v.x v24, a3
; RV32-NEXT: addi a2, sp, 16 ; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmul.vv v24, v24, v8 ; RV32-NEXT: vmul.vv v8, v8, v24
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsrl.vx v8, v24, a1 ; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 3 ; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a2, sp, a2 ; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16 ; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV32-NEXT: addi a2, a0, -16 ; RV32-NEXT: addi a2, a0, -16
; RV32-NEXT: sltu a0, a0, a2 ; RV32-NEXT: sltu a0, a0, a2
; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a2 ; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: vsrl.vi v24, v16, 1
; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsrl.vi v24, v8, 1
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a2, 24 ; RV32-NEXT: li a2, 24
; RV32-NEXT: mul a0, a0, a2 ; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v24, v24, v16 ; RV32-NEXT: vand.vv v24, v24, v8
; RV32-NEXT: vsub.vv v24, v8, v24 ; RV32-NEXT: vsub.vv v24, v16, v24
; RV32-NEXT: vand.vv v8, v24, v0 ; RV32-NEXT: vand.vv v8, v24, v0
; RV32-NEXT: vsrl.vi v24, v24, 2 ; RV32-NEXT: vsrl.vi v24, v24, 2
; RV32-NEXT: vand.vv v24, v24, v0 ; RV32-NEXT: vand.vv v24, v24, v0
; RV32-NEXT: vadd.vv v8, v8, v24 ; RV32-NEXT: vadd.vv v8, v8, v24
; RV32-NEXT: vsrl.vi v24, v8, 4 ; RV32-NEXT: vsrl.vi v24, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v24 ; RV32-NEXT: vadd.vv v8, v8, v24
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vmul.vv v8, v8, v16 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: vsrl.vx v16, v8, a1 ; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 40 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_ctpop_v32i64_unmasked: ; RV64-LABEL: vp_ctpop_v32i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: li a2, 16 ; RV64-NEXT: li a2, 16
; RV64-NEXT: mv a1, a0 ; RV64-NEXT: mv a1, a0
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll

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} }
declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>)
define void @ctpop_v2i64(ptr %x, ptr %y) { define void @ctpop_v2i64(ptr %x, ptr %y) {
; LMULMAX2-RV32-LABEL: ctpop_v2i64: ; LMULMAX2-RV32-LABEL: ctpop_v2i64:
; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX2-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 1
; LMULMAX2-RV32-NEXT: lui a1, 349525 ; LMULMAX2-RV32-NEXT: lui a1, 349525
; LMULMAX2-RV32-NEXT: addi a1, a1, 1365 ; LMULMAX2-RV32-NEXT: addi a1, a1, 1365
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1 ; LMULMAX2-RV32-NEXT: vmv.v.x v9, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX2-RV32-NEXT: vand.vv v9, v9, v10 ; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 1
; LMULMAX2-RV32-NEXT: vand.vv v9, v10, v9
; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v9 ; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v9
; LMULMAX2-RV32-NEXT: lui a1, 209715 ; LMULMAX2-RV32-NEXT: lui a1, 209715
; LMULMAX2-RV32-NEXT: addi a1, a1, 819 ; LMULMAX2-RV32-NEXT: addi a1, a1, 819
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v9, a1 ; LMULMAX2-RV32-NEXT: vmv.v.x v9, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX2-RV32-NEXT: vand.vv v10, v8, v9 ; LMULMAX2-RV32-NEXT: vand.vv v10, v8, v9
; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 2 ; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 2
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; LMULMAX2-RV64-NEXT: vsrl.vx v8, v8, a1 ; LMULMAX2-RV64-NEXT: vsrl.vx v8, v8, a1
; LMULMAX2-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: ctpop_v2i64: ; LMULMAX1-RV32-LABEL: ctpop_v2i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 1
; LMULMAX1-RV32-NEXT: lui a1, 349525 ; LMULMAX1-RV32-NEXT: lui a1, 349525
; LMULMAX1-RV32-NEXT: addi a1, a1, 1365 ; LMULMAX1-RV32-NEXT: addi a1, a1, 1365
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.x v10, a1 ; LMULMAX1-RV32-NEXT: vmv.v.x v9, a1
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV32-NEXT: vand.vv v9, v10, v9
; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v9 ; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v9
; LMULMAX1-RV32-NEXT: lui a1, 209715 ; LMULMAX1-RV32-NEXT: lui a1, 209715
; LMULMAX1-RV32-NEXT: addi a1, a1, 819 ; LMULMAX1-RV32-NEXT: addi a1, a1, 819
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.x v9, a1 ; LMULMAX1-RV32-NEXT: vmv.v.x v9, a1
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vand.vv v10, v8, v9 ; LMULMAX1-RV32-NEXT: vand.vv v10, v8, v9
; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 2 ; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 2
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} }
declare <8 x i32> @llvm.ctpop.v8i32(<8 x i32>) declare <8 x i32> @llvm.ctpop.v8i32(<8 x i32>)
define void @ctpop_v4i64(ptr %x, ptr %y) { define void @ctpop_v4i64(ptr %x, ptr %y) {
; LMULMAX2-RV32-LABEL: ctpop_v4i64: ; LMULMAX2-RV32-LABEL: ctpop_v4i64:
; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 1
; LMULMAX2-RV32-NEXT: lui a1, 349525 ; LMULMAX2-RV32-NEXT: lui a1, 349525
; LMULMAX2-RV32-NEXT: addi a1, a1, 1365 ; LMULMAX2-RV32-NEXT: addi a1, a1, 1365
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v12, a1 ; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32-NEXT: vand.vv v10, v10, v12 ; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 1
; LMULMAX2-RV32-NEXT: vand.vv v10, v12, v10
; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: lui a1, 209715 ; LMULMAX2-RV32-NEXT: lui a1, 209715
; LMULMAX2-RV32-NEXT: addi a1, a1, 819 ; LMULMAX2-RV32-NEXT: addi a1, a1, 819
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1 ; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32-NEXT: vand.vv v12, v8, v10 ; LMULMAX2-RV32-NEXT: vand.vv v12, v8, v10
; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 2 ; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 2
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; LMULMAX2-RV64-NEXT: li a1, 56 ; LMULMAX2-RV64-NEXT: li a1, 56
; LMULMAX2-RV64-NEXT: vsrl.vx v8, v8, a1 ; LMULMAX2-RV64-NEXT: vsrl.vx v8, v8, a1
; LMULMAX2-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: ctpop_v4i64: ; LMULMAX1-RV32-LABEL: ctpop_v4i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a1, a0, 16 ; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle64.v v8, (a1) ; LMULMAX1-RV32-NEXT: vle64.v v9, (a1)
; LMULMAX1-RV32-NEXT: vle64.v v9, (a0)
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV32-NEXT: lui a2, 349525 ; LMULMAX1-RV32-NEXT: lui a2, 349525
; LMULMAX1-RV32-NEXT: addi a2, a2, 1365 ; LMULMAX1-RV32-NEXT: addi a2, a2, 1365
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.x v11, a2 ; LMULMAX1-RV32-NEXT: vmv.v.x v10, a2
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vand.vv v10, v10, v11 ; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 1
; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v10 ; LMULMAX1-RV32-NEXT: vand.vv v11, v11, v10
; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v11
; LMULMAX1-RV32-NEXT: lui a2, 209715 ; LMULMAX1-RV32-NEXT: lui a2, 209715
; LMULMAX1-RV32-NEXT: addi a2, a2, 819 ; LMULMAX1-RV32-NEXT: addi a2, a2, 819
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.x v10, a2 ; LMULMAX1-RV32-NEXT: vmv.v.x v11, a2
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vand.vv v12, v8, v10 ; LMULMAX1-RV32-NEXT: vand.vv v12, v9, v11
; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 2 ; LMULMAX1-RV32-NEXT: vsrl.vi v9, v9, 2
; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v10 ; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v11
; LMULMAX1-RV32-NEXT: vadd.vv v8, v12, v8 ; LMULMAX1-RV32-NEXT: vadd.vv v9, v12, v9
; LMULMAX1-RV32-NEXT: vsrl.vi v12, v8, 4 ; LMULMAX1-RV32-NEXT: vsrl.vi v12, v9, 4
; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v12 ; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v12
; LMULMAX1-RV32-NEXT: lui a2, 61681 ; LMULMAX1-RV32-NEXT: lui a2, 61681
; LMULMAX1-RV32-NEXT: addi a2, a2, -241 ; LMULMAX1-RV32-NEXT: addi a2, a2, -241
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.x v12, a2 ; LMULMAX1-RV32-NEXT: vmv.v.x v12, a2
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v12 ; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v12
; LMULMAX1-RV32-NEXT: lui a2, 4112 ; LMULMAX1-RV32-NEXT: lui a2, 4112
; LMULMAX1-RV32-NEXT: addi a2, a2, 257 ; LMULMAX1-RV32-NEXT: addi a2, a2, 257
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.x v13, a2 ; LMULMAX1-RV32-NEXT: vmv.v.x v13, a2
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmul.vv v8, v8, v13
; LMULMAX1-RV32-NEXT: li a2, 56
; LMULMAX1-RV32-NEXT: vsrl.vx v8, v8, a2
; LMULMAX1-RV32-NEXT: vsrl.vi v14, v9, 1
; LMULMAX1-RV32-NEXT: vand.vv v11, v14, v11
; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v11
; LMULMAX1-RV32-NEXT: vand.vv v11, v9, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v9, v9, 2
; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10
; LMULMAX1-RV32-NEXT: vadd.vv v9, v11, v9
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10
; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v12
; LMULMAX1-RV32-NEXT: vmul.vv v9, v9, v13 ; LMULMAX1-RV32-NEXT: vmul.vv v9, v9, v13
; LMULMAX1-RV32-NEXT: li a2, 56
; LMULMAX1-RV32-NEXT: vsrl.vx v9, v9, a2 ; LMULMAX1-RV32-NEXT: vsrl.vx v9, v9, a2
; LMULMAX1-RV32-NEXT: vse64.v v9, (a0) ; LMULMAX1-RV32-NEXT: vsrl.vi v14, v8, 1
; LMULMAX1-RV32-NEXT: vse64.v v8, (a1) ; LMULMAX1-RV32-NEXT: vand.vv v10, v14, v10
; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: vand.vv v10, v8, v11
; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 2
; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v11
; LMULMAX1-RV32-NEXT: vadd.vv v8, v10, v8
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v12
; LMULMAX1-RV32-NEXT: vmul.vv v8, v8, v13
; LMULMAX1-RV32-NEXT: vsrl.vx v8, v8, a2
; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV32-NEXT: vse64.v v9, (a1)
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: ctpop_v4i64: ; LMULMAX1-RV64-LABEL: ctpop_v4i64:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: addi a1, a0, 16 ; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle64.v v8, (a1) ; LMULMAX1-RV64-NEXT: vle64.v v8, (a1)
; LMULMAX1-RV64-NEXT: vle64.v v9, (a0) ; LMULMAX1-RV64-NEXT: vle64.v v9, (a0)
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll

Show First 20 Lines • Show All 2,127 Lines • ▼ Show 20 Lines
; RV32-LABEL: vp_cttz_v32i64: ; RV32-LABEL: vp_cttz_v32i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 6 ; RV32-NEXT: slli a1, a1, 6
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xc0, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 64 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xc0, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 64 * vlenb
; RV32-NEXT: vmv1r.v v24, v0
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: mul a1, a1, a2 ; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; RV32-NEXT: vmv8r.v v16, v8
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: li a1, 16 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vslidedown.vi v24, v0, 2 ; RV32-NEXT: addi a1, a0, -16
; RV32-NEXT: mv a2, a0 ; RV32-NEXT: sltu a2, a0, a1
; RV32-NEXT: bltu a0, a1, .LBB34_2 ; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: # %bb.1: ; RV32-NEXT: and a2, a2, a1
; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB34_2:
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v8, v16, a1, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: li a4, 56
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: li a3, 32 ; RV32-NEXT: li a3, 32
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v8, -1 ; RV32-NEXT: vmv.v.i v8, -1
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: li a1, 1
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 5 ; RV32-NEXT: slli a4, a4, 5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vxor.vv v8, v16, v8, v0.t
; RV32-NEXT: vxor.vv v16, v16, v8, v0.t ; RV32-NEXT: vsub.vx v16, v16, a1, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: li a5, 56
; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 48 ; RV32-NEXT: li a5, 48
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: lui a4, 349525 ; RV32-NEXT: lui a4, 349525
; RV32-NEXT: addi a4, a4, 1365 ; RV32-NEXT: addi a4, a4, 1365
; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
; RV32-NEXT: csrr a5, vlenb ; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: li a6, 56 ; RV32-NEXT: li a6, 56
; RV32-NEXT: mul a5, a5, a6 ; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5 ; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16 ; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a4 ; RV32-NEXT: vmv.v.x v8, a4
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 24 ; RV32-NEXT: li a5, 24
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 56 ; RV32-NEXT: li a5, 56
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: vand.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 48 ; RV32-NEXT: li a5, 48
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vsub.vv v8, v8, v16, v0.t ; RV32-NEXT: vsub.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 48 ; RV32-NEXT: li a5, 48
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: lui a4, 209715 ; RV32-NEXT: lui a4, 209715
; RV32-NEXT: addi a4, a4, 819 ; RV32-NEXT: addi a4, a4, 819
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a4 ; RV32-NEXT: vmv.v.x v8, a4
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 56
; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 48 ; RV32-NEXT: li a5, 48
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 4 ; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 48 ; RV32-NEXT: li a5, 48
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vsrl.vi v16, v16, 2, v0.t ; RV32-NEXT: vsrl.vi v16, v16, 2, v0.t
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 56
; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 4 ; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t ; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v16, v8, v16, v0.t ; RV32-NEXT: vadd.vv v16, v8, v16, v0.t
; RV32-NEXT: lui a4, 61681 ; RV32-NEXT: lui a4, 61681
; RV32-NEXT: addi a4, a4, -241 ; RV32-NEXT: addi a4, a4, -241
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a4 ; RV32-NEXT: vmv.v.x v8, a4
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 48 ; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: vand.vv v8, v16, v8, v0.t
; RV32-NEXT: lui a4, 4112 ; RV32-NEXT: lui a4, 4112
; RV32-NEXT: addi a4, a4, 257 ; RV32-NEXT: addi a4, a4, 257
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v16, a4 ; RV32-NEXT: vmv.v.x v8, a4
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmul.vv v8, v8, v16, v0.t ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vmul.vv v8, v16, v8, v0.t
; RV32-NEXT: li a2, 56 ; RV32-NEXT: li a2, 56
; RV32-NEXT: li a3, 16
; RV32-NEXT: vsrl.vx v8, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v8, v8, a2, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: bltu a0, a3, .LBB34_2
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: # %bb.1:
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill ; RV32-NEXT: li a0, 16
; RV32-NEXT: addi a3, a0, -16 ; RV32-NEXT: .LBB34_2:
; RV32-NEXT: sltu a0, a0, a3
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a3
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v24 ; RV32-NEXT: vmv1r.v v0, v24
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a3, 40 ; RV32-NEXT: li a3, 40
; RV32-NEXT: mul a0, a0, a3 ; RV32-NEXT: mul a0, a0, a3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsub.vx v8, v16, a1, v0.t
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vxor.vv v16, v16, v8, v0.t ; RV32-NEXT: vxor.vv v8, v16, v8, v0.t
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: vsub.vx v16, v16, a1, v0.t
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vand.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: li a1, 40
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 40 ; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 24 ; RV32-NEXT: li a1, 24
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 40 ; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v8, v16, v0.t ; RV32-NEXT: vand.vv v16, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: li a1, 40
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsub.vv v8, v8, v16, v0.t ; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v8, v16, v0.t ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 40 ; RV32-NEXT: li a1, 40
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 40 ; RV32-NEXT: li a1, 40
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vadd.vv v8, v16, v8, v0.t ; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t ; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 48 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vmul.vv v8, v8, v16, v0.t ; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v8, v8, a2, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 6 ; RV32-NEXT: slli a0, a0, 6
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_cttz_v32i64: ; RV64-LABEL: vp_cttz_v32i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
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; RV32-NEXT: .LBB35_2: ; RV32-NEXT: .LBB35_2:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: li a3, 40 ; RV32-NEXT: li a3, 40
; RV32-NEXT: mul a2, a2, a3 ; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: sub sp, sp, a2 ; RV32-NEXT: sub sp, sp, a2
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
; RV32-NEXT: li a2, 1 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v8, a2 ; RV32-NEXT: vmv.v.i v16, -1
; RV32-NEXT: li a3, 32 ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: slli a3, a3, 5
; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: slli a4, a4, 5 ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vxor.vv v8, v8, v24 ; RV32-NEXT: vxor.vv v16, v8, v16
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: li a3, 1
; RV32-NEXT: vsub.vx v8, v8, a3
; RV32-NEXT: vand.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 1 ; RV32-NEXT: vsrl.vi v16, v8, 1
; RV32-NEXT: lui a4, 349525 ; RV32-NEXT: lui a4, 349525
; RV32-NEXT: addi a4, a4, 1365 ; RV32-NEXT: addi a4, a4, 1365
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a4 ; RV32-NEXT: vmv.v.x v24, a4
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 24 ; RV32-NEXT: li a5, 24
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vsub.vv v8, v8, v16 ; RV32-NEXT: vsub.vv v8, v8, v16
; RV32-NEXT: lui a4, 209715 ; RV32-NEXT: lui a4, 209715
; RV32-NEXT: addi a4, a4, 819 ; RV32-NEXT: addi a4, a4, 819
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v16, a4 ; RV32-NEXT: vmv.v.x v16, a4
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vv v24, v8, v16 ; RV32-NEXT: vand.vv v24, v8, v16
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vadd.vv v8, v24, v8 ; RV32-NEXT: vadd.vv v8, v24, v8
; RV32-NEXT: vsrl.vi v24, v8, 4 ; RV32-NEXT: vsrl.vi v24, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v24 ; RV32-NEXT: vadd.vv v8, v8, v24
; RV32-NEXT: lui a4, 61681 ; RV32-NEXT: lui a4, 61681
; RV32-NEXT: addi a4, a4, -241 ; RV32-NEXT: addi a4, a4, -241
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a4 ; RV32-NEXT: vmv.v.x v24, a4
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 4 ; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: lui a4, 4112 ; RV32-NEXT: lui a4, 4112
; RV32-NEXT: addi a4, a4, 257 ; RV32-NEXT: addi a4, a4, 257
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a4 ; RV32-NEXT: vmv.v.x v24, a4
; RV32-NEXT: addi a3, sp, 16 ; RV32-NEXT: addi a2, sp, 16
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vmul.vv v8, v8, v24 ; RV32-NEXT: vmul.vv v8, v8, v24
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a3, a3, 3 ; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV32-NEXT: addi a3, a0, -16 ; RV32-NEXT: addi a2, a0, -16
; RV32-NEXT: sltu a0, a0, a3 ; RV32-NEXT: sltu a0, a0, a2
; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a3 ; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vxor.vv v8, v0, v8 ; RV32-NEXT: vxor.vv v8, v0, v8
; RV32-NEXT: vsub.vx v0, v0, a2 ; RV32-NEXT: vsub.vx v0, v0, a3
; RV32-NEXT: vand.vv v8, v8, v0 ; RV32-NEXT: vand.vv v8, v8, v0
; RV32-NEXT: vsrl.vi v0, v8, 1 ; RV32-NEXT: vsrl.vi v0, v8, 1
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a2, 24 ; RV32-NEXT: li a2, 24
; RV32-NEXT: mul a0, a0, a2 ; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
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; RV32-LABEL: vp_cttz_zero_undef_v32i64: ; RV32-LABEL: vp_cttz_zero_undef_v32i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 6 ; RV32-NEXT: slli a1, a1, 6
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xc0, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 64 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xc0, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 64 * vlenb
; RV32-NEXT: vmv1r.v v24, v0
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: mul a1, a1, a2 ; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; RV32-NEXT: vmv8r.v v16, v8
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: li a1, 16 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vslidedown.vi v24, v0, 2 ; RV32-NEXT: addi a1, a0, -16
; RV32-NEXT: mv a2, a0 ; RV32-NEXT: sltu a2, a0, a1
; RV32-NEXT: bltu a0, a1, .LBB70_2 ; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: # %bb.1: ; RV32-NEXT: and a2, a2, a1
; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB70_2:
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v8, v16, a1, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: li a4, 56
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: li a3, 32 ; RV32-NEXT: li a3, 32
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v8, -1 ; RV32-NEXT: vmv.v.i v8, -1
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: li a1, 1
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 5 ; RV32-NEXT: slli a4, a4, 5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vxor.vv v8, v16, v8, v0.t
; RV32-NEXT: vxor.vv v16, v16, v8, v0.t ; RV32-NEXT: vsub.vx v16, v16, a1, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: li a5, 56
; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 48 ; RV32-NEXT: li a5, 48
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: lui a4, 349525 ; RV32-NEXT: lui a4, 349525
; RV32-NEXT: addi a4, a4, 1365 ; RV32-NEXT: addi a4, a4, 1365
; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
; RV32-NEXT: csrr a5, vlenb ; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: li a6, 56 ; RV32-NEXT: li a6, 56
; RV32-NEXT: mul a5, a5, a6 ; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5 ; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16 ; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a4 ; RV32-NEXT: vmv.v.x v8, a4
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 24 ; RV32-NEXT: li a5, 24
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 56 ; RV32-NEXT: li a5, 56
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: vand.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 48 ; RV32-NEXT: li a5, 48
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vsub.vv v8, v8, v16, v0.t ; RV32-NEXT: vsub.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 48 ; RV32-NEXT: li a5, 48
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: lui a4, 209715 ; RV32-NEXT: lui a4, 209715
; RV32-NEXT: addi a4, a4, 819 ; RV32-NEXT: addi a4, a4, 819
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a4 ; RV32-NEXT: vmv.v.x v8, a4
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 56
; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 48 ; RV32-NEXT: li a5, 48
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 4 ; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 48 ; RV32-NEXT: li a5, 48
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vsrl.vi v16, v16, 2, v0.t ; RV32-NEXT: vsrl.vi v16, v16, 2, v0.t
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 56
; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 4 ; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t ; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v16, v8, v16, v0.t ; RV32-NEXT: vadd.vv v16, v8, v16, v0.t
; RV32-NEXT: lui a4, 61681 ; RV32-NEXT: lui a4, 61681
; RV32-NEXT: addi a4, a4, -241 ; RV32-NEXT: addi a4, a4, -241
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a4 ; RV32-NEXT: vmv.v.x v8, a4
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 48 ; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: vand.vv v8, v16, v8, v0.t
; RV32-NEXT: lui a4, 4112 ; RV32-NEXT: lui a4, 4112
; RV32-NEXT: addi a4, a4, 257 ; RV32-NEXT: addi a4, a4, 257
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v16, a4 ; RV32-NEXT: vmv.v.x v8, a4
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmul.vv v8, v8, v16, v0.t ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vmul.vv v8, v16, v8, v0.t
; RV32-NEXT: li a2, 56 ; RV32-NEXT: li a2, 56
; RV32-NEXT: li a3, 16
; RV32-NEXT: vsrl.vx v8, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v8, v8, a2, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: bltu a0, a3, .LBB70_2
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: # %bb.1:
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill ; RV32-NEXT: li a0, 16
; RV32-NEXT: addi a3, a0, -16 ; RV32-NEXT: .LBB70_2:
; RV32-NEXT: sltu a0, a0, a3
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a3
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v24 ; RV32-NEXT: vmv1r.v v0, v24
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a3, 40 ; RV32-NEXT: li a3, 40
; RV32-NEXT: mul a0, a0, a3 ; RV32-NEXT: mul a0, a0, a3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsub.vx v8, v16, a1, v0.t
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vxor.vv v16, v16, v8, v0.t ; RV32-NEXT: vxor.vv v8, v16, v8, v0.t
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: vsub.vx v16, v16, a1, v0.t
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vand.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: li a1, 40
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 40 ; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 24 ; RV32-NEXT: li a1, 24
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 40 ; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v8, v16, v0.t ; RV32-NEXT: vand.vv v16, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: li a1, 40
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsub.vv v8, v8, v16, v0.t ; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v8, v16, v0.t ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 40 ; RV32-NEXT: li a1, 40
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 40 ; RV32-NEXT: li a1, 40
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vadd.vv v8, v16, v8, v0.t ; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t ; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 48 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vmul.vv v8, v8, v16, v0.t ; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v8, v8, a2, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 6 ; RV32-NEXT: slli a0, a0, 6
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_cttz_zero_undef_v32i64: ; RV64-LABEL: vp_cttz_zero_undef_v32i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
; RV32-NEXT: .LBB71_2: ; RV32-NEXT: .LBB71_2:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: li a3, 40 ; RV32-NEXT: li a3, 40
; RV32-NEXT: mul a2, a2, a3 ; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: sub sp, sp, a2 ; RV32-NEXT: sub sp, sp, a2
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
; RV32-NEXT: li a2, 1 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v8, a2 ; RV32-NEXT: vmv.v.i v16, -1
; RV32-NEXT: li a3, 32 ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: slli a3, a3, 5
; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: slli a4, a4, 5 ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vxor.vv v8, v8, v24 ; RV32-NEXT: vxor.vv v16, v8, v16
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: li a3, 1
; RV32-NEXT: vsub.vx v8, v8, a3
; RV32-NEXT: vand.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 1 ; RV32-NEXT: vsrl.vi v16, v8, 1
; RV32-NEXT: lui a4, 349525 ; RV32-NEXT: lui a4, 349525
; RV32-NEXT: addi a4, a4, 1365 ; RV32-NEXT: addi a4, a4, 1365
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a4 ; RV32-NEXT: vmv.v.x v24, a4
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 24 ; RV32-NEXT: li a5, 24
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vsub.vv v8, v8, v16 ; RV32-NEXT: vsub.vv v8, v8, v16
; RV32-NEXT: lui a4, 209715 ; RV32-NEXT: lui a4, 209715
; RV32-NEXT: addi a4, a4, 819 ; RV32-NEXT: addi a4, a4, 819
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v16, a4 ; RV32-NEXT: vmv.v.x v16, a4
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vv v24, v8, v16 ; RV32-NEXT: vand.vv v24, v8, v16
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vadd.vv v8, v24, v8 ; RV32-NEXT: vadd.vv v8, v24, v8
; RV32-NEXT: vsrl.vi v24, v8, 4 ; RV32-NEXT: vsrl.vi v24, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v24 ; RV32-NEXT: vadd.vv v8, v8, v24
; RV32-NEXT: lui a4, 61681 ; RV32-NEXT: lui a4, 61681
; RV32-NEXT: addi a4, a4, -241 ; RV32-NEXT: addi a4, a4, -241
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a4 ; RV32-NEXT: vmv.v.x v24, a4
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 4 ; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: lui a4, 4112 ; RV32-NEXT: lui a4, 4112
; RV32-NEXT: addi a4, a4, 257 ; RV32-NEXT: addi a4, a4, 257
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a4 ; RV32-NEXT: vmv.v.x v24, a4
; RV32-NEXT: addi a3, sp, 16 ; RV32-NEXT: addi a2, sp, 16
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vmul.vv v8, v8, v24 ; RV32-NEXT: vmul.vv v8, v8, v24
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a3, a3, 3 ; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV32-NEXT: addi a3, a0, -16 ; RV32-NEXT: addi a2, a0, -16
; RV32-NEXT: sltu a0, a0, a3 ; RV32-NEXT: sltu a0, a0, a2
; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a3 ; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vxor.vv v8, v0, v8 ; RV32-NEXT: vxor.vv v8, v0, v8
; RV32-NEXT: vsub.vx v0, v0, a2 ; RV32-NEXT: vsub.vx v0, v0, a3
; RV32-NEXT: vand.vv v8, v8, v0 ; RV32-NEXT: vand.vv v8, v8, v0
; RV32-NEXT: vsrl.vi v0, v8, 1 ; RV32-NEXT: vsrl.vi v0, v8, 1
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a2, 24 ; RV32-NEXT: li a2, 24
; RV32-NEXT: mul a0, a0, a2 ; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
▲ Show 20 Lines • Show All 98 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll

Show First 20 Lines • Show All 135 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%z = zext <4 x i8> %y to <4 x i32> %z = zext <4 x i8> %y to <4 x i32>
ret <4 x i32> %z ret <4 x i32> %z
} }
define <4 x i64> @sextload_v4i8_v4i64(ptr %x) { define <4 x i64> @sextload_v4i8_v4i64(ptr %x) {
; LMULMAX1-LABEL: sextload_v4i8_v4i64: ; LMULMAX1-LABEL: sextload_v4i8_v4i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; LMULMAX1-NEXT: vle8.v v10, (a0) ; LMULMAX1-NEXT: vle8.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v9, v8 ; LMULMAX1-NEXT: vsext.vf8 v9, v10
; LMULMAX1-NEXT: vsext.vf8 v8, v10
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: sextload_v4i8_v4i64: ; LMULMAX4-LABEL: sextload_v4i8_v4i64:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX4-NEXT: vle8.v v10, (a0) ; LMULMAX4-NEXT: vle8.v v10, (a0)
; LMULMAX4-NEXT: vsext.vf8 v8, v10 ; LMULMAX4-NEXT: vsext.vf8 v8, v10
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <4 x i8>, ptr %x %y = load <4 x i8>, ptr %x
%z = sext <4 x i8> %y to <4 x i64> %z = sext <4 x i8> %y to <4 x i64>
ret <4 x i64> %z ret <4 x i64> %z
} }
define <4 x i64> @zextload_v4i8_v4i64(ptr %x) { define <4 x i64> @zextload_v4i8_v4i64(ptr %x) {
; LMULMAX1-LABEL: zextload_v4i8_v4i64: ; LMULMAX1-LABEL: zextload_v4i8_v4i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; LMULMAX1-NEXT: vle8.v v10, (a0) ; LMULMAX1-NEXT: vle8.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v9, v8 ; LMULMAX1-NEXT: vzext.vf8 v9, v10
; LMULMAX1-NEXT: vzext.vf8 v8, v10
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: zextload_v4i8_v4i64: ; LMULMAX4-LABEL: zextload_v4i8_v4i64:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX4-NEXT: vle8.v v10, (a0) ; LMULMAX4-NEXT: vle8.v v10, (a0)
; LMULMAX4-NEXT: vzext.vf8 v8, v10 ; LMULMAX4-NEXT: vzext.vf8 v8, v10
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
Show All 25 Lines; CHECK-NEXT: ret
%z = zext <8 x i8> %y to <8 x i16> %z = zext <8 x i8> %y to <8 x i16>
ret <8 x i16> %z ret <8 x i16> %z
} }
define <8 x i32> @sextload_v8i8_v8i32(ptr %x) { define <8 x i32> @sextload_v8i8_v8i32(ptr %x) {
; LMULMAX1-LABEL: sextload_v8i8_v8i32: ; LMULMAX1-LABEL: sextload_v8i8_v8i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; LMULMAX1-NEXT: vle8.v v10, (a0) ; LMULMAX1-NEXT: vle8.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4 ; LMULMAX1-NEXT: vslidedown.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v9, v8 ; LMULMAX1-NEXT: vsext.vf4 v9, v10
; LMULMAX1-NEXT: vsext.vf4 v8, v10
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: sextload_v8i8_v8i32: ; LMULMAX4-LABEL: sextload_v8i8_v8i32:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX4-NEXT: vle8.v v10, (a0) ; LMULMAX4-NEXT: vle8.v v10, (a0)
; LMULMAX4-NEXT: vsext.vf4 v8, v10 ; LMULMAX4-NEXT: vsext.vf4 v8, v10
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <8 x i8>, ptr %x %y = load <8 x i8>, ptr %x
%z = sext <8 x i8> %y to <8 x i32> %z = sext <8 x i8> %y to <8 x i32>
ret <8 x i32> %z ret <8 x i32> %z
} }
define <8 x i32> @zextload_v8i8_v8i32(ptr %x) { define <8 x i32> @zextload_v8i8_v8i32(ptr %x) {
; LMULMAX1-LABEL: zextload_v8i8_v8i32: ; LMULMAX1-LABEL: zextload_v8i8_v8i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; LMULMAX1-NEXT: vle8.v v10, (a0) ; LMULMAX1-NEXT: vle8.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4 ; LMULMAX1-NEXT: vslidedown.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v9, v8 ; LMULMAX1-NEXT: vzext.vf4 v9, v10
; LMULMAX1-NEXT: vzext.vf4 v8, v10
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: zextload_v8i8_v8i32: ; LMULMAX4-LABEL: zextload_v8i8_v8i32:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX4-NEXT: vle8.v v10, (a0) ; LMULMAX4-NEXT: vle8.v v10, (a0)
; LMULMAX4-NEXT: vzext.vf4 v8, v10 ; LMULMAX4-NEXT: vzext.vf4 v8, v10
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <8 x i8>, ptr %x %y = load <8 x i8>, ptr %x
%z = zext <8 x i8> %y to <8 x i32> %z = zext <8 x i8> %y to <8 x i32>
ret <8 x i32> %z ret <8 x i32> %z
} }
define <8 x i64> @sextload_v8i8_v8i64(ptr %x) { define <8 x i64> @sextload_v8i8_v8i64(ptr %x) {
; LMULMAX1-LABEL: sextload_v8i8_v8i64: ; LMULMAX1-LABEL: sextload_v8i8_v8i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; LMULMAX1-NEXT: vle8.v v12, (a0) ; LMULMAX1-NEXT: vle8.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4 ; LMULMAX1-NEXT: vslidedown.vi v11, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v10, v8 ; LMULMAX1-NEXT: vsext.vf8 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v11, v12, 2 ; LMULMAX1-NEXT: vslidedown.vi v12, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v9, v11 ; LMULMAX1-NEXT: vsext.vf8 v9, v12
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-NEXT: vslidedown.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v11, v8 ; LMULMAX1-NEXT: vsext.vf8 v11, v12
; LMULMAX1-NEXT: vsext.vf8 v8, v12
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: sextload_v8i8_v8i64: ; LMULMAX4-LABEL: sextload_v8i8_v8i64:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vle8.v v12, (a0) ; LMULMAX4-NEXT: vle8.v v12, (a0)
; LMULMAX4-NEXT: vsext.vf8 v8, v12 ; LMULMAX4-NEXT: vsext.vf8 v8, v12
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <8 x i8>, ptr %x %y = load <8 x i8>, ptr %x
%z = sext <8 x i8> %y to <8 x i64> %z = sext <8 x i8> %y to <8 x i64>
ret <8 x i64> %z ret <8 x i64> %z
} }
define <8 x i64> @zextload_v8i8_v8i64(ptr %x) { define <8 x i64> @zextload_v8i8_v8i64(ptr %x) {
; LMULMAX1-LABEL: zextload_v8i8_v8i64: ; LMULMAX1-LABEL: zextload_v8i8_v8i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; LMULMAX1-NEXT: vle8.v v12, (a0) ; LMULMAX1-NEXT: vle8.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4 ; LMULMAX1-NEXT: vslidedown.vi v11, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v10, v8 ; LMULMAX1-NEXT: vzext.vf8 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v11, v12, 2 ; LMULMAX1-NEXT: vslidedown.vi v12, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v9, v11 ; LMULMAX1-NEXT: vzext.vf8 v9, v12
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-NEXT: vslidedown.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v11, v8 ; LMULMAX1-NEXT: vzext.vf8 v11, v12
; LMULMAX1-NEXT: vzext.vf8 v8, v12
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: zextload_v8i8_v8i64: ; LMULMAX4-LABEL: zextload_v8i8_v8i64:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vle8.v v12, (a0) ; LMULMAX4-NEXT: vle8.v v12, (a0)
; LMULMAX4-NEXT: vzext.vf8 v8, v12 ; LMULMAX4-NEXT: vzext.vf8 v8, v12
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <8 x i8>, ptr %x %y = load <8 x i8>, ptr %x
%z = zext <8 x i8> %y to <8 x i64> %z = zext <8 x i8> %y to <8 x i64>
ret <8 x i64> %z ret <8 x i64> %z
} }
define <16 x i16> @sextload_v16i8_v16i16(ptr %x) { define <16 x i16> @sextload_v16i8_v16i16(ptr %x) {
; LMULMAX1-LABEL: sextload_v16i8_v16i16: ; LMULMAX1-LABEL: sextload_v16i8_v16i16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vle8.v v10, (a0) ; LMULMAX1-NEXT: vle8.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 8 ; LMULMAX1-NEXT: vslidedown.vi v10, v9, 8
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v9, v8 ; LMULMAX1-NEXT: vsext.vf2 v9, v10
; LMULMAX1-NEXT: vsext.vf2 v8, v10
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: sextload_v16i8_v16i16: ; LMULMAX4-LABEL: sextload_v16i8_v16i16:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX4-NEXT: vle8.v v10, (a0) ; LMULMAX4-NEXT: vle8.v v10, (a0)
; LMULMAX4-NEXT: vsext.vf2 v8, v10 ; LMULMAX4-NEXT: vsext.vf2 v8, v10
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <16 x i8>, ptr %x %y = load <16 x i8>, ptr %x
%z = sext <16 x i8> %y to <16 x i16> %z = sext <16 x i8> %y to <16 x i16>
ret <16 x i16> %z ret <16 x i16> %z
} }
define <16 x i16> @zextload_v16i8_v16i16(ptr %x) { define <16 x i16> @zextload_v16i8_v16i16(ptr %x) {
; LMULMAX1-LABEL: zextload_v16i8_v16i16: ; LMULMAX1-LABEL: zextload_v16i8_v16i16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vle8.v v10, (a0) ; LMULMAX1-NEXT: vle8.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 8 ; LMULMAX1-NEXT: vslidedown.vi v10, v9, 8
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v9, v8 ; LMULMAX1-NEXT: vzext.vf2 v9, v10
; LMULMAX1-NEXT: vzext.vf2 v8, v10
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: zextload_v16i8_v16i16: ; LMULMAX4-LABEL: zextload_v16i8_v16i16:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX4-NEXT: vle8.v v10, (a0) ; LMULMAX4-NEXT: vle8.v v10, (a0)
; LMULMAX4-NEXT: vzext.vf2 v8, v10 ; LMULMAX4-NEXT: vzext.vf2 v8, v10
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <16 x i8>, ptr %x %y = load <16 x i8>, ptr %x
%z = zext <16 x i8> %y to <16 x i16> %z = zext <16 x i8> %y to <16 x i16>
ret <16 x i16> %z ret <16 x i16> %z
} }
define <16 x i32> @sextload_v16i8_v16i32(ptr %x) { define <16 x i32> @sextload_v16i8_v16i32(ptr %x) {
; LMULMAX1-LABEL: sextload_v16i8_v16i32: ; LMULMAX1-LABEL: sextload_v16i8_v16i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vle8.v v12, (a0) ; LMULMAX1-NEXT: vle8.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v12, 8 ; LMULMAX1-NEXT: vslidedown.vi v11, v9, 8
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v10, v8 ; LMULMAX1-NEXT: vsext.vf4 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v11, v12, 4 ; LMULMAX1-NEXT: vslidedown.vi v12, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v9, v11 ; LMULMAX1-NEXT: vsext.vf4 v9, v12
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 4 ; LMULMAX1-NEXT: vslidedown.vi v12, v11, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v11, v8 ; LMULMAX1-NEXT: vsext.vf4 v11, v12
; LMULMAX1-NEXT: vsext.vf4 v8, v12
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: sextload_v16i8_v16i32: ; LMULMAX4-LABEL: sextload_v16i8_v16i32:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; LMULMAX4-NEXT: vle8.v v12, (a0) ; LMULMAX4-NEXT: vle8.v v12, (a0)
; LMULMAX4-NEXT: vsext.vf4 v8, v12 ; LMULMAX4-NEXT: vsext.vf4 v8, v12
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <16 x i8>, ptr %x %y = load <16 x i8>, ptr %x
%z = sext <16 x i8> %y to <16 x i32> %z = sext <16 x i8> %y to <16 x i32>
ret <16 x i32> %z ret <16 x i32> %z
} }
define <16 x i32> @zextload_v16i8_v16i32(ptr %x) { define <16 x i32> @zextload_v16i8_v16i32(ptr %x) {
; LMULMAX1-LABEL: zextload_v16i8_v16i32: ; LMULMAX1-LABEL: zextload_v16i8_v16i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vle8.v v12, (a0) ; LMULMAX1-NEXT: vle8.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v12, 8 ; LMULMAX1-NEXT: vslidedown.vi v11, v9, 8
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v10, v8 ; LMULMAX1-NEXT: vzext.vf4 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v11, v12, 4 ; LMULMAX1-NEXT: vslidedown.vi v12, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v9, v11 ; LMULMAX1-NEXT: vzext.vf4 v9, v12
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 4 ; LMULMAX1-NEXT: vslidedown.vi v12, v11, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v11, v8 ; LMULMAX1-NEXT: vzext.vf4 v11, v12
; LMULMAX1-NEXT: vzext.vf4 v8, v12
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: zextload_v16i8_v16i32: ; LMULMAX4-LABEL: zextload_v16i8_v16i32:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; LMULMAX4-NEXT: vle8.v v12, (a0) ; LMULMAX4-NEXT: vle8.v v12, (a0)
; LMULMAX4-NEXT: vzext.vf4 v8, v12 ; LMULMAX4-NEXT: vzext.vf4 v8, v12
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <16 x i8>, ptr %x %y = load <16 x i8>, ptr %x
%z = zext <16 x i8> %y to <16 x i32> %z = zext <16 x i8> %y to <16 x i32>
ret <16 x i32> %z ret <16 x i32> %z
} }
define <16 x i64> @sextload_v16i8_v16i64(ptr %x) { define <16 x i64> @sextload_v16i8_v16i64(ptr %x) {
; LMULMAX1-LABEL: sextload_v16i8_v16i64: ; LMULMAX1-LABEL: sextload_v16i8_v16i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vle8.v v16, (a0) ; LMULMAX1-NEXT: vle8.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v8, v10
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v16, 8 ; LMULMAX1-NEXT: vslidedown.vi v11, v10, 8
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v12, v8 ; LMULMAX1-NEXT: vsext.vf8 v12, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v16, 2 ; LMULMAX1-NEXT: vslidedown.vi v13, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v9, v10 ; LMULMAX1-NEXT: vsext.vf8 v9, v13
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v11, v16, 4 ; LMULMAX1-NEXT: vslidedown.vi v15, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v10, v11 ; LMULMAX1-NEXT: vsext.vf8 v10, v15
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v14, v8, 2 ; LMULMAX1-NEXT: vslidedown.vi v14, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v13, v14 ; LMULMAX1-NEXT: vsext.vf8 v13, v14
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 4 ; LMULMAX1-NEXT: vslidedown.vi v16, v11, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v14, v8 ; LMULMAX1-NEXT: vsext.vf8 v14, v16
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v15, v11, 2 ; LMULMAX1-NEXT: vslidedown.vi v15, v15, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v11, v15 ; LMULMAX1-NEXT: vsext.vf8 v11, v15
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-NEXT: vslidedown.vi v16, v16, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf8 v15, v8 ; LMULMAX1-NEXT: vsext.vf8 v15, v16
; LMULMAX1-NEXT: vsext.vf8 v8, v16
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: sextload_v16i8_v16i64: ; LMULMAX4-LABEL: sextload_v16i8_v16i64:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX4-NEXT: vle8.v v16, (a0) ; LMULMAX4-NEXT: vle8.v v12, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vsext.vf8 v8, v12
; LMULMAX4-NEXT: vsetivli zero, 8, e8, m1, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8 ; LMULMAX4-NEXT: vslidedown.vi v16, v12, 8
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vsext.vf8 v12, v8 ; LMULMAX4-NEXT: vsext.vf8 v12, v16
; LMULMAX4-NEXT: vsext.vf8 v8, v16
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <16 x i8>, ptr %x %y = load <16 x i8>, ptr %x
%z = sext <16 x i8> %y to <16 x i64> %z = sext <16 x i8> %y to <16 x i64>
ret <16 x i64> %z ret <16 x i64> %z
} }
define <16 x i64> @zextload_v16i8_v16i64(ptr %x) { define <16 x i64> @zextload_v16i8_v16i64(ptr %x) {
; LMULMAX1-LABEL: zextload_v16i8_v16i64: ; LMULMAX1-LABEL: zextload_v16i8_v16i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vle8.v v16, (a0) ; LMULMAX1-NEXT: vle8.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v8, v10
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v16, 8 ; LMULMAX1-NEXT: vslidedown.vi v11, v10, 8
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v12, v8 ; LMULMAX1-NEXT: vzext.vf8 v12, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v16, 2 ; LMULMAX1-NEXT: vslidedown.vi v13, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v9, v10 ; LMULMAX1-NEXT: vzext.vf8 v9, v13
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v11, v16, 4 ; LMULMAX1-NEXT: vslidedown.vi v15, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v10, v11 ; LMULMAX1-NEXT: vzext.vf8 v10, v15
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v14, v8, 2 ; LMULMAX1-NEXT: vslidedown.vi v14, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v13, v14 ; LMULMAX1-NEXT: vzext.vf8 v13, v14
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 4 ; LMULMAX1-NEXT: vslidedown.vi v16, v11, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v14, v8 ; LMULMAX1-NEXT: vzext.vf8 v14, v16
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v15, v11, 2 ; LMULMAX1-NEXT: vslidedown.vi v15, v15, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v11, v15 ; LMULMAX1-NEXT: vzext.vf8 v11, v15
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-NEXT: vslidedown.vi v16, v16, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf8 v15, v8 ; LMULMAX1-NEXT: vzext.vf8 v15, v16
; LMULMAX1-NEXT: vzext.vf8 v8, v16
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: zextload_v16i8_v16i64: ; LMULMAX4-LABEL: zextload_v16i8_v16i64:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX4-NEXT: vle8.v v16, (a0) ; LMULMAX4-NEXT: vle8.v v12, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vzext.vf8 v8, v12
; LMULMAX4-NEXT: vsetivli zero, 8, e8, m1, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8 ; LMULMAX4-NEXT: vslidedown.vi v16, v12, 8
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vzext.vf8 v12, v8 ; LMULMAX4-NEXT: vzext.vf8 v12, v16
; LMULMAX4-NEXT: vzext.vf8 v8, v16
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <16 x i8>, ptr %x %y = load <16 x i8>, ptr %x
%z = zext <16 x i8> %y to <16 x i64> %z = zext <16 x i8> %y to <16 x i64>
ret <16 x i64> %z ret <16 x i64> %z
} }
define void @truncstore_v2i8_v2i1(<2 x i8> %x, ptr %z) { define void @truncstore_v2i8_v2i1(<2 x i8> %x, ptr %z) {
; CHECK-LABEL: truncstore_v2i8_v2i1: ; CHECK-LABEL: truncstore_v2i8_v2i1:
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%z = zext <4 x i16> %y to <4 x i32> %z = zext <4 x i16> %y to <4 x i32>
ret <4 x i32> %z ret <4 x i32> %z
} }
define <4 x i64> @sextload_v4i16_v4i64(ptr %x) { define <4 x i64> @sextload_v4i16_v4i64(ptr %x) {
; LMULMAX1-LABEL: sextload_v4i16_v4i64: ; LMULMAX1-LABEL: sextload_v4i16_v4i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; LMULMAX1-NEXT: vle16.v v10, (a0) ; LMULMAX1-NEXT: vle16.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v9, v8 ; LMULMAX1-NEXT: vsext.vf4 v9, v10
; LMULMAX1-NEXT: vsext.vf4 v8, v10
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: sextload_v4i16_v4i64: ; LMULMAX4-LABEL: sextload_v4i16_v4i64:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX4-NEXT: vle16.v v10, (a0) ; LMULMAX4-NEXT: vle16.v v10, (a0)
; LMULMAX4-NEXT: vsext.vf4 v8, v10 ; LMULMAX4-NEXT: vsext.vf4 v8, v10
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <4 x i16>, ptr %x %y = load <4 x i16>, ptr %x
%z = sext <4 x i16> %y to <4 x i64> %z = sext <4 x i16> %y to <4 x i64>
ret <4 x i64> %z ret <4 x i64> %z
} }
define <4 x i64> @zextload_v4i16_v4i64(ptr %x) { define <4 x i64> @zextload_v4i16_v4i64(ptr %x) {
; LMULMAX1-LABEL: zextload_v4i16_v4i64: ; LMULMAX1-LABEL: zextload_v4i16_v4i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; LMULMAX1-NEXT: vle16.v v10, (a0) ; LMULMAX1-NEXT: vle16.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v9, v8 ; LMULMAX1-NEXT: vzext.vf4 v9, v10
; LMULMAX1-NEXT: vzext.vf4 v8, v10
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: zextload_v4i16_v4i64: ; LMULMAX4-LABEL: zextload_v4i16_v4i64:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX4-NEXT: vle16.v v10, (a0) ; LMULMAX4-NEXT: vle16.v v10, (a0)
; LMULMAX4-NEXT: vzext.vf4 v8, v10 ; LMULMAX4-NEXT: vzext.vf4 v8, v10
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
Show All 13 Lines; CHECK-NEXT: ret
store <8 x i8> %y, ptr %z store <8 x i8> %y, ptr %z
ret void ret void
} }
define <8 x i32> @sextload_v8i16_v8i32(ptr %x) { define <8 x i32> @sextload_v8i16_v8i32(ptr %x) {
; LMULMAX1-LABEL: sextload_v8i16_v8i32: ; LMULMAX1-LABEL: sextload_v8i16_v8i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vle16.v v10, (a0) ; LMULMAX1-NEXT: vle16.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4 ; LMULMAX1-NEXT: vslidedown.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v9, v8 ; LMULMAX1-NEXT: vsext.vf2 v9, v10
; LMULMAX1-NEXT: vsext.vf2 v8, v10
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: sextload_v8i16_v8i32: ; LMULMAX4-LABEL: sextload_v8i16_v8i32:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX4-NEXT: vle16.v v10, (a0) ; LMULMAX4-NEXT: vle16.v v10, (a0)
; LMULMAX4-NEXT: vsext.vf2 v8, v10 ; LMULMAX4-NEXT: vsext.vf2 v8, v10
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <8 x i16>, ptr %x %y = load <8 x i16>, ptr %x
%z = sext <8 x i16> %y to <8 x i32> %z = sext <8 x i16> %y to <8 x i32>
ret <8 x i32> %z ret <8 x i32> %z
} }
define <8 x i32> @zextload_v8i16_v8i32(ptr %x) { define <8 x i32> @zextload_v8i16_v8i32(ptr %x) {
; LMULMAX1-LABEL: zextload_v8i16_v8i32: ; LMULMAX1-LABEL: zextload_v8i16_v8i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vle16.v v10, (a0) ; LMULMAX1-NEXT: vle16.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4 ; LMULMAX1-NEXT: vslidedown.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v9, v8 ; LMULMAX1-NEXT: vzext.vf2 v9, v10
; LMULMAX1-NEXT: vzext.vf2 v8, v10
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: zextload_v8i16_v8i32: ; LMULMAX4-LABEL: zextload_v8i16_v8i32:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX4-NEXT: vle16.v v10, (a0) ; LMULMAX4-NEXT: vle16.v v10, (a0)
; LMULMAX4-NEXT: vzext.vf2 v8, v10 ; LMULMAX4-NEXT: vzext.vf2 v8, v10
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <8 x i16>, ptr %x %y = load <8 x i16>, ptr %x
%z = zext <8 x i16> %y to <8 x i32> %z = zext <8 x i16> %y to <8 x i32>
ret <8 x i32> %z ret <8 x i32> %z
} }
define <8 x i64> @sextload_v8i16_v8i64(ptr %x) { define <8 x i64> @sextload_v8i16_v8i64(ptr %x) {
; LMULMAX1-LABEL: sextload_v8i16_v8i64: ; LMULMAX1-LABEL: sextload_v8i16_v8i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vle16.v v12, (a0) ; LMULMAX1-NEXT: vle16.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4 ; LMULMAX1-NEXT: vslidedown.vi v11, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v10, v8 ; LMULMAX1-NEXT: vsext.vf4 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v11, v12, 2 ; LMULMAX1-NEXT: vslidedown.vi v12, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v9, v11 ; LMULMAX1-NEXT: vsext.vf4 v9, v12
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-NEXT: vslidedown.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v11, v8 ; LMULMAX1-NEXT: vsext.vf4 v11, v12
; LMULMAX1-NEXT: vsext.vf4 v8, v12
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: sextload_v8i16_v8i64: ; LMULMAX4-LABEL: sextload_v8i16_v8i64:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vle16.v v12, (a0) ; LMULMAX4-NEXT: vle16.v v12, (a0)
; LMULMAX4-NEXT: vsext.vf4 v8, v12 ; LMULMAX4-NEXT: vsext.vf4 v8, v12
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <8 x i16>, ptr %x %y = load <8 x i16>, ptr %x
%z = sext <8 x i16> %y to <8 x i64> %z = sext <8 x i16> %y to <8 x i64>
ret <8 x i64> %z ret <8 x i64> %z
} }
define <8 x i64> @zextload_v8i16_v8i64(ptr %x) { define <8 x i64> @zextload_v8i16_v8i64(ptr %x) {
; LMULMAX1-LABEL: zextload_v8i16_v8i64: ; LMULMAX1-LABEL: zextload_v8i16_v8i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vle16.v v12, (a0) ; LMULMAX1-NEXT: vle16.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4 ; LMULMAX1-NEXT: vslidedown.vi v11, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v10, v8 ; LMULMAX1-NEXT: vzext.vf4 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v11, v12, 2 ; LMULMAX1-NEXT: vslidedown.vi v12, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v9, v11 ; LMULMAX1-NEXT: vzext.vf4 v9, v12
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-NEXT: vslidedown.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v11, v8 ; LMULMAX1-NEXT: vzext.vf4 v11, v12
; LMULMAX1-NEXT: vzext.vf4 v8, v12
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: zextload_v8i16_v8i64: ; LMULMAX4-LABEL: zextload_v8i16_v8i64:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vle16.v v12, (a0) ; LMULMAX4-NEXT: vle16.v v12, (a0)
; LMULMAX4-NEXT: vzext.vf4 v8, v12 ; LMULMAX4-NEXT: vzext.vf4 v8, v12
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
Show All 23 Lines; LMULMAX4-NEXT: ret
store <16 x i8> %y, ptr %z store <16 x i8> %y, ptr %z
ret void ret void
} }
define <16 x i32> @sextload_v16i16_v16i32(ptr %x) { define <16 x i32> @sextload_v16i16_v16i32(ptr %x) {
; LMULMAX1-LABEL: sextload_v16i16_v16i32: ; LMULMAX1-LABEL: sextload_v16i16_v16i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vle16.v v10, (a0) ; LMULMAX1-NEXT: vle16.v v9, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle16.v v12, (a0) ; LMULMAX1-NEXT: vle16.v v11, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4 ; LMULMAX1-NEXT: vslidedown.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v9, v8 ; LMULMAX1-NEXT: vsext.vf2 v9, v10
; LMULMAX1-NEXT: vsext.vf2 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4 ; LMULMAX1-NEXT: vslidedown.vi v12, v11, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v11, v8 ; LMULMAX1-NEXT: vsext.vf2 v11, v12
; LMULMAX1-NEXT: vsext.vf2 v8, v10
; LMULMAX1-NEXT: vsext.vf2 v10, v12
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: sextload_v16i16_v16i32: ; LMULMAX4-LABEL: sextload_v16i16_v16i32:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; LMULMAX4-NEXT: vle16.v v12, (a0) ; LMULMAX4-NEXT: vle16.v v12, (a0)
; LMULMAX4-NEXT: vsext.vf2 v8, v12 ; LMULMAX4-NEXT: vsext.vf2 v8, v12
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <16 x i16>, ptr %x %y = load <16 x i16>, ptr %x
%z = sext <16 x i16> %y to <16 x i32> %z = sext <16 x i16> %y to <16 x i32>
ret <16 x i32> %z ret <16 x i32> %z
} }
define <16 x i32> @zextload_v16i16_v16i32(ptr %x) { define <16 x i32> @zextload_v16i16_v16i32(ptr %x) {
; LMULMAX1-LABEL: zextload_v16i16_v16i32: ; LMULMAX1-LABEL: zextload_v16i16_v16i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vle16.v v10, (a0) ; LMULMAX1-NEXT: vle16.v v9, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle16.v v12, (a0) ; LMULMAX1-NEXT: vle16.v v11, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4 ; LMULMAX1-NEXT: vslidedown.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v9, v8 ; LMULMAX1-NEXT: vzext.vf2 v9, v10
; LMULMAX1-NEXT: vzext.vf2 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4 ; LMULMAX1-NEXT: vslidedown.vi v12, v11, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v11, v8 ; LMULMAX1-NEXT: vzext.vf2 v11, v12
; LMULMAX1-NEXT: vzext.vf2 v8, v10
; LMULMAX1-NEXT: vzext.vf2 v10, v12
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: zextload_v16i16_v16i32: ; LMULMAX4-LABEL: zextload_v16i16_v16i32:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; LMULMAX4-NEXT: vle16.v v12, (a0) ; LMULMAX4-NEXT: vle16.v v12, (a0)
; LMULMAX4-NEXT: vzext.vf2 v8, v12 ; LMULMAX4-NEXT: vzext.vf2 v8, v12
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <16 x i16>, ptr %x %y = load <16 x i16>, ptr %x
%z = zext <16 x i16> %y to <16 x i32> %z = zext <16 x i16> %y to <16 x i32>
ret <16 x i32> %z ret <16 x i32> %z
} }
define <16 x i64> @sextload_v16i16_v16i64(ptr %x) { define <16 x i64> @sextload_v16i16_v16i64(ptr %x) {
; LMULMAX1-LABEL: sextload_v16i16_v16i64: ; LMULMAX1-LABEL: sextload_v16i16_v16i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vle16.v v12, (a0) ; LMULMAX1-NEXT: vle16.v v9, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle16.v v16, (a0) ; LMULMAX1-NEXT: vle16.v v13, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4 ; LMULMAX1-NEXT: vslidedown.vi v11, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v10, v8 ; LMULMAX1-NEXT: vsext.vf4 v10, v11
; LMULMAX1-NEXT: vsext.vf4 v12, v13
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v15, v16, 4 ; LMULMAX1-NEXT: vslidedown.vi v15, v13, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v14, v15 ; LMULMAX1-NEXT: vsext.vf4 v14, v15
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v11, v12, 2 ; LMULMAX1-NEXT: vslidedown.vi v16, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v9, v11 ; LMULMAX1-NEXT: vsext.vf4 v9, v16
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-NEXT: vslidedown.vi v16, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v11, v8 ; LMULMAX1-NEXT: vsext.vf4 v11, v16
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v16, 2 ; LMULMAX1-NEXT: vslidedown.vi v16, v13, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v13, v8 ; LMULMAX1-NEXT: vsext.vf4 v13, v16
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v15, 2 ; LMULMAX1-NEXT: vslidedown.vi v16, v15, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v15, v8 ; LMULMAX1-NEXT: vsext.vf4 v15, v16
; LMULMAX1-NEXT: vsext.vf4 v8, v12
; LMULMAX1-NEXT: vsext.vf4 v12, v16
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: sextload_v16i16_v16i64: ; LMULMAX4-LABEL: sextload_v16i16_v16i64:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX4-NEXT: vle16.v v16, (a0) ; LMULMAX4-NEXT: vle16.v v12, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vsext.vf4 v8, v12
; LMULMAX4-NEXT: vsetivli zero, 8, e16, m2, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 8, e16, m2, ta, ma
; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8 ; LMULMAX4-NEXT: vslidedown.vi v16, v12, 8
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vsext.vf4 v12, v8 ; LMULMAX4-NEXT: vsext.vf4 v12, v16
; LMULMAX4-NEXT: vsext.vf4 v8, v16
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <16 x i16>, ptr %x %y = load <16 x i16>, ptr %x
%z = sext <16 x i16> %y to <16 x i64> %z = sext <16 x i16> %y to <16 x i64>
ret <16 x i64> %z ret <16 x i64> %z
} }
define <16 x i64> @zextload_v16i16_v16i64(ptr %x) { define <16 x i64> @zextload_v16i16_v16i64(ptr %x) {
; LMULMAX1-LABEL: zextload_v16i16_v16i64: ; LMULMAX1-LABEL: zextload_v16i16_v16i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vle16.v v12, (a0) ; LMULMAX1-NEXT: vle16.v v9, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle16.v v16, (a0) ; LMULMAX1-NEXT: vle16.v v13, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4 ; LMULMAX1-NEXT: vslidedown.vi v11, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v10, v8 ; LMULMAX1-NEXT: vzext.vf4 v10, v11
; LMULMAX1-NEXT: vzext.vf4 v12, v13
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v15, v16, 4 ; LMULMAX1-NEXT: vslidedown.vi v15, v13, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v14, v15 ; LMULMAX1-NEXT: vzext.vf4 v14, v15
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v11, v12, 2 ; LMULMAX1-NEXT: vslidedown.vi v16, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v9, v11 ; LMULMAX1-NEXT: vzext.vf4 v9, v16
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-NEXT: vslidedown.vi v16, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v11, v8 ; LMULMAX1-NEXT: vzext.vf4 v11, v16
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v16, 2 ; LMULMAX1-NEXT: vslidedown.vi v16, v13, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v13, v8 ; LMULMAX1-NEXT: vzext.vf4 v13, v16
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v15, 2 ; LMULMAX1-NEXT: vslidedown.vi v16, v15, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf4 v15, v8 ; LMULMAX1-NEXT: vzext.vf4 v15, v16
; LMULMAX1-NEXT: vzext.vf4 v8, v12
; LMULMAX1-NEXT: vzext.vf4 v12, v16
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: zextload_v16i16_v16i64: ; LMULMAX4-LABEL: zextload_v16i16_v16i64:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX4-NEXT: vle16.v v16, (a0) ; LMULMAX4-NEXT: vle16.v v12, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vzext.vf4 v8, v12
; LMULMAX4-NEXT: vsetivli zero, 8, e16, m2, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 8, e16, m2, ta, ma
; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8 ; LMULMAX4-NEXT: vslidedown.vi v16, v12, 8
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vzext.vf4 v12, v8 ; LMULMAX4-NEXT: vzext.vf4 v12, v16
; LMULMAX4-NEXT: vzext.vf4 v8, v16
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <16 x i16>, ptr %x %y = load <16 x i16>, ptr %x
%z = zext <16 x i16> %y to <16 x i64> %z = zext <16 x i16> %y to <16 x i64>
ret <16 x i64> %z ret <16 x i64> %z
} }
define void @truncstore_v2i32_v2i8(<2 x i32> %x, ptr %z) { define void @truncstore_v2i32_v2i8(<2 x i32> %x, ptr %z) {
; CHECK-LABEL: truncstore_v2i32_v2i8: ; CHECK-LABEL: truncstore_v2i32_v2i8:
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
store <4 x i16> %y, ptr %z store <4 x i16> %y, ptr %z
ret void ret void
} }
define <4 x i64> @sextload_v4i32_v4i64(ptr %x) { define <4 x i64> @sextload_v4i32_v4i64(ptr %x) {
; LMULMAX1-LABEL: sextload_v4i32_v4i64: ; LMULMAX1-LABEL: sextload_v4i32_v4i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vle32.v v10, (a0) ; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v9, v8 ; LMULMAX1-NEXT: vsext.vf2 v9, v10
; LMULMAX1-NEXT: vsext.vf2 v8, v10
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: sextload_v4i32_v4i64: ; LMULMAX4-LABEL: sextload_v4i32_v4i64:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX4-NEXT: vle32.v v10, (a0) ; LMULMAX4-NEXT: vle32.v v10, (a0)
; LMULMAX4-NEXT: vsext.vf2 v8, v10 ; LMULMAX4-NEXT: vsext.vf2 v8, v10
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <4 x i32>, ptr %x %y = load <4 x i32>, ptr %x
%z = sext <4 x i32> %y to <4 x i64> %z = sext <4 x i32> %y to <4 x i64>
ret <4 x i64> %z ret <4 x i64> %z
} }
define <4 x i64> @zextload_v4i32_v4i64(ptr %x) { define <4 x i64> @zextload_v4i32_v4i64(ptr %x) {
; LMULMAX1-LABEL: zextload_v4i32_v4i64: ; LMULMAX1-LABEL: zextload_v4i32_v4i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vle32.v v10, (a0) ; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v9, v8 ; LMULMAX1-NEXT: vzext.vf2 v9, v10
; LMULMAX1-NEXT: vzext.vf2 v8, v10
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: zextload_v4i32_v4i64: ; LMULMAX4-LABEL: zextload_v4i32_v4i64:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX4-NEXT: vle32.v v10, (a0) ; LMULMAX4-NEXT: vle32.v v10, (a0)
; LMULMAX4-NEXT: vzext.vf2 v8, v10 ; LMULMAX4-NEXT: vzext.vf2 v8, v10
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines; LMULMAX4-NEXT: ret
store <8 x i16> %y, ptr %z store <8 x i16> %y, ptr %z
ret void ret void
} }
define <8 x i64> @sextload_v8i32_v8i64(ptr %x) { define <8 x i64> @sextload_v8i32_v8i64(ptr %x) {
; LMULMAX1-LABEL: sextload_v8i32_v8i64: ; LMULMAX1-LABEL: sextload_v8i32_v8i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vle32.v v10, (a0) ; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle32.v v12, (a0) ; LMULMAX1-NEXT: vle32.v v11, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v9, v8 ; LMULMAX1-NEXT: vsext.vf2 v9, v10
; LMULMAX1-NEXT: vsext.vf2 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v12, 2 ; LMULMAX1-NEXT: vslidedown.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v11, v8 ; LMULMAX1-NEXT: vsext.vf2 v11, v12
; LMULMAX1-NEXT: vsext.vf2 v8, v10
; LMULMAX1-NEXT: vsext.vf2 v10, v12
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: sextload_v8i32_v8i64: ; LMULMAX4-LABEL: sextload_v8i32_v8i64:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vle32.v v12, (a0) ; LMULMAX4-NEXT: vle32.v v12, (a0)
; LMULMAX4-NEXT: vsext.vf2 v8, v12 ; LMULMAX4-NEXT: vsext.vf2 v8, v12
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <8 x i32>, ptr %x %y = load <8 x i32>, ptr %x
%z = sext <8 x i32> %y to <8 x i64> %z = sext <8 x i32> %y to <8 x i64>
ret <8 x i64> %z ret <8 x i64> %z
} }
define <8 x i64> @zextload_v8i32_v8i64(ptr %x) { define <8 x i64> @zextload_v8i32_v8i64(ptr %x) {
; LMULMAX1-LABEL: zextload_v8i32_v8i64: ; LMULMAX1-LABEL: zextload_v8i32_v8i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vle32.v v10, (a0) ; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle32.v v12, (a0) ; LMULMAX1-NEXT: vle32.v v11, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v9, v8 ; LMULMAX1-NEXT: vzext.vf2 v9, v10
; LMULMAX1-NEXT: vzext.vf2 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v12, 2 ; LMULMAX1-NEXT: vslidedown.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v11, v8 ; LMULMAX1-NEXT: vzext.vf2 v11, v12
; LMULMAX1-NEXT: vzext.vf2 v8, v10
; LMULMAX1-NEXT: vzext.vf2 v10, v12
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: zextload_v8i32_v8i64: ; LMULMAX4-LABEL: zextload_v8i32_v8i64:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vle32.v v12, (a0) ; LMULMAX4-NEXT: vle32.v v12, (a0)
; LMULMAX4-NEXT: vzext.vf2 v8, v12 ; LMULMAX4-NEXT: vzext.vf2 v8, v12
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines; LMULMAX4-NEXT: ret
ret void ret void
} }
define <16 x i64> @sextload_v16i32_v16i64(ptr %x) { define <16 x i64> @sextload_v16i32_v16i64(ptr %x) {
; LMULMAX1-LABEL: sextload_v16i32_v16i64: ; LMULMAX1-LABEL: sextload_v16i32_v16i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, a0, 48 ; LMULMAX1-NEXT: addi a1, a0, 48
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vle32.v v16, (a1) ; LMULMAX1-NEXT: vle32.v v15, (a1)
; LMULMAX1-NEXT: addi a1, a0, 32 ; LMULMAX1-NEXT: addi a1, a0, 32
; LMULMAX1-NEXT: vle32.v v14, (a1) ; LMULMAX1-NEXT: vle32.v v13, (a1)
; LMULMAX1-NEXT: vle32.v v10, (a0) ; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle32.v v12, (a0) ; LMULMAX1-NEXT: vle32.v v11, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v9, v8 ; LMULMAX1-NEXT: vsext.vf2 v9, v10
; LMULMAX1-NEXT: vsext.vf2 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v12, 2 ; LMULMAX1-NEXT: vslidedown.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v11, v8 ; LMULMAX1-NEXT: vsext.vf2 v11, v12
; LMULMAX1-NEXT: vsext.vf2 v12, v13
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v14, 2 ; LMULMAX1-NEXT: vslidedown.vi v14, v13, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v13, v8 ; LMULMAX1-NEXT: vsext.vf2 v13, v14
; LMULMAX1-NEXT: vsext.vf2 v14, v15
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v16, 2 ; LMULMAX1-NEXT: vslidedown.vi v16, v15, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v15, v8 ; LMULMAX1-NEXT: vsext.vf2 v15, v16
; LMULMAX1-NEXT: vsext.vf2 v8, v10
; LMULMAX1-NEXT: vsext.vf2 v10, v12
; LMULMAX1-NEXT: vsext.vf2 v12, v14
; LMULMAX1-NEXT: vsext.vf2 v14, v16
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: sextload_v16i32_v16i64: ; LMULMAX4-LABEL: sextload_v16i32_v16i64:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; LMULMAX4-NEXT: vle32.v v16, (a0) ; LMULMAX4-NEXT: vle32.v v12, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vsext.vf2 v8, v12
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m4, ta, ma
; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8 ; LMULMAX4-NEXT: vslidedown.vi v16, v12, 8
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vsext.vf2 v12, v8 ; LMULMAX4-NEXT: vsext.vf2 v12, v16
; LMULMAX4-NEXT: vsext.vf2 v8, v16
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <16 x i32>, ptr %x %y = load <16 x i32>, ptr %x
%z = sext <16 x i32> %y to <16 x i64> %z = sext <16 x i32> %y to <16 x i64>
ret <16 x i64> %z ret <16 x i64> %z
} }
define <16 x i64> @zextload_v16i32_v16i64(ptr %x) { define <16 x i64> @zextload_v16i32_v16i64(ptr %x) {
; LMULMAX1-LABEL: zextload_v16i32_v16i64: ; LMULMAX1-LABEL: zextload_v16i32_v16i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, a0, 48 ; LMULMAX1-NEXT: addi a1, a0, 48
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vle32.v v16, (a1) ; LMULMAX1-NEXT: vle32.v v15, (a1)
; LMULMAX1-NEXT: addi a1, a0, 32 ; LMULMAX1-NEXT: addi a1, a0, 32
; LMULMAX1-NEXT: vle32.v v14, (a1) ; LMULMAX1-NEXT: vle32.v v13, (a1)
; LMULMAX1-NEXT: vle32.v v10, (a0) ; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle32.v v12, (a0) ; LMULMAX1-NEXT: vle32.v v11, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v9, v8 ; LMULMAX1-NEXT: vzext.vf2 v9, v10
; LMULMAX1-NEXT: vzext.vf2 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v12, 2 ; LMULMAX1-NEXT: vslidedown.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v11, v8 ; LMULMAX1-NEXT: vzext.vf2 v11, v12
; LMULMAX1-NEXT: vzext.vf2 v12, v13
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v14, 2 ; LMULMAX1-NEXT: vslidedown.vi v14, v13, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v13, v8 ; LMULMAX1-NEXT: vzext.vf2 v13, v14
; LMULMAX1-NEXT: vzext.vf2 v14, v15
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v16, 2 ; LMULMAX1-NEXT: vslidedown.vi v16, v15, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v15, v8 ; LMULMAX1-NEXT: vzext.vf2 v15, v16
; LMULMAX1-NEXT: vzext.vf2 v8, v10
; LMULMAX1-NEXT: vzext.vf2 v10, v12
; LMULMAX1-NEXT: vzext.vf2 v12, v14
; LMULMAX1-NEXT: vzext.vf2 v14, v16
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: zextload_v16i32_v16i64: ; LMULMAX4-LABEL: zextload_v16i32_v16i64:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; LMULMAX4-NEXT: vle32.v v16, (a0) ; LMULMAX4-NEXT: vle32.v v12, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vzext.vf2 v8, v12
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m4, ta, ma
; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8 ; LMULMAX4-NEXT: vslidedown.vi v16, v12, 8
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; LMULMAX4-NEXT: vzext.vf2 v12, v8 ; LMULMAX4-NEXT: vzext.vf2 v12, v16
; LMULMAX4-NEXT: vzext.vf2 v8, v16
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = load <16 x i32>, ptr %x %y = load <16 x i32>, ptr %x
%z = zext <16 x i32> %y to <16 x i64> %z = zext <16 x i32> %y to <16 x i64>
ret <16 x i64> %z ret <16 x i64> %z
} }
define void @truncstore_v2i64_v2i8(<2 x i64> %x, ptr %z) { define void @truncstore_v2i64_v2i8(<2 x i64> %x, ptr %z) {
; CHECK-LABEL: truncstore_v2i64_v2i8: ; CHECK-LABEL: truncstore_v2i64_v2i8:
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll

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; CHECK-NEXT: ret ; CHECK-NEXT: ret
store <2 x float> <float 1.0, float 2.0>, <2 x float>* %x store <2 x float> <float 1.0, float 2.0>, <2 x float>* %x
ret void ret void
} }
define void @buildvec_dominant0_v4f32(<4 x float>* %x) { define void @buildvec_dominant0_v4f32(<4 x float>* %x) {
; CHECK-LABEL: buildvec_dominant0_v4f32: ; CHECK-LABEL: buildvec_dominant0_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: lui a1, 262144 ; CHECK-NEXT: lui a1, 262144
; CHECK-NEXT: vmv.v.x v9, a1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, ma ; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, ma
; CHECK-NEXT: vslideup.vi v9, v8, 2 ; CHECK-NEXT: vslideup.vi v8, v9, 2
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
store <4 x float> <float 2.0, float 2.0, float 0.0, float 2.0>, <4 x float>* %x store <4 x float> <float 2.0, float 2.0, float 0.0, float 2.0>, <4 x float>* %x
ret void ret void
} }
define void @buildvec_dominant1_v4f32(<4 x float>* %x, float %f) { define void @buildvec_dominant1_v4f32(<4 x float>* %x, float %f) {
; CHECK-LABEL: buildvec_dominant1_v4f32: ; CHECK-LABEL: buildvec_dominant1_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v8, zero ; CHECK-NEXT: vfmv.v.f v8, fa0
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma ; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = insertelement <4 x float> poison, float %f, i32 0 %v0 = insertelement <4 x float> poison, float %f, i32 0
%v1 = insertelement <4 x float> %v0, float 0.0, i32 1 %v1 = insertelement <4 x float> %v0, float 0.0, i32 1
%v2 = insertelement <4 x float> %v1, float %f, i32 2 %v2 = insertelement <4 x float> %v1, float %f, i32 2
%v3 = insertelement <4 x float> %v2, float %f, i32 3 %v3 = insertelement <4 x float> %v2, float %f, i32 3
store <4 x float> %v3, <4 x float>* %x store <4 x float> %v3, <4 x float>* %x
ret void ret void
} }
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll

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; LMULMAX8-NEXT: vfwcvt.f.f.v v10, v8 ; LMULMAX8-NEXT: vfwcvt.f.f.v v10, v8
; LMULMAX8-NEXT: vse32.v v10, (a1) ; LMULMAX8-NEXT: vse32.v v10, (a1)
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX1-LABEL: fpext_v8f16_v8f32: ; LMULMAX1-LABEL: fpext_v8f16_v8f32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vle16.v v8, (a0) ; LMULMAX1-NEXT: vle16.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v9, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.f.f.v v10, v9
; LMULMAX1-NEXT: vfwcvt.f.f.v v9, v8 ; LMULMAX1-NEXT: vfwcvt.f.f.v v9, v8
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.f.f.v v10, v8
; LMULMAX1-NEXT: addi a0, a1, 16 ; LMULMAX1-NEXT: addi a0, a1, 16
; LMULMAX1-NEXT: vse32.v v10, (a0) ; LMULMAX1-NEXT: vse32.v v10, (a0)
; LMULMAX1-NEXT: vse32.v v9, (a1) ; LMULMAX1-NEXT: vse32.v v9, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x half>, ptr %x %a = load <8 x half>, ptr %x
%d = fpext <8 x half> %a to <8 x float> %d = fpext <8 x half> %a to <8 x float>
store <8 x float> %d, ptr %y store <8 x float> %d, ptr %y
ret void ret void
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; LMULMAX1-NEXT: vslidedown.vi v10, v8, 4 ; LMULMAX1-NEXT: vslidedown.vi v10, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v11, v10, 2 ; LMULMAX1-NEXT: vslidedown.vi v11, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; LMULMAX1-NEXT: vfwcvt.f.f.v v12, v11 ; LMULMAX1-NEXT: vfwcvt.f.f.v v12, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.f.f.v v11, v12 ; LMULMAX1-NEXT: vfwcvt.f.f.v v11, v12
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; LMULMAX1-NEXT: vfwcvt.f.f.v v12, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.f.f.v v10, v12
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; LMULMAX1-NEXT: vfwcvt.f.f.v v12, v8 ; LMULMAX1-NEXT: vfwcvt.f.f.v v12, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.f.f.v v8, v12 ; LMULMAX1-NEXT: vfwcvt.f.f.v v8, v12
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; LMULMAX1-NEXT: vfwcvt.f.f.v v12, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.f.f.v v10, v12
; LMULMAX1-NEXT: addi a0, a1, 32 ; LMULMAX1-NEXT: addi a0, a1, 32
; LMULMAX1-NEXT: vse64.v v10, (a0) ; LMULMAX1-NEXT: vse64.v v10, (a0)
; LMULMAX1-NEXT: vse64.v v8, (a1) ; LMULMAX1-NEXT: vse64.v v8, (a1)
; LMULMAX1-NEXT: addi a0, a1, 48 ; LMULMAX1-NEXT: addi a0, a1, 48
; LMULMAX1-NEXT: vse64.v v11, (a0) ; LMULMAX1-NEXT: vse64.v v11, (a0)
; LMULMAX1-NEXT: addi a1, a1, 16 ; LMULMAX1-NEXT: addi a1, a1, 16
; LMULMAX1-NEXT: vse64.v v9, (a1) ; LMULMAX1-NEXT: vse64.v v9, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll

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; LMULMAX2-NEXT: vmv.v.i v8, 0 ; LMULMAX2-NEXT: vmv.v.i v8, 0
; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: splat_zero_16f16: ; LMULMAX1-LABEL: splat_zero_16f16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vmv.v.i v8, 0 ; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vse16.v v8, (a1)
; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = insertelement <16 x half> poison, half 0.0, i32 0 %a = insertelement <16 x half> poison, half 0.0, i32 0
%b = shufflevector <16 x half> %a, <16 x half> poison, <16 x i32> zeroinitializer %b = shufflevector <16 x half> %a, <16 x half> poison, <16 x i32> zeroinitializer
store <16 x half> %b, ptr %x store <16 x half> %b, ptr %x
ret void ret void
} }
define void @splat_zero_v8f32(ptr %x) { define void @splat_zero_v8f32(ptr %x) {
; LMULMAX2-LABEL: splat_zero_v8f32: ; LMULMAX2-LABEL: splat_zero_v8f32:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-NEXT: vmv.v.i v8, 0 ; LMULMAX2-NEXT: vmv.v.i v8, 0
; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: splat_zero_v8f32: ; LMULMAX1-LABEL: splat_zero_v8f32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vmv.v.i v8, 0 ; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vse32.v v8, (a1)
; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = insertelement <8 x float> poison, float 0.0, i32 0 %a = insertelement <8 x float> poison, float 0.0, i32 0
%b = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> zeroinitializer %b = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> zeroinitializer
store <8 x float> %b, ptr %x store <8 x float> %b, ptr %x
ret void ret void
} }
define void @splat_zero_v4f64(ptr %x) { define void @splat_zero_v4f64(ptr %x) {
; LMULMAX2-LABEL: splat_zero_v4f64: ; LMULMAX2-LABEL: splat_zero_v4f64:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-NEXT: vmv.v.i v8, 0 ; LMULMAX2-NEXT: vmv.v.i v8, 0
; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: splat_zero_v4f64: ; LMULMAX1-LABEL: splat_zero_v4f64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vmv.v.i v8, 0 ; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vse64.v v8, (a0) ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vse64.v v8, (a1)
; LMULMAX1-NEXT: vse64.v v8, (a0) ; LMULMAX1-NEXT: vse64.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = insertelement <4 x double> poison, double 0.0, i32 0 %a = insertelement <4 x double> poison, double 0.0, i32 0
%b = shufflevector <4 x double> %a, <4 x double> poison, <4 x i32> zeroinitializer %b = shufflevector <4 x double> %a, <4 x double> poison, <4 x i32> zeroinitializer
store <4 x double> %b, ptr %x store <4 x double> %b, ptr %x
ret void ret void
} }
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll

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} }
declare <8 x i32> @llvm.fptoui.sat.v8i32.v8f32(<8 x float>) declare <8 x i32> @llvm.fptoui.sat.v8i32.v8f32(<8 x float>)
define void @fp2si_v2f32_v2i64(ptr %x, ptr %y) { define void @fp2si_v2f32_v2i64(ptr %x, ptr %y) {
; CHECK-LABEL: fp2si_v2f32_v2i64: ; CHECK-LABEL: fp2si_v2f32_v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v9, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v9, 0, v0
; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x float>, ptr %x %a = load <2 x float>, ptr %x
%d = call <2 x i64> @llvm.fptosi.sat.v2i64.v2f32(<2 x float> %a) %d = call <2 x i64> @llvm.fptosi.sat.v2i64.v2f32(<2 x float> %a)
store <2 x i64> %d, ptr %y store <2 x i64> %d, ptr %y
ret void ret void
} }
declare <2 x i64> @llvm.fptosi.sat.v2i64.v2f32(<2 x float>) declare <2 x i64> @llvm.fptosi.sat.v2i64.v2f32(<2 x float>)
define void @fp2ui_v2f32_v2i64(ptr %x, ptr %y) { define void @fp2ui_v2f32_v2i64(ptr %x, ptr %y) {
; CHECK-LABEL: fp2ui_v2f32_v2i64: ; CHECK-LABEL: fp2ui_v2f32_v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8 ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v9, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v9, 0, v0
; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x float>, ptr %x %a = load <2 x float>, ptr %x
%d = call <2 x i64> @llvm.fptoui.sat.v2i64.v2f32(<2 x float> %a) %d = call <2 x i64> @llvm.fptoui.sat.v2i64.v2f32(<2 x float> %a)
store <2 x i64> %d, ptr %y store <2 x i64> %d, ptr %y
ret void ret void
} }
declare <2 x i64> @llvm.fptoui.sat.v2i64.v2f32(<2 x float>) declare <2 x i64> @llvm.fptoui.sat.v2i64.v2f32(<2 x float>)
define void @fp2si_v8f32_v8i64(ptr %x, ptr %y) { define void @fp2si_v8f32_v8i64(ptr %x, ptr %y) {
; ;
; CHECK-LABEL: fp2si_v8f32_v8i64: ; CHECK-LABEL: fp2si_v8f32_v8i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8 ; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <8 x float>, ptr %x %a = load <8 x float>, ptr %x
%d = call <8 x i64> @llvm.fptosi.sat.v8i64.v8f32(<8 x float> %a) %d = call <8 x i64> @llvm.fptosi.sat.v8i64.v8f32(<8 x float> %a)
store <8 x i64> %d, ptr %y store <8 x i64> %d, ptr %y
ret void ret void
} }
declare <8 x i64> @llvm.fptosi.sat.v8i64.v8f32(<8 x float>) declare <8 x i64> @llvm.fptosi.sat.v8i64.v8f32(<8 x float>)
define void @fp2ui_v8f32_v8i64(ptr %x, ptr %y) { define void @fp2ui_v8f32_v8i64(ptr %x, ptr %y) {
; ;
; CHECK-LABEL: fp2ui_v8f32_v8i64: ; CHECK-LABEL: fp2ui_v8f32_v8i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8 ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <8 x float>, ptr %x %a = load <8 x float>, ptr %x
%d = call <8 x i64> @llvm.fptoui.sat.v8i64.v8f32(<8 x float> %a) %d = call <8 x i64> @llvm.fptoui.sat.v8i64.v8f32(<8 x float> %a)
store <8 x i64> %d, ptr %y store <8 x i64> %d, ptr %y
ret void ret void
} }
declare <8 x i64> @llvm.fptoui.sat.v8i64.v8f32(<8 x float>) declare <8 x i64> @llvm.fptoui.sat.v8i64.v8f32(<8 x float>)
define void @fp2si_v2f16_v2i64(ptr %x, ptr %y) { define void @fp2si_v2f16_v2i64(ptr %x, ptr %y) {
; CHECK-LABEL: fp2si_v2f16_v2i64: ; CHECK-LABEL: fp2si_v2f16_v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vfwcvt.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9 ; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v9
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x half>, ptr %x %a = load <2 x half>, ptr %x
%d = call <2 x i64> @llvm.fptosi.sat.v2i64.v2f16(<2 x half> %a) %d = call <2 x i64> @llvm.fptosi.sat.v2i64.v2f16(<2 x half> %a)
store <2 x i64> %d, ptr %y store <2 x i64> %d, ptr %y
ret void ret void
} }
declare <2 x i64> @llvm.fptosi.sat.v2i64.v2f16(<2 x half>) declare <2 x i64> @llvm.fptosi.sat.v2i64.v2f16(<2 x half>)
define void @fp2ui_v2f16_v2i64(ptr %x, ptr %y) { define void @fp2ui_v2f16_v2i64(ptr %x, ptr %y) {
; CHECK-LABEL: fp2ui_v2f16_v2i64: ; CHECK-LABEL: fp2ui_v2f16_v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vfwcvt.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9 ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v9
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x half>, ptr %x %a = load <2 x half>, ptr %x
%d = call <2 x i64> @llvm.fptoui.sat.v2i64.v2f16(<2 x half> %a) %d = call <2 x i64> @llvm.fptoui.sat.v2i64.v2f16(<2 x half> %a)
store <2 x i64> %d, ptr %y store <2 x i64> %d, ptr %y
ret void ret void
} }
declare <2 x i64> @llvm.fptoui.sat.v2i64.v2f16(<2 x half>) declare <2 x i64> @llvm.fptoui.sat.v2i64.v2f16(<2 x half>)
▲ Show 20 Lines • Show All 468 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
store <8 x i8> %d, ptr %y store <8 x i8> %d, ptr %y
ret void ret void
} }
declare <8 x i8> @llvm.fptoui.sat.v8i8.v8f64(<8 x double> %a) declare <8 x i8> @llvm.fptoui.sat.v8i8.v8f64(<8 x double> %a)
define void @fp2si_v2f64_v2i32(ptr %x, ptr %y) { define void @fp2si_v2f64_v2i32(ptr %x, ptr %y) {
; CHECK-LABEL: fp2si_v2f64_v2i32: ; CHECK-LABEL: fp2si_v2f64_v2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vmerge.vim v8, v9, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v9, 0, v0
; CHECK-NEXT: vse32.v v8, (a1) ; CHECK-NEXT: vse32.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, ptr %x %a = load <2 x double>, ptr %x
%d = call <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double> %a) %d = call <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double> %a)
store <2 x i32> %d, ptr %y store <2 x i32> %d, ptr %y
ret void ret void
} }
declare <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double>) declare <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double>)
define void @fp2ui_v2f64_v2i32(ptr %x, ptr %y) { define void @fp2ui_v2f64_v2i32(ptr %x, ptr %y) {
; CHECK-LABEL: fp2ui_v2f64_v2i32: ; CHECK-LABEL: fp2ui_v2f64_v2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
; CHECK-NEXT: vmerge.vim v8, v9, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v9, 0, v0
; CHECK-NEXT: vse32.v v8, (a1) ; CHECK-NEXT: vse32.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, ptr %x %a = load <2 x double>, ptr %x
%d = call <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double> %a) %d = call <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double> %a)
store <2 x i32> %d, ptr %y store <2 x i32> %d, ptr %y
ret void ret void
} }
declare <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double>) declare <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double>)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll

Show First 20 Lines • Show All 485 Lines • ▼ Show 20 Lines
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX1-LABEL: fp2si_v8f32_v8i64: ; LMULMAX1-LABEL: fp2si_v8f32_v8i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: addi a2, a0, 16 ; LMULMAX1-NEXT: addi a2, a0, 16
; LMULMAX1-NEXT: vle32.v v8, (a2) ; LMULMAX1-NEXT: vle32.v v8, (a2)
; LMULMAX1-NEXT: vle32.v v9, (a0) ; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v11, v10 ; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v10, v8
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2 ; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v12, v10 ; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v11, v8
; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v10, v8
; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v8, v9 ; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v9, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v12, v9
; LMULMAX1-NEXT: addi a0, a1, 16 ; LMULMAX1-NEXT: addi a0, a1, 16
; LMULMAX1-NEXT: vse64.v v12, (a0) ; LMULMAX1-NEXT: vse64.v v12, (a0)
; LMULMAX1-NEXT: vse64.v v8, (a1) ; LMULMAX1-NEXT: vse64.v v8, (a1)
; LMULMAX1-NEXT: addi a0, a1, 48 ; LMULMAX1-NEXT: addi a0, a1, 48
; LMULMAX1-NEXT: vse64.v v11, (a0) ; LMULMAX1-NEXT: vse64.v v11, (a0)
; LMULMAX1-NEXT: addi a0, a1, 32 ; LMULMAX1-NEXT: addi a0, a1, 32
; LMULMAX1-NEXT: vse64.v v10, (a0) ; LMULMAX1-NEXT: vse64.v v10, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
Show All 13 Lines
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX1-LABEL: fp2ui_v8f32_v8i64: ; LMULMAX1-LABEL: fp2ui_v8f32_v8i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: addi a2, a0, 16 ; LMULMAX1-NEXT: addi a2, a0, 16
; LMULMAX1-NEXT: vle32.v v8, (a2) ; LMULMAX1-NEXT: vle32.v v8, (a2)
; LMULMAX1-NEXT: vle32.v v9, (a0) ; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v11, v10 ; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v10, v8
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2 ; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v12, v10 ; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v11, v8
; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v10, v8
; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v8, v9 ; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v8, v9
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v9, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v12, v9
; LMULMAX1-NEXT: addi a0, a1, 16 ; LMULMAX1-NEXT: addi a0, a1, 16
; LMULMAX1-NEXT: vse64.v v12, (a0) ; LMULMAX1-NEXT: vse64.v v12, (a0)
; LMULMAX1-NEXT: vse64.v v8, (a1) ; LMULMAX1-NEXT: vse64.v v8, (a1)
; LMULMAX1-NEXT: addi a0, a1, 48 ; LMULMAX1-NEXT: addi a0, a1, 48
; LMULMAX1-NEXT: vse64.v v11, (a0) ; LMULMAX1-NEXT: vse64.v v11, (a0)
; LMULMAX1-NEXT: addi a0, a1, 32 ; LMULMAX1-NEXT: addi a0, a1, 32
; LMULMAX1-NEXT: vse64.v v10, (a0) ; LMULMAX1-NEXT: vse64.v v10, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
▲ Show 20 Lines • Show All 351 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll

Show First 20 Lines • Show All 793 Lines • ▼ Show 20 Lines
declare <16 x i64> @llvm.vp.fshr.v16i64(<16 x i64>, <16 x i64>, <16 x i64>, <16 x i1>, i32) declare <16 x i64> @llvm.vp.fshr.v16i64(<16 x i64>, <16 x i64>, <16 x i64>, <16 x i1>, i32)
define <16 x i64> @fshr_v16i64(<16 x i64> %a, <16 x i64> %b, <16 x i64> %c, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @fshr_v16i64(<16 x i64> %a, <16 x i64> %b, <16 x i64> %c, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: fshr_v16i64: ; RV32-LABEL: fshr_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 3 ; RV32-NEXT: slli a2, a2, 4
; RV32-NEXT: sub sp, sp, a2 ; RV32-NEXT: sub sp, sp, a2
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vle64.v v24, (a0) ; RV32-NEXT: vle64.v v24, (a0)
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: li a0, 63 ; RV32-NEXT: li a0, 63
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vx v8, v24, a0, v0.t ; RV32-NEXT: vand.vx v8, v24, a0, v0.t
; RV32-NEXT: vsrl.vv v16, v16, v8, v0.t ; RV32-NEXT: vsrl.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV32-NEXT: addi a2, sp, 16
; RV32-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload
; RV32-NEXT: vsll.vi v16, v8, 1, v0.t
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v8, -1 ; RV32-NEXT: vmv.v.i v8, -1
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vxor.vv v8, v24, v8, v0.t ; RV32-NEXT: vxor.vv v8, v24, v8, v0.t
; RV32-NEXT: vand.vx v8, v8, a0, v0.t ; RV32-NEXT: vand.vx v8, v8, a0, v0.t
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: vsll.vv v8, v16, v8, v0.t
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsll.vi v24, v24, 1, v0.t
; RV32-NEXT: vsll.vv v8, v24, v8, v0.t
; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: fshr_v16i64: ; RV64-LABEL: fshr_v16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
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declare <16 x i64> @llvm.vp.fshl.v16i64(<16 x i64>, <16 x i64>, <16 x i64>, <16 x i1>, i32) declare <16 x i64> @llvm.vp.fshl.v16i64(<16 x i64>, <16 x i64>, <16 x i64>, <16 x i1>, i32)
define <16 x i64> @fshl_v16i64(<16 x i64> %a, <16 x i64> %b, <16 x i64> %c, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @fshl_v16i64(<16 x i64> %a, <16 x i64> %b, <16 x i64> %c, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: fshl_v16i64: ; RV32-LABEL: fshl_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 3 ; RV32-NEXT: slli a2, a2, 4
; RV32-NEXT: sub sp, sp, a2 ; RV32-NEXT: sub sp, sp, a2
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vle64.v v24, (a0) ; RV32-NEXT: vle64.v v24, (a0)
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vmv8r.v v16, v8 ; RV32-NEXT: vmv8r.v v16, v8
; RV32-NEXT: li a0, 63 ; RV32-NEXT: li a0, 63
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vx v8, v24, a0, v0.t ; RV32-NEXT: vand.vx v8, v24, a0, v0.t
; RV32-NEXT: vsll.vv v8, v16, v8, v0.t ; RV32-NEXT: vsll.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV32-NEXT: addi a2, sp, 16
; RV32-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v16, -1 ; RV32-NEXT: vmv.v.i v8, -1
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vxor.vv v16, v24, v16, v0.t ; RV32-NEXT: vxor.vv v8, v24, v8, v0.t
; RV32-NEXT: vand.vx v16, v16, a0, v0.t ; RV32-NEXT: vand.vx v8, v8, a0, v0.t
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: vsrl.vv v8, v16, v8, v0.t
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsrl.vi v24, v24, 1, v0.t
; RV32-NEXT: vsrl.vv v16, v24, v16, v0.t
; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: fshl_v16i64: ; RV64-LABEL: fshl_v16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
Show All 28 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll

Show First 20 Lines • Show All 450 Lines • ▼ Show 20 Lines
; LMULMAX1-NEXT: vfwcvt.f.x.v v9, v10 ; LMULMAX1-NEXT: vfwcvt.f.x.v v9, v10
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v8, 4 ; LMULMAX1-NEXT: vslidedown.vi v10, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v11, v10, 2 ; LMULMAX1-NEXT: vslidedown.vi v11, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1-NEXT: vsext.vf2 v12, v11 ; LMULMAX1-NEXT: vsext.vf2 v12, v11
; LMULMAX1-NEXT: vfwcvt.f.x.v v11, v12 ; LMULMAX1-NEXT: vfwcvt.f.x.v v11, v12
; LMULMAX1-NEXT: vsext.vf2 v12, v10
; LMULMAX1-NEXT: vfwcvt.f.x.v v10, v12
; LMULMAX1-NEXT: vsext.vf2 v12, v8 ; LMULMAX1-NEXT: vsext.vf2 v12, v8
; LMULMAX1-NEXT: vfwcvt.f.x.v v8, v12 ; LMULMAX1-NEXT: vfwcvt.f.x.v v8, v12
; LMULMAX1-NEXT: vsext.vf2 v12, v10
; LMULMAX1-NEXT: vfwcvt.f.x.v v10, v12
; LMULMAX1-NEXT: addi a0, a1, 32 ; LMULMAX1-NEXT: addi a0, a1, 32
; LMULMAX1-NEXT: vse64.v v10, (a0) ; LMULMAX1-NEXT: vse64.v v10, (a0)
; LMULMAX1-NEXT: vse64.v v8, (a1) ; LMULMAX1-NEXT: vse64.v v8, (a1)
; LMULMAX1-NEXT: addi a0, a1, 48 ; LMULMAX1-NEXT: addi a0, a1, 48
; LMULMAX1-NEXT: vse64.v v11, (a0) ; LMULMAX1-NEXT: vse64.v v11, (a0)
; LMULMAX1-NEXT: addi a1, a1, 16 ; LMULMAX1-NEXT: addi a1, a1, 16
; LMULMAX1-NEXT: vse64.v v9, (a1) ; LMULMAX1-NEXT: vse64.v v9, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
Show All 24 Lines
; LMULMAX1-NEXT: vfwcvt.f.xu.v v9, v10 ; LMULMAX1-NEXT: vfwcvt.f.xu.v v9, v10
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v10, v8, 4 ; LMULMAX1-NEXT: vslidedown.vi v10, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v11, v10, 2 ; LMULMAX1-NEXT: vslidedown.vi v11, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1-NEXT: vzext.vf2 v12, v11 ; LMULMAX1-NEXT: vzext.vf2 v12, v11
; LMULMAX1-NEXT: vfwcvt.f.xu.v v11, v12 ; LMULMAX1-NEXT: vfwcvt.f.xu.v v11, v12
; LMULMAX1-NEXT: vzext.vf2 v12, v10
; LMULMAX1-NEXT: vfwcvt.f.xu.v v10, v12
; LMULMAX1-NEXT: vzext.vf2 v12, v8 ; LMULMAX1-NEXT: vzext.vf2 v12, v8
; LMULMAX1-NEXT: vfwcvt.f.xu.v v8, v12 ; LMULMAX1-NEXT: vfwcvt.f.xu.v v8, v12
; LMULMAX1-NEXT: vzext.vf2 v12, v10
; LMULMAX1-NEXT: vfwcvt.f.xu.v v10, v12
; LMULMAX1-NEXT: addi a0, a1, 32 ; LMULMAX1-NEXT: addi a0, a1, 32
; LMULMAX1-NEXT: vse64.v v10, (a0) ; LMULMAX1-NEXT: vse64.v v10, (a0)
; LMULMAX1-NEXT: vse64.v v8, (a1) ; LMULMAX1-NEXT: vse64.v v8, (a1)
; LMULMAX1-NEXT: addi a0, a1, 48 ; LMULMAX1-NEXT: addi a0, a1, 48
; LMULMAX1-NEXT: vse64.v v11, (a0) ; LMULMAX1-NEXT: vse64.v v11, (a0)
; LMULMAX1-NEXT: addi a1, a1, 16 ; LMULMAX1-NEXT: addi a1, a1, 16
; LMULMAX1-NEXT: vse64.v v9, (a1) ; LMULMAX1-NEXT: vse64.v v9, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
▲ Show 20 Lines • Show All 287 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%y = insertelement <8 x i1> %x, i1 %elt, i32 %idx %y = insertelement <8 x i1> %x, i1 %elt, i32 %idx
ret <8 x i1> %y ret <8 x i1> %y
} }
define <64 x i1> @insertelt_v64i1(<64 x i1> %x, i1 %elt) nounwind { define <64 x i1> @insertelt_v64i1(<64 x i1> %x, i1 %elt) nounwind {
; CHECK-LABEL: insertelt_v64i1: ; CHECK-LABEL: insertelt_v64i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: vsetivli zero, 2, e8, m4, tu, ma ; CHECK-NEXT: vsetivli zero, 2, e8, m4, tu, ma
; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: vslideup.vi v12, v8, 1
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v12, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <64 x i1> %x, i1 %elt, i64 1 %y = insertelement <64 x i1> %x, i1 %elt, i64 1
ret <64 x i1> %y ret <64 x i1> %y
} }
define <64 x i1> @insertelt_idx_v64i1(<64 x i1> %x, i1 %elt, i32 zeroext %idx) nounwind { define <64 x i1> @insertelt_idx_v64i1(<64 x i1> %x, i1 %elt, i32 zeroext %idx) nounwind {
; CHECK-LABEL: insertelt_idx_v64i1: ; CHECK-LABEL: insertelt_idx_v64i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 64 ; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, ma
; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma
; CHECK-NEXT: vslideup.vx v8, v12, a1 ; CHECK-NEXT: vslideup.vx v12, v8, a1
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v12, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <64 x i1> %x, i1 %elt, i32 %idx %y = insertelement <64 x i1> %x, i1 %elt, i32 %idx
ret <64 x i1> %y ret <64 x i1> %y
} }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32: {{.*}} ; RV32: {{.*}}
; RV64: {{.*}} ; RV64: {{.*}}

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll

Show First 20 Lines • Show All 452 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <vscale x 2 x i16> %c ret <vscale x 2 x i16> %c
} }
define <vscale x 2 x i1> @insert_nxv2i1_v4i1_0(<vscale x 2 x i1> %v, ptr %svp) { define <vscale x 2 x i1> @insert_nxv2i1_v4i1_0(<vscale x 2 x i1> %v, ptr %svp) {
; CHECK-LABEL: insert_nxv2i1_v4i1_0: ; CHECK-LABEL: insert_nxv2i1_v4i1_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vlm.v v8, (a0) ; CHECK-NEXT: vlm.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, tu, ma ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmerge.vim v9, v10, 1, v0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, tu, ma
; CHECK-NEXT: vmv.v.v v9, v8 ; CHECK-NEXT: vmv.v.v v9, v8
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <4 x i1>, ptr %svp %sv = load <4 x i1>, ptr %svp
%c = call <vscale x 2 x i1> @llvm.vector.insert.v4i1.nxv2i1(<vscale x 2 x i1> %v, <4 x i1> %sv, i64 0) %c = call <vscale x 2 x i1> @llvm.vector.insert.v4i1.nxv2i1(<vscale x 2 x i1> %v, <4 x i1> %sv, i64 0)
ret <vscale x 2 x i1> %c ret <vscale x 2 x i1> %c
} }
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

Show First 20 Lines • Show All 148 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
ret <4 x i8> <i8 3, i8 1, i8 -1, i8 -3> ret <4 x i8> <i8 3, i8 1, i8 -1, i8 -3>
} }
define <4 x i8> @buildvec_vid_stepn3_add3_v4i8() { define <4 x i8> @buildvec_vid_stepn3_add3_v4i8() {
; CHECK-LABEL: buildvec_vid_stepn3_add3_v4i8: ; CHECK-LABEL: buildvec_vid_stepn3_add3_v4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vid.v v9 ; CHECK-NEXT: vmv.v.i v9, 3
; CHECK-NEXT: vmv.v.i v8, 3 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: li a0, -3 ; CHECK-NEXT: li a0, -3
; CHECK-NEXT: vmacc.vx v8, a0, v9 ; CHECK-NEXT: vmadd.vx v8, a0, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
ret <4 x i8> <i8 3, i8 0, i8 -3, i8 -6> ret <4 x i8> <i8 3, i8 0, i8 -3, i8 -6>
} }
define void @buildvec_vid_stepn3_addn3_v4i32(ptr %z0, ptr %z1, ptr %z2, ptr %z3) { define void @buildvec_vid_stepn3_addn3_v4i32(ptr %z0, ptr %z1, ptr %z2, ptr %z3) {
; CHECK-LABEL: buildvec_vid_stepn3_addn3_v4i32: ; CHECK-LABEL: buildvec_vid_stepn3_addn3_v4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vmv.v.i v8, -3
; CHECK-NEXT: vmv.v.i v9, -3 ; CHECK-NEXT: vid.v v9
; CHECK-NEXT: li a4, -3 ; CHECK-NEXT: li a4, -3
; CHECK-NEXT: vmacc.vx v9, a4, v8 ; CHECK-NEXT: vmadd.vx v9, a4, v8
; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: vse32.v v9, (a1) ; CHECK-NEXT: vse32.v v9, (a1)
; CHECK-NEXT: vse32.v v9, (a2) ; CHECK-NEXT: vse32.v v9, (a2)
; CHECK-NEXT: vse32.v v9, (a3) ; CHECK-NEXT: vse32.v v9, (a3)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
store <4 x i32> <i32 -3, i32 -6, i32 -9, i32 -12>, ptr %z0 store <4 x i32> <i32 -3, i32 -6, i32 -9, i32 -12>, ptr %z0
store <4 x i32> <i32 undef, i32 -6, i32 -9, i32 -12>, ptr %z1 store <4 x i32> <i32 undef, i32 -6, i32 -9, i32 -12>, ptr %z1
store <4 x i32> <i32 undef, i32 undef, i32 -9, i32 -12>, ptr %z2 store <4 x i32> <i32 undef, i32 undef, i32 -9, i32 -12>, ptr %z2
▲ Show 20 Lines • Show All 494 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; LMULMAX2-NEXT: vsext.vf4 v10, v8 ; LMULMAX2-NEXT: vsext.vf4 v10, v8
; LMULMAX2-NEXT: vse32.v v10, (a1) ; LMULMAX2-NEXT: vse32.v v10, (a1)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: sext_v8i8_v8i32: ; LMULMAX1-LABEL: sext_v8i8_v8i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; LMULMAX1-NEXT: vle8.v v8, (a0) ; LMULMAX1-NEXT: vle8.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v9, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v10, v9
; LMULMAX1-NEXT: vsext.vf4 v9, v8 ; LMULMAX1-NEXT: vsext.vf4 v9, v8
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v10, v8
; LMULMAX1-NEXT: addi a0, a1, 16 ; LMULMAX1-NEXT: addi a0, a1, 16
; LMULMAX1-NEXT: vse32.v v10, (a0) ; LMULMAX1-NEXT: vse32.v v10, (a0)
; LMULMAX1-NEXT: vse32.v v9, (a1) ; LMULMAX1-NEXT: vse32.v v9, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x i8>, ptr %x %a = load <8 x i8>, ptr %x
%b = sext <8 x i8> %a to <8 x i32> %b = sext <8 x i8> %a to <8 x i32>
store <8 x i32> %b, ptr %z store <8 x i32> %b, ptr %z
ret void ret void
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v14, v12 ; LMULMAX1-NEXT: vsext.vf4 v14, v12
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v12, v9, 8 ; LMULMAX1-NEXT: vslidedown.vi v12, v9, 8
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v15, v12, 4 ; LMULMAX1-NEXT: vslidedown.vi v15, v12, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vsext.vf4 v16, v15 ; LMULMAX1-NEXT: vsext.vf4 v16, v15
; LMULMAX1-NEXT: vsext.vf4 v15, v10 ; LMULMAX1-NEXT: vsext.vf4 v15, v8
; LMULMAX1-NEXT: vsext.vf4 v10, v12 ; LMULMAX1-NEXT: vsext.vf4 v8, v10
; LMULMAX1-NEXT: vsext.vf4 v12, v8 ; LMULMAX1-NEXT: vsext.vf4 v10, v9
; LMULMAX1-NEXT: vsext.vf4 v8, v9 ; LMULMAX1-NEXT: vsext.vf4 v9, v12
; LMULMAX1-NEXT: addi a0, a1, 32 ; LMULMAX1-NEXT: addi a0, a1, 32
; LMULMAX1-NEXT: vse32.v v10, (a0) ; LMULMAX1-NEXT: vse32.v v9, (a0)
; LMULMAX1-NEXT: vse32.v v8, (a1) ; LMULMAX1-NEXT: vse32.v v10, (a1)
; LMULMAX1-NEXT: addi a0, a1, 96 ; LMULMAX1-NEXT: addi a0, a1, 96
; LMULMAX1-NEXT: vse32.v v15, (a0) ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: addi a0, a1, 64 ; LMULMAX1-NEXT: addi a0, a1, 64
; LMULMAX1-NEXT: vse32.v v12, (a0) ; LMULMAX1-NEXT: vse32.v v15, (a0)
; LMULMAX1-NEXT: addi a0, a1, 48 ; LMULMAX1-NEXT: addi a0, a1, 48
; LMULMAX1-NEXT: vse32.v v16, (a0) ; LMULMAX1-NEXT: vse32.v v16, (a0)
; LMULMAX1-NEXT: addi a0, a1, 16 ; LMULMAX1-NEXT: addi a0, a1, 16
; LMULMAX1-NEXT: vse32.v v14, (a0) ; LMULMAX1-NEXT: vse32.v v14, (a0)
; LMULMAX1-NEXT: addi a0, a1, 112 ; LMULMAX1-NEXT: addi a0, a1, 112
; LMULMAX1-NEXT: vse32.v v13, (a0) ; LMULMAX1-NEXT: vse32.v v13, (a0)
; LMULMAX1-NEXT: addi a0, a1, 80 ; LMULMAX1-NEXT: addi a0, a1, 80
; LMULMAX1-NEXT: vse32.v v11, (a0) ; LMULMAX1-NEXT: vse32.v v11, (a0)
▲ Show 20 Lines • Show All 66 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

Show First 20 Lines • Show All 93 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%s = shufflevector <4 x i16> %x, <4 x i16> %y, <4 x i32> <i32 1, i32 2, i32 0, i32 5> %s = shufflevector <4 x i16> %x, <4 x i16> %y, <4 x i32> <i32 1, i32 2, i32 0, i32 5>
ret <4 x i16> %s ret <4 x i16> %s
} }
define <4 x i16> @vrgather_shuffle_xv_v4i16(<4 x i16> %x) { define <4 x i16> @vrgather_shuffle_xv_v4i16(<4 x i16> %x) {
; CHECK-LABEL: vrgather_shuffle_xv_v4i16: ; CHECK-LABEL: vrgather_shuffle_xv_v4i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vi v10, v9, 4
; CHECK-NEXT: vmv.v.i v0, 12
; CHECK-NEXT: vmv.v.i v9, 5 ; CHECK-NEXT: vmv.v.i v9, 5
; CHECK-NEXT: vid.v v10
; CHECK-NEXT: vmv.v.i v0, 12
; CHECK-NEXT: vrsub.vi v10, v10, 4
; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t ; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = shufflevector <4 x i16> <i16 5, i16 5, i16 5, i16 5>, <4 x i16> %x, <4 x i32> <i32 0, i32 3, i32 6, i32 5> %s = shufflevector <4 x i16> <i16 5, i16 5, i16 5, i16 5>, <4 x i16> %x, <4 x i32> <i32 0, i32 3, i32 6, i32 5>
ret <4 x i16> %s ret <4 x i16> %s
} }
define <4 x i16> @vrgather_shuffle_vx_v4i16(<4 x i16> %x) { define <4 x i16> @vrgather_shuffle_vx_v4i16(<4 x i16> %x) {
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; RV64-NEXT: ret ; RV64-NEXT: ret
%s = shufflevector <8 x i64> %x, <8 x i64> %y, <8 x i32> <i32 1, i32 2, i32 10, i32 5, i32 1, i32 10, i32 3, i32 13> %s = shufflevector <8 x i64> %x, <8 x i64> %y, <8 x i32> <i32 1, i32 2, i32 10, i32 5, i32 1, i32 10, i32 3, i32 13>
ret <8 x i64> %s ret <8 x i64> %s
} }
define <8 x i64> @vrgather_shuffle_xv_v8i64(<8 x i64> %x) { define <8 x i64> @vrgather_shuffle_xv_v8i64(<8 x i64> %x) {
; RV32-LABEL: vrgather_shuffle_xv_v8i64: ; RV32-LABEL: vrgather_shuffle_xv_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: lui a0, %hi(.LCPI12_0) ; RV32-NEXT: lui a0, %hi(.LCPI12_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI12_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI12_0)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vle16.v v16, (a0) ; RV32-NEXT: vle16.v v16, (a0)
; RV32-NEXT: vmv.v.i v20, -1 ; RV32-NEXT: vmv.v.i v20, -1
; RV32-NEXT: vrgatherei16.vv v12, v20, v16 ; RV32-NEXT: vrgatherei16.vv v12, v20, v16
; RV32-NEXT: lui a0, %hi(.LCPI12_1)
; RV32-NEXT: addi a0, a0, %lo(.LCPI12_1)
; RV32-NEXT: vle16.v v16, (a0)
; RV32-NEXT: li a0, 113 ; RV32-NEXT: li a0, 113
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.x v0, a0 ; RV32-NEXT: vmv.v.x v0, a0
; RV32-NEXT: lui a0, %hi(.LCPI12_1)
; RV32-NEXT: addi a0, a0, %lo(.LCPI12_1)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vle16.v v16, (a0)
; RV32-NEXT: vrgatherei16.vv v12, v8, v16, v0.t ; RV32-NEXT: vrgatherei16.vv v12, v8, v16, v0.t
; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrgather_shuffle_xv_v8i64: ; RV64-LABEL: vrgather_shuffle_xv_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a0, %hi(.LCPI12_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI12_0)
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vle64.v v16, (a0)
; RV64-NEXT: li a0, 113 ; RV64-NEXT: li a0, 113
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV64-NEXT: vmv.v.x v0, a0 ; RV64-NEXT: vmv.v.x v0, a0
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: lui a0, %hi(.LCPI12_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI12_0)
; RV64-NEXT: vle64.v v16, (a0)
; RV64-NEXT: vmv.v.i v12, -1 ; RV64-NEXT: vmv.v.i v12, -1
; RV64-NEXT: vrgather.vv v12, v8, v16, v0.t ; RV64-NEXT: vrgather.vv v12, v8, v16, v0.t
; RV64-NEXT: vmv.v.v v8, v12 ; RV64-NEXT: vmv.v.v v8, v12
; RV64-NEXT: ret ; RV64-NEXT: ret
%s = shufflevector <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, <8 x i64> %x, <8 x i32> <i32 8, i32 3, i32 6, i32 5, i32 8, i32 12, i32 14, i32 3> %s = shufflevector <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, <8 x i64> %x, <8 x i32> <i32 8, i32 3, i32 6, i32 5, i32 8, i32 12, i32 14, i32 3>
ret <8 x i64> %s ret <8 x i64> %s
} }
define <8 x i64> @vrgather_shuffle_vx_v8i64(<8 x i64> %x) { define <8 x i64> @vrgather_shuffle_vx_v8i64(<8 x i64> %x) {
; RV32-LABEL: vrgather_shuffle_vx_v8i64: ; RV32-LABEL: vrgather_shuffle_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: lui a0, %hi(.LCPI13_0) ; RV32-NEXT: lui a0, %hi(.LCPI13_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI13_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI13_0)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vle16.v v16, (a0) ; RV32-NEXT: vle16.v v16, (a0)
; RV32-NEXT: vrgatherei16.vv v12, v8, v16 ; RV32-NEXT: vrgatherei16.vv v12, v8, v16
; RV32-NEXT: lui a0, %hi(.LCPI13_1)
; RV32-NEXT: addi a0, a0, %lo(.LCPI13_1)
; RV32-NEXT: vle16.v v8, (a0)
; RV32-NEXT: li a0, 140 ; RV32-NEXT: li a0, 140
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.x v0, a0 ; RV32-NEXT: vmv.v.x v0, a0
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: lui a0, %hi(.LCPI13_1)
; RV32-NEXT: addi a0, a0, %lo(.LCPI13_1)
; RV32-NEXT: vle16.v v8, (a0)
; RV32-NEXT: vmv.v.i v16, 5 ; RV32-NEXT: vmv.v.i v16, 5
; RV32-NEXT: vrgatherei16.vv v12, v16, v8, v0.t ; RV32-NEXT: vrgatherei16.vv v12, v16, v8, v0.t
; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrgather_shuffle_vx_v8i64: ; RV64-LABEL: vrgather_shuffle_vx_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a0, %hi(.LCPI13_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI13_0)
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vle64.v v16, (a0)
; RV64-NEXT: li a0, 115 ; RV64-NEXT: li a0, 115
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV64-NEXT: vmv.v.x v0, a0 ; RV64-NEXT: vmv.v.x v0, a0
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: lui a0, %hi(.LCPI13_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI13_0)
; RV64-NEXT: vle64.v v16, (a0)
; RV64-NEXT: vmv.v.i v12, 5 ; RV64-NEXT: vmv.v.i v12, 5
; RV64-NEXT: vrgather.vv v12, v8, v16, v0.t ; RV64-NEXT: vrgather.vv v12, v8, v16, v0.t
; RV64-NEXT: vmv.v.v v8, v12 ; RV64-NEXT: vmv.v.v v8, v12
; RV64-NEXT: ret ; RV64-NEXT: ret
%s = shufflevector <8 x i64> %x, <8 x i64> <i64 5, i64 5, i64 5, i64 5, i64 5, i64 5, i64 5, i64 5>, <8 x i32> <i32 0, i32 3, i32 10, i32 9, i32 4, i32 1, i32 7, i32 14> %s = shufflevector <8 x i64> %x, <8 x i64> <i64 5, i64 5, i64 5, i64 5, i64 5, i64 5, i64 5, i64 5>, <8 x i32> <i32 0, i32 3, i32 10, i32 9, i32 4, i32 1, i32 7, i32 14>
ret <8 x i64> %s ret <8 x i64> %s
} }
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 4, i32 3, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4> %shuff = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 4, i32 3, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>
ret <8 x i8> %shuff ret <8 x i8> %shuff
} }
define <8 x i8> @splat_ve2_we0(<8 x i8> %v, <8 x i8> %w) { define <8 x i8> @splat_ve2_we0(<8 x i8> %v, <8 x i8> %w) {
; CHECK-LABEL: splat_ve2_we0: ; CHECK-LABEL: splat_ve2_we0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: li a0, 66 ; CHECK-NEXT: li a0, 66
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v0, a0 ; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vi v10, v8, 2 ; CHECK-NEXT: vrgather.vi v10, v8, 2
; CHECK-NEXT: vrgather.vi v10, v9, 0, v0.t ; CHECK-NEXT: vrgather.vi v10, v9, 0, v0.t
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2> %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff ret <8 x i8> %shuff
} }
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 4, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2> %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 4, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff ret <8 x i8> %shuff
} }
define <8 x i8> @splat_ve2_we0_ins_i0we4(<8 x i8> %v, <8 x i8> %w) { define <8 x i8> @splat_ve2_we0_ins_i0we4(<8 x i8> %v, <8 x i8> %w) {
; CHECK-LABEL: splat_ve2_we0_ins_i0we4: ; CHECK-LABEL: splat_ve2_we0_ins_i0we4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 67
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vrgather.vi v10, v8, 2 ; CHECK-NEXT: vrgather.vi v10, v8, 2
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 4 ; CHECK-NEXT: vmv.v.i v8, 4
; CHECK-NEXT: li a0, 67
; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t ; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 12, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2> %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 12, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff ret <8 x i8> %shuff
} }
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define <8 x i8> @splat_ve2_we0_ins_i2we4(<8 x i8> %v, <8 x i8> %w) { define <8 x i8> @splat_ve2_we0_ins_i2we4(<8 x i8> %v, <8 x i8> %w) {
; CHECK-LABEL: splat_ve2_we0_ins_i2we4: ; CHECK-LABEL: splat_ve2_we0_ins_i2we4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v10, 4 ; CHECK-NEXT: vmv.v.i v10, 4
; CHECK-NEXT: vmv.v.i v11, 0 ; CHECK-NEXT: vmv.v.i v11, 0
; CHECK-NEXT: vsetivli zero, 3, e8, mf2, tu, ma ; CHECK-NEXT: vsetivli zero, 3, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vi v11, v10, 2 ; CHECK-NEXT: vslideup.vi v11, v10, 2
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: li a0, 70 ; CHECK-NEXT: li a0, 70
; CHECK-NEXT: vmv.v.x v0, a0 ; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vi v10, v8, 2 ; CHECK-NEXT: vrgather.vi v10, v8, 2
; CHECK-NEXT: vrgather.vv v10, v9, v11, v0.t ; CHECK-NEXT: vrgather.vv v10, v9, v11, v0.t
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 12, i32 2, i32 2, i32 2, i32 8, i32 2> %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 12, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff ret <8 x i8> %shuff
} }
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll

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; LMULMAX2-NEXT: vmv.v.i v8, 0 ; LMULMAX2-NEXT: vmv.v.i v8, 0
; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: splat_zero_v32i8: ; LMULMAX1-LABEL: splat_zero_v32i8:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vmv.v.i v8, 0 ; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vse8.v v8, (a1)
; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = insertelement <32 x i8> poison, i8 0, i32 0 %a = insertelement <32 x i8> poison, i8 0, i32 0
%b = shufflevector <32 x i8> %a, <32 x i8> poison, <32 x i32> zeroinitializer %b = shufflevector <32 x i8> %a, <32 x i8> poison, <32 x i32> zeroinitializer
store <32 x i8> %b, ptr %x store <32 x i8> %b, ptr %x
ret void ret void
} }
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; LMULMAX2-NEXT: vmv.v.i v8, 0 ; LMULMAX2-NEXT: vmv.v.i v8, 0
; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: splat_zero_v16i16: ; LMULMAX1-LABEL: splat_zero_v16i16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vmv.v.i v8, 0 ; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vse16.v v8, (a1)
; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = insertelement <16 x i16> poison, i16 0, i32 0 %a = insertelement <16 x i16> poison, i16 0, i32 0
%b = shufflevector <16 x i16> %a, <16 x i16> poison, <16 x i32> zeroinitializer %b = shufflevector <16 x i16> %a, <16 x i16> poison, <16 x i32> zeroinitializer
store <16 x i16> %b, ptr %x store <16 x i16> %b, ptr %x
ret void ret void
} }
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; LMULMAX2-NEXT: vmv.v.i v8, 0 ; LMULMAX2-NEXT: vmv.v.i v8, 0
; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: splat_zero_v8i32: ; LMULMAX1-LABEL: splat_zero_v8i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vmv.v.i v8, 0 ; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vse32.v v8, (a1)
; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = insertelement <8 x i32> poison, i32 0, i32 0 %a = insertelement <8 x i32> poison, i32 0, i32 0
%b = shufflevector <8 x i32> %a, <8 x i32> poison, <8 x i32> zeroinitializer %b = shufflevector <8 x i32> %a, <8 x i32> poison, <8 x i32> zeroinitializer
store <8 x i32> %b, ptr %x store <8 x i32> %b, ptr %x
ret void ret void
} }
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; LMULMAX2-NEXT: vmv.v.i v8, 0 ; LMULMAX2-NEXT: vmv.v.i v8, 0
; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: splat_zero_v4i64: ; LMULMAX1-RV32-LABEL: splat_zero_v4i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.i v8, 0 ; LMULMAX1-RV32-NEXT: vmv.v.i v8, 0
; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: addi a0, a0, 16 ; LMULMAX1-RV32-NEXT: vse32.v v8, (a1)
; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: splat_zero_v4i64: ; LMULMAX1-RV64-LABEL: splat_zero_v4i64:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vmv.v.i v8, 0 ; LMULMAX1-RV64-NEXT: vmv.v.i v8, 0
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: addi a0, a0, 16 ; LMULMAX1-RV64-NEXT: vse64.v v8, (a1)
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = insertelement <4 x i64> poison, i64 0, i32 0 %a = insertelement <4 x i64> poison, i64 0, i32 0
%b = shufflevector <4 x i64> %a, <4 x i64> poison, <4 x i32> zeroinitializer %b = shufflevector <4 x i64> %a, <4 x i64> poison, <4 x i32> zeroinitializer
store <4 x i64> %b, ptr %x store <4 x i64> %b, ptr %x
ret void ret void
} }
▲ Show 20 Lines • Show All 179 Lines • ▼ Show 20 Lines
; LMULMAX2-NEXT: vmv.v.i v8, -1 ; LMULMAX2-NEXT: vmv.v.i v8, -1
; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: splat_allones_v32i8: ; LMULMAX1-LABEL: splat_allones_v32i8:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vmv.v.i v8, -1 ; LMULMAX1-NEXT: vmv.v.i v8, -1
; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vse8.v v8, (a1)
; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = insertelement <32 x i8> poison, i8 -1, i32 0 %a = insertelement <32 x i8> poison, i8 -1, i32 0
%b = shufflevector <32 x i8> %a, <32 x i8> poison, <32 x i32> zeroinitializer %b = shufflevector <32 x i8> %a, <32 x i8> poison, <32 x i32> zeroinitializer
store <32 x i8> %b, ptr %x store <32 x i8> %b, ptr %x
ret void ret void
} }
Show All 11 Lines
; LMULMAX2-NEXT: vmv.v.i v8, -1 ; LMULMAX2-NEXT: vmv.v.i v8, -1
; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: splat_allones_v16i16: ; LMULMAX1-LABEL: splat_allones_v16i16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vmv.v.i v8, -1 ; LMULMAX1-NEXT: vmv.v.i v8, -1
; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vse16.v v8, (a1)
; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = insertelement <16 x i16> poison, i16 -1, i32 0 %a = insertelement <16 x i16> poison, i16 -1, i32 0
%b = shufflevector <16 x i16> %a, <16 x i16> poison, <16 x i32> zeroinitializer %b = shufflevector <16 x i16> %a, <16 x i16> poison, <16 x i32> zeroinitializer
store <16 x i16> %b, ptr %x store <16 x i16> %b, ptr %x
ret void ret void
} }
Show All 11 Lines
; LMULMAX2-NEXT: vmv.v.i v8, -1 ; LMULMAX2-NEXT: vmv.v.i v8, -1
; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: splat_allones_v8i32: ; LMULMAX1-LABEL: splat_allones_v8i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vmv.v.i v8, -1 ; LMULMAX1-NEXT: vmv.v.i v8, -1
; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vse32.v v8, (a1)
; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = insertelement <8 x i32> poison, i32 -1, i32 0 %a = insertelement <8 x i32> poison, i32 -1, i32 0
%b = shufflevector <8 x i32> %a, <8 x i32> poison, <8 x i32> zeroinitializer %b = shufflevector <8 x i32> %a, <8 x i32> poison, <8 x i32> zeroinitializer
store <8 x i32> %b, ptr %x store <8 x i32> %b, ptr %x
ret void ret void
} }
Show All 11 Lines
; LMULMAX2-NEXT: vmv.v.i v8, -1 ; LMULMAX2-NEXT: vmv.v.i v8, -1
; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: splat_allones_v4i64: ; LMULMAX1-RV32-LABEL: splat_allones_v4i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.i v8, -1 ; LMULMAX1-RV32-NEXT: vmv.v.i v8, -1
; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: addi a0, a0, 16 ; LMULMAX1-RV32-NEXT: vse32.v v8, (a1)
; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: splat_allones_v4i64: ; LMULMAX1-RV64-LABEL: splat_allones_v4i64:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vmv.v.i v8, -1 ; LMULMAX1-RV64-NEXT: vmv.v.i v8, -1
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: addi a0, a0, 16 ; LMULMAX1-RV64-NEXT: vse64.v v8, (a1)
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = insertelement <4 x i64> poison, i64 -1, i32 0 %a = insertelement <4 x i64> poison, i64 -1, i32 0
%b = shufflevector <4 x i64> %a, <4 x i64> poison, <4 x i32> zeroinitializer %b = shufflevector <4 x i64> %a, <4 x i64> poison, <4 x i32> zeroinitializer
store <4 x i64> %b, ptr %x store <4 x i64> %b, ptr %x
ret void ret void
} }
▲ Show 20 Lines • Show All 232 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

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Show First 20 Lines • Show All 1,099 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret void ret void
} }
define void @mulhu_v16i8(ptr %x) { define void @mulhu_v16i8(ptr %x) {
; RV32-LABEL: mulhu_v16i8: ; RV32-LABEL: mulhu_v16i8:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vle8.v v8, (a0) ; RV32-NEXT: vle8.v v8, (a0)
; RV32-NEXT: lui a1, 3 ; RV32-NEXT: li a1, 513
; RV32-NEXT: addi a1, a1, -2044
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a1 ; RV32-NEXT: vmv.v.x v0, a1
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmv.v.i v9, 0 ; RV32-NEXT: vmv.v.i v9, 4
; RV32-NEXT: li a1, -128 ; RV32-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-NEXT: vmerge.vxm v10, v9, a1, v0
; RV32-NEXT: lui a1, 1 ; RV32-NEXT: lui a1, 1
; RV32-NEXT: addi a2, a1, 32 ; RV32-NEXT: addi a2, a1, 78
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a2 ; RV32-NEXT: vmv.v.x v0, a2
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: lui a2, %hi(.LCPI65_0) ; RV32-NEXT: vmerge.vim v9, v9, 3, v0
; RV32-NEXT: addi a2, a2, %lo(.LCPI65_0) ; RV32-NEXT: lui a2, 8
; RV32-NEXT: vle8.v v11, (a2) ; RV32-NEXT: addi a2, a2, 304
; RV32-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-NEXT: vsrl.vv v9, v8, v9
; RV32-NEXT: vmulhu.vv v9, v9, v11
; RV32-NEXT: vsub.vv v8, v8, v9
; RV32-NEXT: vmulhu.vv v8, v8, v10
; RV32-NEXT: vadd.vv v8, v8, v9
; RV32-NEXT: li a2, 513
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a2 ; RV32-NEXT: vmv.v.x v0, a2
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmv.v.i v9, 4 ; RV32-NEXT: vmerge.vim v9, v9, 2, v0
; RV32-NEXT: vmerge.vim v9, v9, 1, v0 ; RV32-NEXT: lui a2, 3
; RV32-NEXT: addi a1, a1, 78 ; RV32-NEXT: addi a2, a2, -2044
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a1 ; RV32-NEXT: vmv.v.x v0, a2
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmerge.vim v9, v9, 3, v0 ; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: lui a1, 8 ; RV32-NEXT: li a2, -128
; RV32-NEXT: addi a1, a1, 304 ; RV32-NEXT: vmerge.vxm v11, v10, a2, v0
; RV32-NEXT: addi a1, a1, 32
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a1 ; RV32-NEXT: vmv.v.x v0, a1
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmerge.vim v9, v9, 2, v0 ; RV32-NEXT: lui a1, %hi(.LCPI65_0)
; RV32-NEXT: addi a1, a1, %lo(.LCPI65_0)
; RV32-NEXT: vle8.v v12, (a1)
; RV32-NEXT: vmerge.vim v10, v10, 1, v0
; RV32-NEXT: vsrl.vv v10, v8, v10
; RV32-NEXT: vmulhu.vv v10, v10, v12
; RV32-NEXT: vsub.vv v8, v8, v10
; RV32-NEXT: vmulhu.vv v8, v8, v11
; RV32-NEXT: vadd.vv v8, v8, v10
; RV32-NEXT: vsrl.vv v8, v8, v9 ; RV32-NEXT: vsrl.vv v8, v8, v9
; RV32-NEXT: vse8.v v8, (a0) ; RV32-NEXT: vse8.v v8, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mulhu_v16i8: ; RV64-LABEL: mulhu_v16i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vle8.v v8, (a0) ; RV64-NEXT: vle8.v v8, (a0)
; RV64-NEXT: lui a1, 3 ; RV64-NEXT: li a1, 513
; RV64-NEXT: addiw a1, a1, -2044
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vmv.v.x v0, a1 ; RV64-NEXT: vmv.v.x v0, a1
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vmv.v.i v9, 0 ; RV64-NEXT: vmv.v.i v9, 4
; RV64-NEXT: li a1, -128 ; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: vmerge.vxm v10, v9, a1, v0
; RV64-NEXT: lui a1, 1 ; RV64-NEXT: lui a1, 1
; RV64-NEXT: addiw a2, a1, 32 ; RV64-NEXT: addiw a2, a1, 78
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vmv.v.x v0, a2 ; RV64-NEXT: vmv.v.x v0, a2
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: lui a2, %hi(.LCPI65_0) ; RV64-NEXT: vmerge.vim v9, v9, 3, v0
; RV64-NEXT: addi a2, a2, %lo(.LCPI65_0) ; RV64-NEXT: lui a2, 8
; RV64-NEXT: vle8.v v11, (a2) ; RV64-NEXT: addiw a2, a2, 304
; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: vsrl.vv v9, v8, v9
; RV64-NEXT: vmulhu.vv v9, v9, v11
; RV64-NEXT: vsub.vv v8, v8, v9
; RV64-NEXT: vmulhu.vv v8, v8, v10
; RV64-NEXT: vadd.vv v8, v8, v9
; RV64-NEXT: li a2, 513
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vmv.v.x v0, a2 ; RV64-NEXT: vmv.v.x v0, a2
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vmv.v.i v9, 4 ; RV64-NEXT: vmerge.vim v9, v9, 2, v0
; RV64-NEXT: vmerge.vim v9, v9, 1, v0 ; RV64-NEXT: lui a2, 3
; RV64-NEXT: addiw a1, a1, 78 ; RV64-NEXT: addiw a2, a2, -2044
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vmv.v.x v0, a1 ; RV64-NEXT: vmv.v.x v0, a2
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vmerge.vim v9, v9, 3, v0 ; RV64-NEXT: vmv.v.i v10, 0
; RV64-NEXT: lui a1, 8 ; RV64-NEXT: li a2, -128
; RV64-NEXT: addiw a1, a1, 304 ; RV64-NEXT: vmerge.vxm v11, v10, a2, v0
; RV64-NEXT: addiw a1, a1, 32
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vmv.v.x v0, a1 ; RV64-NEXT: vmv.v.x v0, a1
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vmerge.vim v9, v9, 2, v0 ; RV64-NEXT: lui a1, %hi(.LCPI65_0)
; RV64-NEXT: addi a1, a1, %lo(.LCPI65_0)
; RV64-NEXT: vle8.v v12, (a1)
; RV64-NEXT: vmerge.vim v10, v10, 1, v0
; RV64-NEXT: vsrl.vv v10, v8, v10
; RV64-NEXT: vmulhu.vv v10, v10, v12
; RV64-NEXT: vsub.vv v8, v8, v10
; RV64-NEXT: vmulhu.vv v8, v8, v11
; RV64-NEXT: vadd.vv v8, v8, v10
; RV64-NEXT: vsrl.vv v8, v8, v9 ; RV64-NEXT: vsrl.vv v8, v8, v9
; RV64-NEXT: vse8.v v8, (a0) ; RV64-NEXT: vse8.v v8, (a0)
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = load <16 x i8>, ptr %x %a = load <16 x i8>, ptr %x
%b = udiv <16 x i8> %a, <i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25> %b = udiv <16 x i8> %a, <i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25>
store <16 x i8> %b, ptr %x store <16 x i8> %b, ptr %x
ret void ret void
} }
define void @mulhu_v8i16(ptr %x) { define void @mulhu_v8i16(ptr %x) {
; CHECK-LABEL: mulhu_v8i16: ; CHECK-LABEL: mulhu_v8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: li a1, 33 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmv.v.x v0, a1
; CHECK-NEXT: vmv.v.i v9, 3
; CHECK-NEXT: vmerge.vim v9, v9, 2, v0
; CHECK-NEXT: vmv.v.i v10, 1
; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vi v9, v10, 6
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.i v11, 0
; CHECK-NEXT: lui a1, 1048568 ; CHECK-NEXT: lui a1, 1048568
; CHECK-NEXT: vsetvli zero, zero, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, zero, e16, m1, tu, ma
; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmv.s.x v12, a1 ; CHECK-NEXT: vmv.s.x v10, a1
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.i v11, 1
; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, ma ; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vi v11, v10, 6 ; CHECK-NEXT: vslideup.vi v9, v11, 6
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: lui a1, %hi(.LCPI66_0) ; CHECK-NEXT: lui a1, %hi(.LCPI66_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI66_0) ; CHECK-NEXT: addi a1, a1, %lo(.LCPI66_0)
; CHECK-NEXT: vle16.v v10, (a1) ; CHECK-NEXT: vle16.v v12, (a1)
; CHECK-NEXT: vsrl.vv v11, v8, v11 ; CHECK-NEXT: vsrl.vv v9, v8, v9
; CHECK-NEXT: vmulhu.vv v10, v11, v10 ; CHECK-NEXT: vmulhu.vv v9, v9, v12
; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: vsub.vv v8, v8, v9
; CHECK-NEXT: vmulhu.vv v8, v8, v12 ; CHECK-NEXT: vmulhu.vv v8, v8, v10
; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: li a1, 33
; CHECK-NEXT: vmv.v.x v0, a1
; CHECK-NEXT: vmv.v.i v9, 3
; CHECK-NEXT: vmerge.vim v9, v9, 2, v0
; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vi v9, v11, 6
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vsrl.vv v8, v8, v9 ; CHECK-NEXT: vsrl.vv v8, v8, v9
; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <8 x i16>, ptr %x %a = load <8 x i16>, ptr %x
%b = udiv <8 x i16> %a, <i16 7, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15> %b = udiv <8 x i16> %a, <i16 7, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
store <8 x i16> %b, ptr %x store <8 x i16> %b, ptr %x
ret void ret void
} }
▲ Show 20 Lines • Show All 193 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
ret void ret void
} }
define void @mulhs_v6i16(ptr %x) { define void @mulhs_v6i16(ptr %x) {
; CHECK-LABEL: mulhs_v6i16: ; CHECK-LABEL: mulhs_v6i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmv.v.i v0, 6
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v0, 6
; CHECK-NEXT: vmv.v.i v9, -7 ; CHECK-NEXT: vmv.v.i v9, -7
; CHECK-NEXT: vmerge.vim v9, v9, 7, v0 ; CHECK-NEXT: vmerge.vim v9, v9, 7, v0
; CHECK-NEXT: vdiv.vv v9, v8, v9 ; CHECK-NEXT: vdiv.vv v9, v8, v9
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vid.v v10 ; CHECK-NEXT: vmv.v.i v10, 7
; CHECK-NEXT: vmv.v.i v11, 7 ; CHECK-NEXT: vid.v v11
; CHECK-NEXT: li a1, -14 ; CHECK-NEXT: li a1, -14
; CHECK-NEXT: vmacc.vx v11, a1, v10 ; CHECK-NEXT: vmadd.vx v11, a1, v10
; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 4 ; CHECK-NEXT: vslidedown.vi v8, v8, 4
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vdiv.vv v8, v8, v11 ; CHECK-NEXT: vdiv.vv v8, v8, v11
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vi v9, v8, 4 ; CHECK-NEXT: vslideup.vi v9, v8, 4
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vse16.v v9, (a0) ; CHECK-NEXT: vse16.v v9, (a0)
▲ Show 20 Lines • Show All 3,608 Lines • ▼ Show 20 Lines; LMULMAX1-NEXT: ret
ret void ret void
} }
define void @mulhu_v16i16(ptr %x) { define void @mulhu_v16i16(ptr %x) {
; LMULMAX2-RV32-LABEL: mulhu_v16i16: ; LMULMAX2-RV32-LABEL: mulhu_v16i16:
; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX2-RV32-NEXT: vle16.v v10, (a0) ; LMULMAX2-RV32-NEXT: vle16.v v10, (a0)
; LMULMAX2-RV32-NEXT: li a1, 257 ; LMULMAX2-RV32-NEXT: lui a1, 2
; LMULMAX2-RV32-NEXT: addi a1, a1, 289
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v0, a1 ; LMULMAX2-RV32-NEXT: vmv.v.x v0, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.i v12, 0 ; LMULMAX2-RV32-NEXT: vmv.v.i v8, 3
; LMULMAX2-RV32-NEXT: lui a1, 1048568 ; LMULMAX2-RV32-NEXT: vmerge.vim v12, v8, 2, v0
; LMULMAX2-RV32-NEXT: vmerge.vxm v14, v12, a1, v0
; LMULMAX2-RV32-NEXT: lui a1, 4 ; LMULMAX2-RV32-NEXT: lui a1, 4
; LMULMAX2-RV32-NEXT: addi a1, a1, 64 ; LMULMAX2-RV32-NEXT: addi a1, a1, 64
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v8, a1 ; LMULMAX2-RV32-NEXT: vmv.v.x v8, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX2-RV32-NEXT: lui a1, %hi(.LCPI182_0)
; LMULMAX2-RV32-NEXT: addi a1, a1, %lo(.LCPI182_0)
; LMULMAX2-RV32-NEXT: vle16.v v16, (a1)
; LMULMAX2-RV32-NEXT: vmv1r.v v0, v8 ; LMULMAX2-RV32-NEXT: vmv1r.v v0, v8
; LMULMAX2-RV32-NEXT: vmerge.vim v12, v12, 1, v0 ; LMULMAX2-RV32-NEXT: vmerge.vim v12, v12, 1, v0
; LMULMAX2-RV32-NEXT: vsrl.vv v12, v10, v12 ; LMULMAX2-RV32-NEXT: li a1, 257
; LMULMAX2-RV32-NEXT: vmulhu.vv v12, v12, v16
; LMULMAX2-RV32-NEXT: vsub.vv v10, v10, v12
; LMULMAX2-RV32-NEXT: vmulhu.vv v10, v10, v14
; LMULMAX2-RV32-NEXT: vadd.vv v10, v10, v12
; LMULMAX2-RV32-NEXT: lui a1, 2
; LMULMAX2-RV32-NEXT: addi a1, a1, 289
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v0, a1 ; LMULMAX2-RV32-NEXT: vmv.v.x v0, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.i v12, 3 ; LMULMAX2-RV32-NEXT: vmv.v.i v14, 0
; LMULMAX2-RV32-NEXT: vmerge.vim v12, v12, 2, v0 ; LMULMAX2-RV32-NEXT: lui a1, %hi(.LCPI182_0)
; LMULMAX2-RV32-NEXT: addi a1, a1, %lo(.LCPI182_0)
; LMULMAX2-RV32-NEXT: vle16.v v16, (a1)
; LMULMAX2-RV32-NEXT: lui a1, 1048568
; LMULMAX2-RV32-NEXT: vmerge.vxm v18, v14, a1, v0
; LMULMAX2-RV32-NEXT: vmv1r.v v0, v8 ; LMULMAX2-RV32-NEXT: vmv1r.v v0, v8
; LMULMAX2-RV32-NEXT: vmerge.vim v8, v12, 1, v0 ; LMULMAX2-RV32-NEXT: vmerge.vim v8, v14, 1, v0
; LMULMAX2-RV32-NEXT: vsrl.vv v8, v10, v8 ; LMULMAX2-RV32-NEXT: vsrl.vv v8, v10, v8
; LMULMAX2-RV32-NEXT: vmulhu.vv v8, v8, v16
; LMULMAX2-RV32-NEXT: vsub.vv v10, v10, v8
; LMULMAX2-RV32-NEXT: vmulhu.vv v10, v10, v18
; LMULMAX2-RV32-NEXT: vadd.vv v8, v10, v8
; LMULMAX2-RV32-NEXT: vsrl.vv v8, v8, v12
; LMULMAX2-RV32-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV32-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret ; LMULMAX2-RV32-NEXT: ret
; ;
; LMULMAX2-RV64-LABEL: mulhu_v16i16: ; LMULMAX2-RV64-LABEL: mulhu_v16i16:
; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX2-RV64-NEXT: vle16.v v10, (a0) ; LMULMAX2-RV64-NEXT: vle16.v v10, (a0)
; LMULMAX2-RV64-NEXT: li a1, 257 ; LMULMAX2-RV64-NEXT: lui a1, 2
; LMULMAX2-RV64-NEXT: addiw a1, a1, 289
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; LMULMAX2-RV64-NEXT: vmv.v.x v0, a1 ; LMULMAX2-RV64-NEXT: vmv.v.x v0, a1
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX2-RV64-NEXT: vmv.v.i v12, 0 ; LMULMAX2-RV64-NEXT: vmv.v.i v8, 3
; LMULMAX2-RV64-NEXT: lui a1, 1048568 ; LMULMAX2-RV64-NEXT: vmerge.vim v12, v8, 2, v0
; LMULMAX2-RV64-NEXT: vmerge.vxm v14, v12, a1, v0
; LMULMAX2-RV64-NEXT: lui a1, 4 ; LMULMAX2-RV64-NEXT: lui a1, 4
; LMULMAX2-RV64-NEXT: addiw a1, a1, 64 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 64
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; LMULMAX2-RV64-NEXT: vmv.v.x v8, a1 ; LMULMAX2-RV64-NEXT: vmv.v.x v8, a1
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI182_0)
; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI182_0)
; LMULMAX2-RV64-NEXT: vle16.v v16, (a1)
; LMULMAX2-RV64-NEXT: vmv1r.v v0, v8 ; LMULMAX2-RV64-NEXT: vmv1r.v v0, v8
; LMULMAX2-RV64-NEXT: vmerge.vim v12, v12, 1, v0 ; LMULMAX2-RV64-NEXT: vmerge.vim v12, v12, 1, v0
; LMULMAX2-RV64-NEXT: vsrl.vv v12, v10, v12 ; LMULMAX2-RV64-NEXT: li a1, 257
; LMULMAX2-RV64-NEXT: vmulhu.vv v12, v12, v16
; LMULMAX2-RV64-NEXT: vsub.vv v10, v10, v12
; LMULMAX2-RV64-NEXT: vmulhu.vv v10, v10, v14
; LMULMAX2-RV64-NEXT: vadd.vv v10, v10, v12
; LMULMAX2-RV64-NEXT: lui a1, 2
; LMULMAX2-RV64-NEXT: addiw a1, a1, 289
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; LMULMAX2-RV64-NEXT: vmv.v.x v0, a1 ; LMULMAX2-RV64-NEXT: vmv.v.x v0, a1
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX2-RV64-NEXT: vmv.v.i v12, 3 ; LMULMAX2-RV64-NEXT: vmv.v.i v14, 0
; LMULMAX2-RV64-NEXT: vmerge.vim v12, v12, 2, v0 ; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI182_0)
; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI182_0)
; LMULMAX2-RV64-NEXT: vle16.v v16, (a1)
; LMULMAX2-RV64-NEXT: lui a1, 1048568
; LMULMAX2-RV64-NEXT: vmerge.vxm v18, v14, a1, v0
; LMULMAX2-RV64-NEXT: vmv1r.v v0, v8 ; LMULMAX2-RV64-NEXT: vmv1r.v v0, v8
; LMULMAX2-RV64-NEXT: vmerge.vim v8, v12, 1, v0 ; LMULMAX2-RV64-NEXT: vmerge.vim v8, v14, 1, v0
; LMULMAX2-RV64-NEXT: vsrl.vv v8, v10, v8 ; LMULMAX2-RV64-NEXT: vsrl.vv v8, v10, v8
; LMULMAX2-RV64-NEXT: vmulhu.vv v8, v8, v16
; LMULMAX2-RV64-NEXT: vsub.vv v10, v10, v8
; LMULMAX2-RV64-NEXT: vmulhu.vv v10, v10, v18
; LMULMAX2-RV64-NEXT: vadd.vv v8, v10, v8
; LMULMAX2-RV64-NEXT: vsrl.vv v8, v8, v12
; LMULMAX2-RV64-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV64-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-LABEL: mulhu_v16i16: ; LMULMAX1-LABEL: mulhu_v16i16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vle16.v v8, (a1) ; LMULMAX1-NEXT: vle16.v v8, (a1)
▲ Show 20 Lines • Show All 497 Lines • ▼ Show 20 Lines
; LMULMAX2-RV32-NEXT: vadd.vv v8, v10, v8 ; LMULMAX2-RV32-NEXT: vadd.vv v8, v10, v8
; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret ; LMULMAX2-RV32-NEXT: ret
; ;
; LMULMAX2-RV64-LABEL: mulhs_v4i64: ; LMULMAX2-RV64-LABEL: mulhs_v4i64:
; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64-NEXT: vmv.v.i v10, 1
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; LMULMAX2-RV64-NEXT: vmv.v.i v0, 5 ; LMULMAX2-RV64-NEXT: vmv.v.i v0, 5
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV64-NEXT: vmv.v.i v10, 1
; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 0, v0 ; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 0, v0
; LMULMAX2-RV64-NEXT: lui a1, 349525 ; LMULMAX2-RV64-NEXT: lui a1, 349525
; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365
; LMULMAX2-RV64-NEXT: slli a2, a1, 32 ; LMULMAX2-RV64-NEXT: slli a2, a1, 32
; LMULMAX2-RV64-NEXT: add a1, a1, a2 ; LMULMAX2-RV64-NEXT: add a1, a1, a2
; LMULMAX2-RV64-NEXT: lui a2, %hi(.LCPI188_0) ; LMULMAX2-RV64-NEXT: lui a2, %hi(.LCPI188_0)
; LMULMAX2-RV64-NEXT: ld a2, %lo(.LCPI188_0)(a2) ; LMULMAX2-RV64-NEXT: ld a2, %lo(.LCPI188_0)(a2)
; LMULMAX2-RV64-NEXT: vmv.v.i v12, -1 ; LMULMAX2-RV64-NEXT: vmv.v.i v12, -1
▲ Show 20 Lines • Show All 2,806 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 12,353 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsext.vf4 v16, v8 ; RV32-NEXT: vsext.vf4 v16, v8
; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV32-NEXT: vluxei32.v v10, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v10, (a0), v16, v0.t
; RV32-NEXT: vmv.v.v v8, v10 ; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64V-LABEL: mgather_baseidx_v32i8: ; RV64V-LABEL: mgather_baseidx_v32i8:
; RV64V: # %bb.0: ; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64V-NEXT: vmv1r.v v12, v0
; RV64V-NEXT: vsext.vf8 v16, v8
; RV64V-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64V-NEXT: vmv1r.v v12, v10
; RV64V-NEXT: vluxei64.v v12, (a0), v16, v0.t
; RV64V-NEXT: vsetivli zero, 16, e8, m2, ta, ma ; RV64V-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; RV64V-NEXT: vslidedown.vi v10, v10, 16 ; RV64V-NEXT: vslidedown.vi v14, v8, 16
; RV64V-NEXT: vslidedown.vi v8, v8, 16
; RV64V-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64V-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64V-NEXT: vsext.vf8 v16, v8 ; RV64V-NEXT: vsext.vf8 v16, v14
; RV64V-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; RV64V-NEXT: vslidedown.vi v14, v10, 16
; RV64V-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64V-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64V-NEXT: vslidedown.vi v0, v0, 2 ; RV64V-NEXT: vslidedown.vi v0, v0, 2
; RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64V-NEXT: vluxei64.v v14, (a0), v16, v0.t
; RV64V-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64V-NEXT: vsext.vf8 v16, v8
; RV64V-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64V-NEXT: vmv1r.v v0, v12
; RV64V-NEXT: vluxei64.v v10, (a0), v16, v0.t ; RV64V-NEXT: vluxei64.v v10, (a0), v16, v0.t
; RV64V-NEXT: li a0, 32 ; RV64V-NEXT: li a0, 32
; RV64V-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; RV64V-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; RV64V-NEXT: vslideup.vi v12, v10, 16 ; RV64V-NEXT: vslideup.vi v10, v14, 16
; RV64V-NEXT: vmv.v.v v8, v12 ; RV64V-NEXT: vmv.v.v v8, v10
; RV64V-NEXT: ret ; RV64V-NEXT: ret
; ;
; RV64ZVE32F-LABEL: mgather_baseidx_v32i8: ; RV64ZVE32F-LABEL: mgather_baseidx_v32i8:
; RV64ZVE32F: # %bb.0: ; RV64ZVE32F: # %bb.0:
; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0 ; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1 ; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB98_2 ; RV64ZVE32F-NEXT: beqz a2, .LBB98_2
▲ Show 20 Lines • Show All 467 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

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Show First 20 Lines • Show All 10,848 Lines • ▼ Show 20 Lines
; ;
; RV64-LABEL: mscatter_baseidx_v32i8: ; RV64-LABEL: mscatter_baseidx_v32i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v10 ; RV64-NEXT: vsext.vf8 v16, v10
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, ma ; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 16
; RV64-NEXT: vslidedown.vi v10, v10, 16 ; RV64-NEXT: vslidedown.vi v10, v10, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v10 ; RV64-NEXT: vsext.vf8 v16, v10
; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 16
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2 ; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV64ZVE32F-LABEL: mscatter_baseidx_v32i8: ; RV64ZVE32F-LABEL: mscatter_baseidx_v32i8:
; RV64ZVE32F: # %bb.0: ; RV64ZVE32F: # %bb.0:
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll

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} }
define i64 @vwreduce_add_v1i64(ptr %x) { define i64 @vwreduce_add_v1i64(ptr %x) {
; RV32-LABEL: vwreduce_add_v1i64: ; RV32-LABEL: vwreduce_add_v1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: vsext.vf2 v9, v8 ; RV32-NEXT: vsext.vf2 v9, v8
; RV32-NEXT: li a0, 32
; RV32-NEXT: vsrl.vx v8, v9, a0
; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v8, v9, a1
; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vwreduce_add_v1i64: ; RV64-LABEL: vwreduce_add_v1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: vsext.vf2 v9, v8 ; RV64-NEXT: vsext.vf2 v9, v8
; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <1 x i32>, ptr %x %v = load <1 x i32>, ptr %x
%e = sext <1 x i32> %v to <1 x i64> %e = sext <1 x i32> %v to <1 x i64>
%red = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> %e) %red = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> %e)
ret i64 %red ret i64 %red
} }
define i64 @vwreduce_uadd_v1i64(ptr %x) { define i64 @vwreduce_uadd_v1i64(ptr %x) {
; RV32-LABEL: vwreduce_uadd_v1i64: ; RV32-LABEL: vwreduce_uadd_v1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: vzext.vf2 v9, v8 ; RV32-NEXT: vzext.vf2 v9, v8
; RV32-NEXT: li a0, 32
; RV32-NEXT: vsrl.vx v8, v9, a0
; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v8, v9, a1
; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vwreduce_uadd_v1i64: ; RV64-LABEL: vwreduce_uadd_v1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: vzext.vf2 v9, v8 ; RV64-NEXT: vzext.vf2 v9, v8
; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: vmv.x.s a0, v9
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll

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} }
define <8 x i1> @fcmp_ord_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ord_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_v8f16: ; CHECK-LABEL: fcmp_ord_vf_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t ; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmand.mm v0, v8, v9 ; CHECK-NEXT: vmand.mm v0, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0 %elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ord", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ord", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_ord_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ord_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_swap_v8f16: ; CHECK-LABEL: fcmp_ord_vf_swap_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t ; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmand.mm v0, v9, v8 ; CHECK-NEXT: vmand.mm v0, v9, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0 %elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"ord", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"ord", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
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} }
define <8 x i1> @fcmp_uno_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_uno_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_v8f16: ; CHECK-LABEL: fcmp_uno_vf_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t ; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v8, v9 ; CHECK-NEXT: vmor.mm v0, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0 %elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"uno", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"uno", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_uno_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_uno_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_swap_v8f16: ; CHECK-LABEL: fcmp_uno_vf_swap_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t ; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0 %elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"uno", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"uno", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
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} }
define <8 x i1> @fcmp_ord_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ord_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_v8f64: ; CHECK-LABEL: fcmp_ord_vf_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vmfeq.vf v16, v12, fa0, v0.t ; CHECK-NEXT: vmfeq.vv v16, v8, v8, v0.t
; CHECK-NEXT: vmfeq.vv v12, v8, v8, v0.t ; CHECK-NEXT: vmfeq.vf v8, v12, fa0, v0.t
; CHECK-NEXT: vmand.mm v0, v12, v16 ; CHECK-NEXT: vmand.mm v0, v16, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> poison, double %b, i32 0 %elt.head = insertelement <8 x double> poison, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"ord", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"ord", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_ord_vf_swap_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ord_vf_swap_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_swap_v8f64: ; CHECK-LABEL: fcmp_ord_vf_swap_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vmfeq.vf v16, v12, fa0, v0.t ; CHECK-NEXT: vmfeq.vv v16, v8, v8, v0.t
; CHECK-NEXT: vmfeq.vv v12, v8, v8, v0.t ; CHECK-NEXT: vmfeq.vf v8, v12, fa0, v0.t
; CHECK-NEXT: vmand.mm v0, v16, v12 ; CHECK-NEXT: vmand.mm v0, v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> poison, double %b, i32 0 %elt.head = insertelement <8 x double> poison, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %vb, <8 x double> %va, metadata !"ord", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %vb, <8 x double> %va, metadata !"ord", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_ueq_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ueq_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 zeroext %evl) {
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} }
define <8 x i1> @fcmp_uno_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_uno_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_v8f64: ; CHECK-LABEL: fcmp_uno_vf_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vmfne.vf v16, v12, fa0, v0.t ; CHECK-NEXT: vmfne.vv v16, v8, v8, v0.t
; CHECK-NEXT: vmfne.vv v12, v8, v8, v0.t ; CHECK-NEXT: vmfne.vf v8, v12, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v12, v16 ; CHECK-NEXT: vmor.mm v0, v16, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> poison, double %b, i32 0 %elt.head = insertelement <8 x double> poison, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"uno", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"uno", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_uno_vf_swap_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_uno_vf_swap_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_swap_v8f64: ; CHECK-LABEL: fcmp_uno_vf_swap_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vmfne.vf v16, v12, fa0, v0.t ; CHECK-NEXT: vmfne.vv v16, v8, v8, v0.t
; CHECK-NEXT: vmfne.vv v12, v8, v8, v0.t ; CHECK-NEXT: vmfne.vf v8, v12, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v16, v12 ; CHECK-NEXT: vmor.mm v0, v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> poison, double %b, i32 0 %elt.head = insertelement <8 x double> poison, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %vb, <8 x double> %va, metadata !"uno", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %vb, <8 x double> %va, metadata !"uno", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
declare <32 x i1> @llvm.vp.fcmp.v32f64(<32 x double>, <32 x double>, metadata, <32 x i1>, i32) declare <32 x i1> @llvm.vp.fcmp.v32f64(<32 x double>, <32 x double>, metadata, <32 x i1>, i32)
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll

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store <2 x i16> <i16 3, i16 6>, ptr %p store <2 x i16> <i16 3, i16 6>, ptr %p
ret void ret void
} }
define void @store_constant_v2i32(ptr %p) { define void @store_constant_v2i32(ptr %p) {
; CHECK-LABEL: store_constant_v2i32: ; CHECK-LABEL: store_constant_v2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vmv.v.i v8, 3
; CHECK-NEXT: vmv.v.i v9, 3 ; CHECK-NEXT: vid.v v9
; CHECK-NEXT: li a1, 3 ; CHECK-NEXT: li a1, 3
; CHECK-NEXT: vmacc.vx v9, a1, v8 ; CHECK-NEXT: vmadd.vx v9, a1, v8
; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
store <2 x i32> <i32 3, i32 6>, ptr %p store <2 x i32> <i32 3, i32 6>, ptr %p
ret void ret void
} }
define void @store_constant_v4i8(ptr %p) { define void @store_constant_v4i8(ptr %p) {
; RV32-LABEL: store_constant_v4i8: ; RV32-LABEL: store_constant_v4i8:
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
store <4 x i8> <i8 0, i8 1, i8 2, i8 3>, ptr %p store <4 x i8> <i8 0, i8 1, i8 2, i8 3>, ptr %p
ret void ret void
} }
define void @store_constant_v2i8_align1(ptr %p) { define void @store_constant_v2i8_align1(ptr %p) {
; CHECK-LABEL: store_constant_v2i8_align1: ; CHECK-LABEL: store_constant_v2i8_align1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vmv.v.i v8, 3
; CHECK-NEXT: vmv.v.i v9, 3 ; CHECK-NEXT: vid.v v9
; CHECK-NEXT: li a1, 3 ; CHECK-NEXT: li a1, 3
; CHECK-NEXT: vmacc.vx v9, a1, v8 ; CHECK-NEXT: vmadd.vx v9, a1, v8
; CHECK-NEXT: vse8.v v9, (a0) ; CHECK-NEXT: vse8.v v9, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
store <2 x i8> <i8 3, i8 6>, ptr %p, align 1 store <2 x i8> <i8 3, i8 6>, ptr %p, align 1
ret void ret void
} }
define void @store_constant_splat_v2i8(ptr %p) { define void @store_constant_splat_v2i8(ptr %p) {
; CHECK-LABEL: store_constant_splat_v2i8: ; CHECK-LABEL: store_constant_splat_v2i8:
Show All 28 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll

Show First 20 Lines • Show All 1,643 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
%vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer
%v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 12) %v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 12)
ret <32 x i64> %v ret <32 x i64> %v
} }
define <32 x i64> @vadd_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) { define <32 x i64> @vadd_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
; RV32-LABEL: vadd_vx_v32i64_evl27: ; RV32-LABEL: vadd_vx_v32i64_evl27:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v1, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: li a0, 32 ; RV32-NEXT: li a0, 32
; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: vmv.v.i v24, -1
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
; RV32-NEXT: vsetivli zero, 11, e64, m8, ta, ma ; RV32-NEXT: vsetivli zero, 11, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: vadd.vv v16, v16, v24, v0.t ; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_v32i64_evl27: ; RV64-LABEL: vadd_vx_v32i64_evl27:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v24, v0, 2 ; RV64-NEXT: vslidedown.vi v24, v0, 2
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vadd.vi v8, v8, -1, v0.t ; RV64-NEXT: vadd.vi v8, v8, -1, v0.t
Show All 9 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,221 Lines • ▼ Show 20 Lines
} }
define <32 x i1> @fcmps_uno_fv_v32f16(<32 x half> %va, half %b) nounwind strictfp { define <32 x i1> @fcmps_uno_fv_v32f16(<32 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmps_uno_fv_v32f16: ; CHECK-LABEL: fcmps_uno_fv_v32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32 ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vmfle.vv v16, v8, v8 ; CHECK-NEXT: vmfle.vf v16, v12, fa0
; CHECK-NEXT: vmfle.vf v8, v12, fa0 ; CHECK-NEXT: vmnot.m v12, v16
; CHECK-NEXT: vmnot.m v8, v8 ; CHECK-NEXT: vmfle.vv v13, v8, v8
; CHECK-NEXT: vmorn.mm v0, v8, v16 ; CHECK-NEXT: vmorn.mm v0, v12, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <32 x half> poison, half %b, i32 0 %head = insertelement <32 x half> poison, half %b, i32 0
%splat = shufflevector <32 x half> %head, <32 x half> poison, <32 x i32> zeroinitializer %splat = shufflevector <32 x half> %head, <32 x half> poison, <32 x i32> zeroinitializer
%1 = call <32 x i1> @llvm.experimental.constrained.fcmps.v32f16(<32 x half> %splat, <32 x half> %va, metadata !"uno", metadata !"fpexcept.strict") strictfp %1 = call <32 x i1> @llvm.experimental.constrained.fcmps.v32f16(<32 x half> %splat, <32 x half> %va, metadata !"uno", metadata !"fpexcept.strict") strictfp
ret <32 x i1> %1 ret <32 x i1> %1
} }
declare <1 x i1> @llvm.experimental.constrained.fcmps.v1f32(<1 x float>, <1 x float>, metadata, metadata) declare <1 x i1> @llvm.experimental.constrained.fcmps.v1f32(<1 x float>, <1 x float>, metadata, metadata)
▲ Show 20 Lines • Show All 4,786 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll

Show First 20 Lines • Show All 1,935 Lines • ▼ Show 20 Lines
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpgather_baseidx_v32i8_v32f64(ptr %base, <32 x i8> %idxs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_baseidx_v32i8_v32f64(ptr %base, <32 x i8> %idxs, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_v32i8_v32f64: ; RV32-LABEL: vpgather_baseidx_v32i8_v32f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vsext.vf4 v16, v8 ; RV32-NEXT: vsext.vf4 v16, v8
; RV32-NEXT: vsll.vi v24, v16, 3 ; RV32-NEXT: li a3, 16
; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: mv a2, a1
; RV32-NEXT: bltu a1, a3, .LBB87_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB87_2:
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: addi a2, a1, -16 ; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a3, a1, a2 ; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a3, a3, -1 ; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a2, a3, a2 ; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v8, v24, 16
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: li a2, 16
; RV32-NEXT: bltu a1, a2, .LBB87_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB87_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vluxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_v32i8_v32f64: ; RV64-LABEL: vpgather_baseidx_v32i8_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v10, v0 ; RV64-NEXT: vmv1r.v v10, v0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v8
; RV64-NEXT: vsll.vi v24, v16, 3
; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; RV64-NEXT: vslidedown.vi v12, v8, 16 ; RV64-NEXT: vslidedown.vi v8, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v12 ; RV64-NEXT: vsext.vf8 v16, v8
; RV64-NEXT: vsll.vi v16, v16, 3 ; RV64-NEXT: vsll.vi v16, v16, 3
; RV64-NEXT: vsext.vf8 v24, v8
; RV64-NEXT: vsll.vi v24, v24, 3
; RV64-NEXT: addi a2, a1, -16 ; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a3, a1, a2 ; RV64-NEXT: sltu a3, a1, a2
; RV64-NEXT: addi a3, a3, -1 ; RV64-NEXT: addi a3, a3, -1
; RV64-NEXT: and a2, a3, a2 ; RV64-NEXT: and a2, a3, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2 ; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t ; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
Show All 9 Lines; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, ptr %base, <32 x i8> %idxs %ptrs = getelementptr inbounds double, ptr %base, <32 x i8> %idxs
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpgather_baseidx_sext_v32i8_v32f64(ptr %base, <32 x i8> %idxs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_baseidx_sext_v32i8_v32f64(ptr %base, <32 x i8> %idxs, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_sext_v32i8_v32f64: ; RV32-LABEL: vpgather_baseidx_sext_v32i8_v32f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vsext.vf4 v16, v8 ; RV32-NEXT: vsext.vf4 v16, v8
; RV32-NEXT: vsll.vi v24, v16, 3 ; RV32-NEXT: li a3, 16
; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: mv a2, a1
; RV32-NEXT: bltu a1, a3, .LBB88_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB88_2:
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: addi a2, a1, -16 ; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a3, a1, a2 ; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a3, a3, -1 ; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a2, a3, a2 ; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v8, v24, 16
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: li a2, 16
; RV32-NEXT: bltu a1, a2, .LBB88_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB88_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vluxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_v32i8_v32f64: ; RV64-LABEL: vpgather_baseidx_sext_v32i8_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v10, v0 ; RV64-NEXT: vmv1r.v v10, v0
; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; RV64-NEXT: vslidedown.vi v12, v8, 16 ; RV64-NEXT: vslidedown.vi v12, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v12 ; RV64-NEXT: vsext.vf8 v16, v12
; RV64-NEXT: vsext.vf8 v24, v8 ; RV64-NEXT: vsext.vf8 v24, v8
; RV64-NEXT: vsll.vi v16, v16, 3
; RV64-NEXT: vsll.vi v24, v24, 3 ; RV64-NEXT: vsll.vi v24, v24, 3
; RV64-NEXT: vsll.vi v16, v16, 3
; RV64-NEXT: addi a2, a1, -16 ; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a3, a1, a2 ; RV64-NEXT: sltu a3, a1, a2
; RV64-NEXT: addi a3, a3, -1 ; RV64-NEXT: addi a3, a3, -1
; RV64-NEXT: and a2, a3, a2 ; RV64-NEXT: and a2, a3, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2 ; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t ; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
Show All 10 Lines; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs %ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpgather_baseidx_zext_v32i8_v32f64(ptr %base, <32 x i8> %idxs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_baseidx_zext_v32i8_v32f64(ptr %base, <32 x i8> %idxs, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_zext_v32i8_v32f64: ; RV32-LABEL: vpgather_baseidx_zext_v32i8_v32f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vzext.vf4 v16, v8 ; RV32-NEXT: vzext.vf4 v16, v8
; RV32-NEXT: vsll.vi v24, v16, 3 ; RV32-NEXT: li a3, 16
; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: mv a2, a1
; RV32-NEXT: bltu a1, a3, .LBB89_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB89_2:
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: addi a2, a1, -16 ; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a3, a1, a2 ; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a3, a3, -1 ; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a2, a3, a2 ; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v8, v24, 16
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: li a2, 16
; RV32-NEXT: bltu a1, a2, .LBB89_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB89_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vluxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_v32i8_v32f64: ; RV64-LABEL: vpgather_baseidx_zext_v32i8_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v10, v0 ; RV64-NEXT: vmv1r.v v10, v0
; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; RV64-NEXT: vslidedown.vi v12, v8, 16 ; RV64-NEXT: vslidedown.vi v12, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vzext.vf8 v16, v12 ; RV64-NEXT: vzext.vf8 v16, v12
; RV64-NEXT: vzext.vf8 v24, v8 ; RV64-NEXT: vzext.vf8 v24, v8
; RV64-NEXT: vsll.vi v16, v16, 3
; RV64-NEXT: vsll.vi v24, v24, 3 ; RV64-NEXT: vsll.vi v24, v24, 3
; RV64-NEXT: vsll.vi v16, v16, 3
; RV64-NEXT: addi a2, a1, -16 ; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a3, a1, a2 ; RV64-NEXT: sltu a3, a1, a2
; RV64-NEXT: addi a3, a3, -1 ; RV64-NEXT: addi a3, a3, -1
; RV64-NEXT: and a2, a3, a2 ; RV64-NEXT: and a2, a3, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2 ; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t ; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
Show All 10 Lines; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs %ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpgather_baseidx_v32i16_v32f64(ptr %base, <32 x i16> %idxs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_baseidx_v32i16_v32f64(ptr %base, <32 x i16> %idxs, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_v32i16_v32f64: ; RV32-LABEL: vpgather_baseidx_v32i16_v32f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vsext.vf2 v16, v8 ; RV32-NEXT: vsext.vf2 v16, v8
; RV32-NEXT: vsll.vi v24, v16, 3 ; RV32-NEXT: li a3, 16
; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: mv a2, a1
; RV32-NEXT: bltu a1, a3, .LBB90_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB90_2:
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: addi a2, a1, -16 ; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a3, a1, a2 ; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a3, a3, -1 ; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a2, a3, a2 ; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v8, v24, 16
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: li a2, 16
; RV32-NEXT: bltu a1, a2, .LBB90_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB90_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vluxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_v32i16_v32f64: ; RV64-LABEL: vpgather_baseidx_v32i16_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v12, v0 ; RV64-NEXT: vmv1r.v v12, v0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf4 v16, v8
; RV64-NEXT: vsll.vi v24, v16, 3
; RV64-NEXT: vsetivli zero, 16, e16, m4, ta, ma ; RV64-NEXT: vsetivli zero, 16, e16, m4, ta, ma
; RV64-NEXT: vslidedown.vi v16, v8, 16 ; RV64-NEXT: vslidedown.vi v8, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf4 v24, v16 ; RV64-NEXT: vsext.vf4 v16, v8
; RV64-NEXT: vsll.vi v16, v24, 3 ; RV64-NEXT: vsll.vi v16, v16, 3
; RV64-NEXT: vsext.vf4 v24, v8
; RV64-NEXT: vsll.vi v24, v24, 3
; RV64-NEXT: addi a2, a1, -16 ; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a3, a1, a2 ; RV64-NEXT: sltu a3, a1, a2
; RV64-NEXT: addi a3, a3, -1 ; RV64-NEXT: addi a3, a3, -1
; RV64-NEXT: and a2, a3, a2 ; RV64-NEXT: and a2, a3, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2 ; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t ; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
Show All 9 Lines; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, ptr %base, <32 x i16> %idxs %ptrs = getelementptr inbounds double, ptr %base, <32 x i16> %idxs
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpgather_baseidx_sext_v32i16_v32f64(ptr %base, <32 x i16> %idxs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_baseidx_sext_v32i16_v32f64(ptr %base, <32 x i16> %idxs, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_sext_v32i16_v32f64: ; RV32-LABEL: vpgather_baseidx_sext_v32i16_v32f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vsext.vf2 v16, v8 ; RV32-NEXT: vsext.vf2 v16, v8
; RV32-NEXT: vsll.vi v24, v16, 3 ; RV32-NEXT: li a3, 16
; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: mv a2, a1
; RV32-NEXT: bltu a1, a3, .LBB91_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB91_2:
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: addi a2, a1, -16 ; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a3, a1, a2 ; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a3, a3, -1 ; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a2, a3, a2 ; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v8, v24, 16
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: li a2, 16
; RV32-NEXT: bltu a1, a2, .LBB91_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB91_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vluxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_v32i16_v32f64: ; RV64-LABEL: vpgather_baseidx_sext_v32i16_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v12, v0 ; RV64-NEXT: vmv1r.v v12, v0
; RV64-NEXT: vsetivli zero, 16, e16, m4, ta, ma ; RV64-NEXT: vsetivli zero, 16, e16, m4, ta, ma
; RV64-NEXT: vslidedown.vi v16, v8, 16 ; RV64-NEXT: vslidedown.vi v16, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf4 v24, v16 ; RV64-NEXT: vsext.vf4 v0, v16
; RV64-NEXT: vsext.vf4 v0, v8 ; RV64-NEXT: vsext.vf4 v16, v8
; RV64-NEXT: vsll.vi v16, v24, 3 ; RV64-NEXT: vsll.vi v24, v16, 3
; RV64-NEXT: vsll.vi v24, v0, 3 ; RV64-NEXT: vsll.vi v16, v0, 3
; RV64-NEXT: addi a2, a1, -16 ; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a3, a1, a2 ; RV64-NEXT: sltu a3, a1, a2
; RV64-NEXT: addi a3, a3, -1 ; RV64-NEXT: addi a3, a3, -1
; RV64-NEXT: and a2, a3, a2 ; RV64-NEXT: and a2, a3, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v12, 2 ; RV64-NEXT: vslidedown.vi v0, v12, 2
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t ; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
Show All 10 Lines; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs %ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpgather_baseidx_zext_v32i16_v32f64(ptr %base, <32 x i16> %idxs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_baseidx_zext_v32i16_v32f64(ptr %base, <32 x i16> %idxs, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_zext_v32i16_v32f64: ; RV32-LABEL: vpgather_baseidx_zext_v32i16_v32f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vzext.vf2 v16, v8 ; RV32-NEXT: vzext.vf2 v16, v8
; RV32-NEXT: vsll.vi v24, v16, 3 ; RV32-NEXT: li a3, 16
; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: mv a2, a1
; RV32-NEXT: bltu a1, a3, .LBB92_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB92_2:
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: addi a2, a1, -16 ; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a3, a1, a2 ; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a3, a3, -1 ; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a2, a3, a2 ; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v8, v24, 16
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: li a2, 16
; RV32-NEXT: bltu a1, a2, .LBB92_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB92_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vluxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_v32i16_v32f64: ; RV64-LABEL: vpgather_baseidx_zext_v32i16_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v12, v0 ; RV64-NEXT: vmv1r.v v12, v0
; RV64-NEXT: vsetivli zero, 16, e16, m4, ta, ma ; RV64-NEXT: vsetivli zero, 16, e16, m4, ta, ma
; RV64-NEXT: vslidedown.vi v16, v8, 16 ; RV64-NEXT: vslidedown.vi v16, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vzext.vf4 v24, v16 ; RV64-NEXT: vzext.vf4 v0, v16
; RV64-NEXT: vzext.vf4 v0, v8 ; RV64-NEXT: vzext.vf4 v16, v8
; RV64-NEXT: vsll.vi v16, v24, 3 ; RV64-NEXT: vsll.vi v24, v16, 3
; RV64-NEXT: vsll.vi v24, v0, 3 ; RV64-NEXT: vsll.vi v16, v0, 3
; RV64-NEXT: addi a2, a1, -16 ; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a3, a1, a2 ; RV64-NEXT: sltu a3, a1, a2
; RV64-NEXT: addi a3, a3, -1 ; RV64-NEXT: addi a3, a3, -1
; RV64-NEXT: and a2, a3, a2 ; RV64-NEXT: and a2, a3, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v12, 2 ; RV64-NEXT: vslidedown.vi v0, v12, 2
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t ; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
Show All 36 Lines
; RV32-NEXT: .LBB93_2: ; RV32-NEXT: .LBB93_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: vluxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_v32i32_v32f64: ; RV64-LABEL: vpgather_baseidx_v32i32_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: sub sp, sp, a2
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV64-NEXT: vmv1r.v v24, v0 ; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf2 v16, v8
; RV64-NEXT: vsll.vi v16, v16, 3
; RV64-NEXT: addi a2, sp, 16
; RV64-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV64-NEXT: vslidedown.vi v16, v8, 16 ; RV64-NEXT: vslidedown.vi v8, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf2 v0, v16 ; RV64-NEXT: vsext.vf2 v16, v8
; RV64-NEXT: vsll.vi v16, v0, 3 ; RV64-NEXT: vsll.vi v8, v16, 3
; RV64-NEXT: vsext.vf2 v0, v8
; RV64-NEXT: vsll.vi v8, v0, 3
; RV64-NEXT: addi a2, a1, -16 ; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a3, a1, a2 ; RV64-NEXT: sltu a3, a1, a2
; RV64-NEXT: addi a3, a3, -1 ; RV64-NEXT: addi a3, a3, -1
; RV64-NEXT: and a2, a3, a2 ; RV64-NEXT: and a2, a3, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v24, 2 ; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t ; RV64-NEXT: vluxei64.v v16, (a0), v8, v0.t
; RV64-NEXT: li a2, 16 ; RV64-NEXT: li a2, 16
; RV64-NEXT: bltu a1, a2, .LBB93_2 ; RV64-NEXT: bltu a1, a2, .LBB93_2
; RV64-NEXT: # %bb.1: ; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16 ; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB93_2: ; RV64-NEXT: .LBB93_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vmv1r.v v0, v24
; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t ; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, ptr %base, <32 x i32> %idxs %ptrs = getelementptr inbounds double, ptr %base, <32 x i32> %idxs
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpgather_baseidx_sext_v32i32_v32f64(ptr %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_baseidx_sext_v32i32_v32f64(ptr %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_sext_v32i32_v32f64: ; RV32-LABEL: vpgather_baseidx_sext_v32i32_v32f64:
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; RV32-NEXT: .LBB94_2: ; RV32-NEXT: .LBB94_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: vluxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_v32i32_v32f64: ; RV64-LABEL: vpgather_baseidx_sext_v32i32_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a2, a2, 1
; RV64-NEXT: sub sp, sp, a2
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; RV64-NEXT: addi a2, sp, 16
; RV64-NEXT: vs1r.v v0, (a2) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV64-NEXT: vslidedown.vi v16, v8, 16 ; RV64-NEXT: vslidedown.vi v16, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf2 v0, v16 ; RV64-NEXT: vsext.vf2 v0, v16
; RV64-NEXT: vsext.vf2 v24, v8 ; RV64-NEXT: vsext.vf2 v16, v8
; RV64-NEXT: vsll.vi v8, v16, 3
; RV64-NEXT: vsll.vi v16, v0, 3 ; RV64-NEXT: vsll.vi v16, v0, 3
; RV64-NEXT: vsll.vi v8, v24, 3
; RV64-NEXT: vl1r.v v24, (a2) # Unknown-size Folded Reload
; RV64-NEXT: addi a2, a1, -16 ; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a3, a1, a2 ; RV64-NEXT: sltu a3, a1, a2
; RV64-NEXT: addi a3, a3, -1 ; RV64-NEXT: addi a3, a3, -1
; RV64-NEXT: and a2, a3, a2 ; RV64-NEXT: and a2, a3, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v24, 2 ; RV64-NEXT: vslidedown.vi v0, v24, 2
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t ; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: li a2, 16 ; RV64-NEXT: li a2, 16
; RV64-NEXT: bltu a1, a2, .LBB94_2 ; RV64-NEXT: bltu a1, a2, .LBB94_2
; RV64-NEXT: # %bb.1: ; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16 ; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB94_2: ; RV64-NEXT: .LBB94_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vmv1r.v v0, v24
; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t ; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 1
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = sext <32 x i32> %idxs to <32 x i64> %eidxs = sext <32 x i32> %idxs to <32 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs %ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpgather_baseidx_zext_v32i32_v32f64(ptr %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_baseidx_zext_v32i32_v32f64(ptr %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) {
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; RV32-NEXT: .LBB95_2: ; RV32-NEXT: .LBB95_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: vluxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_v32i32_v32f64: ; RV64-LABEL: vpgather_baseidx_zext_v32i32_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a2, a2, 1
; RV64-NEXT: sub sp, sp, a2
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; RV64-NEXT: addi a2, sp, 16
; RV64-NEXT: vs1r.v v0, (a2) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV64-NEXT: vslidedown.vi v16, v8, 16 ; RV64-NEXT: vslidedown.vi v16, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vzext.vf2 v0, v16 ; RV64-NEXT: vzext.vf2 v0, v16
; RV64-NEXT: vzext.vf2 v24, v8 ; RV64-NEXT: vzext.vf2 v16, v8
; RV64-NEXT: vsll.vi v8, v16, 3
; RV64-NEXT: vsll.vi v16, v0, 3 ; RV64-NEXT: vsll.vi v16, v0, 3
; RV64-NEXT: vsll.vi v8, v24, 3
; RV64-NEXT: vl1r.v v24, (a2) # Unknown-size Folded Reload
; RV64-NEXT: addi a2, a1, -16 ; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a3, a1, a2 ; RV64-NEXT: sltu a3, a1, a2
; RV64-NEXT: addi a3, a3, -1 ; RV64-NEXT: addi a3, a3, -1
; RV64-NEXT: and a2, a3, a2 ; RV64-NEXT: and a2, a3, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v24, 2 ; RV64-NEXT: vslidedown.vi v0, v24, 2
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t ; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: li a2, 16 ; RV64-NEXT: li a2, 16
; RV64-NEXT: bltu a1, a2, .LBB95_2 ; RV64-NEXT: bltu a1, a2, .LBB95_2
; RV64-NEXT: # %bb.1: ; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16 ; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB95_2: ; RV64-NEXT: .LBB95_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vmv1r.v v0, v24
; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t ; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 1
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = zext <32 x i32> %idxs to <32 x i64> %eidxs = zext <32 x i32> %idxs to <32 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs %ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpgather_baseidx_v32f64(ptr %base, <32 x i64> %idxs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_baseidx_v32f64(ptr %base, <32 x i64> %idxs, <32 x i1> %m, i32 zeroext %evl) {
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llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll

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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f32.nxv8i32(<vscale x 8 x float> %f) %x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f32.nxv8i32(<vscale x 8 x float> %f)
ret <vscale x 8 x i32> %x ret <vscale x 8 x i32> %x
} }
define <vscale x 4 x i16> @test_signed_v4f32_v4i16(<vscale x 4 x float> %f) { define <vscale x 4 x i16> @test_signed_v4f32_v4i16(<vscale x 4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i16: ; CHECK-LABEL: test_signed_v4f32_v4i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f32.nxv4i16(<vscale x 4 x float> %f) %x = call <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f32.nxv4i16(<vscale x 4 x float> %f)
ret <vscale x 4 x i16> %x ret <vscale x 4 x i16> %x
} }
define <vscale x 8 x i16> @test_signed_v8f32_v8i16(<vscale x 8 x float> %f) { define <vscale x 8 x i16> @test_signed_v8f32_v8i16(<vscale x 8 x float> %f) {
; CHECK-LABEL: test_signed_v8f32_v8i16: ; CHECK-LABEL: test_signed_v8f32_v8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f32.nxv8i16(<vscale x 8 x float> %f) %x = call <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f32.nxv8i16(<vscale x 8 x float> %f)
ret <vscale x 8 x i16> %x ret <vscale x 8 x i16> %x
} }
define <vscale x 2 x i64> @test_signed_v2f32_v2i64(<vscale x 2 x float> %f) { define <vscale x 2 x i64> @test_signed_v2f32_v2i64(<vscale x 2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i64: ; CHECK-LABEL: test_signed_v2f32_v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8 ; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f32.nxv2i64(<vscale x 2 x float> %f) %x = call <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f32.nxv2i64(<vscale x 2 x float> %f)
ret <vscale x 2 x i64> %x ret <vscale x 2 x i64> %x
} }
define <vscale x 4 x i64> @test_signed_v4f32_v4i64(<vscale x 4 x float> %f) { define <vscale x 4 x i64> @test_signed_v4f32_v4i64(<vscale x 4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i64: ; CHECK-LABEL: test_signed_v4f32_v4i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8 ; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f32.nxv4i64(<vscale x 4 x float> %f) %x = call <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f32.nxv4i64(<vscale x 4 x float> %f)
ret <vscale x 4 x i64> %x ret <vscale x 4 x i64> %x
} }
; Double ; Double
declare <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f64.nxv2i32(<vscale x 2 x double>) declare <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f64.nxv2i32(<vscale x 2 x double>)
declare <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f64.nxv4i32(<vscale x 4 x double>) declare <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f64.nxv4i32(<vscale x 4 x double>)
declare <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f64.nxv8i32(<vscale x 8 x double>) declare <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f64.nxv8i32(<vscale x 8 x double>)
declare <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f64.nxv4i16(<vscale x 4 x double>) declare <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f64.nxv4i16(<vscale x 4 x double>)
declare <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f64.nxv8i16(<vscale x 8 x double>) declare <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f64.nxv8i16(<vscale x 8 x double>)
declare <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f64.nxv2i64(<vscale x 2 x double>) declare <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f64.nxv2i64(<vscale x 2 x double>)
declare <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f64.nxv4i64(<vscale x 4 x double>) declare <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f64.nxv4i64(<vscale x 4 x double>)
define <vscale x 2 x i32> @test_signed_v2f64_v2i32(<vscale x 2 x double> %f) { define <vscale x 2 x i32> @test_signed_v2f64_v2i32(<vscale x 2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i32: ; CHECK-LABEL: test_signed_v2f64_v2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f64.nxv2i32(<vscale x 2 x double> %f) %x = call <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f64.nxv2i32(<vscale x 2 x double> %f)
ret <vscale x 2 x i32> %x ret <vscale x 2 x i32> %x
} }
define <vscale x 4 x i32> @test_signed_v4f64_v4i32(<vscale x 4 x double> %f) { define <vscale x 4 x i32> @test_signed_v4f64_v4i32(<vscale x 4 x double> %f) {
; CHECK-LABEL: test_signed_v4f64_v4i32: ; CHECK-LABEL: test_signed_v4f64_v4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f64.nxv4i32(<vscale x 4 x double> %f) %x = call <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f64.nxv4i32(<vscale x 4 x double> %f)
ret <vscale x 4 x i32> %x ret <vscale x 4 x i32> %x
} }
define <vscale x 8 x i32> @test_signed_v8f64_v8i32(<vscale x 8 x double> %f) { define <vscale x 8 x i32> @test_signed_v8f64_v8i32(<vscale x 8 x double> %f) {
; CHECK-LABEL: test_signed_v8f64_v8i32: ; CHECK-LABEL: test_signed_v8f64_v8i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
; CHECK-NEXT: vmerge.vim v8, v16, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v16, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f64.nxv8i32(<vscale x 8 x double> %f) %x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f64.nxv8i32(<vscale x 8 x double> %f)
ret <vscale x 8 x i32> %x ret <vscale x 8 x i32> %x
} }
define <vscale x 4 x i16> @test_signed_v4f64_v4i16(<vscale x 4 x double> %f) { define <vscale x 4 x i16> @test_signed_v4f64_v4i16(<vscale x 4 x double> %f) {
; CHECK-LABEL: test_signed_v4f64_v4i16: ; CHECK-LABEL: test_signed_v4f64_v4i16:
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
declare <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f16.nxv8i16(<vscale x 8 x half>) declare <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f16.nxv8i16(<vscale x 8 x half>)
declare <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f16.nxv2i64(<vscale x 2 x half>) declare <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f16.nxv2i64(<vscale x 2 x half>)
declare <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f16.nxv4i64(<vscale x 4 x half>) declare <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f16.nxv4i64(<vscale x 4 x half>)
define <vscale x 2 x i32> @test_signed_v2f16_v2i32(<vscale x 2 x half> %f) { define <vscale x 2 x i32> @test_signed_v2f16_v2i32(<vscale x 2 x half> %f) {
; CHECK-LABEL: test_signed_v2f16_v2i32: ; CHECK-LABEL: test_signed_v2f16_v2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v9, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v9, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f16.nxv2i32(<vscale x 2 x half> %f) %x = call <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f16.nxv2i32(<vscale x 2 x half> %f)
ret <vscale x 2 x i32> %x ret <vscale x 2 x i32> %x
} }
define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) { define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i32: ; CHECK-LABEL: test_signed_v4f16_v4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8 ; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f16.nxv4i32(<vscale x 4 x half> %f) %x = call <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f16.nxv4i32(<vscale x 4 x half> %f)
ret <vscale x 4 x i32> %x ret <vscale x 4 x i32> %x
} }
define <vscale x 8 x i32> @test_signed_v8f16_v8i32(<vscale x 8 x half> %f) { define <vscale x 8 x i32> @test_signed_v8f16_v8i32(<vscale x 8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i32: ; CHECK-LABEL: test_signed_v8f16_v8i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8 ; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f16.nxv8i32(<vscale x 8 x half> %f) %x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f16.nxv8i32(<vscale x 8 x half> %f)
ret <vscale x 8 x i32> %x ret <vscale x 8 x i32> %x
} }
define <vscale x 4 x i16> @test_signed_v4f16_v4i16(<vscale x 4 x half> %f) { define <vscale x 4 x i16> @test_signed_v4f16_v4i16(<vscale x 4 x half> %f) {
Show All 19 Lines; CHECK-NEXT: ret
%x = call <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f16.nxv8i16(<vscale x 8 x half> %f) %x = call <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f16.nxv8i16(<vscale x 8 x half> %f)
ret <vscale x 8 x i16> %x ret <vscale x 8 x i16> %x
} }
define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) { define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) {
; CHECK-LABEL: test_signed_v2f16_v2i64: ; CHECK-LABEL: test_signed_v2f16_v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vfwcvt.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v9 ; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v9
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f16.nxv2i64(<vscale x 2 x half> %f) %x = call <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f16.nxv2i64(<vscale x 2 x half> %f)
ret <vscale x 2 x i64> %x ret <vscale x 2 x i64> %x
} }
define <vscale x 4 x i64> @test_signed_v4f16_v4i64(<vscale x 4 x half> %f) { define <vscale x 4 x i64> @test_signed_v4f16_v4i64(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i64: ; CHECK-LABEL: test_signed_v4f16_v4i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.f.f.v v10, v8 ; CHECK-NEXT: vfwcvt.f.f.v v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v10 ; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v10
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f16.nxv4i64(<vscale x 4 x half> %f) %x = call <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f16.nxv4i64(<vscale x 4 x half> %f)
ret <vscale x 4 x i64> %x ret <vscale x 4 x i64> %x
} }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK32: {{.*}} ; CHECK32: {{.*}}
; CHECK64: {{.*}} ; CHECK64: {{.*}}

llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f32.nxv8i32(<vscale x 8 x float> %f) %x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f32.nxv8i32(<vscale x 8 x float> %f)
ret <vscale x 8 x i32> %x ret <vscale x 8 x i32> %x
} }
define <vscale x 4 x i16> @test_signed_v4f32_v4i16(<vscale x 4 x float> %f) { define <vscale x 4 x i16> @test_signed_v4f32_v4i16(<vscale x 4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i16: ; CHECK-LABEL: test_signed_v4f32_v4i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f32.nxv4i16(<vscale x 4 x float> %f) %x = call <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f32.nxv4i16(<vscale x 4 x float> %f)
ret <vscale x 4 x i16> %x ret <vscale x 4 x i16> %x
} }
define <vscale x 8 x i16> @test_signed_v8f32_v8i16(<vscale x 8 x float> %f) { define <vscale x 8 x i16> @test_signed_v8f32_v8i16(<vscale x 8 x float> %f) {
; CHECK-LABEL: test_signed_v8f32_v8i16: ; CHECK-LABEL: test_signed_v8f32_v8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f32.nxv8i16(<vscale x 8 x float> %f) %x = call <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f32.nxv8i16(<vscale x 8 x float> %f)
ret <vscale x 8 x i16> %x ret <vscale x 8 x i16> %x
} }
define <vscale x 2 x i64> @test_signed_v2f32_v2i64(<vscale x 2 x float> %f) { define <vscale x 2 x i64> @test_signed_v2f32_v2i64(<vscale x 2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i64: ; CHECK-LABEL: test_signed_v2f32_v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8 ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f32.nxv2i64(<vscale x 2 x float> %f) %x = call <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f32.nxv2i64(<vscale x 2 x float> %f)
ret <vscale x 2 x i64> %x ret <vscale x 2 x i64> %x
} }
define <vscale x 4 x i64> @test_signed_v4f32_v4i64(<vscale x 4 x float> %f) { define <vscale x 4 x i64> @test_signed_v4f32_v4i64(<vscale x 4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i64: ; CHECK-LABEL: test_signed_v4f32_v4i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8 ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f32.nxv4i64(<vscale x 4 x float> %f) %x = call <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f32.nxv4i64(<vscale x 4 x float> %f)
ret <vscale x 4 x i64> %x ret <vscale x 4 x i64> %x
} }
; Double ; Double
declare <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f64.nxv2i32(<vscale x 2 x double>) declare <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f64.nxv2i32(<vscale x 2 x double>)
declare <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f64.nxv4i32(<vscale x 4 x double>) declare <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f64.nxv4i32(<vscale x 4 x double>)
declare <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f64.nxv8i32(<vscale x 8 x double>) declare <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f64.nxv8i32(<vscale x 8 x double>)
declare <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f64.nxv4i16(<vscale x 4 x double>) declare <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f64.nxv4i16(<vscale x 4 x double>)
declare <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f64.nxv8i16(<vscale x 8 x double>) declare <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f64.nxv8i16(<vscale x 8 x double>)
declare <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f64.nxv2i64(<vscale x 2 x double>) declare <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f64.nxv2i64(<vscale x 2 x double>)
declare <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f64.nxv4i64(<vscale x 4 x double>) declare <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f64.nxv4i64(<vscale x 4 x double>)
define <vscale x 2 x i32> @test_signed_v2f64_v2i32(<vscale x 2 x double> %f) { define <vscale x 2 x i32> @test_signed_v2f64_v2i32(<vscale x 2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i32: ; CHECK-LABEL: test_signed_v2f64_v2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f64.nxv2i32(<vscale x 2 x double> %f) %x = call <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f64.nxv2i32(<vscale x 2 x double> %f)
ret <vscale x 2 x i32> %x ret <vscale x 2 x i32> %x
} }
define <vscale x 4 x i32> @test_signed_v4f64_v4i32(<vscale x 4 x double> %f) { define <vscale x 4 x i32> @test_signed_v4f64_v4i32(<vscale x 4 x double> %f) {
; CHECK-LABEL: test_signed_v4f64_v4i32: ; CHECK-LABEL: test_signed_v4f64_v4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f64.nxv4i32(<vscale x 4 x double> %f) %x = call <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f64.nxv4i32(<vscale x 4 x double> %f)
ret <vscale x 4 x i32> %x ret <vscale x 4 x i32> %x
} }
define <vscale x 8 x i32> @test_signed_v8f64_v8i32(<vscale x 8 x double> %f) { define <vscale x 8 x i32> @test_signed_v8f64_v8i32(<vscale x 8 x double> %f) {
; CHECK-LABEL: test_signed_v8f64_v8i32: ; CHECK-LABEL: test_signed_v8f64_v8i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
; CHECK-NEXT: vmerge.vim v8, v16, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v16, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f64.nxv8i32(<vscale x 8 x double> %f) %x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f64.nxv8i32(<vscale x 8 x double> %f)
ret <vscale x 8 x i32> %x ret <vscale x 8 x i32> %x
} }
define <vscale x 4 x i16> @test_signed_v4f64_v4i16(<vscale x 4 x double> %f) { define <vscale x 4 x i16> @test_signed_v4f64_v4i16(<vscale x 4 x double> %f) {
; CHECK32-LABEL: test_signed_v4f64_v4i16: ; CHECK32-LABEL: test_signed_v4f64_v4i16:
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
declare <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f16.nxv8i16(<vscale x 8 x half>) declare <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f16.nxv8i16(<vscale x 8 x half>)
declare <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f16.nxv2i64(<vscale x 2 x half>) declare <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f16.nxv2i64(<vscale x 2 x half>)
declare <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f16.nxv4i64(<vscale x 4 x half>) declare <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f16.nxv4i64(<vscale x 4 x half>)
define <vscale x 2 x i32> @test_signed_v2f16_v2i32(<vscale x 2 x half> %f) { define <vscale x 2 x i32> @test_signed_v2f16_v2i32(<vscale x 2 x half> %f) {
; CHECK-LABEL: test_signed_v2f16_v2i32: ; CHECK-LABEL: test_signed_v2f16_v2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8 ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v9, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v9, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f16.nxv2i32(<vscale x 2 x half> %f) %x = call <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f16.nxv2i32(<vscale x 2 x half> %f)
ret <vscale x 2 x i32> %x ret <vscale x 2 x i32> %x
} }
define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) { define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i32: ; CHECK-LABEL: test_signed_v4f16_v4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8 ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f16.nxv4i32(<vscale x 4 x half> %f) %x = call <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f16.nxv4i32(<vscale x 4 x half> %f)
ret <vscale x 4 x i32> %x ret <vscale x 4 x i32> %x
} }
define <vscale x 8 x i32> @test_signed_v8f16_v8i32(<vscale x 8 x half> %f) { define <vscale x 8 x i32> @test_signed_v8f16_v8i32(<vscale x 8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i32: ; CHECK-LABEL: test_signed_v8f16_v8i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8 ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f16.nxv8i32(<vscale x 8 x half> %f) %x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f16.nxv8i32(<vscale x 8 x half> %f)
ret <vscale x 8 x i32> %x ret <vscale x 8 x i32> %x
} }
define <vscale x 4 x i16> @test_signed_v4f16_v4i16(<vscale x 4 x half> %f) { define <vscale x 4 x i16> @test_signed_v4f16_v4i16(<vscale x 4 x half> %f) {
Show All 19 Lines; CHECK-NEXT: ret
%x = call <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f16.nxv8i16(<vscale x 8 x half> %f) %x = call <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f16.nxv8i16(<vscale x 8 x half> %f)
ret <vscale x 8 x i16> %x ret <vscale x 8 x i16> %x
} }
define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) { define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) {
; CHECK-LABEL: test_signed_v2f16_v2i64: ; CHECK-LABEL: test_signed_v2f16_v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vfwcvt.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v9 ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v9
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f16.nxv2i64(<vscale x 2 x half> %f) %x = call <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f16.nxv2i64(<vscale x 2 x half> %f)
ret <vscale x 2 x i64> %x ret <vscale x 2 x i64> %x
} }
define <vscale x 4 x i64> @test_signed_v4f16_v4i64(<vscale x 4 x half> %f) { define <vscale x 4 x i64> @test_signed_v4f16_v4i64(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i64: ; CHECK-LABEL: test_signed_v4f16_v4i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.f.f.v v10, v8 ; CHECK-NEXT: vfwcvt.f.f.v v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v10 ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v10
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f16.nxv4i64(<vscale x 4 x half> %f) %x = call <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f16.nxv4i64(<vscale x 4 x half> %f)
ret <vscale x 4 x i64> %x ret <vscale x 4 x i64> %x
} }

llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll

Show First 20 Lines • Show All 2,170 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsext.vf4 v16, v8 ; RV32-NEXT: vsext.vf4 v16, v8
; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV32-NEXT: vluxei32.v v10, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v10, (a0), v16, v0.t
; RV32-NEXT: vmv.v.v v8, v10 ; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_nxv16i8: ; RV64-LABEL: mgather_baseidx_nxv16i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmv1r.v v12, v0
; RV64-NEXT: vsext.vf8 v16, v8
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vluxei64.v v10, (a0), v16, v0.t
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: srli a1, a1, 3 ; RV64-NEXT: srli a1, a1, 3
; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma ; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vx v0, v0, a1 ; RV64-NEXT: vslidedown.vx v0, v0, a1
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v9 ; RV64-NEXT: vsext.vf8 v16, v9
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vluxei64.v v11, (a0), v16, v0.t ; RV64-NEXT: vluxei64.v v11, (a0), v16, v0.t
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v8
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vmv1r.v v0, v12
; RV64-NEXT: vluxei64.v v10, (a0), v16, v0.t
; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret ; RV64-NEXT: ret
%ptrs = getelementptr inbounds i8, ptr %base, <vscale x 16 x i8> %idxs %ptrs = getelementptr inbounds i8, ptr %base, <vscale x 16 x i8> %idxs
%v = call <vscale x 16 x i8> @llvm.masked.gather.nxv16i8.nxv16p0(<vscale x 16 x ptr> %ptrs, i32 2, <vscale x 16 x i1> %m, <vscale x 16 x i8> %passthru) %v = call <vscale x 16 x i8> @llvm.masked.gather.nxv16i8.nxv16p0(<vscale x 16 x ptr> %ptrs, i32 2, <vscale x 16 x i1> %m, <vscale x 16 x i8> %passthru)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
declare <vscale x 32 x i8> @llvm.masked.gather.nxv32i8.nxv32p0(<vscale x 32 x ptr>, i32, <vscale x 32 x i1>, <vscale x 32 x i8>) declare <vscale x 32 x i8> @llvm.masked.gather.nxv32i8.nxv32p0(<vscale x 32 x ptr>, i32, <vscale x 32 x i1>, <vscale x 32 x i8>)
define <vscale x 32 x i8> @mgather_baseidx_nxv32i8(ptr %base, <vscale x 32 x i8> %idxs, <vscale x 32 x i1> %m, <vscale x 32 x i8> %passthru) { define <vscale x 32 x i8> @mgather_baseidx_nxv32i8(ptr %base, <vscale x 32 x i8> %idxs, <vscale x 32 x i1> %m, <vscale x 32 x i8> %passthru) {
; RV32-LABEL: mgather_baseidx_nxv32i8: ; RV32-LABEL: mgather_baseidx_nxv32i8:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: vsext.vf4 v16, v8
; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: srli a1, a1, 2 ; RV32-NEXT: srli a1, a1, 2
; RV32-NEXT: vsetvli a2, zero, e8, mf2, ta, ma ; RV32-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; RV32-NEXT: vslidedown.vx v0, v0, a1 ; RV32-NEXT: vslidedown.vx v0, v0, a1
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
; RV32-NEXT: vsext.vf4 v16, v10 ; RV32-NEXT: vsext.vf4 v24, v10
; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV32-NEXT: vluxei32.v v14, (a0), v24, v0.t
; RV32-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; RV32-NEXT: vsext.vf4 v24, v8
; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV32-NEXT: vluxei32.v v14, (a0), v16, v0.t ; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: vluxei32.v v12, (a0), v24, v0.t
; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_nxv32i8: ; RV64-LABEL: mgather_baseidx_nxv32i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v16, v0 ; RV64-NEXT: vmv1r.v v16, v0
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v24, v8
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vluxei64.v v12, (a0), v24, v0.t
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: srli a2, a1, 3 ; RV64-NEXT: srli a2, a1, 2
; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma ; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; RV64-NEXT: vslidedown.vx v0, v0, a2 ; RV64-NEXT: vslidedown.vx v17, v0, a2
; RV64-NEXT: vsetvli a3, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v24, v10
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vmv1r.v v0, v17
; RV64-NEXT: vluxei64.v v14, (a0), v24, v0.t
; RV64-NEXT: srli a1, a1, 3
; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vx v0, v16, a1
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v24, v9 ; RV64-NEXT: vsext.vf8 v24, v9
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vluxei64.v v13, (a0), v24, v0.t ; RV64-NEXT: vluxei64.v v13, (a0), v24, v0.t
; RV64-NEXT: srli a1, a1, 2 ; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma ; RV64-NEXT: vsext.vf8 v24, v8
; RV64-NEXT: vslidedown.vx v0, v16, a1
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v10
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vluxei64.v v14, (a0), v16, v0.t ; RV64-NEXT: vmv1r.v v0, v16
; RV64-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; RV64-NEXT: vluxei64.v v12, (a0), v24, v0.t
; RV64-NEXT: vslidedown.vx v0, v0, a2 ; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vx v0, v17, a1
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v11 ; RV64-NEXT: vsext.vf8 v16, v11
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vluxei64.v v15, (a0), v16, v0.t ; RV64-NEXT: vluxei64.v v15, (a0), v16, v0.t
; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret ; RV64-NEXT: ret
%ptrs = getelementptr inbounds i8, ptr %base, <vscale x 32 x i8> %idxs %ptrs = getelementptr inbounds i8, ptr %base, <vscale x 32 x i8> %idxs
%v = call <vscale x 32 x i8> @llvm.masked.gather.nxv32i8.nxv32p0(<vscale x 32 x ptr> %ptrs, i32 2, <vscale x 32 x i1> %m, <vscale x 32 x i8> %passthru) %v = call <vscale x 32 x i8> @llvm.masked.gather.nxv32i8.nxv32p0(<vscale x 32 x ptr> %ptrs, i32 2, <vscale x 32 x i1> %m, <vscale x 32 x i8> %passthru)
ret <vscale x 32 x i8> %v ret <vscale x 32 x i8> %v
} }

llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll

Show First 20 Lines • Show All 899 Lines • ▼ Show 20 Lines
; Folding this would create a loop in the DAG becuase the chain from the VLE is ; Folding this would create a loop in the DAG becuase the chain from the VLE is
; used by the vssubu. ; used by the vssubu.
define void @test_dag_loop() { define void @test_dag_loop() {
; CHECK-LABEL: test_dag_loop: ; CHECK-LABEL: test_dag_loop:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v8, (zero) ; CHECK-NEXT: vle16.v v8, (zero)
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: vsetivli zero, 0, e8, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 0, e8, m4, tu, mu
; CHECK-NEXT: vmv4r.v v20, v16 ; CHECK-NEXT: vmv4r.v v20, v16
; CHECK-NEXT: vssubu.vx v20, v16, zero, v0.t ; CHECK-NEXT: vssubu.vx v20, v16, zero, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma
; CHECK-NEXT: vmseq.vv v0, v20, v16 ; CHECK-NEXT: vmseq.vv v0, v20, v16
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetivli zero, 1, e16, m8, tu, ma ; CHECK-NEXT: vsetivli zero, 1, e16, m8, tu, ma
Show All 18 Lines

llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll

Show First 20 Lines • Show All 228 Lines • ▼ Show 20 Lines
} }
define <vscale x 1 x i1> @fcmp_ord_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ord_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_nxv1f16: ; CHECK-LABEL: fcmp_ord_vf_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t ; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmand.mm v0, v8, v9 ; CHECK-NEXT: vmand.mm v0, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_ord_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ord_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_swap_nxv1f16: ; CHECK-LABEL: fcmp_ord_vf_swap_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t ; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmand.mm v0, v9, v8 ; CHECK-NEXT: vmand.mm v0, v9, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
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} }
define <vscale x 1 x i1> @fcmp_uno_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_uno_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_nxv1f16: ; CHECK-LABEL: fcmp_uno_vf_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t ; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v8, v9 ; CHECK-NEXT: vmor.mm v0, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_uno_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_uno_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_swap_nxv1f16: ; CHECK-LABEL: fcmp_uno_vf_swap_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t ; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
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} }
define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_nxv8f16: ; CHECK-LABEL: fcmp_ord_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vmfeq.vf v12, v10, fa0, v0.t ; CHECK-NEXT: vmfeq.vv v12, v8, v8, v0.t
; CHECK-NEXT: vmfeq.vv v10, v8, v8, v0.t ; CHECK-NEXT: vmfeq.vf v8, v10, fa0, v0.t
; CHECK-NEXT: vmand.mm v0, v10, v12 ; CHECK-NEXT: vmand.mm v0, v12, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ord_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ord_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_swap_nxv8f16: ; CHECK-LABEL: fcmp_ord_vf_swap_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vmfeq.vf v12, v10, fa0, v0.t ; CHECK-NEXT: vmfeq.vv v12, v8, v8, v0.t
; CHECK-NEXT: vmfeq.vv v10, v8, v8, v0.t ; CHECK-NEXT: vmfeq.vf v8, v10, fa0, v0.t
; CHECK-NEXT: vmand.mm v0, v12, v10 ; CHECK-NEXT: vmand.mm v0, v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
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} }
define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_nxv8f16: ; CHECK-LABEL: fcmp_uno_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vmfne.vf v12, v10, fa0, v0.t ; CHECK-NEXT: vmfne.vv v12, v8, v8, v0.t
; CHECK-NEXT: vmfne.vv v10, v8, v8, v0.t ; CHECK-NEXT: vmfne.vf v8, v10, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v10, v12 ; CHECK-NEXT: vmor.mm v0, v12, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_uno_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_uno_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_swap_nxv8f16: ; CHECK-LABEL: fcmp_uno_vf_swap_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vmfne.vf v12, v10, fa0, v0.t ; CHECK-NEXT: vmfne.vv v12, v8, v8, v0.t
; CHECK-NEXT: vmfne.vv v10, v8, v8, v0.t ; CHECK-NEXT: vmfne.vf v8, v10, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v12, v10 ; CHECK-NEXT: vmor.mm v0, v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
declare <vscale x 64 x i1> @llvm.vp.fcmp.nxv64f16(<vscale x 64 x half>, <vscale x 64 x half>, metadata, <vscale x 64 x i1>, i32) declare <vscale x 64 x i1> @llvm.vp.fcmp.nxv64f16(<vscale x 64 x half>, <vscale x 64 x half>, metadata, <vscale x 64 x i1>, i32)
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} }
define <vscale x 1 x i1> @fcmp_ord_vf_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ord_vf_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_nxv1f64: ; CHECK-LABEL: fcmp_ord_vf_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t ; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmand.mm v0, v8, v9 ; CHECK-NEXT: vmand.mm v0, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_ord_vf_swap_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ord_vf_swap_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_swap_nxv1f64: ; CHECK-LABEL: fcmp_ord_vf_swap_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t ; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmand.mm v0, v9, v8 ; CHECK-NEXT: vmand.mm v0, v9, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %vb, <vscale x 1 x double> %va, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %vb, <vscale x 1 x double> %va, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
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} }
define <vscale x 1 x i1> @fcmp_uno_vf_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_uno_vf_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_nxv1f64: ; CHECK-LABEL: fcmp_uno_vf_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t ; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v8, v9 ; CHECK-NEXT: vmor.mm v0, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_uno_vf_swap_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_uno_vf_swap_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_swap_nxv1f64: ; CHECK-LABEL: fcmp_uno_vf_swap_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t ; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %vb, <vscale x 1 x double> %va, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %vb, <vscale x 1 x double> %va, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
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} }
define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_nxv8f64: ; CHECK-LABEL: fcmp_ord_vf_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; CHECK-NEXT: vfmv.v.f v16, fa0 ; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vf v24, v16, fa0, v0.t ; CHECK-NEXT: vmfeq.vv v24, v8, v8, v0.t
; CHECK-NEXT: vmfeq.vv v16, v8, v8, v0.t ; CHECK-NEXT: vmfeq.vf v8, v16, fa0, v0.t
; CHECK-NEXT: vmand.mm v0, v16, v24 ; CHECK-NEXT: vmand.mm v0, v24, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ord_vf_swap_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ord_vf_swap_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_swap_nxv8f64: ; CHECK-LABEL: fcmp_ord_vf_swap_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; CHECK-NEXT: vfmv.v.f v16, fa0 ; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vf v24, v16, fa0, v0.t ; CHECK-NEXT: vmfeq.vv v24, v8, v8, v0.t
; CHECK-NEXT: vmfeq.vv v16, v8, v8, v0.t ; CHECK-NEXT: vmfeq.vf v8, v16, fa0, v0.t
; CHECK-NEXT: vmand.mm v0, v24, v16 ; CHECK-NEXT: vmand.mm v0, v8, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %va, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %va, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
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} }
define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_nxv8f64: ; CHECK-LABEL: fcmp_uno_vf_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; CHECK-NEXT: vfmv.v.f v16, fa0 ; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfne.vf v24, v16, fa0, v0.t ; CHECK-NEXT: vmfne.vv v24, v8, v8, v0.t
; CHECK-NEXT: vmfne.vv v16, v8, v8, v0.t ; CHECK-NEXT: vmfne.vf v8, v16, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v16, v24 ; CHECK-NEXT: vmor.mm v0, v24, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_uno_vf_swap_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_uno_vf_swap_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_swap_nxv8f64: ; CHECK-LABEL: fcmp_uno_vf_swap_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; CHECK-NEXT: vfmv.v.f v16, fa0 ; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfne.vf v24, v16, fa0, v0.t ; CHECK-NEXT: vmfne.vv v24, v8, v8, v0.t
; CHECK-NEXT: vmfne.vv v16, v8, v8, v0.t ; CHECK-NEXT: vmfne.vf v8, v16, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v24, v16 ; CHECK-NEXT: vmor.mm v0, v8, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %va, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %va, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
declare <vscale x 32 x i1> @llvm.vp.fcmp.nxv32f64(<vscale x 32 x double>, <vscale x 32 x double>, metadata, <vscale x 32 x i1>, i32) declare <vscale x 32 x i1> @llvm.vp.fcmp.nxv32f64(<vscale x 32 x double>, <vscale x 32 x double>, metadata, <vscale x 32 x i1>, i32)
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llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll

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define <16 x i8> @v8i8_2(<8 x i8> %a, <8 x i8> %b) { define <16 x i8> @v8i8_2(<8 x i8> %a, <8 x i8> %b) {
; CHECK-LABEL: v8i8_2: ; CHECK-LABEL: v8i8_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vid.v v11 ; CHECK-NEXT: vid.v v11
; CHECK-NEXT: vrsub.vi v12, v11, 15 ; CHECK-NEXT: vrsub.vi v12, v11, 15
; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vrgather.vv v10, v8, v12
; CHECK-NEXT: vrsub.vi v8, v11, 7
; CHECK-NEXT: li a0, 255 ; CHECK-NEXT: li a0, 255
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v0, a0 ; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; CHECK-NEXT: vrsub.vi v8, v11, 7
; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t ; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v16i8 = shufflevector <8 x i8> %a, <8 x i8> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v16i8 = shufflevector <8 x i8> %a, <8 x i8> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <16 x i8> %v16i8 ret <16 x i8> %v16i8
} }
define <16 x i8> @v16i8(<16 x i8> %a) { define <16 x i8> @v16i8(<16 x i8> %a) {
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define <16 x i16> @v8i16_2(<8 x i16> %a, <8 x i16> %b) { define <16 x i16> @v8i16_2(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: v8i16_2: ; CHECK-LABEL: v8i16_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v9 ; CHECK-NEXT: vmv1r.v v12, v9
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vid.v v14 ; CHECK-NEXT: vid.v v14
; CHECK-NEXT: vrsub.vi v16, v14, 15 ; CHECK-NEXT: vrsub.vi v16, v14, 15
; CHECK-NEXT: vrgather.vv v10, v8, v16 ; CHECK-NEXT: vrgather.vv v10, v8, v16
; CHECK-NEXT: vrsub.vi v8, v14, 7
; CHECK-NEXT: li a0, 255 ; CHECK-NEXT: li a0, 255
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v0, a0 ; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vrsub.vi v8, v14, 7
; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t ; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v16i16 = shufflevector <8 x i16> %a, <8 x i16> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v16i16 = shufflevector <8 x i16> %a, <8 x i16> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <16 x i16> %v16i16 ret <16 x i16> %v16i16
} }
define <16 x i16> @v16i16(<16 x i16> %a) { define <16 x i16> @v16i16(<16 x i16> %a) {
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define <8 x i32> @v4i32_2(<4 x i32> %a, <4 x i32> %b) { define <8 x i32> @v4i32_2(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: v4i32_2: ; CHECK-LABEL: v4i32_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v9 ; CHECK-NEXT: vmv1r.v v12, v9
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vid.v v14 ; CHECK-NEXT: vid.v v14
; CHECK-NEXT: vrsub.vi v16, v14, 7 ; CHECK-NEXT: vrsub.vi v16, v14, 7
; CHECK-NEXT: vrgather.vv v10, v8, v16 ; CHECK-NEXT: vrgather.vv v10, v8, v16
; CHECK-NEXT: vrsub.vi v8, v14, 3
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v0, 15 ; CHECK-NEXT: vmv.v.i v0, 15
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vrsub.vi v8, v14, 3
; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t ; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v8i32 = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v8i32 = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x i32> %v8i32 ret <8 x i32> %v8i32
} }
define <8 x i32> @v8i32(<8 x i32> %a) { define <8 x i32> @v8i32(<8 x i32> %a) {
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define <16 x i32> @v8i32_2(<8 x i32> %a, <8 x i32> %b) { define <16 x i32> @v8i32_2(<8 x i32> %a, <8 x i32> %b) {
; CHECK-LABEL: v8i32_2: ; CHECK-LABEL: v8i32_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv2r.v v16, v10 ; CHECK-NEXT: vmv2r.v v16, v10
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vid.v v20 ; CHECK-NEXT: vid.v v20
; CHECK-NEXT: vrsub.vi v24, v20, 15 ; CHECK-NEXT: vrsub.vi v24, v20, 15
; CHECK-NEXT: vrgather.vv v12, v8, v24 ; CHECK-NEXT: vrgather.vv v12, v8, v24
; CHECK-NEXT: vrsub.vi v8, v20, 7
; CHECK-NEXT: li a0, 255 ; CHECK-NEXT: li a0, 255
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v0, a0 ; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vrsub.vi v8, v20, 7
; CHECK-NEXT: vrgather.vv v12, v16, v8, v0.t ; CHECK-NEXT: vrgather.vv v12, v16, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v16i32 = shufflevector <8 x i32> %a, <8 x i32> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v16i32 = shufflevector <8 x i32> %a, <8 x i32> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <16 x i32> %v16i32 ret <16 x i32> %v16i32
} }
define <16 x i32> @v16i32(<16 x i32> %a) { define <16 x i32> @v16i32(<16 x i32> %a) {
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; RV32-LABEL: v4i64_2: ; RV32-LABEL: v4i64_2:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vmv2r.v v16, v10 ; RV32-NEXT: vmv2r.v v16, v10
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vid.v v18 ; RV32-NEXT: vid.v v18
; RV32-NEXT: vrsub.vi v19, v18, 7 ; RV32-NEXT: vrsub.vi v19, v18, 7
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV32-NEXT: vrgatherei16.vv v12, v8, v19 ; RV32-NEXT: vrgatherei16.vv v12, v8, v19
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV32-NEXT: vmv.v.i v0, 15
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vrsub.vi v8, v18, 3 ; RV32-NEXT: vrsub.vi v8, v18, 3
; RV32-NEXT: vmv.v.i v0, 15
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV32-NEXT: vrgatherei16.vv v12, v16, v8, v0.t ; RV32-NEXT: vrgatherei16.vv v12, v16, v8, v0.t
; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: v4i64_2: ; RV64-LABEL: v4i64_2:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv2r.v v16, v10 ; RV64-NEXT: vmv2r.v v16, v10
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vid.v v20 ; RV64-NEXT: vid.v v20
; RV64-NEXT: vrsub.vi v24, v20, 7 ; RV64-NEXT: vrsub.vi v24, v20, 7
; RV64-NEXT: vrgather.vv v12, v8, v24 ; RV64-NEXT: vrgather.vv v12, v8, v24
; RV64-NEXT: vrsub.vi v8, v20, 3
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV64-NEXT: vmv.v.i v0, 15 ; RV64-NEXT: vmv.v.i v0, 15
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vrsub.vi v8, v20, 3
; RV64-NEXT: vrgather.vv v12, v16, v8, v0.t ; RV64-NEXT: vrgather.vv v12, v16, v8, v0.t
; RV64-NEXT: vmv.v.v v8, v12 ; RV64-NEXT: vmv.v.v v8, v12
; RV64-NEXT: ret ; RV64-NEXT: ret
%v8i64 = shufflevector <4 x i64> %a, <4 x i64> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v8i64 = shufflevector <4 x i64> %a, <4 x i64> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x i64> %v8i64 ret <8 x i64> %v8i64
} }
define <2 x half> @v2f16(<2 x half> %a) { define <2 x half> @v2f16(<2 x half> %a) {
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define <16 x half> @v8f16_2(<8 x half> %a, <8 x half> %b) { define <16 x half> @v8f16_2(<8 x half> %a, <8 x half> %b) {
; CHECK-LABEL: v8f16_2: ; CHECK-LABEL: v8f16_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v9 ; CHECK-NEXT: vmv1r.v v12, v9
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vid.v v14 ; CHECK-NEXT: vid.v v14
; CHECK-NEXT: vrsub.vi v16, v14, 15 ; CHECK-NEXT: vrsub.vi v16, v14, 15
; CHECK-NEXT: vrgather.vv v10, v8, v16 ; CHECK-NEXT: vrgather.vv v10, v8, v16
; CHECK-NEXT: vrsub.vi v8, v14, 7
; CHECK-NEXT: li a0, 255 ; CHECK-NEXT: li a0, 255
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v0, a0 ; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vrsub.vi v8, v14, 7
; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t ; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v16f16 = shufflevector <8 x half> %a, <8 x half> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v16f16 = shufflevector <8 x half> %a, <8 x half> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <16 x half> %v16f16 ret <16 x half> %v16f16
} }
define <16 x half> @v16f16(<16 x half> %a) { define <16 x half> @v16f16(<16 x half> %a) {
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define <8 x float> @v4f32_2(<4 x float> %a, <4 x float> %b) { define <8 x float> @v4f32_2(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: v4f32_2: ; CHECK-LABEL: v4f32_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v9 ; CHECK-NEXT: vmv1r.v v12, v9
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vid.v v14 ; CHECK-NEXT: vid.v v14
; CHECK-NEXT: vrsub.vi v16, v14, 7 ; CHECK-NEXT: vrsub.vi v16, v14, 7
; CHECK-NEXT: vrgather.vv v10, v8, v16 ; CHECK-NEXT: vrgather.vv v10, v8, v16
; CHECK-NEXT: vrsub.vi v8, v14, 3
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v0, 15 ; CHECK-NEXT: vmv.v.i v0, 15
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vrsub.vi v8, v14, 3
; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t ; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v8f32 = shufflevector <4 x float> %a, <4 x float> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v8f32 = shufflevector <4 x float> %a, <4 x float> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x float> %v8f32 ret <8 x float> %v8f32
} }
define <8 x float> @v8f32(<8 x float> %a) { define <8 x float> @v8f32(<8 x float> %a) {
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define <16 x float> @v8f32_2(<8 x float> %a, <8 x float> %b) { define <16 x float> @v8f32_2(<8 x float> %a, <8 x float> %b) {
; CHECK-LABEL: v8f32_2: ; CHECK-LABEL: v8f32_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv2r.v v16, v10 ; CHECK-NEXT: vmv2r.v v16, v10
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vid.v v20 ; CHECK-NEXT: vid.v v20
; CHECK-NEXT: vrsub.vi v24, v20, 15 ; CHECK-NEXT: vrsub.vi v24, v20, 15
; CHECK-NEXT: vrgather.vv v12, v8, v24 ; CHECK-NEXT: vrgather.vv v12, v8, v24
; CHECK-NEXT: vrsub.vi v8, v20, 7
; CHECK-NEXT: li a0, 255 ; CHECK-NEXT: li a0, 255
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v0, a0 ; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vrsub.vi v8, v20, 7
; CHECK-NEXT: vrgather.vv v12, v16, v8, v0.t ; CHECK-NEXT: vrgather.vv v12, v16, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v16f32 = shufflevector <8 x float> %a, <8 x float> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v16f32 = shufflevector <8 x float> %a, <8 x float> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <16 x float> %v16f32 ret <16 x float> %v16f32
} }
define <2 x double> @v2f64(<2 x double> %a) { define <2 x double> @v2f64(<2 x double> %a) {
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; RV32-LABEL: v4f64_2: ; RV32-LABEL: v4f64_2:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vmv2r.v v16, v10 ; RV32-NEXT: vmv2r.v v16, v10
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vid.v v18 ; RV32-NEXT: vid.v v18
; RV32-NEXT: vrsub.vi v19, v18, 7 ; RV32-NEXT: vrsub.vi v19, v18, 7
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV32-NEXT: vrgatherei16.vv v12, v8, v19 ; RV32-NEXT: vrgatherei16.vv v12, v8, v19
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV32-NEXT: vmv.v.i v0, 15
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vrsub.vi v8, v18, 3 ; RV32-NEXT: vrsub.vi v8, v18, 3
; RV32-NEXT: vmv.v.i v0, 15
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV32-NEXT: vrgatherei16.vv v12, v16, v8, v0.t ; RV32-NEXT: vrgatherei16.vv v12, v16, v8, v0.t
; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: v4f64_2: ; RV64-LABEL: v4f64_2:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv2r.v v16, v10 ; RV64-NEXT: vmv2r.v v16, v10
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vid.v v20 ; RV64-NEXT: vid.v v20
; RV64-NEXT: vrsub.vi v24, v20, 7 ; RV64-NEXT: vrsub.vi v24, v20, 7
; RV64-NEXT: vrgather.vv v12, v8, v24 ; RV64-NEXT: vrgather.vv v12, v8, v24
; RV64-NEXT: vrsub.vi v8, v20, 3
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV64-NEXT: vmv.v.i v0, 15 ; RV64-NEXT: vmv.v.i v0, 15
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vrsub.vi v8, v20, 3
; RV64-NEXT: vrgather.vv v12, v16, v8, v0.t ; RV64-NEXT: vrgather.vv v12, v16, v8, v0.t
; RV64-NEXT: vmv.v.v v8, v12 ; RV64-NEXT: vmv.v.v v8, v12
; RV64-NEXT: ret ; RV64-NEXT: ret
%v8f64 = shufflevector <4 x double> %a, <4 x double> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v8f64 = shufflevector <4 x double> %a, <4 x double> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x double> %v8f64 ret <8 x double> %v8f64
} }
define <32 x i8> @v32i8(<32 x i8> %a) { define <32 x i8> @v32i8(<32 x i8> %a) {
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llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s ; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s
declare <2 x i64> @llvm.sshl.sat.v2i64(<2 x i64>, <2 x i64>) declare <2 x i64> @llvm.sshl.sat.v2i64(<2 x i64>, <2 x i64>)
declare <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32>, <4 x i32>) declare <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32>, <4 x i32>)
declare <8 x i16> @llvm.sshl.sat.v8i16(<8 x i16>, <8 x i16>) declare <8 x i16> @llvm.sshl.sat.v8i16(<8 x i16>, <8 x i16>)
declare <16 x i8> @llvm.sshl.sat.v16i8(<16 x i8>, <16 x i8>) declare <16 x i8> @llvm.sshl.sat.v16i8(<16 x i8>, <16 x i8>)
define <2 x i64> @vec_v2i64(<2 x i64> %x, <2 x i64> %y) nounwind { define <2 x i64> @vec_v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; CHECK-LABEL: vec_v2i64: ; CHECK-LABEL: vec_v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: li a0, -1 ; CHECK-NEXT: li a0, -1
; CHECK-NEXT: srli a1, a0, 1 ; CHECK-NEXT: srli a1, a0, 1
; CHECK-NEXT: vsll.vv v10, v8, v9 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vsra.vv v9, v10, v9 ; CHECK-NEXT: vmv.v.x v10, a1
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vsll.vv v11, v8, v9
; CHECK-NEXT: vmv.v.x v9, a1 ; CHECK-NEXT: vsra.vv v9, v11, v9
; CHECK-NEXT: vmsne.vv v9, v8, v9
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: slli a0, a0, 63 ; CHECK-NEXT: slli a0, a0, 63
; CHECK-NEXT: vmerge.vxm v9, v9, a0, v0 ; CHECK-NEXT: vmerge.vxm v8, v10, a0, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v9
; CHECK-NEXT: vmerge.vvm v8, v10, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v11, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <2 x i64> @llvm.sshl.sat.v2i64(<2 x i64> %x, <2 x i64> %y) %tmp = call <2 x i64> @llvm.sshl.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
ret <2 x i64> %tmp ret <2 x i64> %tmp
} }
define <4 x i32> @vec_v4i32(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i32> @vec_v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; CHECK-LABEL: vec_v4i32: ; CHECK-LABEL: vec_v4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: addiw a0, a0, -1 ; CHECK-NEXT: addiw a0, a0, -1
; CHECK-NEXT: vsll.vv v10, v8, v9 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vsra.vv v9, v10, v9 ; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vsll.vv v11, v8, v9
; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsra.vv v9, v11, v9
; CHECK-NEXT: vmsne.vv v9, v8, v9
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: li a0, 1 ; CHECK-NEXT: li a0, 1
; CHECK-NEXT: slli a0, a0, 31 ; CHECK-NEXT: slli a0, a0, 31
; CHECK-NEXT: vmerge.vxm v9, v9, a0, v0 ; CHECK-NEXT: vmerge.vxm v8, v10, a0, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v9
; CHECK-NEXT: vmerge.vvm v8, v10, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v11, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32> %x, <4 x i32> %y) %tmp = call <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
ret <4 x i32> %tmp ret <4 x i32> %tmp
} }
define <8 x i16> @vec_v8i16(<8 x i16> %x, <8 x i16> %y) nounwind { define <8 x i16> @vec_v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
; CHECK-LABEL: vec_v8i16: ; CHECK-LABEL: vec_v8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: lui a0, 8 ; CHECK-NEXT: lui a0, 8
; CHECK-NEXT: addiw a1, a0, -1 ; CHECK-NEXT: addiw a1, a0, -1
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: vsll.vv v10, v8, v9 ; CHECK-NEXT: vsll.vv v10, v8, v9
; CHECK-NEXT: vsra.vv v9, v10, v9 ; CHECK-NEXT: vsra.vv v9, v10, v9
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv.v.x v9, a1 ; CHECK-NEXT: vmv.v.x v9, a1
; CHECK-NEXT: vmerge.vxm v9, v9, a0, v0 ; CHECK-NEXT: vmerge.vxm v9, v9, a0, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmerge.vvm v8, v10, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v10, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <8 x i16> @llvm.sshl.sat.v8i16(<8 x i16> %x, <8 x i16> %y) %tmp = call <8 x i16> @llvm.sshl.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
ret <8 x i16> %tmp ret <8 x i16> %tmp
} }
define <16 x i8> @vec_v16i8(<16 x i8> %x, <16 x i8> %y) nounwind { define <16 x i8> @vec_v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
; CHECK-LABEL: vec_v16i8: ; CHECK-LABEL: vec_v16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsll.vv v11, v8, v9
; CHECK-NEXT: vsra.vv v9, v11, v9
; CHECK-NEXT: vmsne.vv v9, v8, v9
; CHECK-NEXT: vmsle.vi v0, v8, -1 ; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsll.vv v10, v8, v9
; CHECK-NEXT: vsra.vv v9, v10, v9
; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: li a0, 128 ; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vmerge.vxm v9, v9, a0, v0 ; CHECK-NEXT: vmerge.vxm v8, v10, a0, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v9
; CHECK-NEXT: vmerge.vvm v8, v10, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v11, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <16 x i8> @llvm.sshl.sat.v16i8(<16 x i8> %x, <16 x i8> %y) %tmp = call <16 x i8> @llvm.sshl.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
ret <16 x i8> %tmp ret <16 x i8> %tmp
} }
declare <vscale x 2 x i64> @llvm.sshl.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) declare <vscale x 2 x i64> @llvm.sshl.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
declare <vscale x 4 x i32> @llvm.sshl.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) declare <vscale x 4 x i32> @llvm.sshl.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
declare <vscale x 8 x i16> @llvm.sshl.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) declare <vscale x 8 x i16> @llvm.sshl.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
declare <vscale x 16 x i8> @llvm.sshl.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) declare <vscale x 16 x i8> @llvm.sshl.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
define <vscale x 2 x i64> @vec_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y) nounwind { define <vscale x 2 x i64> @vec_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y) nounwind {
; CHECK-LABEL: vec_nxv2i64: ; CHECK-LABEL: vec_nxv2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: srli a1, a0, 1
; CHECK-NEXT: vsll.vv v12, v8, v10 ; CHECK-NEXT: vsll.vv v12, v8, v10
; CHECK-NEXT: vsra.vv v14, v12, v10 ; CHECK-NEXT: vsra.vv v14, v12, v10
; CHECK-NEXT: vmsne.vv v10, v8, v14 ; CHECK-NEXT: vmsne.vv v10, v8, v14
; CHECK-NEXT: vmv.v.x v8, a1 ; CHECK-NEXT: li a0, -1
; CHECK-NEXT: srli a1, a0, 1
; CHECK-NEXT: vmv.v.x v14, a1
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: slli a0, a0, 63 ; CHECK-NEXT: slli a0, a0, 63
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: vmerge.vxm v8, v14, a0, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <vscale x 2 x i64> @llvm.sshl.sat.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y) %tmp = call <vscale x 2 x i64> @llvm.sshl.sat.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y)
ret <vscale x 2 x i64> %tmp ret <vscale x 2 x i64> %tmp
} }
define <vscale x 4 x i32> @vec_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) nounwind { define <vscale x 4 x i32> @vec_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) nounwind {
; CHECK-LABEL: vec_nxv4i32: ; CHECK-LABEL: vec_nxv4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: addiw a0, a0, -1
; CHECK-NEXT: vsll.vv v12, v8, v10 ; CHECK-NEXT: vsll.vv v12, v8, v10
; CHECK-NEXT: vsra.vv v14, v12, v10 ; CHECK-NEXT: vsra.vv v14, v12, v10
; CHECK-NEXT: vmsne.vv v10, v8, v14 ; CHECK-NEXT: vmsne.vv v10, v8, v14
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: addiw a0, a0, -1
; CHECK-NEXT: vmv.v.x v14, a0
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: li a0, 1 ; CHECK-NEXT: li a0, 1
; CHECK-NEXT: slli a0, a0, 31 ; CHECK-NEXT: slli a0, a0, 31
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: vmerge.vxm v8, v14, a0, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <vscale x 4 x i32> @llvm.sshl.sat.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) %tmp = call <vscale x 4 x i32> @llvm.sshl.sat.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y)
ret <vscale x 4 x i32> %tmp ret <vscale x 4 x i32> %tmp
} }
define <vscale x 8 x i16> @vec_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y) nounwind { define <vscale x 8 x i16> @vec_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y) nounwind {
; CHECK-LABEL: vec_nxv8i16: ; CHECK-LABEL: vec_nxv8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: lui a0, 8
; CHECK-NEXT: addiw a1, a0, -1
; CHECK-NEXT: vsll.vv v12, v8, v10 ; CHECK-NEXT: vsll.vv v12, v8, v10
; CHECK-NEXT: vsra.vv v14, v12, v10 ; CHECK-NEXT: vsra.vv v14, v12, v10
; CHECK-NEXT: vmsne.vv v10, v8, v14 ; CHECK-NEXT: vmsne.vv v10, v8, v14
; CHECK-NEXT: lui a0, 8
; CHECK-NEXT: addiw a1, a0, -1
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: vmv.v.x v8, a1 ; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <vscale x 8 x i16> @llvm.sshl.sat.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y) %tmp = call <vscale x 8 x i16> @llvm.sshl.sat.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y)
ret <vscale x 8 x i16> %tmp ret <vscale x 8 x i16> %tmp
} }
define <vscale x 16 x i8> @vec_nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y) nounwind { define <vscale x 16 x i8> @vec_nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y) nounwind {
; CHECK-LABEL: vec_nxv16i8: ; CHECK-LABEL: vec_nxv16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsll.vv v12, v8, v10 ; CHECK-NEXT: vsll.vv v12, v8, v10
; CHECK-NEXT: vsra.vv v14, v12, v10 ; CHECK-NEXT: vsra.vv v14, v12, v10
; CHECK-NEXT: vmsne.vv v10, v8, v14 ; CHECK-NEXT: vmsne.vv v10, v8, v14
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vmv.v.x v14, a0
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: li a0, 128 ; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: vmerge.vxm v8, v14, a0, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <vscale x 16 x i8> @llvm.sshl.sat.nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y) %tmp = call <vscale x 16 x i8> @llvm.sshl.sat.nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y)
ret <vscale x 16 x i8> %tmp ret <vscale x 16 x i8> %tmp
} }

llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll

Show All 11 Lines
; RV32-NEXT: vmerge.vim v10, v8, 1, v0 ; RV32-NEXT: vmerge.vim v10, v8, 1, v0
; RV32-NEXT: vid.v v9 ; RV32-NEXT: vid.v v9
; RV32-NEXT: vadd.vv v11, v9, v9 ; RV32-NEXT: vadd.vv v11, v9, v9
; RV32-NEXT: vrgather.vv v9, v10, v11 ; RV32-NEXT: vrgather.vv v9, v10, v11
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmerge.vim v8, v8, 1, v0 ; RV32-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-NEXT: vadd.vi v12, v11, -16
; RV32-NEXT: lui a0, 16 ; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -256 ; RV32-NEXT: addi a0, a0, -256
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a0 ; RV32-NEXT: vmv.v.x v0, a0
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV32-NEXT: vadd.vi v12, v11, -16
; RV32-NEXT: vrgather.vv v9, v8, v12, v0.t ; RV32-NEXT: vrgather.vv v9, v8, v12, v0.t
; RV32-NEXT: vmsne.vi v9, v9, 0 ; RV32-NEXT: vmsne.vi v9, v9, 0
; RV32-NEXT: vadd.vi v12, v11, 1 ; RV32-NEXT: vadd.vi v12, v11, 1
; RV32-NEXT: vrgather.vv v13, v10, v12 ; RV32-NEXT: vrgather.vv v13, v10, v12
; RV32-NEXT: vadd.vi v10, v11, -15 ; RV32-NEXT: vadd.vi v10, v11, -15
; RV32-NEXT: vrgather.vv v13, v8, v10, v0.t ; RV32-NEXT: vrgather.vv v13, v8, v10, v0.t
; RV32-NEXT: vmsne.vi v8, v13, 0 ; RV32-NEXT: vmsne.vi v8, v13, 0
; RV32-NEXT: vmv.v.v v0, v9 ; RV32-NEXT: vmv.v.v v0, v9
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vector_deinterleave_v16i1_v32i1: ; RV64-LABEL: vector_deinterleave_v16i1_v32i1:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vmv.v.i v8, 0 ; RV64-NEXT: vmv.v.i v8, 0
; RV64-NEXT: vmerge.vim v10, v8, 1, v0 ; RV64-NEXT: vmerge.vim v10, v8, 1, v0
; RV64-NEXT: vid.v v9 ; RV64-NEXT: vid.v v9
; RV64-NEXT: vadd.vv v11, v9, v9 ; RV64-NEXT: vadd.vv v11, v9, v9
; RV64-NEXT: vrgather.vv v9, v10, v11 ; RV64-NEXT: vrgather.vv v9, v10, v11
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2 ; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vmerge.vim v8, v8, 1, v0 ; RV64-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-NEXT: vadd.vi v12, v11, -16
; RV64-NEXT: lui a0, 16 ; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -256 ; RV64-NEXT: addiw a0, a0, -256
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vmv.v.x v0, a0 ; RV64-NEXT: vmv.v.x v0, a0
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64-NEXT: vadd.vi v12, v11, -16
; RV64-NEXT: vrgather.vv v9, v8, v12, v0.t ; RV64-NEXT: vrgather.vv v9, v8, v12, v0.t
; RV64-NEXT: vmsne.vi v9, v9, 0 ; RV64-NEXT: vmsne.vi v9, v9, 0
; RV64-NEXT: vadd.vi v12, v11, 1 ; RV64-NEXT: vadd.vi v12, v11, 1
; RV64-NEXT: vrgather.vv v13, v10, v12 ; RV64-NEXT: vrgather.vv v13, v10, v12
; RV64-NEXT: vadd.vi v10, v11, -15 ; RV64-NEXT: vadd.vi v10, v11, -15
; RV64-NEXT: vrgather.vv v13, v8, v10, v0.t ; RV64-NEXT: vrgather.vv v13, v8, v10, v0.t
; RV64-NEXT: vmsne.vi v8, v13, 0 ; RV64-NEXT: vmsne.vi v8, v13, 0
; RV64-NEXT: vmv.v.v v0, v9 ; RV64-NEXT: vmv.v.v v0, v9
▲ Show 20 Lines • Show All 154 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh | FileCheck -check-prefixes=CHECK,RV32 %s ; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh | FileCheck -check-prefixes=CHECK,RV32 %s
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh | FileCheck -check-prefixes=CHECK,RV64 %s ; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh | FileCheck -check-prefixes=CHECK,RV64 %s
; Integers ; Integers
define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) { define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) {
; CHECK-LABEL: vector_interleave_v32i1_v16i1: ; CHECK-LABEL: vector_interleave_v32i1_v16i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v0, v8, 2 ; CHECK-NEXT: vslideup.vi v0, v8, 2
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 16, e8, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 16 ; CHECK-NEXT: vslidedown.vi v10, v8, 16
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vwaddu.vv v12, v8, v10 ; CHECK-NEXT: vwaddu.vv v12, v8, v10
; CHECK-NEXT: li a1, -1 ; CHECK-NEXT: li a1, -1
; CHECK-NEXT: vwmaccu.vx v12, a1, v10 ; CHECK-NEXT: vwmaccu.vx v12, a1, v10
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: vmsne.vi v0, v12, 0
▲ Show 20 Lines • Show All 166 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir

Show All 25 Linesbody: |
bb.0: bb.0:
liveins: $x14, $x16 liveins: $x14, $x16
; 82 = e32,m4 ; 82 = e32,m4
; CHECK-LABEL: name: copy_convert_to_vmv_v_v ; CHECK-LABEL: name: copy_convert_to_vmv_v_v
; CHECK: liveins: $x14, $x16 ; CHECK: liveins: $x14, $x16
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 killed $x16, $noreg, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 killed $x16, $noreg, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: $v12m4 = PseudoVMV_V_V_M4 $v28m4, $noreg, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v12m4 = PseudoVMV_V_V_M4 undef $v12m4, $v28m4, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
$x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype
$v28m4 = PseudoVLE32_V_M4 killed $x16, $noreg, 5, implicit $vl, implicit $vtype $v28m4 = PseudoVLE32_V_M4 killed $x16, $noreg, 5, implicit $vl, implicit $vtype
$v12m4 = COPY $v28m4 $v12m4 = COPY $v28m4
... ...
--- ---
name: copy_convert_to_vmv_v_i name: copy_convert_to_vmv_v_i
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $x14 liveins: $x14
; 82 = e32,m4 ; 82 = e32,m4
; CHECK-LABEL: name: copy_convert_to_vmv_v_i ; CHECK-LABEL: name: copy_convert_to_vmv_v_i
; CHECK: liveins: $x14 ; CHECK: liveins: $x14
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: $v28m4 = PseudoVMV_V_I_M4 0, $noreg, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v28m4 = PseudoVMV_V_I_M4 undef $v28m4, 0, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: $v12m4 = PseudoVMV_V_I_M4 0, $noreg, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v12m4 = PseudoVMV_V_I_M4 undef $v12m4, 0, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
$x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype
$v28m4 = PseudoVMV_V_I_M4 0, $noreg, 5, implicit $vl, implicit $vtype $v28m4 = PseudoVMV_V_I_M4 undef $v28m4, 0, $noreg, 5, 0, implicit $vl, implicit $vtype
$v12m4 = COPY $v28m4 $v12m4 = COPY $v28m4
... ...
--- ---
name: copy_from_whole_load_store name: copy_from_whole_load_store
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $x14, $x16 liveins: $x14, $x16
Show All 14 Lines
body: | body: |
bb.0: bb.0:
liveins: $x14, $x16 liveins: $x14, $x16
; 82 = e32,m4 ; 82 = e32,m4
; CHECK-LABEL: name: copy_with_vleff ; CHECK-LABEL: name: copy_with_vleff
; CHECK: liveins: $x14, $x16 ; CHECK: liveins: $x14, $x16
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: $v28m4 = PseudoVMV_V_I_M4 0, $noreg, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v28m4 = PseudoVMV_V_I_M4 undef $v28m4, 0, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: $v4m4, $x0 = PseudoVLE32FF_V_M4 $x16, $noreg, 5 /* e32 */, implicit-def $vl ; CHECK-NEXT: $v4m4, $x0 = PseudoVLE32FF_V_M4 $x16, $noreg, 5 /* e32 */, implicit-def $vl
; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4 ; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4
$x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype
$v28m4 = PseudoVMV_V_I_M4 0, $noreg, 5, implicit $vl, implicit $vtype $v28m4 = PseudoVMV_V_I_M4 undef $v28m4, 0, $noreg, 5, 0, implicit $vl, implicit $vtype
$v4m4,$x0 = PseudoVLE32FF_V_M4 $x16, $noreg, 5, implicit-def $vl $v4m4,$x0 = PseudoVLE32FF_V_M4 $x16, $noreg, 5, implicit-def $vl
$v12m4 = COPY $v28m4 $v12m4 = COPY $v28m4
... ...
--- ---
name: copy_with_vsetvl_x0_x0_1 name: copy_with_vsetvl_x0_x0_1
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
Show All 30 Lines bb.0:
; CHECK: liveins: $x14, $x16, $x17, $x18 ; CHECK: liveins: $x14, $x16, $x17, $x18
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 killed $x16, $noreg, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 killed $x16, $noreg, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: $x0 = PseudoVSETVLIX0 $x0, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: $x0 = PseudoVSETVLIX0 $x0, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: $v0m2 = PseudoVLE32_V_M2 $x18, $noreg, 4 /* e16 */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v0m2 = PseudoVLE32_V_M2 $x18, $noreg, 4 /* e16 */, implicit $vl, implicit $vtype
; CHECK-NEXT: $x0 = PseudoVSETVLIX0 $x0, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: $x0 = PseudoVSETVLIX0 $x0, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: $v4m4 = PseudoVLE32_V_M4 killed $x18, $noreg, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v4m4 = PseudoVLE32_V_M4 killed $x18, $noreg, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: $v12m4 = PseudoVMV_V_V_M4 $v28m4, $noreg, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v12m4 = PseudoVMV_V_V_M4 undef $v12m4, $v28m4, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
$x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype
$v28m4 = PseudoVLE32_V_M4 killed $x16, $noreg, 5, implicit $vl, implicit $vtype $v28m4 = PseudoVLE32_V_M4 killed $x16, $noreg, 5, implicit $vl, implicit $vtype
$x0 = PseudoVSETVLIX0 $x0, 73, implicit-def $vl, implicit-def $vtype $x0 = PseudoVSETVLIX0 $x0, 73, implicit-def $vl, implicit-def $vtype
$v0m2 = PseudoVLE32_V_M2 $x18, $noreg, 4, implicit $vl, implicit $vtype $v0m2 = PseudoVLE32_V_M2 $x18, $noreg, 4, implicit $vl, implicit $vtype
$x0 = PseudoVSETVLIX0 $x0, 82, implicit-def $vl, implicit-def $vtype $x0 = PseudoVSETVLIX0 $x0, 82, implicit-def $vl, implicit-def $vtype
$v4m4 = PseudoVLE32_V_M4 killed $x18, $noreg, 5, implicit $vl, implicit $vtype $v4m4 = PseudoVLE32_V_M4 killed $x18, $noreg, 5, implicit $vl, implicit $vtype
$v12m4 = COPY $v28m4 $v12m4 = COPY $v28m4
... ...
▲ Show 20 Lines • Show All 104 Lines • ▼ Show 20 Linesbody: |
bb.0: bb.0:
liveins: $x14, $x16 liveins: $x14, $x16
; 80 = e32,m1 ; 80 = e32,m1
; CHECK-LABEL: name: copy_zvlsseg_reg_2 ; CHECK-LABEL: name: copy_zvlsseg_reg_2
; CHECK: liveins: $x14, $x16 ; CHECK: liveins: $x14, $x16
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 80 /* e32, m1, ta, mu */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 80 /* e32, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: $v8_v9 = PseudoVLSEG2E32_V_M1 killed $x16, $noreg, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v8_v9 = PseudoVLSEG2E32_V_M1 killed $x16, $noreg, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: $v10 = PseudoVMV_V_V_M1 $v8, $noreg, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v10 = PseudoVMV_V_V_M1 undef $v10, $v8, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: $v11 = PseudoVMV_V_V_M1 $v9, $noreg, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v11 = PseudoVMV_V_V_M1 undef $v11, $v9, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
$x15 = PseudoVSETVLI $x14, 80, implicit-def $vl, implicit-def $vtype $x15 = PseudoVSETVLI $x14, 80, implicit-def $vl, implicit-def $vtype
$v8_v9 = PseudoVLSEG2E32_V_M1 killed $x16, $noreg, 5, implicit $vl, implicit $vtype $v8_v9 = PseudoVLSEG2E32_V_M1 killed $x16, $noreg, 5, implicit $vl, implicit $vtype
$v10_v11 = COPY $v8_v9 $v10_v11 = COPY $v8_v9
... ...
--- ---
name: copy_fractional_lmul name: copy_fractional_lmul
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll

Show First 20 Lines • Show All 972 Lines • ▼ Show 20 Lines
} }
; Test Widen VECREDUCE_SEQ_FADD ; Test Widen VECREDUCE_SEQ_FADD
declare half @llvm.vector.reduce.fadd.nxv3f16(half, <vscale x 3 x half>) declare half @llvm.vector.reduce.fadd.nxv3f16(half, <vscale x 3 x half>)
define half @vreduce_ord_fadd_nxv3f16(<vscale x 3 x half> %v, half %s) { define half @vreduce_ord_fadd_nxv3f16(<vscale x 3 x half> %v, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv3f16: ; CHECK-LABEL: vreduce_ord_fadd_nxv3f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: slli a1, a0, 1 ; CHECK-NEXT: slli a1, a0, 1
; CHECK-NEXT: add a1, a1, a0 ; CHECK-NEXT: add a1, a1, a0
; CHECK-NEXT: add a0, a1, a0 ; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: lui a2, 1048568
; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a2
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vfredosum.vs v8, v8, v9 ; CHECK-NEXT: vfredosum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fadd.nxv3f16(half %s, <vscale x 3 x half> %v) %red = call half @llvm.vector.reduce.fadd.nxv3f16(half %s, <vscale x 3 x half> %v)
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fadd.nxv6f16(half, <vscale x 6 x half>) declare half @llvm.vector.reduce.fadd.nxv6f16(half, <vscale x 6 x half>)
define half @vreduce_ord_fadd_nxv6f16(<vscale x 6 x half> %v, half %s) { define half @vreduce_ord_fadd_nxv6f16(<vscale x 6 x half> %v, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv6f16: ; CHECK-LABEL: vreduce_ord_fadd_nxv6f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vmv.v.x v11, a0
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vx v9, v10, a0 ; CHECK-NEXT: vslideup.vx v9, v11, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vfredosum.vs v8, v8, v10 ; CHECK-NEXT: vfredosum.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fadd.nxv6f16(half %s, <vscale x 6 x half> %v) %red = call half @llvm.vector.reduce.fadd.nxv6f16(half %s, <vscale x 6 x half> %v)
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fadd.nxv10f16(half, <vscale x 10 x half>) declare half @llvm.vector.reduce.fadd.nxv10f16(half, <vscale x 10 x half>)
define half @vreduce_ord_fadd_nxv10f16(<vscale x 10 x half> %v, half %s) { define half @vreduce_ord_fadd_nxv10f16(<vscale x 10 x half> %v, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv10f16: ; CHECK-LABEL: vreduce_ord_fadd_nxv10f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0 ; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vx v10, v12, a0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: vmv.v.v v11, v12 ; CHECK-NEXT: vmv.v.v v11, v12
; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vx v11, v12, a0 ; CHECK-NEXT: vslideup.vx v11, v12, a0
; CHECK-NEXT: vslideup.vx v10, v12, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vfredosum.vs v8, v8, v12 ; CHECK-NEXT: vfredosum.vs v8, v8, v12
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fadd.nxv10f16(half %s, <vscale x 10 x half> %v) %red = call half @llvm.vector.reduce.fadd.nxv10f16(half %s, <vscale x 10 x half> %v)
ret half %red ret half %red
} }
Show All 14 Lines; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fadd.nxv12f16(half %s, <vscale x 12 x half> %v) %red = call half @llvm.vector.reduce.fadd.nxv12f16(half %s, <vscale x 12 x half> %v)
ret half %red ret half %red
} }
; Test Widen vector reduce type (fadd/fmin/fmax) ; Test Widen vector reduce type (fadd/fmin/fmax)
define half @vreduce_fadd_nxv3f16(<vscale x 3 x half> %v, half %s) { define half @vreduce_fadd_nxv3f16(<vscale x 3 x half> %v, half %s) {
; CHECK-LABEL: vreduce_fadd_nxv3f16: ; CHECK-LABEL: vreduce_fadd_nxv3f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: slli a1, a0, 1 ; CHECK-NEXT: slli a1, a0, 1
; CHECK-NEXT: add a1, a1, a0 ; CHECK-NEXT: add a1, a1, a0
; CHECK-NEXT: add a0, a1, a0 ; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: lui a2, 1048568
; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a2
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call reassoc half @llvm.vector.reduce.fadd.nxv3f16(half %s, <vscale x 3 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.nxv3f16(half %s, <vscale x 3 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_fadd_nxv6f16(<vscale x 6 x half> %v, half %s) { define half @vreduce_fadd_nxv6f16(<vscale x 6 x half> %v, half %s) {
; CHECK-LABEL: vreduce_fadd_nxv6f16: ; CHECK-LABEL: vreduce_fadd_nxv6f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vmv.v.x v11, a0
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vx v9, v10, a0 ; CHECK-NEXT: vslideup.vx v9, v11, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vfredusum.vs v8, v8, v10 ; CHECK-NEXT: vfredusum.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call reassoc half @llvm.vector.reduce.fadd.nxv6f16(half %s, <vscale x 6 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.nxv6f16(half %s, <vscale x 6 x half> %v)
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fmin.nxv10f16(<vscale x 10 x half>) declare half @llvm.vector.reduce.fmin.nxv10f16(<vscale x 10 x half>)
define half @vreduce_fmin_nxv10f16(<vscale x 10 x half> %v) { define half @vreduce_fmin_nxv10f16(<vscale x 10 x half> %v) {
; CHECK-LABEL: vreduce_fmin_nxv10f16: ; CHECK-LABEL: vreduce_fmin_nxv10f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI73_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI73_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfmv.v.f v12, fa5
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: lui a1, %hi(.LCPI73_0)
; CHECK-NEXT: flh fa5, %lo(.LCPI73_0)(a1)
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; CHECK-NEXT: vfmv.v.f v12, fa5
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vx v10, v12, a0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: vmv.v.v v11, v12 ; CHECK-NEXT: vmv.v.v v11, v12
; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vx v11, v12, a0 ; CHECK-NEXT: vslideup.vx v11, v12, a0
; CHECK-NEXT: vslideup.vx v10, v12, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vfmv.s.f v12, fa5 ; CHECK-NEXT: vfmv.s.f v12, fa5
; CHECK-NEXT: vfredmin.vs v8, v8, v12 ; CHECK-NEXT: vfredmin.vs v8, v8, v12
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fmin.nxv10f16(<vscale x 10 x half> %v) %red = call half @llvm.vector.reduce.fmin.nxv10f16(<vscale x 10 x half> %v)
ret half %red ret half %red
} }
Show All 17 Lines

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

Show First 20 Lines • Show All 278 Lines • ▼ Show 20 Linesbody: |
; CHECK-NEXT: [[PseudoVLE32_V_MF2_:%[0-9]+]]:vr = PseudoVLE32_V_MF2 [[COPY2]], $noreg, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVLE32_V_MF2_:%[0-9]+]]:vr = PseudoVLE32_V_MF2 [[COPY2]], $noreg, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: BEQ [[COPY3]], [[COPY4]], %bb.2 ; CHECK-NEXT: BEQ [[COPY3]], [[COPY4]], %bb.2
; CHECK-NEXT: PseudoBR %bb.1 ; CHECK-NEXT: PseudoBR %bb.1
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.if.then: ; CHECK-NEXT: bb.1.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %dead1:vr = IMPLICIT_DEF
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
; CHECK-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[PseudoVLE32_V_MF2_]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 %dead1, [[PseudoVLE32_V_MF2_]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: PseudoBR %bb.3 ; CHECK-NEXT: PseudoBR %bb.3
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.else: ; CHECK-NEXT: bb.2.if.else:
; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %dead2:vr = IMPLICIT_DEF
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
; CHECK-NEXT: early-clobber %2:vr = PseudoVSEXT_VF2_M1 [[PseudoVLE32_V_MF2_]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: early-clobber %2:vr = PseudoVSEXT_VF2_M1 %dead2, [[PseudoVLE32_V_MF2_]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.end: ; CHECK-NEXT: bb.3.if.end:
; CHECK-NEXT: [[PHI:%[0-9]+]]:vr = PHI %1, %bb.1, %2, %bb.2 ; CHECK-NEXT: [[PHI:%[0-9]+]]:vr = PHI %1, %bb.1, %2, %bb.2
; CHECK-NEXT: PseudoVSE64_V_M1 [[PHI]], [[COPY1]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE64_V_M1 [[PHI]], [[COPY1]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype
; CHECK-NEXT: PseudoRET ; CHECK-NEXT: PseudoRET
bb.0.entry: bb.0.entry:
successors: %bb.2(0x30000000), %bb.1(0x50000000) successors: %bb.2(0x30000000), %bb.1(0x50000000)
liveins: $x10, $x11, $x12, $x13 liveins: $x10, $x11, $x12, $x13
%7:gprnox0 = COPY $x13 %7:gprnox0 = COPY $x13
%6:gpr = COPY $x12 %6:gpr = COPY $x12
%5:gpr = COPY $x11 %5:gpr = COPY $x11
%4:gpr = COPY $x10 %4:gpr = COPY $x10
%0:vr = PseudoVLE32_V_MF2 %5, %7, 5 %0:vr = PseudoVLE32_V_MF2 %5, %7, 5
%8:gpr = COPY $x0 %8:gpr = COPY $x0
BEQ %4, %8, %bb.2 BEQ %4, %8, %bb.2
PseudoBR %bb.1 PseudoBR %bb.1
bb.1.if.then: bb.1.if.then:
early-clobber %1:vr = PseudoVZEXT_VF2_M1 %0, %7, 6 %dead1:vr = IMPLICIT_DEF
early-clobber %1:vr = PseudoVZEXT_VF2_M1 %dead1, %0, %7, 6, 0
PseudoBR %bb.3 PseudoBR %bb.3
bb.2.if.else: bb.2.if.else:
early-clobber %2:vr = PseudoVSEXT_VF2_M1 %0, %7, 6 %dead2:vr = IMPLICIT_DEF
early-clobber %2:vr = PseudoVSEXT_VF2_M1 %dead2, %0, %7, 6, 0
bb.3.if.end: bb.3.if.end:
%3:vr = PHI %1, %bb.1, %2, %bb.2 %3:vr = PHI %1, %bb.1, %2, %bb.2
PseudoVSE64_V_M1 %3, %6, %7, 6 PseudoVSE64_V_M1 %3, %6, %7, 6
PseudoRET PseudoRET
... ...
--- ---
▲ Show 20 Lines • Show All 177 Lines • ▼ Show 20 Linesbody: |
; CHECK-NEXT: liveins: $x10, $x11 ; CHECK-NEXT: liveins: $x10, $x11
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 223 /* e64, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 223 /* e64, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVID_V_MF2_:%[0-9]+]]:vr = PseudoVID_V_MF2 %pt, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVID_V_MF2_:%[0-9]+]]:vr = PseudoVID_V_MF2 %pt, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: %pt2:vr = IMPLICIT_DEF
; CHECK-NEXT: dead [[PseudoVSETVLIX0_1:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead [[PseudoVSETVLIX0_1:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 0, -1, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 %pt2, 0, -1, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PseudoVMSEQ_VI_MF2_:%[0-9]+]]:vmv0 = PseudoVMSEQ_VI_MF2 killed [[PseudoVID_V_MF2_]], 0, -1, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVMSEQ_VI_MF2_:%[0-9]+]]:vmv0 = PseudoVMSEQ_VI_MF2 killed [[PseudoVID_V_MF2_]], 0, -1, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: $v0 = COPY [[PseudoVMSEQ_VI_MF2_]] ; CHECK-NEXT: $v0 = COPY [[PseudoVMSEQ_VI_MF2_]]
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 23 /* e32, mf2, tu, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 23 /* e32, mf2, tu, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl
; CHECK-NEXT: [[PseudoVLE32_V_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVLE32_V_MF2_MASK [[PseudoVMV_V_I_MF2_]], killed [[COPY]], $v0, -1, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVLE32_V_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVLE32_V_MF2_MASK [[PseudoVMV_V_I_MF2_]], killed [[COPY]], $v0, -1, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
Show All 18 Lines bb.0:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $x10, $x11 liveins: $x10, $x11
%0:gpr = COPY $x11 %0:gpr = COPY $x11
%1:gpr = COPY $x10 %1:gpr = COPY $x10
%2:gpr = IMPLICIT_DEF %2:gpr = IMPLICIT_DEF
%pt:vr = IMPLICIT_DEF %pt:vr = IMPLICIT_DEF
%3:vr = PseudoVID_V_MF2 %pt, -1, 6, 0 %3:vr = PseudoVID_V_MF2 %pt, -1, 6, 0
%4:vrnov0 = PseudoVMV_V_I_MF2 0, -1, 5 %pt2:vr = IMPLICIT_DEF
%4:vrnov0 = PseudoVMV_V_I_MF2 %pt2, 0, -1, 5, 0
bb.1: bb.1:
successors: %bb.2(0x40000000), %bb.3(0x40000000) successors: %bb.2(0x40000000), %bb.3(0x40000000)
%5:vmv0 = PseudoVMSEQ_VI_MF2 killed %3, 0, -1, 5 %5:vmv0 = PseudoVMSEQ_VI_MF2 killed %3, 0, -1, 5
$v0 = COPY %5 $v0 = COPY %5
%6:vrnov0 = PseudoVLE32_V_MF2_MASK %4, killed %0, $v0, -1, 5, 0 %6:vrnov0 = PseudoVLE32_V_MF2_MASK %4, killed %0, $v0, -1, 5, 0
%7:gpr = PseudoVCPOP_M_B1 %5, -1, 0 %7:gpr = PseudoVCPOP_M_B1 %5, -1, 0
▲ Show 20 Lines • Show All 198 Lines • ▼ Show 20 Lines
body: | body: |
; CHECK-LABEL: name: redusum_loop ; CHECK-LABEL: name: redusum_loop
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $x10, $x12 ; CHECK-NEXT: liveins: $x10, $x12
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x12 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x12
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: %dead:vr = IMPLICIT_DEF
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 4, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 4, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 0, 4, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 %dead, 0, 4, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY [[PseudoVMV_V_I_M1_]] ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY [[PseudoVMV_V_I_M1_]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vr = COPY [[COPY2]] ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vr = COPY [[COPY2]]
; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 1 ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 1
; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW killed [[LUI]], -2048 ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW killed [[LUI]], -2048
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.vector.body: ; CHECK-NEXT: bb.1.vector.body:
; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000) ; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY1]], %bb.0, %5, %bb.1 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY1]], %bb.0, %5, %bb.1
; CHECK-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[ADDIW]], %bb.0, %4, %bb.1 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[ADDIW]], %bb.0, %4, %bb.1
; CHECK-NEXT: [[PHI2:%[0-9]+]]:vr = PHI [[COPY3]], %bb.0, %16, %bb.1 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:vr = PHI [[COPY3]], %bb.0, %16, %bb.1
; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 [[PHI]], 4, 5 /* e32 */, implicit $vl, implicit $vtype :: (load (s128) from %ir.lsr.iv12, align 4) ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 [[PHI]], 4, 5 /* e32 */, implicit $vl, implicit $vtype :: (load (s128) from %ir.lsr.iv12, align 4)
craig.topperUnsubmitted
Not Done
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What happened here?

craig.topper: What happened here?
reamesAuthorUnsubmitted
Done
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It looks my hand update to the MIR was wrong. The undef form is post register allocation, I should have used an implicit_def instruction here. Same problem in vsetvli-insert.mir.

Thanks for catching this.

reames: It looks my hand update to the MIR was wrong. The undef form is post register allocation, I…
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 killed [[PseudoVLE32_V_M1_]], [[PHI2]], 4, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 killed [[PseudoVLE32_V_M1_]], [[PHI2]], 4, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = nsw ADDI [[PHI1]], -4 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = nsw ADDI [[PHI1]], -4
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI [[PHI]], 16 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI [[PHI]], 16
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: BNE [[ADDI]], [[COPY4]], %bb.1 ; CHECK-NEXT: BNE [[ADDI]], [[COPY4]], %bb.1
; CHECK-NEXT: PseudoBR %bb.2 ; CHECK-NEXT: PseudoBR %bb.2
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.middle.block: ; CHECK-NEXT: bb.2.middle.block:
; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF ; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVMV_S_X_M1_:%[0-9]+]]:vr = PseudoVMV_S_X_M1 [[DEF]], [[COPY5]], 1, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVMV_S_X_M1_:%[0-9]+]]:vr = PseudoVMV_S_X_M1 [[DEF]], [[COPY5]], 1, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_E8_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1_E8 [[DEF1]], [[PseudoVADD_VV_M1_]], killed [[PseudoVMV_S_X_M1_]], 4, 5 /* e32 */, 1 /* ta, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_E8_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1_E8 [[DEF1]], [[PseudoVADD_VV_M1_]], killed [[PseudoVMV_S_X_M1_]], 4, 5 /* e32 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: PseudoVSE32_V_M1 killed [[PseudoVREDSUM_VS_M1_E8_]], [[COPY]], 1, 5 /* e32 */, implicit $vl, implicit $vtype :: (store (s32) into %ir.res) ; CHECK-NEXT: PseudoVSE32_V_M1 killed [[PseudoVREDSUM_VS_M1_E8_]], [[COPY]], 1, 5 /* e32 */, implicit $vl, implicit $vtype :: (store (s32) into %ir.res)
; CHECK-NEXT: PseudoRET ; CHECK-NEXT: PseudoRET
bb.0.entry: bb.0.entry:
liveins: $x10, $x12 liveins: $x10, $x12
%8:gpr = COPY $x12 %8:gpr = COPY $x12
%6:gpr = COPY $x10 %6:gpr = COPY $x10
%11:vr = PseudoVMV_V_I_M1 0, 4, 5 %dead:vr = IMPLICIT_DEF
%11:vr = PseudoVMV_V_I_M1 %dead, 0, 4, 5, 0
%12:vr = COPY %11 %12:vr = COPY %11
%10:vr = COPY %12 %10:vr = COPY %12
%13:gpr = LUI 1 %13:gpr = LUI 1
%9:gpr = ADDIW killed %13, -2048 %9:gpr = ADDIW killed %13, -2048
bb.1.vector.body: bb.1.vector.body:
successors: %bb.2(0x04000000), %bb.1(0x7c000000) successors: %bb.2(0x04000000), %bb.1(0x7c000000)
▲ Show 20 Lines • Show All 207 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir

Show First 20 Lines • Show All 194 Lines • ▼ Show 20 Lines bb.0.entry:
; CHECK-LABEL: name: load_zext ; CHECK-LABEL: name: load_zext
; CHECK: liveins: $x10, $x11 ; CHECK: liveins: $x10, $x11
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVLE32_V_MF2_:%[0-9]+]]:vr = PseudoVLE32_V_MF2 [[COPY1]], $noreg, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVLE32_V_MF2_:%[0-9]+]]:vr = PseudoVLE32_V_MF2 [[COPY1]], $noreg, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: early-clobber %3:vr = PseudoVZEXT_VF2_M1 killed [[PseudoVLE32_V_MF2_]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: %dead:vr = IMPLICIT_DEF
; CHECK-NEXT: early-clobber %3:vr = PseudoVZEXT_VF2_M1 %dead, killed [[PseudoVLE32_V_MF2_]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: $v8 = COPY %3 ; CHECK-NEXT: $v8 = COPY %3
; CHECK-NEXT: PseudoRET implicit $v8 ; CHECK-NEXT: PseudoRET implicit $v8
%1:gprnox0 = COPY $x11 %1:gprnox0 = COPY $x11
%0:gpr = COPY $x10 %0:gpr = COPY $x10
%2:vr = PseudoVLE32_V_MF2 %0, %1, 5 %2:vr = PseudoVLE32_V_MF2 %0, %1, 5
early-clobber %3:vr = PseudoVZEXT_VF2_M1 killed %2, %1, 6 %dead:vr = IMPLICIT_DEF
early-clobber %3:vr = PseudoVZEXT_VF2_M1 %dead, killed %2, %1, 6, 0
$v8 = COPY %3 $v8 = COPY %3
PseudoRET implicit $v8 PseudoRET implicit $v8
... ...
--- ---
name: vmv_x_s name: vmv_x_s
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines bb.0 (%ir-block.0):
liveins: $x10 liveins: $x10
; CHECK-LABEL: name: vreduce_add_v2i64 ; CHECK-LABEL: name: vreduce_add_v2i64
; CHECK: liveins: $x10 ; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 [[COPY]], 2, 6 /* e64 */, implicit $vl, implicit $vtype :: (load (s128) from %ir.x) ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 [[COPY]], 2, 6 /* e64 */, implicit $vl, implicit $vtype :: (load (s128) from %ir.x)
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 152 /* e64, m1, tu, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 0, -1, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 undef $v2, 0, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF ; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_E8_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1_E8 [[DEF]], killed [[PseudoVLE64_V_M1_]], killed [[PseudoVMV_V_I_M1_]], 2, 6 /* e64 */, 1 /* ta, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_E8_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1_E8 [[DEF]], killed [[PseudoVLE64_V_M1_]], killed [[PseudoVMV_V_I_M1_]], 2, 6 /* e64 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[PseudoVMV_X_S_M1_:%[0-9]+]]:gpr = PseudoVMV_X_S_M1 killed [[PseudoVREDSUM_VS_M1_E8_]], 6 /* e64 */, implicit $vtype ; CHECK-NEXT: [[PseudoVMV_X_S_M1_:%[0-9]+]]:gpr = PseudoVMV_X_S_M1 killed [[PseudoVREDSUM_VS_M1_E8_]], 6 /* e64 */, implicit $vtype
; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S_M1_]] ; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S_M1_]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%0:gpr = COPY $x10 %0:gpr = COPY $x10
%1:vr = PseudoVLE64_V_M1 %0, 2, 6 :: (load (s128) from %ir.x) %1:vr = PseudoVLE64_V_M1 %0, 2, 6 :: (load (s128) from %ir.x)
%2:vr = PseudoVMV_V_I_M1 0, -1, 6 %2:vr = PseudoVMV_V_I_M1 undef $v2, 0, -1, 6, 0
%4:vr = IMPLICIT_DEF %4:vr = IMPLICIT_DEF
%3:vr = PseudoVREDSUM_VS_M1_E8 %4, killed %1, killed %2, 2, 6, 1 %3:vr = PseudoVREDSUM_VS_M1_E8 %4, killed %1, killed %2, 2, 6, 1
%5:gpr = PseudoVMV_X_S_M1 killed %3, 6 %5:gpr = PseudoVMV_X_S_M1 killed %3, 6
$x10 = COPY %5 $x10 = COPY %5
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines bb.0:
liveins: $x10, $v8, $x11 liveins: $x10, $v8, $x11
; CHECK-LABEL: name: vmv_v_i_different_lmuls ; CHECK-LABEL: name: vmv_v_i_different_lmuls
; CHECK: liveins: $x10, $v8, $x11 ; CHECK: liveins: $x10, $v8, $x11
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 4, 217 /* e64, m2, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 4, 217 /* e64, m2, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVID_V_M2_:%[0-9]+]]:vrm2 = PseudoVID_V_M2 %pt, 4, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVID_V_M2_:%[0-9]+]]:vrm2 = PseudoVID_V_M2 %pt, 4, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 198 /* e8, mf4, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 134 /* e8, mf4, tu, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
; CHECK-NEXT: [[PseudoVMV_V_I_MF4_:%[0-9]+]]:vr = PseudoVMV_V_I_MF4 0, 4, 3 /* e8 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVMV_V_I_MF4_:%[0-9]+]]:vr = PseudoVMV_V_I_MF4 undef [[PseudoVMV_V_I_MF4_]], 0, 4, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: PseudoRET ; CHECK-NEXT: PseudoRET
%pt:vrm2 = IMPLICIT_DEF %pt:vrm2 = IMPLICIT_DEF
%0:vrm2 = PseudoVID_V_M2 %pt, 4, 6, 3 %0:vrm2 = PseudoVID_V_M2 %pt, 4, 6, 3
%4:vr = PseudoVMV_V_I_MF4 0, 4, 3 %4:vr = PseudoVMV_V_I_MF4 undef %4, 0, 4, 3, 0
PseudoRET PseudoRET
... ...

llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir

Show First 20 Lines • Show All 163 Lines • ▼ Show 20 Linesbody: |
; CHECK-NEXT: $x10 = SLLI killed $x10, 1 ; CHECK-NEXT: $x10 = SLLI killed $x10, 1
; CHECK-NEXT: $x10 = ADD $x2, killed $x10 ; CHECK-NEXT: $x10 = ADD $x2, killed $x10
; CHECK-NEXT: SD killed renamable $x17, killed $x10, 72 :: (store (s64)) ; CHECK-NEXT: SD killed renamable $x17, killed $x10, 72 :: (store (s64))
; CHECK-NEXT: $x10 = PseudoReadVLENB ; CHECK-NEXT: $x10 = PseudoReadVLENB
; CHECK-NEXT: $x10 = SLLI killed $x10, 1 ; CHECK-NEXT: $x10 = SLLI killed $x10, 1
; CHECK-NEXT: $x10 = ADD $x2, killed $x10 ; CHECK-NEXT: $x10 = ADD $x2, killed $x10
; CHECK-NEXT: SD killed renamable $x16, killed $x10, 64 :: (store (s64) into %fixed-stack.1, align 16) ; CHECK-NEXT: SD killed renamable $x16, killed $x10, 64 :: (store (s64) into %fixed-stack.1, align 16)
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 69 /* e8, mf8, ta, mu */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 69 /* e8, mf8, ta, mu */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: renamable $v8 = PseudoVMV_V_I_MF8 0, 2, 3 /* e8 */, implicit $vl, implicit $vtype ; CHECK-NEXT: renamable $v8 = PseudoVMV_V_I_MF8 undef $v8, 0, 2, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: $x10 = ADDI $x2, 32 ; CHECK-NEXT: $x10 = ADDI $x2, 32
; CHECK-NEXT: VS1R_V killed renamable $v8, killed $x10 :: (store unknown-size into %stack.1, align 8) ; CHECK-NEXT: VS1R_V killed renamable $v8, killed $x10 :: (store unknown-size into %stack.1, align 8)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.while.cond: ; CHECK-NEXT: bb.1.while.cond:
; CHECK-NEXT: successors: %bb.2(0x30000000), %bb.1(0x50000000) ; CHECK-NEXT: successors: %bb.2(0x30000000), %bb.1(0x50000000)
; CHECK-NEXT: liveins: $x8, $x9 ; CHECK-NEXT: liveins: $x8, $x9
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: BNE $x0, $x0, %bb.1 ; CHECK-NEXT: BNE $x0, $x0, %bb.1
Show All 14 Lines bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $x11, $x14, $x16, $x17 liveins: $x11, $x14, $x16, $x17
renamable $x8 = COPY $x14 renamable $x8 = COPY $x14
renamable $x9 = COPY $x11 renamable $x9 = COPY $x11
SD killed renamable $x17, %fixed-stack.0, 0 :: (store (s64)) SD killed renamable $x17, %fixed-stack.0, 0 :: (store (s64))
SD killed renamable $x16, %fixed-stack.1, 0 :: (store (s64) into %fixed-stack.1, align 16) SD killed renamable $x16, %fixed-stack.1, 0 :: (store (s64) into %fixed-stack.1, align 16)
dead $x0 = PseudoVSETIVLI 2, 69, implicit-def $vl, implicit-def $vtype dead $x0 = PseudoVSETIVLI 2, 69, implicit-def $vl, implicit-def $vtype
renamable $v8 = PseudoVMV_V_I_MF8 0, 2, 3, implicit $vl, implicit $vtype renamable $v8 = PseudoVMV_V_I_MF8 undef $v8, 0, 2, 3, 0, implicit $vl, implicit $vtype
VS1R_V killed renamable $v8, %stack.1 :: (store unknown-size into %stack.1, align 8) VS1R_V killed renamable $v8, %stack.1 :: (store unknown-size into %stack.1, align 8)
bb.1.while.cond: bb.1.while.cond:
successors: %bb.2(0x30000000), %bb.1(0x50000000) successors: %bb.2(0x30000000), %bb.1(0x50000000)
liveins: $x8, $x9 liveins: $x8, $x9
BNE $x0, $x0, %bb.1 BNE $x0, $x0, %bb.1
PseudoBR %bb.2 PseudoBR %bb.2
Show All 15 Lines