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[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
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Authored by reames on Jun 27 2023, 10:59 AM.

Details

Summary

This change continues with the line of work discussed in https://discourse.llvm.org/t/riscv-transition-in-vector-pseudo-structure-policy-variants/71295. In D153155, we started removing the legacy distinction between unsuffixed (TA) and _TU pseudos. This patch continues that effort for the unary instruction families.

The change consists of a few interacting pieces:

  • Adding a vector policy operand to VPseudoUnaryNoMaskTU.
  • Then using VPseudoUnaryNoMaskTU for all cases where VPseudoUnaryNoMask was previously used and deleting the unsuffixed form.
  • Then renaming VPseudoUnaryNoMaskTU to VPseudoUnaryNoMask, and adjusting the RISCVMaskedPseudo table to use the combined pseudo.
  • Fixing up two places in C++ code which manually construct VMV_V_* instructions.

Normally, I'd try to factor this into a couple of changes, but in this case, the table structure is tried to naming and thus we can't really separate the otherwise NFC bits.

As before, we see codegen changes (some improvements and some regressions) due to scheduling differences caused by the extra implicit_def instructions.

Diff Detail

Event Timeline

reames created this revision.Jun 27 2023, 10:59 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 27 2023, 10:59 AM
reames requested review of this revision.Jun 27 2023, 10:59 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 27 2023, 10:59 AM
craig.topper added inline comments.Jun 27 2023, 12:57 PM
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
3426

While you're here, can you fix this typo. MMV->VMV

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
778

What happened here?

reames added inline comments.Jun 27 2023, 1:08 PM
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
3426

Fixed in 49428ba.

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
778

It looks my hand update to the MIR was wrong. The undef form is post register allocation, I should have used an implicit_def instruction here. Same problem in vsetvli-insert.mir.

Thanks for catching this.

reames updated this revision to Diff 535544.Jun 28 2023, 3:01 PM

Address review comment

This revision is now accepted and ready to land.Jun 28 2023, 3:23 PM
This revision was landed with ongoing or failed builds.Jun 29 2023, 7:34 AM
This revision was automatically updated to reflect the committed changes.