[XCore] Remove unused TableGen classes and multiclasses.

[kosarev]

Summary

And warn on them from now on.

[nigelp-xmos]

Removing unused content LGTM. Haven't tested the parent -warn-on-unused-entities functionality.

[brad]

My apologies I had not noticed this was part of a stacked set of diffs.

llvm/lib/Target/XCore/CMakeLists.txt

 add_llvm_component_group(XCore)
 
 set(LLVM_TARGET_DEFINITIONS XCore.td)
 
 tablegen(LLVM XCoreGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM XCoreGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM XCoreGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM XCoreGenDAGISel.inc -gen-dag-isel -warn-on-unused-entities)
 tablegen(LLVM XCoreGenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM XCoreGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM XCoreGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM XCoreGenSubtargetInfo.inc -gen-subtarget)
 
 add_public_tablegen_target(XCoreCommonTableGen)
 
 add_llvm_target(XCoreCodeGen

llvm/lib/Target/XCore/XCoreInstrInfo.td

_F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
        [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
 
 class F3R_np<bits<5> opc, string OpcStr> :
   _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
        !strconcat(OpcStr, " $dst, $b, $c"), []>;
 // Three operand long
 
 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
-multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
-                      SDNode OpNode> {
-  def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
-                  !strconcat(OpcStr, " $dst, $b, $c"),
-                  [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
-  def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
-                       !strconcat(OpcStr, " $dst, $b, $c"),
-                       [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
-}
-
-/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
                         SDNode OpNode> {
   def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
                   !strconcat(OpcStr, " $dst, $b, $c"),
                   [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
   def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
                            !strconcat(OpcStr, " $dst, $b, $c"),
                            [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
                   [(Int immU16:$a)]>;
 }
 
 multiclass FU6_LU6_np<bits<10> opc, string OpcStr> {
   def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
   def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
 }
 
-// Two operand short
-
-class F2R_np<bits<6> opc, string OpcStr> :
-  _F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b),
-       !strconcat(OpcStr, " $dst, $b"), []>;
-
-// Two operand long
-
 //===----------------------------------------------------------------------===//
 // Pseudo Instructions
 //===----------------------------------------------------------------------===//
 
 let Defs = [SP], Uses = [SP] in {
 def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt, i32imm:$amt2),
                                "# ADJCALLSTACKDOWN $amt, $amt2",
                                [(callseq_start timm:$amt, timm:$amt2)]>;