[lld][ARM] Add support for 16-bit thumb group relocations

[john.brawn]

Summary

This adds support for the following relocations:

• R_ARM_THM_ALU_ABS_G0_NC
• R_ARM_THM_ALU_ABS_G1_NC
• R_ARM_THM_ALU_ABS_G2_NC
• R_ARM_THM_ALU_ABS_G3

[peter.smith]

One tiny nit aside, looks good to me. Please leave some time for MaskRay to take a look.

For reference: the R_ARM_THM_ALU_ABS_G* relocations are defined in the Static Thumb16 Relocations table https://github.com/ARM-software/abi-aa/blob/main/aaelf32/aaelf32.rst#5615static-thumb16-relocations .

lld/ELF/Arch/ARM.cpp

698

All the other uses of ~ in the file are of the form & ~0x00ff . Would be good to keep it consistent.

[MaskRay]

In D153407#4437758, @peter.smith wrote:

One tiny nit aside, looks good to me. Please leave some time for MaskRay to take a look.

For reference: the R_ARM_THM_ALU_ABS_G* relocations are defined in the Static Thumb16 Relocations table https://github.com/ARM-software/abi-aa/blob/main/aaelf32/aaelf32.rst#5615static-thumb16-relocations .

Thanks. Looks good to me as well. It would be good to place the link to the summary/commit message.

lld/ELF/Arch/ARM.cpp

690

This may be an instance that duplicating write16(loc, (read16(loc) &~ 0x00ff) | (val & 0xff)); is better than a chain of [[fallthrough]];...

If the case code is close enough, we should not worry much that we made a mistake in the formula.

lld/test/ELF/arm-thumb-alu.s

43

Add -NEXT for all these continuation lines. This will make FileCheck report a better error when something goes wrong.

52

2-space indentation is more common.

lld/ELF/Arch/ARM.cpp

 RelExpr ARM::getRelExpr(RelType type, const Symbol &s,
                         const uint8_t *loc) const {
   switch (type) {
   case R_ARM_ABS32:
   case R_ARM_MOVW_ABS_NC:
   case R_ARM_MOVT_ABS:
   case R_ARM_THM_MOVW_ABS_NC:
   case R_ARM_THM_MOVT_ABS:
+  case R_ARM_THM_ALU_ABS_G0_NC:
+  case R_ARM_THM_ALU_ABS_G1_NC:
+  case R_ARM_THM_ALU_ABS_G2_NC:
+  case R_ARM_THM_ALU_ABS_G3:
     return R_ABS;
   case R_ARM_THM_JUMP8:
   case R_ARM_THM_JUMP11:
     return R_PC;
   case R_ARM_CALL:
   case R_ARM_JUMP24:
   case R_ARM_PC24:
   case R_ARM_PLT32:
write16(loc,
               0xf240 |                     // opcode
                   ((val >> 1) & 0x0400) |  // i
                   ((val >> 12) & 0x000f)); // imm4
     write16(loc + 2,
               (read16(loc + 2) & 0x8f00) | // opcode
                   ((val << 4) & 0x7000) |    // imm3
                   (val & 0x00ff));           // imm8
     break;
+  case R_ARM_THM_ALU_ABS_G3:
+    write16(loc, (read16(loc) &~ 0x00ff) | ((val >> 24) & 0x00ff));
+    break;
+  case R_ARM_THM_ALU_ABS_G2_NC:
+    write16(loc, (read16(loc) &~ 0x00ff) | ((val >> 16) & 0x00ff));
+    break;
+  case R_ARM_THM_ALU_ABS_G1_NC:
+    write16(loc, (read16(loc) &~ 0x00ff) | ((val >> 8) & 0x00ff));
+    break;
+  case R_ARM_THM_ALU_ABS_G0_NC:
+    write16(loc, (read16(loc) &~ 0x00ff) | (val & 0x00ff));
+    break;
   case R_ARM_ALU_PC_G0:
     encodeAluGroup(loc, rel, val, 0, true);
     break;
   case R_ARM_ALU_PC_G0_NC:
     encodeAluGroup(loc, rel, val, 0, false);
     break;
   case R_ARM_ALU_PC_G1:
     encodeAluGroup(loc, rel, val, 1, true);
case R_ARM_THM_MOVT_BREL: {
     // Encoding T3: A = imm4:i:imm3:imm8
     uint16_t hi = read16(buf);
     uint16_t lo = read16(buf + 2);
     return SignExtend64<16>(((hi & 0x000f) << 12) | // imm4
                             ((hi & 0x0400) << 1) |  // i
                             ((lo & 0x7000) >> 4) |  // imm3
                             (lo & 0x00ff));         // imm8
   }
+  case R_ARM_THM_ALU_ABS_G0_NC:
+  case R_ARM_THM_ALU_ABS_G1_NC:
+  case R_ARM_THM_ALU_ABS_G2_NC:
+  case R_ARM_THM_ALU_ABS_G3:
+    return read16(buf) & 0xff;
   case R_ARM_ALU_PC_G0:
   case R_ARM_ALU_PC_G0_NC:
   case R_ARM_ALU_PC_G1:
   case R_ARM_ALU_PC_G1_NC:
   case R_ARM_ALU_PC_G2: {
     // 12-bit immediate is a modified immediate made up of a 4-bit even
     // right rotation and 8-bit constant. After the rotation the value
     // is zero-extended. When bit 23 is set the instruction is an add, when

lld/test/ELF/arm-thumb-alu.s

+// REQUIRES: arm
+
+// RUN: split-file %s %t
+// RUN: llvm-mc -filetype=obj -triple=thumbv6m-unknown-linux-gnueabi %t/asm -o %t.o
+// RUN: ld.lld --script %t/lds %t.o -o %t2
+// RUN: llvm-objdump -d %t2 --triple=thumbv6m-unknown-linux-gnueabi --no-show-raw-insn | FileCheck %s
+
+//--- lds
+SECTIONS {
+  .tests 0x00001000 : AT(0x00001000) { *(.tests) }
+  .sym1  0x11223344 : AT(0x11223344) { *(.sym1) }
+  .sym2  0x00ffffff : AT(0x00ffffff) { *(.sym2) }
+  .fn    0x55667788 : AT(0x55667788) { *(.fn) }
+}
+
+//--- asm
+  .section .tests, "ax", %progbits
+
+// CHECK-LABEL: <R_ARM_THM_ALU_ABS_G0_NC>:
+// CHECK:      adds    r0, #0x44
+// CHECK-NEXT: movs    r0, #0x44
+// CHECK-NEXT: movs    r0, #0x45
+// CHECK-NEXT: movs    r0, #0x43
+// CHECK-NEXT: movs    r0, #0xff
+// CHECK-NEXT: movs    r0, #0x0
+// CHECK-NEXT: movs    r0, #0xfe
+// CHECK-NEXT: movs    r0, #0x89
+// CHECK-NEXT: movs    r0, #0x8b
+R_ARM_THM_ALU_ABS_G0_NC:
+  adds r0, :lower0_7:sym1
+  movs r0, :lower0_7:sym1
+  movs r0, :lower0_7:sym1+1
+  movs r0, :lower0_7:sym1+0xff
+  movs r0, :lower0_7:sym2
+  movs r0, :lower0_7:sym2+1
+  movs r0, :lower0_7:sym2+0xff
+  movs r0, :lower0_7:fn
+  movs r0, :lower0_7:fn+2
+
+// CHECK-LABEL: <R_ARM_THM_ALU_ABS_G1_NC>:
+// CHECK:      adds    r0, #0x33
+// CHECK-NEXT: movs    r0, #0x33
+// CHECK-NEXT: movs    r0, #0x33
+// CHECK-NEXT: movs    r0, #0x34
+// CHECK-NEXT: movs    r0, #0xff
+// CHECK-NEXT: movs    r0, #0x0
+// CHECK-NEXT: movs    r0, #0x0
+// CHECK-NEXT: movs    r0, #0x77
+// CHECK-NEXT: movs    r0, #0x77
+R_ARM_THM_ALU_ABS_G1_NC:
+  adds r0, :lower8_15:sym1
+  movs r0, :lower8_15:sym1
+  movs r0, :lower8_15:sym1+1
+  movs r0, :lower8_15:sym1+0xff
+  movs r0, :lower8_15:sym2
+  movs r0, :lower8_15:sym2+1
+  movs r0, :lower8_15:sym2+0xff
+  movs r0, :lower8_15:fn
+  movs r0, :lower8_15:fn+2
+
+// CHECK-LABEL: <R_ARM_THM_ALU_ABS_G2_NC>:
+// CHECK:      adds    r0, #0x22
+// CHECK-NEXT: movs    r0, #0x22
+// CHECK-NEXT: movs    r0, #0x22
+// CHECK-NEXT: movs    r0, #0x22
+// CHECK-NEXT: movs    r0, #0xff
+// CHECK-NEXT: movs    r0, #0x0
+// CHECK-NEXT: movs    r0, #0x0
+// CHECK-NEXT: movs    r0, #0x66
+// CHECK-NEXT: movs    r0, #0x66
+R_ARM_THM_ALU_ABS_G2_NC:
+  adds r0, :upper0_7:sym1
+  movs r0, :upper0_7:sym1
+  movs r0, :upper0_7:sym1+1
+  movs r0, :upper0_7:sym1+0xff
+  movs r0, :upper0_7:sym2
+  movs r0, :upper0_7:sym2+1
+  movs r0, :upper0_7:sym2+0xff
+  movs r0, :upper0_7:fn
+  movs r0, :upper0_7:fn+2
+
+// CHECK-LABEL: <R_ARM_THM_ALU_ABS_G3>:
+// CHECK:      adds    r0, #0x11
+// CHECK-NEXT: movs    r0, #0x11
+// CHECK-NEXT: movs    r0, #0x11
+// CHECK-NEXT: movs    r0, #0x11
+// CHECK-NEXT: movs    r0, #0x0
+// CHECK-NEXT: movs    r0, #0x1
+// CHECK-NEXT: movs    r0, #0x1
+// CHECK-NEXT: movs    r0, #0x55
+// CHECK-NEXT: movs    r0, #0x55
+R_ARM_THM_ALU_ABS_G3:
+  adds r0, :upper8_15:sym1
+  movs r0, :upper8_15:sym1
+  movs r0, :upper8_15:sym1+1
+  movs r0, :upper8_15:sym1+0xff
+  movs r0, :upper8_15:sym2
+  movs r0, :upper8_15:sym2+1
+  movs r0, :upper8_15:sym2+0xff
+  movs r0, :upper8_15:fn
+  movs r0, :upper8_15:fn+2
+
+  .section .sym1, "aw", %progbits
+sym1:
+  .byte 0
+
+  .section .sym2, "aw", %progbits
+sym2:
+  .byte 0
+
+  .section .fn, "ax", %progbits
+  .thumb_func
+fn:
+  bx lr