[RISCV] Move getRVVMCOpcode to RISCVInstrInfo.h

[wangpc]

Summary

To simplify more code.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.h

265

Can we change uint16_t to unsigned?

265

That would match what MachineInstr::getOpcode returns

[• pcwang-thead]

Use unsigned.

[• pcwang-thead]

One concern: is it possible to be false positive for these usages (though I haven't found any failed test)? When mapping pseudos to MC opcode, we may lost some information like MASK, TIED, TU/TA, etc.

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

2145

For example, we didn't catch _MASK here.

[wangpc]

Ping

[craig.topper]

In D152512#4412707, @pcwang-thead wrote:

One concern: is it possible to be false positive for these usages (though I haven't found any failed test)? When mapping pseudos to MC opcode, we may lost some information like MASK, TIED, TU/TA, etc.

I am concerned about that. The operand numbers are different between the different versions. And they have different properties.

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

 /// VL and only sets VTYPE.
 static bool isVLPreservingConfig(const MachineInstr &MI) {
   if (MI.getOpcode() != RISCV::PseudoVSETVLIX0)
     return false;
   assert(RISCV::X0 == MI.getOperand(1).getReg());
   return RISCV::X0 == MI.getOperand(0).getReg();
 }
 
-static uint16_t getRVVMCOpcode(uint16_t RVVPseudoOpcode) {
-  const RISCVVPseudosTable::PseudoInfo *RVV =
-      RISCVVPseudosTable::getPseudoInfo(RVVPseudoOpcode);
-  if (!RVV)
-    return 0;
-  return RVV->BaseInstr;
-}
-
 static bool isScalarMoveInstr(const MachineInstr &MI) {
-  switch (getRVVMCOpcode(MI.getOpcode())) {
+  switch (RISCV::getRVVMCOpcode(MI.getOpcode())) {
   default:
     return false;
   case RISCV::VMV_S_X:
   case RISCV::VFMV_S_F:
     return true;
   }
 }
 
 static bool isVSlideInstr(const MachineInstr &MI) {
-  switch (getRVVMCOpcode(MI.getOpcode())) {
+  switch (RISCV::getRVVMCOpcode(MI.getOpcode())) {
   default:
     return false;
   case RISCV::VSLIDEDOWN_VX:
   case RISCV::VSLIDEDOWN_VI:
   case RISCV::VSLIDEUP_VX:
   case RISCV::VSLIDEUP_VI:
     return true;
   }
 }
 
 /// Get the EEW for a load or store instruction.  Return std::nullopt if MI is
 /// not a load or store which ignores SEW.
 static std::optional<unsigned> getEEWForLoadStore(const MachineInstr &MI) {
-  switch (getRVVMCOpcode(MI.getOpcode())) {
+  switch (RISCV::getRVVMCOpcode(MI.getOpcode())) {
   default:
     return std::nullopt;
   case RISCV::VLE8_V:
   case RISCV::VLSE8_V:
   case RISCV::VSE8_V:
   case RISCV::VSSE8_V:
     return 8;
   case RISCV::VLE16_V:

llvm/lib/Target/RISCV/RISCVInstrInfo.h

 
 // Implemented in RISCVGenInstrInfo.inc
 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
 
 // Return true if both input instructions have equal rounding mode. If at least
 // one of the instructions does not have rounding mode, false will be returned.
 bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2);
 
+// Returns the MC opcode of RVV pseudo instruction.
+unsigned getRVVMCOpcode(unsigned RVVPseudoOpcode);
+
 // Special immediate for AVL operand of V pseudo instructions to indicate VLMax.
 static constexpr int64_t VLMaxSentinel = -1LL;
 
 // Mask assignments for floating-point
 static constexpr unsigned FPMASK_Negative_Infinity = 0x001;
 static constexpr unsigned FPMASK_Negative_Normal = 0x002;
 static constexpr unsigned FPMASK_Negative_Subnormal = 0x004;
 static constexpr unsigned FPMASK_Negative_Zero = 0x008;

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

if ((MI.getOpcode() == RISCV::VSETVLI || MI.getOpcode() == RISCV::VSETIVLI ||
     OS << (Policy & RISCVII::TAIL_AGNOSTIC ? "ta" : "tu") << ", "
        << (Policy & RISCVII::MASK_AGNOSTIC ? "ma" : "mu");
   }
 
   OS.flush();
   return Comment;
 }
 
-// clang-format off
-#define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL)                                \
-  RISCV::PseudoV##OP##_##TYPE##_##LMUL
-
-#define CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE)                                    \
-  CASE_VFMA_OPCODE_COMMON(OP, TYPE, M1):                                       \
-  case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M2):                                  \
-  case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M4):                                  \
-  case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M8)
-
-#define CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE)                                   \
-  CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF2):                                      \
-  case CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE)
-
-#define CASE_VFMA_OPCODE_LMULS_MF4(OP, TYPE)                                   \
-  CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF4):                                      \
-  case CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE)
-
-#define CASE_VFMA_OPCODE_LMULS(OP, TYPE)                                       \
-  CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF8):                                      \
-  case CASE_VFMA_OPCODE_LMULS_MF4(OP, TYPE)
-
-#define CASE_VFMA_SPLATS(OP)                                                   \
-  CASE_VFMA_OPCODE_LMULS_MF4(OP, VF16):                                        \
-  case CASE_VFMA_OPCODE_LMULS_MF2(OP, VF32):                                   \
-  case CASE_VFMA_OPCODE_LMULS_M1(OP, VF64)
-// clang-format on
-
 bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
                                            unsigned &SrcOpIdx1,
                                            unsigned &SrcOpIdx2) const {
   const MCInstrDesc &Desc = MI.getDesc();
   if (!Desc.isCommutable())
     return false;
 
   switch (MI.getOpcode()) {
bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
   case RISCV::TH_MULS:
   case RISCV::TH_MULSW:
   case RISCV::TH_MULSH:
     // Operands 2 and 3 are commutable.
     return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
   case RISCV::PseudoCCMOVGPR:
     // Operands 4 and 5 are commutable.
     return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 4, 5);
-  case CASE_VFMA_SPLATS(FMADD):
-  case CASE_VFMA_SPLATS(FMSUB):
-  case CASE_VFMA_SPLATS(FMACC):
-  case CASE_VFMA_SPLATS(FMSAC):
-  case CASE_VFMA_SPLATS(FNMADD):
-  case CASE_VFMA_SPLATS(FNMSUB):
-  case CASE_VFMA_SPLATS(FNMACC):
-  case CASE_VFMA_SPLATS(FNMSAC):
-  case CASE_VFMA_OPCODE_LMULS_MF4(FMACC, VV):
-  case CASE_VFMA_OPCODE_LMULS_MF4(FMSAC, VV):
-  case CASE_VFMA_OPCODE_LMULS_MF4(FNMACC, VV):
-  case CASE_VFMA_OPCODE_LMULS_MF4(FNMSAC, VV):
-  case CASE_VFMA_OPCODE_LMULS(MADD, VX):
-  case CASE_VFMA_OPCODE_LMULS(NMSUB, VX):
-  case CASE_VFMA_OPCODE_LMULS(MACC, VX):
-  case CASE_VFMA_OPCODE_LMULS(NMSAC, VX):
-  case CASE_VFMA_OPCODE_LMULS(MACC, VV):
-  case CASE_VFMA_OPCODE_LMULS(NMSAC, VV): {
+  }
+
+  switch (RISCV::getRVVMCOpcode(MI.getOpcode())) {
+  case RISCV::VFMADD_VF:
+  case RISCV::VFMSUB_VF:
+  case RISCV::VFMACC_VF:
+  case RISCV::VFMSAC_VF:
+  case RISCV::VFNMADD_VF:
+  case RISCV::VFNMSUB_VF:
+  case RISCV::VFNMACC_VF:
+  case RISCV::VFNMSAC_VF:
+  case RISCV::VFMACC_VV:
+  case RISCV::VFMSAC_VV:
+  case RISCV::VFNMACC_VV:
+  case RISCV::VFNMSAC_VV:
+  case RISCV::VMACC_VV:
+  case RISCV::VNMSAC_VV:
+  case RISCV::VMADD_VX:
+  case RISCV::VNMSUB_VX:
+  case RISCV::VMACC_VX:
+  case RISCV::VNMSAC_VX: {
     // If the tail policy is undisturbed we can't commute.
     assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags));
     if ((MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 1) == 0)
       return false;
 
     // For these instructions we can only swap operand 1 and operand 3 by
     // changing the opcode.
     unsigned CommutableOpIdx1 = 1;
     unsigned CommutableOpIdx2 = 3;
     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1,
                               CommutableOpIdx2))
       return false;
     return true;
   }
-  case CASE_VFMA_OPCODE_LMULS_MF4(FMADD, VV):
-  case CASE_VFMA_OPCODE_LMULS_MF4(FMSUB, VV):
-  case CASE_VFMA_OPCODE_LMULS_MF4(FNMADD, VV):
-  case CASE_VFMA_OPCODE_LMULS_MF4(FNMSUB, VV):
-  case CASE_VFMA_OPCODE_LMULS(MADD, VV):
-  case CASE_VFMA_OPCODE_LMULS(NMSUB, VV): {
+  case RISCV::VFMADD_VV:
+  case RISCV::VFMSUB_VV:
+  case RISCV::VFNMADD_VV:
+  case RISCV::VFNMSUB_VV:
+  case RISCV::VMADD_VV:
+  case RISCV::VNMSUB_VV: {
     // If the tail policy is undisturbed we can't commute.
     assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags));
     if ((MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 1) == 0)
       return false;
 
     // For these instructions we have more freedom. We can commute with the
     // other multiplicand or with the addend/subtrahend/minuend.
 
case RISCV::PseudoCCMOVGPR: {
     // CCMOV can be commuted by inverting the condition.
     auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm());
     CC = RISCVCC::getOppositeBranchCondition(CC);
     auto &WorkingMI = cloneIfNew(MI);
     WorkingMI.getOperand(3).setImm(CC);
     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI*/ false,
                                                    OpIdx1, OpIdx2);
   }
-  case CASE_VFMA_SPLATS(FMACC):
-  case CASE_VFMA_SPLATS(FMADD):
-  case CASE_VFMA_SPLATS(FMSAC):
-  case CASE_VFMA_SPLATS(FMSUB):
-  case CASE_VFMA_SPLATS(FNMACC):
-  case CASE_VFMA_SPLATS(FNMADD):
-  case CASE_VFMA_SPLATS(FNMSAC):
-  case CASE_VFMA_SPLATS(FNMSUB):
-  case CASE_VFMA_OPCODE_LMULS_MF4(FMACC, VV):
-  case CASE_VFMA_OPCODE_LMULS_MF4(FMSAC, VV):
-  case CASE_VFMA_OPCODE_LMULS_MF4(FNMACC, VV):
-  case CASE_VFMA_OPCODE_LMULS_MF4(FNMSAC, VV):
-  case CASE_VFMA_OPCODE_LMULS(MADD, VX):
-  case CASE_VFMA_OPCODE_LMULS(NMSUB, VX):
-  case CASE_VFMA_OPCODE_LMULS(MACC, VX):
-  case CASE_VFMA_OPCODE_LMULS(NMSAC, VX):
-  case CASE_VFMA_OPCODE_LMULS(MACC, VV):
-  case CASE_VFMA_OPCODE_LMULS(NMSAC, VV): {
+  }
+
+  switch (RISCV::getRVVMCOpcode(MI.getOpcode())) {
+  case RISCV::VFMADD_VF:
+  case RISCV::VFMSUB_VF:
+  case RISCV::VFMACC_VF:
+  case RISCV::VFMSAC_VF:
+  case RISCV::VFNMADD_VF:
+  case RISCV::VFNMSUB_VF:
+  case RISCV::VFNMACC_VF:
+  case RISCV::VFNMSAC_VF:
+  case RISCV::VFMACC_VV:
+  case RISCV::VFMSAC_VV:
+  case RISCV::VFNMACC_VV:
+  case RISCV::VFNMSAC_VV:
+  case RISCV::VMACC_VV:
+  case RISCV::VNMSAC_VV:
+  case RISCV::VMADD_VX:
+  case RISCV::VNMSUB_VX:
+  case RISCV::VMACC_VX:
+  case RISCV::VNMSAC_VX: {
     // It only make sense to toggle these between clobbering the
     // addend/subtrahend/minuend one of the multiplicands.
     assert((OpIdx1 == 1 || OpIdx2 == 1) && "Unexpected opcode index");
     assert((OpIdx1 == 3 || OpIdx2 == 3) && "Unexpected opcode index");
     unsigned Opc;
     switch (MI.getOpcode()) {
       default:
         llvm_unreachable("Unexpected opcode");
switch (MI.getOpcode()) {
       CASE_VFMA_CHANGE_OPCODE_LMULS(NMSAC, NMSUB, VV)
     }
 
     auto &WorkingMI = cloneIfNew(MI);
     WorkingMI.setDesc(get(Opc));
     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
                                                    OpIdx1, OpIdx2);
   }
-  case CASE_VFMA_OPCODE_LMULS_MF4(FMADD, VV):
-  case CASE_VFMA_OPCODE_LMULS_MF4(FMSUB, VV):
-  case CASE_VFMA_OPCODE_LMULS_MF4(FNMADD, VV):
-  case CASE_VFMA_OPCODE_LMULS_MF4(FNMSUB, VV):
-  case CASE_VFMA_OPCODE_LMULS(MADD, VV):
-  case CASE_VFMA_OPCODE_LMULS(NMSUB, VV): {
+  case RISCV::VFMADD_VV:
+  case RISCV::VFMSUB_VV:
+  case RISCV::VFNMADD_VV:
+  case RISCV::VFNMSUB_VV:
+  case RISCV::VMADD_VV:
+  case RISCV::VNMSUB_VV: {
     assert((OpIdx1 == 1 || OpIdx2 == 1) && "Unexpected opcode index");
     // If one of the operands, is the addend we need to change opcode.
     // Otherwise we're just swapping 2 of the multiplicands.
     if (OpIdx1 == 3 || OpIdx2 == 3) {
       unsigned Opc;
       switch (MI.getOpcode()) {
         default:
           llvm_unreachable("Unexpected opcode");
MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
   }
 
   return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
 }
 
 #undef CASE_VFMA_CHANGE_OPCODE_SPLATS
 #undef CASE_VFMA_CHANGE_OPCODE_LMULS
 #undef CASE_VFMA_CHANGE_OPCODE_COMMON
-#undef CASE_VFMA_SPLATS
-#undef CASE_VFMA_OPCODE_LMULS
-#undef CASE_VFMA_OPCODE_COMMON
-
-// clang-format off
-#define CASE_WIDEOP_OPCODE_COMMON(OP, LMUL)                                    \
-  RISCV::PseudoV##OP##_##LMUL##_TIED
-
-#define CASE_WIDEOP_OPCODE_LMULS_MF4(OP)                                       \
-  CASE_WIDEOP_OPCODE_COMMON(OP, MF4):                                          \
-  case CASE_WIDEOP_OPCODE_COMMON(OP, MF2):                                     \
-  case CASE_WIDEOP_OPCODE_COMMON(OP, M1):                                      \
-  case CASE_WIDEOP_OPCODE_COMMON(OP, M2):                                      \
-  case CASE_WIDEOP_OPCODE_COMMON(OP, M4)
-
-#define CASE_WIDEOP_OPCODE_LMULS(OP)                                           \
-  CASE_WIDEOP_OPCODE_COMMON(OP, MF8):                                          \
-  case CASE_WIDEOP_OPCODE_LMULS_MF4(OP)
-// clang-format on
 
 #define CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL)                             \
   case RISCV::PseudoV##OP##_##LMUL##_TIED:                                     \
     NewOpc = RISCV::PseudoV##OP##_##LMUL;                                      \
     break;
 
 #define CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP)                                 \
   CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF4)                                    \
   CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2)                                    \
   CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1)                                     \
   CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2)                                     \
   CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4)
 
 #define CASE_WIDEOP_CHANGE_OPCODE_LMULS(OP)                                    \
   CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF8)                                    \
   CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP)
 
 MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI,
                                                     LiveVariables *LV,
                                                     LiveIntervals *LIS) const {
-  switch (MI.getOpcode()) {
+  switch (RISCV::getRVVMCOpcode(MI.getOpcode())) {
   default:
     break;
-  case CASE_WIDEOP_OPCODE_LMULS_MF4(FWADD_WV):
-  case CASE_WIDEOP_OPCODE_LMULS_MF4(FWSUB_WV):
-  case CASE_WIDEOP_OPCODE_LMULS(WADD_WV):
-  case CASE_WIDEOP_OPCODE_LMULS(WADDU_WV):
-  case CASE_WIDEOP_OPCODE_LMULS(WSUB_WV):
-  case CASE_WIDEOP_OPCODE_LMULS(WSUBU_WV): {
+  case RISCV::VFWADD_WV:
+  case RISCV::VFWSUB_WV:
+  case RISCV::VWADD_WV:
+  case RISCV::VWADDU_WV:
+  case RISCV::VWSUB_WV:
+  case RISCV::VWSUBU_WV: {
     // If the tail policy is undisturbed we can't convert.
     assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags) &&
            MI.getNumExplicitOperands() == 6);
     if ((MI.getOperand(5).getImm() & 1) == 0)
       return nullptr;
 
     // clang-format off
     unsigned NewOpc;
MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI,
   }
   }
 
   return nullptr;
 }
 
 #undef CASE_WIDEOP_CHANGE_OPCODE_LMULS
 #undef CASE_WIDEOP_CHANGE_OPCODE_COMMON
-#undef CASE_WIDEOP_OPCODE_LMULS
-#undef CASE_WIDEOP_OPCODE_COMMON
 
 void RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,
                                            MachineBasicBlock &MBB,
                                            MachineBasicBlock::iterator II,
                                            const DebugLoc &DL, Register DestReg,
                                            int64_t Amount,
                                            MachineInstr::MIFlag Flag) const {
   assert(Amount > 0 && "There is no need to get VLEN scaled value.");
bool RISCV::hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2) {
   int16_t MI2FrmOpIdx =
       RISCV::getNamedOperandIdx(MI2.getOpcode(), RISCV::OpName::frm);
   if (MI1FrmOpIdx < 0 || MI2FrmOpIdx < 0)
     return false;
   MachineOperand FrmOp1 = MI1.getOperand(MI1FrmOpIdx);
   MachineOperand FrmOp2 = MI2.getOperand(MI2FrmOpIdx);
   return FrmOp1.getImm() == FrmOp2.getImm();
 }
+
+unsigned RISCV::getRVVMCOpcode(unsigned RVVPseudoOpcode) {
+  const RISCVVPseudosTable::PseudoInfo *RVV =
+      RISCVVPseudosTable::getPseudoInfo(RVVPseudoOpcode);
+  if (!RVV)
+    return 0;
+  return RVV->BaseInstr;
+}