[DAG] Peek through trunc when combining select into shifts.

[deadalnix]

Summary

This fixes a regression in D127115

Depends on D127115

[deadalnix]

This causes a regression in CodeGen/PowerPC/select_const.ll (at least in the no isel case).

[foad]

A trunc can change the value of the shift amount, so how is it correct to peek through it?

[RKSimon]

Yes, we're going to need a KnownBits check to ensure we were truncating away known zero bits

[deadalnix]

Check the truncate doesn't lose information.
Remove the zero extent case as it seems to only regress things.

[RKSimon]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

13255

Please can you move this as an NFC pre-commit and then rebase the patch? Just to show that there are no changes to the logic in isTruncateOf.

[deadalnix]

Rebase on top of an NFC that moves isTruncateOf.

[deadalnix]

Rebase

[deadalnix]

rebase again

[nikic]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

2449

Outdated comment about zext.

2455

isTruncateOf() handles truncates and some kind of weird setcc pattern. Do we need/want that pattern here? Is there test coverage for it?

[deadalnix]

Rebase, add tests for setcc patterns in isTruncateOf.

[deadalnix]

Rebase, ping?

[nikic]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

2460

if (Known.countMaxActiveBits() < Sel.getScalarValueSizeInBits()) or so?

[deadalnix]

Use countMaxActiveBits

[nikic]

LGTM

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue DAGCombiner::foldBinOpIntoSelect(SDNode *BO) {
   // Don't do this unless the old select is going away. We want to eliminate the
   // binary operator, not replace a binop with a select.
   // TODO: Handle ISD::SELECT_CC.
   unsigned SelOpNo = 0;
   SDValue Sel = BO->getOperand(0);
   if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) {
     SelOpNo = 1;
     Sel = BO->getOperand(1);
+
+    // Peek through any trunc/zext to shift amount type.
+    if ((BinOpcode == ISD::SHL || BinOpcode == ISD::SRA ||
+         BinOpcode == ISD::SRL) &&
+        (Sel.getOpcode() == ISD::TRUNCATE ||
+         Sel.getOpcode() == ISD::ZERO_EXTEND) &&
+        Sel.hasOneUse())
+      Sel = Sel.getOperand(0);
   }
 
   if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse())
     return SDValue();
 
   SDValue CT = Sel.getOperand(1);
   if (!isConstantOrConstantVector(CT, true) &&
       !DAG.isConstantFPBuildVectorOrConstantFP(CT))
     return SDValue();
 
   SDValue CF = Sel.getOperand(2);
   if (!isConstantOrConstantVector(CF, true) &&
       !DAG.isConstantFPBuildVectorOrConstantFP(CF))
static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
   else if (isNullOrNullSplat(Op1))
     Op = Op0;
   else
     return false;
 
   Known = DAG.computeKnownBits(Op);
 
   return (Known.Zero | 1).isAllOnes();
 }
 
 /// Given an extending node with a pop-count operand, if the target does not
 /// support a pop-count in the narrow source type but does support it in the
 /// destination type, widen the pop-count to the destination type.
 static SDValue widenCtPop(SDNode *Extend, SelectionDAG &DAG) {
   assert((Extend->getOpcode() == ISD::ZERO_EXTEND ||
           Extend->getOpcode() == ISD::ANY_EXTEND) && "Expected extend op");
 

llvm/test/CodeGen/X86/dagcombine-select.ll

; CHECK-NEXT:    retq
   %sel = select i1 %cond, i32 2, i32 3
   %bo = shl i32 %sel, 8
   ret i32 %bo
 }
 
 define i32 @shl_constant_sel_constants(i1 %cond) {
 ; CHECK-LABEL: shl_constant_sel_constants:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movl %edi, %ecx
-; CHECK-NEXT:    andb $1, %cl
-; CHECK-NEXT:    xorb $3, %cl
-; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    # kill: def $cl killed $cl killed $ecx
-; CHECK-NEXT:    shll %cl, %eax
+; CHECK-NEXT:    notb %dil
+; CHECK-NEXT:    movzbl %dil, %eax
+; CHECK-NEXT:    andl $1, %eax
+; CHECK-NEXT:    leal 4(,%rax,4), %eax
 ; CHECK-NEXT:    retq
   %sel = select i1 %cond, i32 2, i32 3
   %bo = shl i32 1, %sel
   ret i32 %bo
 }
 
 define i32 @lshr_constant_sel_constants(i1 %cond) {
 ; CHECK-LABEL: lshr_constant_sel_constants:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movl %edi, %ecx
-; CHECK-NEXT:    andb $1, %cl
-; CHECK-NEXT:    xorb $3, %cl
-; CHECK-NEXT:    movl $64, %eax
-; CHECK-NEXT:    # kill: def $cl killed $cl killed $ecx
-; CHECK-NEXT:    shrl %cl, %eax
+; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT:    andl $1, %edi
+; CHECK-NEXT:    leal 8(,%rdi,8), %eax
 ; CHECK-NEXT:    retq
   %sel = select i1 %cond, i32 2, i32 3
   %bo = lshr i32 64, %sel
   ret i32 %bo
 }
 
 define i32 @ashr_constant_sel_constants(i1 %cond) {
 ; CHECK-LABEL: ashr_constant_sel_constants:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movl %edi, %ecx
-; CHECK-NEXT:    andb $1, %cl
-; CHECK-NEXT:    xorb $3, %cl
-; CHECK-NEXT:    movl $128, %eax
-; CHECK-NEXT:    # kill: def $cl killed $cl killed $ecx
-; CHECK-NEXT:    shrl %cl, %eax
+; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT:    andl $1, %edi
+; CHECK-NEXT:    shll $4, %edi
+; CHECK-NEXT:    leal 16(%rdi), %eax
 ; CHECK-NEXT:    retq
   %sel = select i1 %cond, i32 2, i32 3
   %bo = ashr i32 128, %sel
   ret i32 %bo
 }
 
 define double @fsub_constant_sel_constants(i1 %cond) {
 ; CHECK-LABEL: fsub_constant_sel_constants: