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| Differential D151898
[RISCV] Guard Advance Interrupt Architecture CSRs with Smaia and Ssaia extensions. AbandonedPublic Authored by garvitgupta08 on Jun 1 2023, 9:30 AM.
Details
Summary Smaia and Ssaia extension for advance interrupt architecture CSRs are added in This patch adds the same because these CSRs should be recognized by name when
Diff Detail
Event TimelineComment Actions I don't think we want to do this. There's precedent for making all CSRs always visible, and it does little harm to expose them. Requiring OSes to specify -march=ssfoo_ssbar_ssbaz_... to do anything useful is just a waste of everyone's time IMO, and often wrong because OSes don't want to require those extensions, they just want to support them if present, so then you instead have to .option arch, +ssfoo all over the place. Or people will just use the numeric values instead of the names, which then makes the code less readable. This revision now requires changes to proceed.Jun 1 2023, 12:10 PM Comment Actions
ok, I was not aware if this was done intentionally. But as you said, exposing all of them (especially the ones which are still in experimental stage) does harm because the same encodings are used by other CSRs. For eg. - miselect and mireg CSR in Advanced interrupt Architecture has the same encoding as of the mnscratch and mnepc CSR respectively in Sifive S76-MC. Therefore guarding CSRs which are in experimental stage will allow other CSRs with same encodings to be there until one of them is fully supported by community. Comment Actions I tend to think the same way as @jrtc27 on gating CSRs. The overlapping encodings is a good point but I'm not sure it changes things radically - it just means you have an additional alias for a given CSR number which seems unlikey to be something you'd stumble into accidentally. Comment Actions Thanks for the review asb and jrtc27. Let me think more on how to handle this in a better way so that we can have multiple csrs with different functionality but with same encodings.
Revision Contents
Diff 527458 llvm/lib/Target/RISCV/RISCVSystemOperands.td
llvm/test/MC/RISCV/hypervisor-csr-names.s
llvm/test/MC/RISCV/machine-csr-names.s
llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
llvm/test/MC/RISCV/rv32-machine-csr-names.s
llvm/test/MC/RISCV/rv32-supervisor-csr-names.s
llvm/test/MC/RISCV/rvi-aliases-valid.s
llvm/test/MC/RISCV/supervisor-csr-names.s
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