[AMDGPU][AsmParser][NFC] Simplify the EndpgmImm operand definition.

[kosarev]

Summary

Clears the road to eliminating custom default operand handlers. Also
unifies naming of related entities.

Part of https://github.com/llvm/llvm-project/issues/62629.

[kosarev]

But maybe we should just rename EndpgmImm to Endpgm instead (and then eventually do the same for the other *Imm operands)?

[kosarev]

Removed the Imm suffix. Endpgm doesn't look any different from other
operands of this kind, so maybe let's be consistent (and concise).

[arsenm]

llvm/lib/Target/AMDGPU/SIInstrInfo.td

1026

IIRC endpgm was special to avoid printing it because it's not real and was used for some tooling hack?

[kosarev]

llvm/lib/Target/AMDGPU/SIInstrInfo.td

1026

Yes, we don't print it when it's 0. I guess it might be useful to keep s_endpgm reassemblable when the operand happens to be non-zero, whatever the reason for that might be.

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

void cvtSDWA(MCInst &Inst, const OperandVector &Operands,
                uint64_t BasicInstType,
                bool SkipDstVcc = false,
                bool SkipSrcVcc = false);
 
   AMDGPUOperand::Ptr defaultBLGP() const;
   AMDGPUOperand::Ptr defaultCBSZ() const;
   AMDGPUOperand::Ptr defaultABID() const;
 
-  OperandMatchResultTy parseEndpgmOp(OperandVector &Operands);
-  AMDGPUOperand::Ptr defaultEndpgmImmOperands() const;
+  OperandMatchResultTy parseEndpgm(OperandVector &Operands);
+  AMDGPUOperand::Ptr defaultEndpgm() const;
 
   AMDGPUOperand::Ptr defaultWaitVDST() const;
   AMDGPUOperand::Ptr defaultWaitEXP() const;
   OperandMatchResultTy parseVOPD(OperandVector &Operands);
 };
 
 } // end anonymous namespace
 
Operands.push_back(
     AMDGPUOperand::CreateImm(this, Val, S, AMDGPUOperand::ImmTyDppCtrl));
   return MatchOperand_Success;
 }
 
 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultDppRowMask() const {
   return AMDGPUOperand::CreateImm(this, 0xf, SMLoc(), AMDGPUOperand::ImmTyDppRowMask);
 }
 
-AMDGPUOperand::Ptr AMDGPUAsmParser::defaultEndpgmImmOperands() const {
+AMDGPUOperand::Ptr AMDGPUAsmParser::defaultEndpgm() const {
   return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyEndpgm);
 }
 
 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultDppBankMask() const {
   return AMDGPUOperand::CreateImm(this, 0xf, SMLoc(), AMDGPUOperand::ImmTyDppBankMask);
 }
 
 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultDppBoundCtrl() const {
default:
     return Match_InvalidOperand;
   }
 }
 
 //===----------------------------------------------------------------------===//
 // endpgm
 //===----------------------------------------------------------------------===//
 
-OperandMatchResultTy AMDGPUAsmParser::parseEndpgmOp(OperandVector &Operands) {
+OperandMatchResultTy AMDGPUAsmParser::parseEndpgm(OperandVector &Operands) {
   SMLoc S = getLoc();
   int64_t Imm = 0;
 
   if (!parseExpr(Imm)) {
     // The operand is optional, if not present default to 0
     Imm = 0;
   }
 

llvm/lib/Target/AMDGPU/SIInstrInfo.td

 def SwizzleMatchClass : AsmOperandClass {
   let Name = "Swizzle";
   let PredicateMethod = "isSwizzle";
   let ParserMethod = "parseSwizzleOp";
   let RenderMethod = "addImmOperands";
   let IsOptional = 1;
 }
 
-def EndpgmMatchClass : AsmOperandClass {
-  let Name = "EndpgmImm";
-  let PredicateMethod = "isEndpgm";
-  let ParserMethod = "parseEndpgmOp";
-  let RenderMethod = "addImmOperands";
-  let IsOptional = 1;
-}
-
 def SWaitMatchClass : AsmOperandClass {
   let Name = "SWaitCnt";
   let RenderMethod = "addImmOperands";
   let ParserMethod = "parseSWaitCntOps";
 }
 
 def DepCtrMatchClass : AsmOperandClass {
   let Name = "DepCtr";
def SendMsgImm : Operand<i32> {
   let ParserMatchClass = SendMsgMatchClass;
 }
 
 def SwizzleImm : Operand<i16> {
   let PrintMethod = "printSwizzle";
   let ParserMatchClass = SwizzleMatchClass;
 }
 
-def EndpgmImm : Operand<i16> {
-  let PrintMethod = "printEndpgm";
-  let ParserMatchClass = EndpgmMatchClass;
-}
+def Endpgm : CustomOperand<i16, 1>;
 
 def WAIT_FLAG : Operand <i32> {
   let ParserMatchClass = SWaitMatchClass;
   let PrintMethod = "printWaitFlag";
 }
 
 def DepCtrImm : Operand <i32> {
   let ParserMatchClass = DepCtrMatchClass;

llvm/lib/Target/AMDGPU/SOPInstructions.td

multiclass SOPP_With_Relaxation <string opName, dag ins,
                   string asmOps, list<dag> pattern=[]> {
   def "" : SOPP_Pseudo <opName, ins, asmOps, pattern>;
   def _pad_s_nop : SOPP_Pseudo <opName # "_pad_s_nop", ins, asmOps, pattern, " ", opName>;
 }
 
 def S_NOP : SOPP_Pseudo<"s_nop" , (ins i16imm:$simm16), "$simm16">;
 
 let isTerminator = 1 in {
-def S_ENDPGM : SOPP_Pseudo<"s_endpgm", (ins EndpgmImm:$simm16), "$simm16", [], ""> {
+def S_ENDPGM : SOPP_Pseudo<"s_endpgm", (ins Endpgm:$simm16), "$simm16", [], ""> {
   let isBarrier = 1;
   let isReturn = 1;
   let hasSideEffects = 1;
 }
 
 def S_ENDPGM_SAVED : SOPP_Pseudo<"s_endpgm_saved", (ins)> {
   let SubtargetPredicate = isGFX8Plus;
   let simm16 = 0;