MachineCombiner: use height in improvesCriticialPathLen()

[artagnon]

Summary

improvesCriticialPathLen() currently has an early-exit on
CombinerObjective::MustReduceDepth introduced in 766589ef (add
'MustReduceDepth' as an objective/cost-metric for the MachineCombiner),
by only considering transforms that would reduce the root depth.
However, the patch was introduced because MachineCombiner's use of
MachineTraceMetrics was incomplete, as noted in the Phabricator
discussion. This patch attempts to make better use of
MachineTraceMetrics in MachineCombiner, by also computing instruction
heights, and asserting that the critical path length = depth + slack +
height. We then unify the cost model in improvesCriticalPathLen(), since
there are only two essential differences between the MustReduceDepth
case and the other case: the MustReduceDepth case doesn't want to
consider slack, and wants to be more conservative with respect to the
cost comparison.

[artagnon]

This patch gives us improvements on standard benchmarks like Embench.

A couple of things to note:

• I need some help with the height calculation, as it is wrong in some places.
• I've only updated the RISC-V tests. Will update tests for other architectures, once the patch is closer to final form.

[shiva0217]

llvm/lib/CodeGen/MachineCombiner.cpp

265

Should it go through all users as following?

for (MachineInstr &UseInstr : MRI->use_instructions(MO.getReg())) {

[shiva0217]

Theoretically, NewRootHeight and OldRootHeight should be equal.
Does it make sense to remove the Heights calculations?

llvm/lib/CodeGen/MachineCombiner.cpp

269

In MachineTraceMetrics::Ensemble::computeInstrHeights function, Loop header PHI heights are all 0.

It seems it could be addressed by defining.

unsigned
MachineTraceMetrics::Trace::getPHIHeight(const MachineInstr &PHI) const{
  // Loop header PHI heights are all 0.
  return TBI.Succ ? getInstrCycles(PHI).Height : 0;
}

[artagnon]

In D150664#4348803, @shiva0217 wrote:

Theoretically, NewRootHeight and OldRootHeight should be equal.

You're absolutely right; I'll try to explain the improvements I'm seeing, and re-think this patch.

llvm/include/llvm/CodeGen/MachineTraceMetrics.h

public:
   /// InstrCycles represents the cycle height and depth of an instruction in a
   /// trace.
   struct InstrCycles {
     /// Earliest issue cycle as determined by data dependencies and instruction
     /// latencies from the beginning of the trace. Data dependencies from
     /// before the trace are not included.
     unsigned Depth;
 
-    /// Minimum number of cycles from this instruction is issued to the of the
-    /// trace, as determined by data dependencies and instruction latencies.
+    /// Minimum number of cycles from this instruction is issued to the end of
+    /// the trace, as determined by data dependencies and instruction latencies.
     unsigned Height;
   };
 
   /// A trace represents a plausible sequence of executed basic blocks that
   /// passes through the current basic block one. The Trace class serves as a
   /// handle to internal cached data structures.
   class Trace {
     Ensemble &TE;

llvm/lib/CodeGen/MachineCombiner.cpp

public:
   void getAnalysisUsage(AnalysisUsage &AU) const override;
   bool runOnMachineFunction(MachineFunction &MF) override;
   StringRef getPassName() const override { return "Machine InstCombiner"; }
 
 private:
   bool combineInstructions(MachineBasicBlock *);
   MachineInstr *getOperandDef(const MachineOperand &MO);
   bool isTransientMI(const MachineInstr *MI);
-  unsigned getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
-                    DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
-                    MachineTraceMetrics::Trace BlockTrace,
-                    const MachineBasicBlock &MBB);
+  std::pair<unsigned, unsigned>
+  getInstrCycles(SmallVectorImpl<MachineInstr *> &InsInstrs,
   unsigned getLatency(MachineInstr *Root, MachineInstr *NewRoot,
                       MachineTraceMetrics::Trace BlockTrace);
   bool
   improvesCriticalPathLen(MachineBasicBlock *MBB, MachineInstr *Root,
                           MachineTraceMetrics::Trace BlockTrace,
                           SmallVectorImpl<MachineInstr *> &InsInstrs,
                           SmallVectorImpl<MachineInstr *> &DelInstrs,
                           DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
void MachineCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.addPreserved<MachineLoopInfo>();
   AU.addRequired<MachineTraceMetrics>();
   AU.addPreserved<MachineTraceMetrics>();
   AU.addRequired<LazyMachineBlockFrequencyInfoPass>();
   AU.addRequired<ProfileSummaryInfoWrapperPass>();
   MachineFunctionPass::getAnalysisUsage(AU);
 }
 
-MachineInstr *
-MachineCombiner::getOperandDef(const MachineOperand &MO) {
-  MachineInstr *DefInstr = nullptr;
+MachineInstr *MachineCombiner::getOperandDef(const MachineOperand &MO) {
   // We need a virtual register definition.
-  if (MO.isReg() && MO.getReg().isVirtual())
-    DefInstr = MRI->getUniqueVRegDef(MO.getReg());
-  // PHI's have no depth etc.
-  if (DefInstr && DefInstr->isPHI())
-    DefInstr = nullptr;
-  return DefInstr;
+  if (!(MO.isReg() && MO.getReg().isVirtual()))
+    return nullptr;
+  return MRI->getUniqueVRegDef(MO.getReg());
 }
 
 /// Return true if MI is unlikely to generate an actual target instruction.
 bool MachineCombiner::isTransientMI(const MachineInstr *MI) {
   if (!MI->isCopy())
     return MI->isTransient();
 
   // If MI is a COPY, check if its src and dst registers can be coalesced.
bool MachineCombiner::isTransientMI(const MachineInstr *MI) {
   if (Src.isVirtual())
     std::swap(Src, Dst);
 
   // Now Src is physical register, Dst is virtual register.
   auto DstRC = MRI->getRegClass(Dst);
   return DstRC->contains(Src);
 }
 
-/// Computes depth of instructions in vector \InsInstr.
+/// Computes depth and height of the last instruction in \InsInstr.
 ///
 /// \param InsInstrs is a vector of machine instructions
 /// \param InstrIdxForVirtReg is a dense map of virtual register to index
 /// of defining machine instruction in \p InsInstrs
 /// \param BlockTrace is a trace of machine instructions
 ///
 /// \returns Depth of last instruction in \InsInstrs ("NewRoot")
-unsigned
-MachineCombiner::getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
-                          DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
-                          MachineTraceMetrics::Trace BlockTrace,
-                          const MachineBasicBlock &MBB) {
+std::pair<unsigned, unsigned> MachineCombiner::getInstrCycles(
+    SmallVectorImpl<MachineInstr *> &InsInstrs,
+    MachineTraceMetrics::Trace BlockTrace, const MachineBasicBlock &MBB) {
   SmallVector<unsigned, 16> InstrDepth;
   // For each instruction in the new sequence compute the depth based on the
   // operands. Use the trace information when possible. For new operands which
   // are tracked in the InstrIdxForVirtReg map depth is looked up in InstrDepth
   for (auto *InstrPtr : InsInstrs) { // for each Use
     unsigned IDepth = 0;
-    for (const MachineOperand &MO : InstrPtr->operands()) {
+    for (const MachineOperand &MO : InstrPtr->uses()) {
       // Check for virtual register operand.
       if (!(MO.isReg() && MO.getReg().isVirtual()))
         continue;
-      if (!MO.isUse())
-        continue;
       unsigned DepthOp = 0;
       unsigned LatencyOp = 0;
       DenseMap<unsigned, unsigned>::iterator II =
           InstrIdxForVirtReg.find(MO.getReg());
       if (II != InstrIdxForVirtReg.end()) {
         // Operand is new virtual register not in trace
         assert(II->second < InstrDepth.size() && "Bad Index");
         MachineInstr *DefInstr = InsInstrs[II->second];
         assert(DefInstr &&
                "There must be a definition for a new virtual register");
         DepthOp = InstrDepth[II->second];
         int DefIdx = DefInstr->findRegisterDefOperandIdx(MO.getReg());
         int UseIdx = InstrPtr->findRegisterUseOperandIdx(MO.getReg());
         LatencyOp = TSchedModel.computeOperandLatency(DefInstr, DefIdx,
                                                       InstrPtr, UseIdx);
       } else {
         MachineInstr *DefInstr = getOperandDef(MO);
         if (DefInstr && (TII->getMachineCombinerTraceStrategy() !=
                              MachineTraceStrategy::TS_Local ||
                          DefInstr->getParent() == &MBB)) {
           DepthOp = BlockTrace.getInstrCycles(*DefInstr).Depth;
-          if (!isTransientMI(DefInstr))
-            LatencyOp = TSchedModel.computeOperandLatency(
-                DefInstr, DefInstr->findRegisterDefOperandIdx(MO.getReg()),
-                InstrPtr, InstrPtr->findRegisterUseOperandIdx(MO.getReg()));
+          if (!isTransientMI(DefInstr)) {
+            int DefIdx = DefInstr->findRegisterDefOperandIdx(MO.getReg());
+            int UseIdx = InstrPtr->findRegisterUseOperandIdx(MO.getReg());
+            LatencyOp = TSchedModel.computeOperandLatency(DefInstr, DefIdx,
+                                                          InstrPtr, UseIdx);
+          }
         }
       }
       IDepth = std::max(IDepth, DepthOp + LatencyOp);
     }
     InstrDepth.push_back(IDepth);
   }
+  // Compute the height of the last instruction based on the operands, using
+  // trace information.
   unsigned NewRootIdx = InsInstrs.size() - 1;
-  return InstrDepth[NewRootIdx];
+  auto *DefInstr = InsInstrs[NewRootIdx];
+  unsigned IHeight = 0;
+  for (const MachineOperand &MO : DefInstr->defs()) {
+    // Check for virtual register operand.
+    if (!(MO.isReg() && MO.getReg().isVirtual()))
+      continue;
+    unsigned HeightOp = 0;
+    unsigned LatencyOp = 0;
+
+    // Get the first instruction that uses MO
+    MachineRegisterInfo::use_iterator UI = MRI->use_begin(MO.getReg());
+    if (UI == MRI->use_end())
+      continue;
+    MachineInstr *UseInstr = UI->getParent();
+    HeightOp = BlockTrace.getInstrCycles(*UseInstr).Height;
+    int DefIdx = DefInstr->findRegisterDefOperandIdx(MO.getReg());
+    int UseIdx = UseInstr->findRegisterUseOperandIdx(MO.getReg());
+    LatencyOp =
+        TSchedModel.computeOperandLatency(DefInstr, DefIdx, UseInstr, UseIdx);
+    IHeight = std::max(IHeight, HeightOp + LatencyOp);
+  }
+  return {InstrDepth[NewRootIdx], IHeight};
 }
 
 /// Computes instruction latency as max of latency of defined operands.
 ///
 /// \param Root is a machine instruction that could be replaced by NewRoot.
 /// It is used to compute a more accurate latency information for NewRoot in
 /// case there is a dependent instruction in the same trace (\p BlockTrace)
 /// \param NewRoot is the instruction for which the latency is computed

 /// path. The definition of "improve" may be restricted by specifying that the
 /// new path improves the data dependency chain (MustReduceDepth).
 bool MachineCombiner::improvesCriticalPathLen(
     MachineBasicBlock *MBB, MachineInstr *Root,
     MachineTraceMetrics::Trace BlockTrace,
     SmallVectorImpl<MachineInstr *> &InsInstrs,
     SmallVectorImpl<MachineInstr *> &DelInstrs,
     DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
-    MachineCombinerPattern Pattern,
-    bool SlackIsAccurate) {
-  // Get depth and latency of NewRoot and Root.
-  unsigned NewRootDepth =
-      getDepth(InsInstrs, InstrIdxForVirtReg, BlockTrace, *MBB);
-  unsigned RootDepth = BlockTrace.getInstrCycles(*Root).Depth;
-
-  LLVM_DEBUG(dbgs() << "  Dependence data for " << *Root << "\tNewRootDepth: "
-                    << NewRootDepth << "\tRootDepth: " << RootDepth);
+    MachineCombinerPattern Pattern, bool SlackIsAccurate) {
+  LLVM_DEBUG(dbgs() << "  Dependence data for " << *Root);
 
-  // For a transform such as reassociation, the cost equation is
-  // conservatively calculated so that we must improve the depth (data
-  // dependency cycles) in the critical path to proceed with the transform.
-  // Being conservative also protects against inaccuracies in the underlying
-  // machine trace metrics and CPU models.
-  if (getCombinerObjective(Pattern) == CombinerObjective::MustReduceDepth) {
-    LLVM_DEBUG(dbgs() << "\tIt MustReduceDepth ");
-    LLVM_DEBUG(NewRootDepth < RootDepth
-                   ? dbgs() << "\t  and it does it\n"
-                   : dbgs() << "\t  but it does NOT do it\n");
-    return NewRootDepth < RootDepth;
-  }
-
-  // A more flexible cost calculation for the critical path includes the slack
-  // of the original code sequence. This may allow the transform to proceed
-  // even if the instruction depths (data dependency cycles) become worse.
-
-  // Account for the latency of the inserted and deleted instructions by
-  unsigned NewRootLatency, RootLatency;
-  if (TII->accumulateInstrSeqToRootLatency(*Root)) {
-    std::tie(NewRootLatency, RootLatency) =
-        getLatenciesForInstrSequences(*Root, InsInstrs, DelInstrs, BlockTrace);
-  } else {
-    NewRootLatency = TSchedModel.computeInstrLatency(InsInstrs.back());
-    RootLatency = TSchedModel.computeInstrLatency(Root);
-  }
+  // Compute depths and heights of Root and NewRoot from the BlockTrace.
+  unsigned RootDepth = BlockTrace.getInstrCycles(*Root).Depth;
+  unsigned RootHeight = BlockTrace.getInstrCycles(*Root).Height;
+  unsigned NewRootDepth, NewRootHeight;
+  std::tie(NewRootDepth, NewRootHeight) =
+      getInstrCycles(InsInstrs, InstrIdxForVirtReg, BlockTrace, *MBB);
+
+  // For a transform such as reassociation, the cost equation is conservatively
+  // calculated so that we must improve the the critical path length to proceed
+  // with the transform. Being conservative also protects against inaccuracies
+  // in the underlying machine trace metrics and CPU models.
+  bool MustReduceDepth =
+      (getCombinerObjective(Pattern) == CombinerObjective::MustReduceDepth);
 
   unsigned RootSlack = BlockTrace.getInstrSlack(*Root);
-  unsigned NewCycleCount = NewRootDepth + NewRootLatency;
-  unsigned OldCycleCount =
-      RootDepth + RootLatency + (SlackIsAccurate ? RootSlack : 0);
-  LLVM_DEBUG(dbgs() << "\n\tNewRootLatency: " << NewRootLatency
-                    << "\tRootLatency: " << RootLatency << "\n\tRootSlack: "
-                    << RootSlack << " SlackIsAccurate=" << SlackIsAccurate
-                    << "\n\tNewRootDepth + NewRootLatency = " << NewCycleCount
-                    << "\n\tRootDepth + RootLatency + RootSlack = "
-                    << OldCycleCount;);
-  LLVM_DEBUG(NewCycleCount <= OldCycleCount
-                 ? dbgs() << "\n\t  It IMPROVES PathLen because"
-                 : dbgs() << "\n\t  It DOES NOT improve PathLen because");
-  LLVM_DEBUG(dbgs() << "\n\t\tNewCycleCount = " << NewCycleCount
-                    << ", OldCycleCount = " << OldCycleCount << "\n");
-
-  return NewCycleCount <= OldCycleCount;
+  unsigned CriticalPath = RootDepth + RootHeight +
+                          (SlackIsAccurate && !MustReduceDepth ? RootSlack : 0);
+  unsigned NewCriticalPath = NewRootDepth + NewRootHeight;
+  bool ReducesCriticalPathLen = MustReduceDepth
+                                    ? NewCriticalPath < CriticalPath
+                                    : NewCriticalPath <= CriticalPath;
+  LLVM_DEBUG(dbgs() << "\tNewRootDepth: " << NewRootDepth << ", OldRootDepth: "
+                    << RootDepth << "\n\tNewRootHeight: " << NewRootHeight
+                    << ", OldRootHeight: " << RootHeight
+                    << "\tRootSlack: " << RootSlack);
+  LLVM_DEBUG(
+      ReducesCriticalPathLen
+          ? dbgs() << "\n\t  It IMPROVES Critical PathLen because"
+          : dbgs() << "\n\t  It DOES NOT improve Critical PathLen because");
+  LLVM_DEBUG(dbgs() << "\n\t\tNewCriticalPath = " << NewCriticalPath
+                    << ", OldCriticalPath = " << CriticalPath << "\n");
+  return ReducesCriticalPathLen;
 }
 
 /// helper routine to convert instructions into SC
 void MachineCombiner::instr2instrSC(
     SmallVectorImpl<MachineInstr *> &Instrs,
     SmallVectorImpl<const MCSchedClassDesc *> &InstrsSC) {
   for (auto *InstrPtr : Instrs) {
     unsigned Opc = InstrPtr->getOpcode();

llvm/test/CodeGen/RISCV/addcarry.ll

 ; RISCV32-NEXT:    mul a4, a1, a2
 ; RISCV32-NEXT:    add a4, a6, a4
 ; RISCV32-NEXT:    sltu a7, a4, a6
 ; RISCV32-NEXT:    sltu a5, a6, a5
 ; RISCV32-NEXT:    mulhu a6, a0, a3
 ; RISCV32-NEXT:    mulhu t0, a1, a2
 ; RISCV32-NEXT:    add a6, a6, t0
 ; RISCV32-NEXT:    add a5, a6, a5
-; RISCV32-NEXT:    add a5, a5, a7
 ; RISCV32-NEXT:    mul a6, a1, a3
+; RISCV32-NEXT:    add a6, a7, a6
 ; RISCV32-NEXT:    add a5, a5, a6
 ; RISCV32-NEXT:    bgez a1, .LBB0_2
 ; RISCV32-NEXT:  # %bb.1:
 ; RISCV32-NEXT:    sub a5, a5, a2
 ; RISCV32-NEXT:  .LBB0_2:
 ; RISCV32-NEXT:    bgez a3, .LBB0_4
 ; RISCV32-NEXT:  # %bb.3:
 ; RISCV32-NEXT:    sub a5, a5, a0

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll

 ; LMULMAX8RV64-NEXT:    and a1, a1, a2
 ; LMULMAX8RV64-NEXT:    vslidedown.vi v8, v9, 1
 ; LMULMAX8RV64-NEXT:    vmv.x.s a3, v8
 ; LMULMAX8RV64-NEXT:    and a2, a3, a2
 ; LMULMAX8RV64-NEXT:    slli a2, a2, 15
 ; LMULMAX8RV64-NEXT:    vslidedown.vi v8, v9, 2
 ; LMULMAX8RV64-NEXT:    vmv.x.s a3, v8
 ; LMULMAX8RV64-NEXT:    slli a3, a3, 30
-; LMULMAX8RV64-NEXT:    or a1, a1, a3
+; LMULMAX8RV64-NEXT:    or a2, a2, a3
 ; LMULMAX8RV64-NEXT:    or a1, a1, a2
 ; LMULMAX8RV64-NEXT:    sw a1, 0(a0)
 ; LMULMAX8RV64-NEXT:    slli a1, a1, 19
 ; LMULMAX8RV64-NEXT:    srli a1, a1, 51
 ; LMULMAX8RV64-NEXT:    sh a1, 4(a0)
 ; LMULMAX8RV64-NEXT:    ret
 ;
 ; LMULMAX1RV32-LABEL: fp2si_v3f32_v3i15:

 ; LMULMAX1RV64-NEXT:    and a1, a1, a2
 ; LMULMAX1RV64-NEXT:    vslidedown.vi v8, v9, 1
 ; LMULMAX1RV64-NEXT:    vmv.x.s a3, v8
 ; LMULMAX1RV64-NEXT:    and a2, a3, a2
 ; LMULMAX1RV64-NEXT:    slli a2, a2, 15
 ; LMULMAX1RV64-NEXT:    vslidedown.vi v8, v9, 2
 ; LMULMAX1RV64-NEXT:    vmv.x.s a3, v8
 ; LMULMAX1RV64-NEXT:    slli a3, a3, 30
-; LMULMAX1RV64-NEXT:    or a1, a1, a3
+; LMULMAX1RV64-NEXT:    or a2, a2, a3
 ; LMULMAX1RV64-NEXT:    or a1, a1, a2
 ; LMULMAX1RV64-NEXT:    sw a1, 0(a0)
 ; LMULMAX1RV64-NEXT:    slli a1, a1, 19
 ; LMULMAX1RV64-NEXT:    srli a1, a1, 51
 ; LMULMAX1RV64-NEXT:    sh a1, 4(a0)
 ; LMULMAX1RV64-NEXT:    ret
   %z = fptosi <3 x float> %x to <3 x i15>
   ret <3 x i15> %z

 ; LMULMAX8RV64-NEXT:    and a1, a1, a2
 ; LMULMAX8RV64-NEXT:    vslidedown.vi v8, v9, 1
 ; LMULMAX8RV64-NEXT:    vmv.x.s a3, v8
 ; LMULMAX8RV64-NEXT:    and a2, a3, a2
 ; LMULMAX8RV64-NEXT:    slli a2, a2, 15
 ; LMULMAX8RV64-NEXT:    vslidedown.vi v8, v9, 2
 ; LMULMAX8RV64-NEXT:    vmv.x.s a3, v8
 ; LMULMAX8RV64-NEXT:    slli a3, a3, 30
-; LMULMAX8RV64-NEXT:    or a1, a1, a3
+; LMULMAX8RV64-NEXT:    or a2, a2, a3
 ; LMULMAX8RV64-NEXT:    or a1, a1, a2
 ; LMULMAX8RV64-NEXT:    sw a1, 0(a0)
 ; LMULMAX8RV64-NEXT:    slli a1, a1, 19
 ; LMULMAX8RV64-NEXT:    srli a1, a1, 51
 ; LMULMAX8RV64-NEXT:    sh a1, 4(a0)
 ; LMULMAX8RV64-NEXT:    ret
 ;
 ; LMULMAX1RV32-LABEL: fp2ui_v3f32_v3i15:

 ; LMULMAX1RV64-NEXT:    and a1, a1, a2
 ; LMULMAX1RV64-NEXT:    vslidedown.vi v8, v9, 1
 ; LMULMAX1RV64-NEXT:    vmv.x.s a3, v8
 ; LMULMAX1RV64-NEXT:    and a2, a3, a2
 ; LMULMAX1RV64-NEXT:    slli a2, a2, 15
 ; LMULMAX1RV64-NEXT:    vslidedown.vi v8, v9, 2
 ; LMULMAX1RV64-NEXT:    vmv.x.s a3, v8
 ; LMULMAX1RV64-NEXT:    slli a3, a3, 30
-; LMULMAX1RV64-NEXT:    or a1, a1, a3
+; LMULMAX1RV64-NEXT:    or a2, a2, a3
 ; LMULMAX1RV64-NEXT:    or a1, a1, a2
 ; LMULMAX1RV64-NEXT:    sw a1, 0(a0)
 ; LMULMAX1RV64-NEXT:    slli a1, a1, 19
 ; LMULMAX1RV64-NEXT:    srli a1, a1, 51
 ; LMULMAX1RV64-NEXT:    sh a1, 4(a0)
 ; LMULMAX1RV64-NEXT:    ret
   %z = fptoui <3 x float> %x to <3 x i15>
   ret <3 x i15> %z

llvm/test/CodeGen/RISCV/sadd_sat.ll

; RV64IZbb-NEXT:    ret
   ret i32 %tmp;
 }
 
 define i64 @func2(i64 %x, i64 %y) nounwind {
 ; RV32I-LABEL: func2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a4, a1
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    add a5, a4, a3
 ; RV32I-NEXT:    add a0, a0, a2
 ; RV32I-NEXT:    sltu a1, a0, a1
-; RV32I-NEXT:    add a1, a5, a1
+; RV32I-NEXT:    add a1, a3, a1
+; RV32I-NEXT:    add a1, a4, a1
 ; RV32I-NEXT:    xor a2, a4, a1
 ; RV32I-NEXT:    xor a3, a4, a3
 ; RV32I-NEXT:    not a3, a3
 ; RV32I-NEXT:    and a2, a3, a2
 ; RV32I-NEXT:    bgez a2, .LBB1_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    srai a0, a1, 31
 ; RV32I-NEXT:    lui a1, 524288

 ; RV64-NEXT:    xor a0, a0, a1
 ; RV64-NEXT:  .LBB1_2:
 ; RV64-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func2:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    mv a4, a1
 ; RV32IZbb-NEXT:    mv a1, a0
-; RV32IZbb-NEXT:    add a5, a4, a3
 ; RV32IZbb-NEXT:    add a0, a0, a2
 ; RV32IZbb-NEXT:    sltu a1, a0, a1
-; RV32IZbb-NEXT:    add a1, a5, a1
+; RV32IZbb-NEXT:    add a1, a3, a1
+; RV32IZbb-NEXT:    add a1, a4, a1
 ; RV32IZbb-NEXT:    xor a2, a4, a1
 ; RV32IZbb-NEXT:    xor a3, a4, a3
 ; RV32IZbb-NEXT:    andn a2, a2, a3
 ; RV32IZbb-NEXT:    bgez a2, .LBB1_2
 ; RV32IZbb-NEXT:  # %bb.1:
 ; RV32IZbb-NEXT:    srai a0, a1, 31
 ; RV32IZbb-NEXT:    lui a1, 524288
 ; RV32IZbb-NEXT:    xor a1, a0, a1

llvm/test/CodeGen/RISCV/sadd_sat_plus.ll

; RV64IZbb-NEXT:    ret
   ret i32 %tmp
 }
 
 define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
 ; RV32I-LABEL: func64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a2, a1
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    add a3, a2, a5
 ; RV32I-NEXT:    add a0, a0, a4
 ; RV32I-NEXT:    sltu a1, a0, a1
-; RV32I-NEXT:    add a1, a3, a1
+; RV32I-NEXT:    add a1, a5, a1
+; RV32I-NEXT:    add a1, a2, a1
 ; RV32I-NEXT:    xor a3, a2, a1
 ; RV32I-NEXT:    xor a2, a2, a5
 ; RV32I-NEXT:    not a2, a2
 ; RV32I-NEXT:    and a2, a2, a3
 ; RV32I-NEXT:    bgez a2, .LBB1_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    srai a0, a1, 31
 ; RV32I-NEXT:    lui a1, 524288

 ; RV64-NEXT:    xor a0, a0, a1
 ; RV64-NEXT:  .LBB1_2:
 ; RV64-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func64:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    mv a2, a1
 ; RV32IZbb-NEXT:    mv a1, a0
-; RV32IZbb-NEXT:    add a3, a2, a5
 ; RV32IZbb-NEXT:    add a0, a0, a4
 ; RV32IZbb-NEXT:    sltu a1, a0, a1
-; RV32IZbb-NEXT:    add a1, a3, a1
+; RV32IZbb-NEXT:    add a1, a5, a1
+; RV32IZbb-NEXT:    add a1, a2, a1
 ; RV32IZbb-NEXT:    xor a3, a2, a1
 ; RV32IZbb-NEXT:    xor a2, a2, a5
 ; RV32IZbb-NEXT:    andn a2, a3, a2
 ; RV32IZbb-NEXT:    bgez a2, .LBB1_2
 ; RV32IZbb-NEXT:  # %bb.1:
 ; RV32IZbb-NEXT:    srai a0, a1, 31
 ; RV32IZbb-NEXT:    lui a1, 524288
 ; RV32IZbb-NEXT:    xor a1, a0, a1

llvm/test/CodeGen/RISCV/ssub_sat.ll

; RV64IZbb-NEXT:    ret
   ret i32 %tmp;
 }
 
 define i64 @func2(i64 %x, i64 %y) nounwind {
 ; RV32-LABEL: func2:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    mv a4, a1
 ; RV32-NEXT:    sltu a1, a0, a2
-; RV32-NEXT:    sub a5, a4, a3
-; RV32-NEXT:    sub a1, a5, a1
+; RV32-NEXT:    add a1, a3, a1
+; RV32-NEXT:    sub a1, a4, a1
 ; RV32-NEXT:    xor a5, a4, a1
 ; RV32-NEXT:    xor a3, a4, a3
 ; RV32-NEXT:    and a3, a3, a5
 ; RV32-NEXT:    bltz a3, .LBB1_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    sub a0, a0, a2
 ; RV32-NEXT:    ret
 ; RV32-NEXT:  .LBB1_2:

llvm/test/CodeGen/RISCV/ssub_sat_plus.ll

; RV64IZbb-NEXT:    ret
   ret i32 %tmp
 }
 
 define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
 ; RV32-LABEL: func64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    mv a2, a1
 ; RV32-NEXT:    sltu a1, a0, a4
-; RV32-NEXT:    sub a3, a2, a5
-; RV32-NEXT:    sub a1, a3, a1
+; RV32-NEXT:    add a1, a5, a1
+; RV32-NEXT:    sub a1, a2, a1
 ; RV32-NEXT:    xor a3, a2, a1
 ; RV32-NEXT:    xor a2, a2, a5
 ; RV32-NEXT:    and a2, a2, a3
 ; RV32-NEXT:    bltz a2, .LBB1_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    sub a0, a0, a4
 ; RV32-NEXT:    ret
 ; RV32-NEXT:  .LBB1_2:

llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll

 ; RISCV32-NEXT:    add t5, t4, t1
 ; RISCV32-NEXT:    mul t6, t3, a2
 ; RISCV32-NEXT:    add s0, t6, t5
 ; RISCV32-NEXT:    mul t1, t0, a5
 ; RISCV32-NEXT:    mul s3, a6, a4
 ; RISCV32-NEXT:    add s4, s3, t1
 ; RISCV32-NEXT:    add t1, s0, s4
 ; RISCV32-NEXT:    sltu t2, t1, s0
-; RISCV32-NEXT:    sltu s0, s0, t6
+; RISCV32-NEXT:    sltu t6, s0, t6
 ; RISCV32-NEXT:    sltu t4, t5, t4
-; RISCV32-NEXT:    mulhu t5, t3, a2
-; RISCV32-NEXT:    add t4, t5, t4
-; RISCV32-NEXT:    add s0, t4, s0
+; RISCV32-NEXT:    mulhu s0, t3, a2
+; RISCV32-NEXT:    add t4, t4, t6
+; RISCV32-NEXT:    add s0, s0, t4
 ; RISCV32-NEXT:    mul t4, t3, t0
 ; RISCV32-NEXT:    mul t5, a7, a5
 ; RISCV32-NEXT:    add t4, t5, t4
 ; RISCV32-NEXT:    mulhu s1, t0, a5
 ; RISCV32-NEXT:    add s2, s1, t4
 ; RISCV32-NEXT:    mul t4, a2, a6
 ; RISCV32-NEXT:    mul t5, a3, a4
 ; RISCV32-NEXT:    add t4, t5, t4
 ; RISCV32-NEXT:    mulhu t5, a6, a4
 ; RISCV32-NEXT:    add t6, t5, t4
 ; RISCV32-NEXT:    add t4, t6, s2
 ; RISCV32-NEXT:    sltu s3, s4, s3
 ; RISCV32-NEXT:    add t4, t4, s3
-; RISCV32-NEXT:    add t4, s0, t4
 ; RISCV32-NEXT:    add t4, t4, t2
+; RISCV32-NEXT:    add t4, s0, t4
 ; RISCV32-NEXT:    beq t4, s0, .LBB0_2
 ; RISCV32-NEXT:  # %bb.1: # %start
 ; RISCV32-NEXT:    sltu t2, t4, s0
 ; RISCV32-NEXT:  .LBB0_2: # %start
 ; RISCV32-NEXT:    sltu s0, s2, s1
 ; RISCV32-NEXT:    snez s1, t3
 ; RISCV32-NEXT:    snez s2, a7
 ; RISCV32-NEXT:    and s1, s2, s1

 ; RISCV32-NEXT:    or a2, t6, a2
 ; RISCV32-NEXT:    or a2, a2, t5
 ; RISCV32-NEXT:    or a7, t0, a7
 ; RISCV32-NEXT:    snez a7, a7
 ; RISCV32-NEXT:    or a3, a6, a3
 ; RISCV32-NEXT:    snez a3, a3
 ; RISCV32-NEXT:    and a3, a3, a7
 ; RISCV32-NEXT:    or a2, a3, a2
-; RISCV32-NEXT:    or a3, t3, t2
-; RISCV32-NEXT:    or a2, a2, a3
+; RISCV32-NEXT:    or a2, a2, t3
+; RISCV32-NEXT:    or a2, a2, t2
 ; RISCV32-NEXT:    mul a3, a5, a4
 ; RISCV32-NEXT:    andi a2, a2, 1
 ; RISCV32-NEXT:    sw a3, 0(a0)
 ; RISCV32-NEXT:    sw a1, 4(a0)
 ; RISCV32-NEXT:    sw t1, 8(a0)
 ; RISCV32-NEXT:    sw t4, 12(a0)
 ; RISCV32-NEXT:    sb a2, 16(a0)
 ; RISCV32-NEXT:    lw s0, 28(sp) # 4-byte Folded Reload

llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

 ; RV64MV-NEXT:    andi a1, a1, 2047
 ; RV64MV-NEXT:    vslidedown.vi v9, v8, 1
 ; RV64MV-NEXT:    vmv.x.s a2, v9
 ; RV64MV-NEXT:    andi a2, a2, 2047
 ; RV64MV-NEXT:    slli a2, a2, 11
 ; RV64MV-NEXT:    vslidedown.vi v8, v8, 2
 ; RV64MV-NEXT:    vmv.x.s a3, v8
 ; RV64MV-NEXT:    slli a3, a3, 22
-; RV64MV-NEXT:    or a1, a1, a3
+; RV64MV-NEXT:    or a2, a2, a3
 ; RV64MV-NEXT:    or a1, a1, a2
 ; RV64MV-NEXT:    sw a1, 0(a0)
 ; RV64MV-NEXT:    slli a1, a1, 31
 ; RV64MV-NEXT:    srli a1, a1, 63
 ; RV64MV-NEXT:    sb a1, 4(a0)
 ; RV64MV-NEXT:    ret
   %ld = load <3 x i11>, ptr %X
   %urem = urem <3 x i11> %ld, <i11 6, i11 7, i11 -5>
   %cmp = icmp ne <3 x i11> %urem, <i11 0, i11 1, i11 2>
   %ext = sext <3 x i1> %cmp to <3 x i11>
   store <3 x i11> %ext, ptr %X
   ret void
 }

llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll

 ; RV32I-NEXT:    lbu a3, 5(a0)
 ; RV32I-NEXT:    lbu a4, 4(a0)
 ; RV32I-NEXT:    lbu a5, 6(a0)
 ; RV32I-NEXT:    lbu a6, 7(a0)
 ; RV32I-NEXT:    slli a3, a3, 8
 ; RV32I-NEXT:    or a3, a3, a4
 ; RV32I-NEXT:    slli a5, a5, 16
 ; RV32I-NEXT:    slli a6, a6, 24
-; RV32I-NEXT:    or a4, a6, a5
-; RV32I-NEXT:    or a3, a4, a3
+; RV32I-NEXT:    or a3, a5, a3
+; RV32I-NEXT:    or a3, a6, a3
 ; RV32I-NEXT:    lbu a4, 1(a1)
 ; RV32I-NEXT:    lbu a5, 0(a1)
 ; RV32I-NEXT:    lbu a6, 2(a1)
 ; RV32I-NEXT:    lbu a1, 3(a1)
 ; RV32I-NEXT:    slli a4, a4, 8
 ; RV32I-NEXT:    or a4, a4, a5
 ; RV32I-NEXT:    slli a6, a6, 16
 ; RV32I-NEXT:    slli a1, a1, 24

 ; RV32I-NEXT:    lbu a3, 1(a0)
 ; RV32I-NEXT:    lbu a4, 0(a0)
 ; RV32I-NEXT:    lbu a5, 2(a0)
 ; RV32I-NEXT:    lbu a6, 3(a0)
 ; RV32I-NEXT:    slli a3, a3, 8
 ; RV32I-NEXT:    or a3, a3, a4
 ; RV32I-NEXT:    slli a5, a5, 16
 ; RV32I-NEXT:    slli a6, a6, 24
-; RV32I-NEXT:    or a4, a6, a5
-; RV32I-NEXT:    or a3, a4, a3
+; RV32I-NEXT:    or a3, a5, a3
+; RV32I-NEXT:    or a3, a6, a3
 ; RV32I-NEXT:    lbu a4, 1(a1)
 ; RV32I-NEXT:    lbu a5, 0(a1)
 ; RV32I-NEXT:    lbu a6, 2(a1)
 ; RV32I-NEXT:    lbu a1, 3(a1)
 ; RV32I-NEXT:    slli a4, a4, 8
 ; RV32I-NEXT:    or a4, a4, a5
 ; RV32I-NEXT:    slli a6, a6, 16
 ; RV32I-NEXT:    slli a1, a1, 24

 ; RV64I-NEXT:    sb a0, 1(a2)
 ; RV64I-NEXT:    ret
 ;
 ; RV32I-LABEL: ashr_8bytes:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lbu a3, 5(a0)
 ; RV32I-NEXT:    lbu a4, 4(a0)
 ; RV32I-NEXT:    lbu a5, 6(a0)
-; RV32I-NEXT:    lbu a6, 7(a0)
 ; RV32I-NEXT:    slli a3, a3, 8
 ; RV32I-NEXT:    or a3, a3, a4
 ; RV32I-NEXT:    slli a5, a5, 16
-; RV32I-NEXT:    slli a4, a6, 24
-; RV32I-NEXT:    or a5, a4, a5
-; RV32I-NEXT:    or a3, a5, a3
-; RV32I-NEXT:    lbu a5, 1(a1)
+; RV32I-NEXT:    lbu a4, 1(a1)
 ; RV32I-NEXT:    lbu a6, 0(a1)
-; RV32I-NEXT:    lbu a7, 2(a1)
+; RV32I-NEXT:    or a3, a5, a3
+; RV32I-NEXT:    lbu a5, 7(a0)
+; RV32I-NEXT:    slli a4, a4, 8
+; RV32I-NEXT:    or a4, a4, a6
+; RV32I-NEXT:    lbu a6, 2(a1)
 ; RV32I-NEXT:    lbu a1, 3(a1)
-; RV32I-NEXT:    slli a5, a5, 8
-; RV32I-NEXT:    or a5, a5, a6
-; RV32I-NEXT:    slli a7, a7, 16
+; RV32I-NEXT:    slli a5, a5, 24
+; RV32I-NEXT:    or a3, a5, a3
+; RV32I-NEXT:    slli a6, a6, 16
 ; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    or a1, a1, a7
-; RV32I-NEXT:    or a1, a1, a5
-; RV32I-NEXT:    slli a5, a1, 3
-; RV32I-NEXT:    addi a6, a5, -32
-; RV32I-NEXT:    sra a1, a3, a5
+; RV32I-NEXT:    or a1, a1, a6
+; RV32I-NEXT:    or a1, a1, a4
+; RV32I-NEXT:    slli a4, a1, 3
+; RV32I-NEXT:    addi a6, a4, -32
+; RV32I-NEXT:    sra a1, a3, a4
 ; RV32I-NEXT:    bltz a6, .LBB5_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    srai a4, a4, 31
+; RV32I-NEXT:    srai a5, a5, 31
 ; RV32I-NEXT:    mv a0, a1
-; RV32I-NEXT:    mv a1, a4
+; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    j .LBB5_3
 ; RV32I-NEXT:  .LBB5_2:
-; RV32I-NEXT:    lbu a4, 1(a0)
+; RV32I-NEXT:    lbu a5, 1(a0)
 ; RV32I-NEXT:    lbu a6, 0(a0)
 ; RV32I-NEXT:    lbu a7, 2(a0)
 ; RV32I-NEXT:    lbu a0, 3(a0)
-; RV32I-NEXT:    slli a4, a4, 8
-; RV32I-NEXT:    or a4, a4, a6
+; RV32I-NEXT:    slli a5, a5, 8
+; RV32I-NEXT:    or a5, a5, a6
 ; RV32I-NEXT:    slli a7, a7, 16
 ; RV32I-NEXT:    slli a0, a0, 24
 ; RV32I-NEXT:    or a0, a0, a7
-; RV32I-NEXT:    or a0, a0, a4
-; RV32I-NEXT:    srl a0, a0, a5
+; RV32I-NEXT:    or a0, a0, a5
+; RV32I-NEXT:    srl a0, a0, a4
 ; RV32I-NEXT:    slli a3, a3, 1
-; RV32I-NEXT:    not a4, a5
+; RV32I-NEXT:    not a4, a4
 ; RV32I-NEXT:    sll a3, a3, a4
 ; RV32I-NEXT:    or a0, a0, a3
 ; RV32I-NEXT:  .LBB5_3:
 ; RV32I-NEXT:    sb a1, 4(a2)
 ; RV32I-NEXT:    srli a3, a1, 16
 ; RV32I-NEXT:    sb a3, 6(a2)
 ; RV32I-NEXT:    srli a3, a1, 24
 ; RV32I-NEXT:    sb a3, 7(a2)

 ; RV64I-NEXT:    lbu a4, 8(a0)
 ; RV64I-NEXT:    lbu a5, 10(a0)
 ; RV64I-NEXT:    lbu a6, 11(a0)
 ; RV64I-NEXT:    slli a3, a3, 8
 ; RV64I-NEXT:    or a3, a3, a4
 ; RV64I-NEXT:    slli a5, a5, 16
 ; RV64I-NEXT:    slli a6, a6, 24
 ; RV64I-NEXT:    or a4, a6, a5
-; RV64I-NEXT:    or a3, a4, a3
-; RV64I-NEXT:    lbu a4, 13(a0)
-; RV64I-NEXT:    lbu a5, 12(a0)
-; RV64I-NEXT:    lbu a6, 14(a0)
-; RV64I-NEXT:    lbu a7, 15(a0)
-; RV64I-NEXT:    slli a4, a4, 8
-; RV64I-NEXT:    or a4, a4, a5
-; RV64I-NEXT:    slli a6, a6, 16
-; RV64I-NEXT:    slli a7, a7, 24
-; RV64I-NEXT:    or a5, a7, a6
-; RV64I-NEXT:    or a4, a5, a4
-; RV64I-NEXT:    slli a4, a4, 32
-; RV64I-NEXT:    or a3, a4, a3
+; RV64I-NEXT:    lbu a5, 13(a0)
+; RV64I-NEXT:    lbu a6, 12(a0)
+; RV64I-NEXT:    lbu a7, 14(a0)
+; RV64I-NEXT:    lbu t0, 15(a0)
+; RV64I-NEXT:    slli a5, a5, 8
+; RV64I-NEXT:    or a5, a5, a6
+; RV64I-NEXT:    slli a7, a7, 16
+; RV64I-NEXT:    slli t0, t0, 24
+; RV64I-NEXT:    or a6, t0, a7
+; RV64I-NEXT:    or a5, a6, a5
+; RV64I-NEXT:    slli a5, a5, 32
+; RV64I-NEXT:    or a3, a5, a3
+; RV64I-NEXT:    or a3, a3, a4
 ; RV64I-NEXT:    lbu a4, 5(a1)
 ; RV64I-NEXT:    lbu a5, 4(a1)
 ; RV64I-NEXT:    lbu a6, 6(a1)
 ; RV64I-NEXT:    lbu a7, 7(a1)
 ; RV64I-NEXT:    slli a4, a4, 8
 ; RV64I-NEXT:    or a4, a4, a5
 ; RV64I-NEXT:    slli a6, a6, 16
 ; RV64I-NEXT:    slli a7, a7, 24

 ; RV64I-NEXT:    lbu a4, 0(a0)
 ; RV64I-NEXT:    lbu a5, 2(a0)
 ; RV64I-NEXT:    lbu a6, 3(a0)
 ; RV64I-NEXT:    slli a3, a3, 8
 ; RV64I-NEXT:    or a3, a3, a4
 ; RV64I-NEXT:    slli a5, a5, 16
 ; RV64I-NEXT:    slli a6, a6, 24
 ; RV64I-NEXT:    or a4, a6, a5
-; RV64I-NEXT:    or a3, a4, a3
-; RV64I-NEXT:    lbu a4, 5(a0)
-; RV64I-NEXT:    lbu a5, 4(a0)
-; RV64I-NEXT:    lbu a6, 6(a0)
-; RV64I-NEXT:    lbu a7, 7(a0)
-; RV64I-NEXT:    slli a4, a4, 8
-; RV64I-NEXT:    or a4, a4, a5
-; RV64I-NEXT:    slli a6, a6, 16
-; RV64I-NEXT:    slli a7, a7, 24
-; RV64I-NEXT:    or a5, a7, a6
-; RV64I-NEXT:    or a4, a5, a4
-; RV64I-NEXT:    slli a4, a4, 32
-; RV64I-NEXT:    or a3, a4, a3
+; RV64I-NEXT:    lbu a5, 5(a0)
+; RV64I-NEXT:    lbu a6, 4(a0)
+; RV64I-NEXT:    lbu a7, 6(a0)
+; RV64I-NEXT:    lbu t0, 7(a0)
+; RV64I-NEXT:    slli a5, a5, 8
+; RV64I-NEXT:    or a5, a5, a6
+; RV64I-NEXT:    slli a7, a7, 16
+; RV64I-NEXT:    slli t0, t0, 24
+; RV64I-NEXT:    or a6, t0, a7
+; RV64I-NEXT:    or a5, a6, a5
+; RV64I-NEXT:    slli a5, a5, 32
+; RV64I-NEXT:    or a3, a5, a3
+; RV64I-NEXT:    or a3, a3, a4
 ; RV64I-NEXT:    lbu a4, 5(a1)
 ; RV64I-NEXT:    lbu a5, 4(a1)
 ; RV64I-NEXT:    lbu a6, 6(a1)
 ; RV64I-NEXT:    lbu a7, 7(a1)
 ; RV64I-NEXT:    slli a4, a4, 8
 ; RV64I-NEXT:    or a4, a4, a5
 ; RV64I-NEXT:    slli a6, a6, 16
 ; RV64I-NEXT:    slli a7, a7, 24

 ; RV64I-NEXT:    lbu a3, 9(a0)
 ; RV64I-NEXT:    lbu a4, 8(a0)
 ; RV64I-NEXT:    lbu a5, 10(a0)
 ; RV64I-NEXT:    lbu a6, 11(a0)
 ; RV64I-NEXT:    slli a3, a3, 8
 ; RV64I-NEXT:    or a3, a3, a4
 ; RV64I-NEXT:    slli a5, a5, 16
 ; RV64I-NEXT:    slli a6, a6, 24
-; RV64I-NEXT:    or a4, a6, a5
-; RV64I-NEXT:    or a3, a4, a3
+; RV64I-NEXT:    or a5, a6, a5
 ; RV64I-NEXT:    lbu a4, 13(a0)
-; RV64I-NEXT:    lbu a5, 12(a0)
-; RV64I-NEXT:    lbu a6, 14(a0)
-; RV64I-NEXT:    lbu a7, 15(a0)
+; RV64I-NEXT:    lbu a6, 12(a0)
+; RV64I-NEXT:    lbu a7, 14(a0)
+; RV64I-NEXT:    lbu t0, 15(a0)
 ; RV64I-NEXT:    slli a4, a4, 8
-; RV64I-NEXT:    or a4, a4, a5
-; RV64I-NEXT:    slli a6, a6, 16
-; RV64I-NEXT:    slli a7, a7, 24
-; RV64I-NEXT:    or a5, a7, a6
-; RV64I-NEXT:    or a4, a5, a4
-; RV64I-NEXT:    slli a5, a4, 32
-; RV64I-NEXT:    or a3, a5, a3
+; RV64I-NEXT:    or a4, a4, a6
+; RV64I-NEXT:    slli a7, a7, 16
+; RV64I-NEXT:    slli t0, t0, 24
+; RV64I-NEXT:    or a6, t0, a7
+; RV64I-NEXT:    or a4, a6, a4
+; RV64I-NEXT:    slli a6, a4, 32
+; RV64I-NEXT:    or a3, a6, a3
+; RV64I-NEXT:    or a3, a3, a5
 ; RV64I-NEXT:    lbu a5, 5(a1)
 ; RV64I-NEXT:    lbu a6, 4(a1)
 ; RV64I-NEXT:    lbu a7, 6(a1)
 ; RV64I-NEXT:    lbu t0, 7(a1)
 ; RV64I-NEXT:    slli a5, a5, 8
 ; RV64I-NEXT:    or a5, a5, a6
 ; RV64I-NEXT:    slli a7, a7, 16
 ; RV64I-NEXT:    slli t0, t0, 24

llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll

 ; RV32I-NEXT:    lbu a3, 5(a0)
 ; RV32I-NEXT:    lbu a4, 4(a0)
 ; RV32I-NEXT:    lbu a5, 6(a0)
 ; RV32I-NEXT:    lbu a6, 7(a0)
 ; RV32I-NEXT:    slli a3, a3, 8
 ; RV32I-NEXT:    or a3, a3, a4
 ; RV32I-NEXT:    slli a5, a5, 16
 ; RV32I-NEXT:    slli a6, a6, 24
-; RV32I-NEXT:    or a4, a6, a5
-; RV32I-NEXT:    or a3, a4, a3
+; RV32I-NEXT:    or a3, a5, a3
+; RV32I-NEXT:    or a3, a6, a3
 ; RV32I-NEXT:    lbu a4, 1(a1)
 ; RV32I-NEXT:    lbu a5, 0(a1)
 ; RV32I-NEXT:    lbu a6, 2(a1)
 ; RV32I-NEXT:    lbu a1, 3(a1)
 ; RV32I-NEXT:    slli a4, a4, 8
 ; RV32I-NEXT:    or a4, a4, a5
 ; RV32I-NEXT:    slli a6, a6, 16
 ; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    or a5, a1, a6
-; RV32I-NEXT:    or a5, a5, a4
+; RV32I-NEXT:    or a5, a6, a4
+; RV32I-NEXT:    or a5, a1, a5
 ; RV32I-NEXT:    addi a4, a5, -32
 ; RV32I-NEXT:    srl a1, a3, a5
 ; RV32I-NEXT:    bltz a4, .LBB3_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:    j .LBB3_3
 ; RV32I-NEXT:  .LBB3_2:
 ; RV32I-NEXT:    lbu a6, 1(a0)

 ; RV32I-NEXT:    lbu a3, 1(a0)
 ; RV32I-NEXT:    lbu a4, 0(a0)
 ; RV32I-NEXT:    lbu a5, 2(a0)
 ; RV32I-NEXT:    lbu a6, 3(a0)
 ; RV32I-NEXT:    slli a3, a3, 8
 ; RV32I-NEXT:    or a3, a3, a4
 ; RV32I-NEXT:    slli a5, a5, 16
 ; RV32I-NEXT:    slli a6, a6, 24
-; RV32I-NEXT:    or a4, a6, a5
-; RV32I-NEXT:    or a3, a4, a3
+; RV32I-NEXT:    or a3, a5, a3
+; RV32I-NEXT:    or a3, a6, a3
 ; RV32I-NEXT:    lbu a4, 1(a1)
 ; RV32I-NEXT:    lbu a5, 0(a1)
 ; RV32I-NEXT:    lbu a6, 2(a1)
 ; RV32I-NEXT:    lbu a1, 3(a1)
 ; RV32I-NEXT:    slli a4, a4, 8
 ; RV32I-NEXT:    or a4, a4, a5
 ; RV32I-NEXT:    slli a6, a6, 16
 ; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    or a5, a1, a6
-; RV32I-NEXT:    or a5, a5, a4
+; RV32I-NEXT:    or a5, a6, a4
+; RV32I-NEXT:    or a5, a1, a5
 ; RV32I-NEXT:    addi a4, a5, -32
 ; RV32I-NEXT:    sll a1, a3, a5
 ; RV32I-NEXT:    bltz a4, .LBB4_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:    j .LBB4_3
 ; RV32I-NEXT:  .LBB4_2:
 ; RV32I-NEXT:    lbu a6, 5(a0)

 ; RV64I-NEXT:    sb a0, 1(a2)
 ; RV64I-NEXT:    ret
 ;
 ; RV32I-LABEL: ashr_8bytes:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lbu a3, 5(a0)
 ; RV32I-NEXT:    lbu a4, 4(a0)
 ; RV32I-NEXT:    lbu a5, 6(a0)
-; RV32I-NEXT:    lbu a6, 7(a0)
 ; RV32I-NEXT:    slli a3, a3, 8
 ; RV32I-NEXT:    or a3, a3, a4
 ; RV32I-NEXT:    slli a5, a5, 16
-; RV32I-NEXT:    slli a4, a6, 24
-; RV32I-NEXT:    or a5, a4, a5
-; RV32I-NEXT:    or a3, a5, a3
-; RV32I-NEXT:    lbu a5, 1(a1)
+; RV32I-NEXT:    lbu a4, 1(a1)
 ; RV32I-NEXT:    lbu a6, 0(a1)
-; RV32I-NEXT:    lbu a7, 2(a1)
+; RV32I-NEXT:    or a3, a5, a3
+; RV32I-NEXT:    lbu a5, 7(a0)
+; RV32I-NEXT:    slli a4, a4, 8
+; RV32I-NEXT:    or a4, a4, a6
+; RV32I-NEXT:    lbu a6, 2(a1)
 ; RV32I-NEXT:    lbu a1, 3(a1)
-; RV32I-NEXT:    slli a5, a5, 8
-; RV32I-NEXT:    or a5, a5, a6
-; RV32I-NEXT:    slli a7, a7, 16
+; RV32I-NEXT:    slli a5, a5, 24
+; RV32I-NEXT:    or a3, a5, a3
+; RV32I-NEXT:    slli a6, a6, 16
 ; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    or a1, a1, a7
-; RV32I-NEXT:    or a5, a1, a5
-; RV32I-NEXT:    addi a6, a5, -32
-; RV32I-NEXT:    sra a1, a3, a5
+; RV32I-NEXT:    or a4, a6, a4
+; RV32I-NEXT:    or a4, a1, a4
+; RV32I-NEXT:    addi a6, a4, -32
+; RV32I-NEXT:    sra a1, a3, a4
 ; RV32I-NEXT:    bltz a6, .LBB5_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    srai a4, a4, 31
+; RV32I-NEXT:    srai a5, a5, 31
 ; RV32I-NEXT:    mv a0, a1
-; RV32I-NEXT:    mv a1, a4
+; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    j .LBB5_3
 ; RV32I-NEXT:  .LBB5_2:
-; RV32I-NEXT:    lbu a4, 1(a0)
+; RV32I-NEXT:    lbu a5, 1(a0)
 ; RV32I-NEXT:    lbu a6, 0(a0)
 ; RV32I-NEXT:    lbu a7, 2(a0)
 ; RV32I-NEXT:    lbu a0, 3(a0)
-; RV32I-NEXT:    slli a4, a4, 8
-; RV32I-NEXT:    or a4, a4, a6
+; RV32I-NEXT:    slli a5, a5, 8
+; RV32I-NEXT:    or a5, a5, a6
 ; RV32I-NEXT:    slli a7, a7, 16
 ; RV32I-NEXT:    slli a0, a0, 24
 ; RV32I-NEXT:    or a0, a0, a7
-; RV32I-NEXT:    or a0, a0, a4
-; RV32I-NEXT:    srl a0, a0, a5
-; RV32I-NEXT:    not a4, a5
+; RV32I-NEXT:    or a0, a0, a5
+; RV32I-NEXT:    srl a0, a0, a4
+; RV32I-NEXT:    not a4, a4
 ; RV32I-NEXT:    slli a3, a3, 1
 ; RV32I-NEXT:    sll a3, a3, a4
 ; RV32I-NEXT:    or a0, a0, a3
 ; RV32I-NEXT:  .LBB5_3:
 ; RV32I-NEXT:    sb a1, 4(a2)
 ; RV32I-NEXT:    srli a3, a1, 16
 ; RV32I-NEXT:    sb a3, 6(a2)
 ; RV32I-NEXT:    srli a3, a1, 24

 ; RV64I-NEXT:    lbu a4, 8(a0)
 ; RV64I-NEXT:    lbu a5, 10(a0)
 ; RV64I-NEXT:    lbu a6, 11(a0)
 ; RV64I-NEXT:    slli a3, a3, 8
 ; RV64I-NEXT:    or a3, a3, a4
 ; RV64I-NEXT:    slli a5, a5, 16
 ; RV64I-NEXT:    slli a6, a6, 24
 ; RV64I-NEXT:    or a4, a6, a5
-; RV64I-NEXT:    or a3, a4, a3
-; RV64I-NEXT:    lbu a4, 13(a0)
-; RV64I-NEXT:    lbu a5, 12(a0)
-; RV64I-NEXT:    lbu a6, 14(a0)
-; RV64I-NEXT:    lbu a7, 15(a0)
-; RV64I-NEXT:    slli a4, a4, 8
-; RV64I-NEXT:    or a4, a4, a5
-; RV64I-NEXT:    slli a6, a6, 16
-; RV64I-NEXT:    slli a7, a7, 24
-; RV64I-NEXT:    or a5, a7, a6
-; RV64I-NEXT:    or a4, a5, a4
-; RV64I-NEXT:    slli a4, a4, 32
-; RV64I-NEXT:    or a3, a4, a3
+; RV64I-NEXT:    lbu a5, 13(a0)
+; RV64I-NEXT:    lbu a6, 12(a0)
+; RV64I-NEXT:    lbu a7, 14(a0)
+; RV64I-NEXT:    lbu t0, 15(a0)
+; RV64I-NEXT:    slli a5, a5, 8
+; RV64I-NEXT:    or a5, a5, a6
+; RV64I-NEXT:    slli a7, a7, 16
+; RV64I-NEXT:    slli t0, t0, 24
+; RV64I-NEXT:    or a6, t0, a7
+; RV64I-NEXT:    or a5, a6, a5
+; RV64I-NEXT:    slli a5, a5, 32
+; RV64I-NEXT:    or a3, a5, a3
+; RV64I-NEXT:    or a3, a3, a4
 ; RV64I-NEXT:    lbu a4, 1(a1)
 ; RV64I-NEXT:    lbu a5, 0(a1)
 ; RV64I-NEXT:    lbu a6, 2(a1)
 ; RV64I-NEXT:    lbu a7, 3(a1)
 ; RV64I-NEXT:    slli a4, a4, 8
 ; RV64I-NEXT:    or a4, a4, a5
 ; RV64I-NEXT:    slli a6, a6, 16
 ; RV64I-NEXT:    slli a7, a7, 24
 ; RV64I-NEXT:    or a5, a7, a6
-; RV64I-NEXT:    or a4, a5, a4
-; RV64I-NEXT:    lbu a5, 5(a1)
-; RV64I-NEXT:    lbu a6, 4(a1)
-; RV64I-NEXT:    lbu a7, 6(a1)
+; RV64I-NEXT:    lbu a6, 5(a1)
+; RV64I-NEXT:    lbu a7, 4(a1)
+; RV64I-NEXT:    lbu t0, 6(a1)
 ; RV64I-NEXT:    lbu a1, 7(a1)
-; RV64I-NEXT:    slli a5, a5, 8
-; RV64I-NEXT:    or a5, a5, a6
-; RV64I-NEXT:    slli a7, a7, 16
+; RV64I-NEXT:    slli a6, a6, 8
+; RV64I-NEXT:    or a6, a6, a7
+; RV64I-NEXT:    slli t0, t0, 16
 ; RV64I-NEXT:    slli a1, a1, 24
-; RV64I-NEXT:    or a1, a1, a7
-; RV64I-NEXT:    or a1, a1, a5
+; RV64I-NEXT:    or a1, a1, t0
+; RV64I-NEXT:    or a1, a1, a6
 ; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    or a5, a1, a4
+; RV64I-NEXT:    or a1, a1, a4
+; RV64I-NEXT:    or a5, a1, a5
 ; RV64I-NEXT:    addi a4, a5, -64
 ; RV64I-NEXT:    srl a1, a3, a5
 ; RV64I-NEXT:    bltz a4, .LBB6_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    j .LBB6_3
 ; RV64I-NEXT:  .LBB6_2:
 ; RV64I-NEXT:    lbu a6, 1(a0)

 ; RV64I-NEXT:    lbu a4, 0(a0)
 ; RV64I-NEXT:    lbu a5, 2(a0)
 ; RV64I-NEXT:    lbu a6, 3(a0)
 ; RV64I-NEXT:    slli a3, a3, 8
 ; RV64I-NEXT:    or a3, a3, a4
 ; RV64I-NEXT:    slli a5, a5, 16
 ; RV64I-NEXT:    slli a6, a6, 24
 ; RV64I-NEXT:    or a4, a6, a5
-; RV64I-NEXT:    or a3, a4, a3
-; RV64I-NEXT:    lbu a4, 5(a0)
-; RV64I-NEXT:    lbu a5, 4(a0)
-; RV64I-NEXT:    lbu a6, 6(a0)
-; RV64I-NEXT:    lbu a7, 7(a0)
-; RV64I-NEXT:    slli a4, a4, 8
-; RV64I-NEXT:    or a4, a4, a5
-; RV64I-NEXT:    slli a6, a6, 16
-; RV64I-NEXT:    slli a7, a7, 24
-; RV64I-NEXT:    or a5, a7, a6
-; RV64I-NEXT:    or a4, a5, a4
-; RV64I-NEXT:    slli a4, a4, 32
-; RV64I-NEXT:    or a3, a4, a3
+; RV64I-NEXT:    lbu a5, 5(a0)
+; RV64I-NEXT:    lbu a6, 4(a0)
+; RV64I-NEXT:    lbu a7, 6(a0)
+; RV64I-NEXT:    lbu t0, 7(a0)
+; RV64I-NEXT:    slli a5, a5, 8
+; RV64I-NEXT:    or a5, a5, a6
+; RV64I-NEXT:    slli a7, a7, 16
+; RV64I-NEXT:    slli t0, t0, 24
+; RV64I-NEXT:    or a6, t0, a7
+; RV64I-NEXT:    or a5, a6, a5
+; RV64I-NEXT:    slli a5, a5, 32
+; RV64I-NEXT:    or a3, a5, a3
+; RV64I-NEXT:    or a3, a3, a4
 ; RV64I-NEXT:    lbu a4, 1(a1)
 ; RV64I-NEXT:    lbu a5, 0(a1)
 ; RV64I-NEXT:    lbu a6, 2(a1)
 ; RV64I-NEXT:    lbu a7, 3(a1)
 ; RV64I-NEXT:    slli a4, a4, 8
 ; RV64I-NEXT:    or a4, a4, a5
 ; RV64I-NEXT:    slli a6, a6, 16
 ; RV64I-NEXT:    slli a7, a7, 24
 ; RV64I-NEXT:    or a5, a7, a6
-; RV64I-NEXT:    or a4, a5, a4
-; RV64I-NEXT:    lbu a5, 5(a1)
-; RV64I-NEXT:    lbu a6, 4(a1)
-; RV64I-NEXT:    lbu a7, 6(a1)
+; RV64I-NEXT:    lbu a6, 5(a1)
+; RV64I-NEXT:    lbu a7, 4(a1)
+; RV64I-NEXT:    lbu t0, 6(a1)
 ; RV64I-NEXT:    lbu a1, 7(a1)
-; RV64I-NEXT:    slli a5, a5, 8
-; RV64I-NEXT:    or a5, a5, a6
-; RV64I-NEXT:    slli a7, a7, 16
+; RV64I-NEXT:    slli a6, a6, 8
+; RV64I-NEXT:    or a6, a6, a7
+; RV64I-NEXT:    slli t0, t0, 16
 ; RV64I-NEXT:    slli a1, a1, 24
-; RV64I-NEXT:    or a1, a1, a7
-; RV64I-NEXT:    or a1, a1, a5
+; RV64I-NEXT:    or a1, a1, t0
+; RV64I-NEXT:    or a1, a1, a6
 ; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    or a5, a1, a4
+; RV64I-NEXT:    or a1, a1, a4
+; RV64I-NEXT:    or a5, a1, a5
 ; RV64I-NEXT:    addi a4, a5, -64
 ; RV64I-NEXT:    sll a1, a3, a5
 ; RV64I-NEXT:    bltz a4, .LBB7_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    j .LBB7_3
 ; RV64I-NEXT:  .LBB7_2:
 ; RV64I-NEXT:    lbu a6, 9(a0)

 ; RV64I-NEXT:    lbu a3, 9(a0)
 ; RV64I-NEXT:    lbu a4, 8(a0)
 ; RV64I-NEXT:    lbu a5, 10(a0)
 ; RV64I-NEXT:    lbu a6, 11(a0)
 ; RV64I-NEXT:    slli a3, a3, 8
 ; RV64I-NEXT:    or a3, a3, a4
 ; RV64I-NEXT:    slli a5, a5, 16
 ; RV64I-NEXT:    slli a6, a6, 24
-; RV64I-NEXT:    or a4, a6, a5
-; RV64I-NEXT:    or a3, a4, a3
+; RV64I-NEXT:    or a5, a6, a5
 ; RV64I-NEXT:    lbu a4, 13(a0)
-; RV64I-NEXT:    lbu a5, 12(a0)
-; RV64I-NEXT:    lbu a6, 14(a0)
-; RV64I-NEXT:    lbu a7, 15(a0)
+; RV64I-NEXT:    lbu a6, 12(a0)
+; RV64I-NEXT:    lbu a7, 14(a0)
+; RV64I-NEXT:    lbu t0, 15(a0)
 ; RV64I-NEXT:    slli a4, a4, 8
-; RV64I-NEXT:    or a4, a4, a5
-; RV64I-NEXT:    slli a6, a6, 16
-; RV64I-NEXT:    slli a7, a7, 24
-; RV64I-NEXT:    or a5, a7, a6
-; RV64I-NEXT:    or a4, a5, a4
-; RV64I-NEXT:    slli a5, a4, 32
-; RV64I-NEXT:    or a3, a5, a3
+; RV64I-NEXT:    or a4, a4, a6
+; RV64I-NEXT:    slli a7, a7, 16
+; RV64I-NEXT:    slli t0, t0, 24
+; RV64I-NEXT:    or a6, t0, a7
+; RV64I-NEXT:    or a4, a6, a4
+; RV64I-NEXT:    slli a6, a4, 32
+; RV64I-NEXT:    or a3, a6, a3
+; RV64I-NEXT:    or a3, a3, a5
 ; RV64I-NEXT:    lbu a5, 1(a1)
 ; RV64I-NEXT:    lbu a6, 0(a1)
 ; RV64I-NEXT:    lbu a7, 2(a1)
 ; RV64I-NEXT:    lbu t0, 3(a1)
 ; RV64I-NEXT:    slli a5, a5, 8
 ; RV64I-NEXT:    or a5, a5, a6
 ; RV64I-NEXT:    slli a7, a7, 16
 ; RV64I-NEXT:    slli t0, t0, 24
 ; RV64I-NEXT:    or a6, t0, a7
-; RV64I-NEXT:    or a5, a6, a5
-; RV64I-NEXT:    lbu a6, 5(a1)
-; RV64I-NEXT:    lbu a7, 4(a1)
-; RV64I-NEXT:    lbu t0, 6(a1)
+; RV64I-NEXT:    lbu a7, 5(a1)
+; RV64I-NEXT:    lbu t0, 4(a1)
+; RV64I-NEXT:    lbu t1, 6(a1)
 ; RV64I-NEXT:    lbu a1, 7(a1)
-; RV64I-NEXT:    slli a6, a6, 8
-; RV64I-NEXT:    or a6, a6, a7
-; RV64I-NEXT:    slli t0, t0, 16
+; RV64I-NEXT:    slli a7, a7, 8
+; RV64I-NEXT:    or a7, a7, t0
+; RV64I-NEXT:    slli t1, t1, 16
 ; RV64I-NEXT:    slli a1, a1, 24
-; RV64I-NEXT:    or a1, a1, t0
-; RV64I-NEXT:    or a1, a1, a6
+; RV64I-NEXT:    or a1, a1, t1
+; RV64I-NEXT:    or a1, a1, a7
 ; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    or a5, a1, a5
+; RV64I-NEXT:    or a1, a1, a5
+; RV64I-NEXT:    or a5, a1, a6
 ; RV64I-NEXT:    addi a6, a5, -64
 ; RV64I-NEXT:    sra a1, a3, a5
 ; RV64I-NEXT:    bltz a6, .LBB8_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    sraiw a3, a4, 31
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    mv a1, a3
 ; RV64I-NEXT:    j .LBB8_3

llvm/test/CodeGen/RISCV/xaluo.ll

entry:
   %obit = extractvalue {i32, i1} %t, 1
   store i32 %val, ptr %res
   ret i1 %obit
 }
 
 define zeroext i1 @saddo1.i64(i64 %v1, i64 %v2, ptr %res) {
 ; RV32-LABEL: saddo1.i64:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    add a5, a1, a3
 ; RV32-NEXT:    add a2, a0, a2
 ; RV32-NEXT:    sltu a0, a2, a0
-; RV32-NEXT:    add a5, a5, a0
+; RV32-NEXT:    add a0, a3, a0
+; RV32-NEXT:    add a5, a1, a0
 ; RV32-NEXT:    xor a0, a1, a5
 ; RV32-NEXT:    xor a1, a1, a3
 ; RV32-NEXT:    not a1, a1
 ; RV32-NEXT:    and a0, a1, a0
 ; RV32-NEXT:    slti a0, a0, 0
 ; RV32-NEXT:    sw a2, 0(a4)
 ; RV32-NEXT:    sw a5, 4(a4)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: saddo1.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    add a3, a0, a1
 ; RV64-NEXT:    slt a0, a3, a0
 ; RV64-NEXT:    slti a1, a1, 0
 ; RV64-NEXT:    xor a0, a1, a0
 ; RV64-NEXT:    sd a3, 0(a2)
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: saddo1.i64:
 ; RV32ZBA:       # %bb.0: # %entry
-; RV32ZBA-NEXT:    add a5, a1, a3
 ; RV32ZBA-NEXT:    add a2, a0, a2
 ; RV32ZBA-NEXT:    sltu a0, a2, a0
-; RV32ZBA-NEXT:    add a5, a5, a0
+; RV32ZBA-NEXT:    add a0, a3, a0
+; RV32ZBA-NEXT:    add a5, a1, a0
 ; RV32ZBA-NEXT:    xor a0, a1, a5
 ; RV32ZBA-NEXT:    xor a1, a1, a3
 ; RV32ZBA-NEXT:    not a1, a1
 ; RV32ZBA-NEXT:    and a0, a1, a0
 ; RV32ZBA-NEXT:    slti a0, a0, 0
 ; RV32ZBA-NEXT:    sw a2, 0(a4)
 ; RV32ZBA-NEXT:    sw a5, 4(a4)
 ; RV32ZBA-NEXT:    ret
entry:
   store i32 %val, ptr %res
   ret i1 %obit
 }
 
 define zeroext i1 @ssubo.i64(i64 %v1, i64 %v2, ptr %res) {
 ; RV32-LABEL: ssubo.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sltu a5, a0, a2
-; RV32-NEXT:    sub a6, a1, a3
-; RV32-NEXT:    sub a5, a6, a5
+; RV32-NEXT:    add a5, a3, a5
+; RV32-NEXT:    sub a5, a1, a5
 ; RV32-NEXT:    xor a6, a1, a5
 ; RV32-NEXT:    xor a1, a1, a3
 ; RV32-NEXT:    and a1, a1, a6
 ; RV32-NEXT:    slti a1, a1, 0
 ; RV32-NEXT:    sub a0, a0, a2
 ; RV32-NEXT:    sw a0, 0(a4)
 ; RV32-NEXT:    sw a5, 4(a4)
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ssubo.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sgtz a3, a1
 ; RV64-NEXT:    sub a1, a0, a1
 ; RV64-NEXT:    slt a0, a1, a0
 ; RV64-NEXT:    xor a0, a3, a0
 ; RV64-NEXT:    sd a1, 0(a2)
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: ssubo.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sltu a5, a0, a2
-; RV32ZBA-NEXT:    sub a6, a1, a3
-; RV32ZBA-NEXT:    sub a5, a6, a5
+; RV32ZBA-NEXT:    add a5, a3, a5
+; RV32ZBA-NEXT:    sub a5, a1, a5
 ; RV32ZBA-NEXT:    xor a6, a1, a5
 ; RV32ZBA-NEXT:    xor a1, a1, a3
 ; RV32ZBA-NEXT:    and a1, a1, a6
 ; RV32ZBA-NEXT:    slti a1, a1, 0
 ; RV32ZBA-NEXT:    sub a0, a0, a2
 ; RV32ZBA-NEXT:    sw a0, 0(a4)
 ; RV32ZBA-NEXT:    sw a5, 4(a4)
 ; RV32ZBA-NEXT:    mv a0, a1