[AIX][TLS] Generate 64-bit local-exec access code sequence

[amyk]

Summary

This patch adds support for the TLS local-exec access model on AIX to allow
for the ability to generate the 64-bit (specifically, non-optimized) code sequence.

For this patch in particular, the sequence that is generated involves a load of the
variable offset, followed by an add of the loaded variable offset to r13 (which is
thread pointer, respectively). This code sequence looks like the following:

ld reg1,var[TC](2)
add reg2, reg1, r13     // r13 contains the thread pointer

The TOC (.tc pseudo-op) entries generated in the assembly files are also
changed where we add the @le relocation for the variable offset.

[amyk]

Fix issue with respect to generating the incorrect code for the large code model.

[amyk]

Rebase patch and add test case for floats.

[amyk]

Rebase and pinging this patch for review.

[kamaub]

Thank you for this patch, just some review comments.

llvm/lib/Target/PowerPC/PPC.h

130–132

Accidentally repeated the initial comment?
What is the difference between TLS Initial Exec model and Initial Exec models on AIX?

Follow up, I wondering since it is named TPREL to mean Thread pointer relative, which indicates using r13 instead of the get addr call like with dynamic models should we say something like:

/// MO_TPREL_FLAG - If this bit is set the symbol reference is relative to
/// the thread pointer and is used for TLS Initial Exec , or  TLS Local Exec model.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

816

I think we should expand to say local exec explicitly

823

inline this variable

825

Please add an llvm unreachable after this if

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

3332–3354

I was wanted to suggest a wording that states the key points more explicitly

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

1927

Should this have an IsAIX guard?

llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large.ll

2

Please change the xcoff test cases to pwr7 for testing consistency

[amyk]

• Updated documentation for local-exec 64-bit in PPCISelLoweing.cpp, and for the ADD_TLS node, etc
• Remove assert(), add llvm_unreachable() and report_fatal_error() calls
• Simplified some code

llvm/lib/Target/PowerPC/PPC.h

130–132

Thanks, Kamau. I've updated this comment.

For initial-exec on AIX, it appears that the regular access sequence looks the same as the local-exec sequence, with the exception that we have a specific the initial exec relocation specifier (ie) for the TLS data in the TOC.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

3333

• Add documentation on what we're trying to do/produce for local-exec and the code sequence.
• Add the local exec code sequence in the patch description.
• Update the comment for ADD_TLS in PPCISelLowering.h as this node is not only used for initial-exec.

3342

Suggestion:

• Remove assert().
• Add an else to handle the 32-bit behaviour for now. We can report_fatal_error() for 32-bit mode.
• Remove the TODO for 32-bit.

[amyk]

Leaving comments from a group code review.

llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp

112

Verify if this change is appropriate for SignAndSizeForFKData.

llvm/lib/Target/PowerPC/PPC.h

132

Missing an and in this comment.

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

1911

• Clean up comments to combine both this pattern and the one below.
• Expand this comment to say that it's used for global-dynamic, or loading for local-exec (offset for the TLS variable is in the TOC)
• Remove code model comments from the PPCaddTls.

1919

• Remove this comment, as it is not necessary to explain the small/large code model intricacies here.
• Add the comment on why we need ADDTLS (in order to add the offset to r13, and in case we can optimized the user of the address).

1927

We've discussed this - having a guard specifically for AIX should not be necessary as producing the PPCaddTls node with two i64 inputs is only possible on AIX.

[DiggerLin]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

3331

TM only use once, change the above code to

TLSModel::Model Model = getTargetMachine().getTLSModel(GV); ?

[amyk]

• Rebase patch.
• Update comments.
• Remove the target machine variable as per Digger's comments.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

3331

Thanks for the suggestion. I've incorporated this into the patch.

[amyk]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp

112

I talked to @DiggerLin and I think this change is appropriate and should be something we expect.

For the TLS relocations, we don't expect them to have the sign bit set (and XL doesn't appear to set them for the R_TLS* relocations either). The SignAndSizeForFKData should correspond to the relocations that we emit in the llvm-readobj --relocs --expand-relocs output for IsSigned and Length:

; RELOC-NEXT:     Relocation {
; RELOC-NEXT:       Virtual Address: 0x68
; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (27)
; RELOC-NEXT:       IsSigned: No
; RELOC-NEXT:       FixupBitValue: 0
; RELOC-NEXT:       Length: 64
; RELOC-NEXT:       Type: R_TLS_LE (0x23)
; RELOC-NEXT:     }

like in these tests:

llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large.ll
llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll

The IsSigned and Length values appear correct and match what XL emits.

Also, according to the AIX documentation for the Relocation Information for XCOFF File, it states that the relocation sign and size contents:

0x80 (1 bit) - Indicates whether the relocation reference is signed (1) or unsigned (0).
0x40 (1 bit) - If this field is one, it indicates that the binder replaced the original instruction with a modified instruction.
0x3F(6 bits) - Specifies the bit length of the relocatable reference minus one. The current architecture allows for fields of up to 32 bits (XCOFF32) or 64 bits (XCOFF64) to be relocated.

I believe this is mainly consistent to what is currently implemented in the file - we are not using IsSigned for the R_TLS_LE relocation, and we are ensuring the length is 32 for XCOFF32, and 64 for XCOFF64, like what XL does.

[lei]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

152

These comments seem to be something appeneded each time a new condtion was added. Can we clean up lines 150-155 to be more general and representative? eg

// If the variant kind is a type of VK_PPC_AIX_TLS*, the entry represents the region handle for the symbol and
// we add the corresponding relocation specifier @[m|gd|le].

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

824

I dont' think we need the tmp variable Model, can just update the if stmt thus:

if (TM.getTLSModel(MO.getGlobal() == TLSModel::LocalExec)

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

3332–3353

I don't think Model is used anywhere else... can probably inline that as well.

3333

Is64Bit is only used once. Please inline and remove this variable def.

[lei]

llvm/include/llvm/MC/MCExpr.h

302

I realize this was done similar to VK_PPC_AIX_TLS*. but the symbol outputed seems to be too general and feels like we should fix this. Shouldn't this be something more along the lines of symbol@aix@tlsle?

[nemanjai]

LGTM.

llvm/include/llvm/MC/MCExpr.h

302

These are actual strings printed in ASM (i.e. the textual representation of the relocation) so we can't freely add aix in there since the assembler would not know what to do with that.

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

152

I think it makes sense to unify the gd/le, but m is the region handle while the other two are variable offsets. Or we can simply state something like:

// On AIX, we have a region handle (symbol@m) and the variable offset
// (symbol@{gd|le}) for TLS variables, depending on the TLS model.

The details for which is which should be obvious from the code.

[lei]

LGTM

llvm/include/llvm/MC/MCExpr.h

302

I see. Thank-you.

[amyk]

llvm/include/llvm/MC/MCExpr.h

302

That's correct. Thanks for answering this question, Nemanja.

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

152

Good suggestion. I'll update the patch to reflect this.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

824

My initial plan was to introduce these variables to be used for later when we implement the other models.
I'll be more explicit about this next time (especially if I have a future plan on why I added these variables).

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

3332–3353

My initial plan was to introduce these variables to be used for later when we implement the other models.
I'll be more explicit about this next time (especially if I have a future plan on why I added these variables).

3333

My initial plan was to introduce these variables to be used for later when we implement the other models.
I'll be more explicit about this next time (especially if I have a future plan on why I added these variables).

[DiggerLin]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

824

TLSModel::Model Model = TM.getTLSModel(MO.getGlobal());
 if (Model == TLSModel::LocalExec)

change to

if(TM.getTLSModel(MO.getGlobal() == TLSModel::LocalExec))

[DiggerLin]

llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large.ll

151

in order to make the test case more readable, suggest to remove all not related the local_exec TLS function CHECK.

275

ditto

llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll

177

ditto

194

ditto

[amyk]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

152

I like this suggestion. I'll update the comment accordingly.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

824

Discussed this with Digger.
Digger is OK if we keep this variable, as I have justified above on why I added it.

[DiggerLin]

llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll

177

sorry for this one, we need to keep this one.

[amyk]

• Update comments.
• Address Digger's comments in simplifying the RELOC and SYM checks in the relocation LIT test cases.

[hubert.reinterpretcast]

llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll

7

It helps to test with more than variable in .tdata (or in .tbss).

Defect opened:
https://github.com/llvm/llvm-project/issues/63885

[amyk]

llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll

7

I posted https://reviews.llvm.org/D155415 in hopes in addressing this.

llvm/include/llvm/MC/MCExpr.h

enum VariantKind : uint16_t {
     VK_PPC_TLS,             // symbol@tls
     VK_PPC_GOT_TLSGD,       // symbol@got@tlsgd
     VK_PPC_GOT_TLSGD_LO,    // symbol@got@tlsgd@l
     VK_PPC_GOT_TLSGD_HI,    // symbol@got@tlsgd@h
     VK_PPC_GOT_TLSGD_HA,    // symbol@got@tlsgd@ha
     VK_PPC_TLSGD,           // symbol@tlsgd
     VK_PPC_AIX_TLSGD,       // symbol@gd
     VK_PPC_AIX_TLSGDM,      // symbol@m
+    VK_PPC_AIX_TLSLE,       // symbol@le
     VK_PPC_GOT_TLSLD,       // symbol@got@tlsld
     VK_PPC_GOT_TLSLD_LO,    // symbol@got@tlsld@l
     VK_PPC_GOT_TLSLD_HI,    // symbol@got@tlsld@h
     VK_PPC_GOT_TLSLD_HA,    // symbol@got@tlsld@ha
     VK_PPC_GOT_PCREL,       // symbol@got@pcrel
     VK_PPC_GOT_TLSGD_PCREL, // symbol@got@tlsgd@pcrel
     VK_PPC_GOT_TLSLD_PCREL, // symbol@got@tlsld@pcrel
     VK_PPC_GOT_TPREL_PCREL, // symbol@got@tprel@pcrel

llvm/lib/MC/MCExpr.cpp

StringRef MCSymbolRefExpr::getVariantKindName(VariantKind Kind) {
   case VK_PPC_GOT_TLSGD_LO: return "got@tlsgd@l";
   case VK_PPC_GOT_TLSGD_HI: return "got@tlsgd@h";
   case VK_PPC_GOT_TLSGD_HA: return "got@tlsgd@ha";
   case VK_PPC_TLSGD: return "tlsgd";
   case VK_PPC_AIX_TLSGD:
     return "gd";
   case VK_PPC_AIX_TLSGDM:
     return "m";
+  case VK_PPC_AIX_TLSLE:
+    return "le";
   case VK_PPC_GOT_TLSLD: return "got@tlsld";
   case VK_PPC_GOT_TLSLD_LO: return "got@tlsld@l";
   case VK_PPC_GOT_TLSLD_HI: return "got@tlsld@h";
   case VK_PPC_GOT_TLSLD_HA: return "got@tlsld@ha";
   case VK_PPC_GOT_PCREL:
     return "got@pcrel";
   case VK_PPC_GOT_TLSGD_PCREL:
     return "got@tlsgd@pcrel";

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

PPCTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
       : PPCTargetStreamer(S), OS(OS) {}
 
   void emitTCEntry(const MCSymbol &S,
                    MCSymbolRefExpr::VariantKind Kind) override {
     if (const MCSymbolXCOFF *XSym = dyn_cast<MCSymbolXCOFF>(&S)) {
       MCSymbolXCOFF *TCSym =
           cast<MCSectionXCOFF>(Streamer.getCurrentSectionOnly())
               ->getQualNameSymbol();
-      // If the variant kind is VK_PPC_AIX_TLSGDM the entry represents the
-      // region handle for the symbol, we add the relocation specifier @m.
-      // If the variant kind is VK_PPC_AIX_TLSGD the entry represents the
-      // variable offset for the symbol, we add the relocation specifier @gd.
+      // On AIX, we have a region handle (symbol@m) and the variable offset
+      // (symbol@{gd|le}) for TLS variables, depending on the TLS model.
       if (Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGD ||
-          Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM)
+          Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM ||
+          Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSLE)
         OS << "\t.tc " << TCSym->getName() << "," << XSym->getName() << "@"
            << MCSymbolRefExpr::getVariantKindName(Kind) << '\n';
       else
         OS << "\t.tc " << TCSym->getName() << "," << XSym->getName() << '\n';
 
       if (TCSym->hasRename())
         Streamer.emitXCOFFRenameDirective(TCSym, TCSym->getSymbolTableName());
       return;

llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp

const uint8_t SignAndSizeForFKData =
         ((unsigned)Fixup.getKind() == FK_Data_4 ? 31 : 63);
     switch (Modifier) {
     default:
       report_fatal_error("Unsupported modifier");
     case MCSymbolRefExpr::VK_PPC_AIX_TLSGD:
       return {XCOFF::RelocationType::R_TLS, SignAndSizeForFKData};
     case MCSymbolRefExpr::VK_PPC_AIX_TLSGDM:
       return {XCOFF::RelocationType::R_TLSM, SignAndSizeForFKData};
+    case MCSymbolRefExpr::VK_PPC_AIX_TLSLE:
+      return {XCOFF::RelocationType::R_TLS_LE, SignAndSizeForFKData};
     case MCSymbolRefExpr::VK_None:
       return {XCOFF::RelocationType::R_POS, SignAndSizeForFKData};
     }
   }
 }

llvm/lib/Target/PowerPC/PPC.h

enum TOF {
     // PC Relative linker optimization.
     MO_PCREL_OPT_FLAG = 16,
 
     /// MO_TLSGD_FLAG - If this bit is set the symbol reference is relative to
     /// TLS General Dynamic model for Linux and the variable offset of TLS
     /// General Dynamic model for AIX.
     MO_TLSGD_FLAG = 32,
 
-    /// MO_TPREL_FLAG - If this bit is set the symbol reference is relative to
-    /// TLS Initial Exec model.
+    /// MO_TPREL_FLAG - If this bit is set, the symbol reference is relative to
+    /// the thread pointer and the symbol can be used for the TLS Initial Exec
+    /// and Local Exec models.
     MO_TPREL_FLAG = 64,
 
     /// MO_TLSLD_FLAG - If this bit is set the symbol reference is relative to
     /// TLS Local Dynamic model.
     MO_TLSLD_FLAG = 128,
 
     /// MO_TLSGDM_FLAG - If this bit is set the symbol reference is relative
     /// to the region handle of TLS General Dynamic model for AIX.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

auto getTOCEntryLoadingExprForXCOFF =
     constexpr int16_t PositiveTOCRange = INT16_MAX;
 
     if (EntryDistanceFromTOCBase > PositiveTOCRange)
       return getTOCRelocAdjustedExprForXCOFF(Expr, EntryDistanceFromTOCBase);
 
     return Expr;
   };
   auto GetVKForMO = [&](const MachineOperand &MO) {
+    // For TLS local-exec accesses on AIX, we have one TOC entry for the symbol
+    // (with the variable offset), which is differentiated by MO_TPREL_FLAG.
+    if (MO.getTargetFlags() & PPCII::MO_TPREL_FLAG) {
+      // TODO: Update the query and the comment above to add a check for initial
+      // exec when this TLS model is supported on AIX in the future, as both
+      // local-exec and initial-exec can use MO_TPREL_FLAG.
+      assert(MO.isGlobal() && "Only expecting a global MachineOperand here!\n");
+      TLSModel::Model Model = TM.getTLSModel(MO.getGlobal());
+      if (Model == TLSModel::LocalExec)
+        return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSLE;
+      llvm_unreachable("Only expecting local-exec accesses!");
+    }
     // For GD TLS access on AIX, we have two TOC entries for the symbol (one for
     // the variable offset and the other for the region handle). They are
     // differentiated by MO_TLSGD_FLAG and MO_TLSGDM_FLAG.
     if (MO.getTargetFlags() & PPCII::MO_TLSGDM_FLAG)
       return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM;
     if (MO.getTargetFlags() & PPCII::MO_TLSGD_FLAG)
       return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGD;
     return MCSymbolRefExpr::VariantKind::VK_None;

llvm/lib/Target/PowerPC/PPCISelLowering.h

enum NodeType : unsigned {
     ADDIS_GOT_TPREL_HA,
 
     /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
     /// TLS model, produces a LD instruction with base register G8RReg
     /// and offset sym\@got\@tprel\@l.  This completes the addition that
     /// finds the offset of "sym" relative to the thread pointer.
     LD_GOT_TPREL_L,
 
-    /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
-    /// model, produces an ADD instruction that adds the contents of
-    /// G8RReg to the thread pointer.  Symbol contains a relocation
-    /// sym\@tls which is to be replaced by the thread pointer and
-    /// identifies to the linker that the instruction is part of a
+    /// G8RC = ADD_TLS G8RReg, Symbol - Can be used by the initial-exec
+    /// and local-exec TLS models, produces an ADD instruction that adds
+    /// the contents of G8RReg to the thread pointer.  Symbol contains a
+    /// relocation sym\@tls which is to be replaced by the thread pointer
+    /// and identifies to the linker that the instruction is part of a
     /// TLS sequence.
     ADD_TLS,
 
     /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS
     /// model, produces an ADDIS8 instruction that adds the GOT base
     /// register to sym\@got\@tlsgd\@ha.
     ADDIS_TLSGD_HA,
 

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
   GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
 
   if (DAG.getTarget().useEmulatedTLS())
     report_fatal_error("Emulated TLS is not yet supported on AIX");
 
   SDLoc dl(GA);
   const GlobalValue *GV = GA->getGlobal();
   EVT PtrVT = getPointerTy(DAG.getDataLayout());
+  bool Is64Bit = Subtarget.isPPC64();
+  TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
 
-  // The general-dynamic model is the only access model supported for now, so
-  // all the GlobalTLSAddress nodes are lowered with this model.
+  if (Model == TLSModel::LocalExec) {
+    if (Is64Bit) {
+      // For local-exec on AIX (64-bit), the sequence that is generated involves
+      // a load of the variable offset (from the TOC), followed by an add of the
+      // loaded variable offset to R13 (the thread pointer).
+      // This code sequence looks like:
+      //    ld reg1,var[TC](2)
+      //    add reg2, reg1, r13     // r13 contains the thread pointer
+      SDValue TLSReg = DAG.getRegister(PPC::X13, MVT::i64);
+      SDValue VariableOffsetTGA =
+          DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TPREL_FLAG);
+      SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
+      return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, VariableOffset);
+    } else {
+      report_fatal_error("On AIX, the local-exec TLS model is only supported "
+                         "on PPC64 for now.");
+    }
+  }
+
+  // The Local-Exec and General-Dynamic TLS models are currently the only
+  // supported access models. If Local-exec is not possible or specified, all
+  // GlobalTLSAddress nodes are lowered using the general-dynamic model.
   // We need to generate two TOC entries, one for the variable offset, one for
   // the region handle. The global address for the TOC entry of the region
   // handle is created with the MO_TLSGDM_FLAG flag and the global address
   // for the TOC entry of the variable offset is created with MO_TLSGD_FLAG.
   SDValue VariableOffsetTGA =
       DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGD_FLAG);
   SDValue RegionHandleTGA =
       DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGDM_FLAG);
   SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
           (ADDIS8 $in, tglobaladdr:$g)>;
 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
           (ADDIS8 $in, tconstpool:$g)>;
 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
           (ADDIS8 $in, tjumptable:$g)>;
 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
           (ADDIS8 $in, tblockaddress:$g)>;
 
 // AIX 64-bit small code model TLS access.
+// This is used for global dynamic accesses when loading the region handle and
+// variable offset, and also for local-exec accesses to load the offset of a
+// TLS variable from the TOC, prior to adding it to r13.
 def : Pat<(i64 (PPCtoc_entry tglobaltlsaddr:$disp, i64:$reg)),
           (i64 (LDtoc tglobaltlsaddr:$disp, i64:$reg))>;
 
+// The following pattern matches 64-bit local-exec TLS accesses on AIX.
+// PPCaddTls is used in local-exec accesses in order to:
+//   - Get the address of a variable (adding the variable offset to the thread
+//     pointer in r13).
+//   - Create an opportunity to optimize the user of the loaded address.
+def : Pat<(PPCaddTls i64:$in, i64:$addr),
+          (ADD8TLS $in, $addr)>;
+
 // 64-bits atomic loads and stores
 def : Pat<(atomic_load_64 DSForm:$src), (LD  memrix:$src)>;
 def : Pat<(atomic_load_64 XForm:$src),  (LDX memrr:$src)>;
 
 def : Pat<(atomic_store_64 DSForm:$ptr, i64:$val), (STD  g8rc:$val, memrix:$ptr)>;
 def : Pat<(atomic_store_64 XForm:$ptr,  i64:$val), (STDX g8rc:$val, memrr:$ptr)>;
 
 let Predicates = [IsISA3_0, In64BitMode] in {
 def : Pat<(i64 (int_ppc_cmpeqb g8rc:$a, g8rc:$b)),

llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-double.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc  -verify-machineinstrs -mcpu=pwr7 -ppc-asm-full-reg-names \
+; RUN:      -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s \
+; RUN:      --check-prefix=SMALL64
+; RUN: llc  -verify-machineinstrs -mcpu=pwr7 -ppc-asm-full-reg-names \
+; RUN:      -mtriple powerpc64-ibm-aix-xcoff --code-model=large < %s \
+; RUN:      | FileCheck %s --check-prefix=LARGE64
+
+@ThreadLocalVarInit = thread_local(localexec) global double 0x4021947AE147AE14, align 8
+@VarInit = global double 8.787000e+01, align 8
+@IThreadLocalVarUninit = internal thread_local(localexec) global double 0.000000e+00, align 8
+@IThreadLocalVarInit = internal thread_local(localexec) global double 5.870000e+00, align 8
+@ThreadLocalVarUninit = thread_local(localexec) global double 0.000000e+00, align 8
+declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) #1
+
+define void @storeITLUninit(double noundef %x) {
+; SMALL64-LABEL: storeITLUninit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C0(r2) # target-flags(ppc-tprel) @IThreadLocalVarUninit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    stfd f1, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: storeITLUninit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C0@u(r2)
+; LARGE64-NEXT:    ld r3, L..C0@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    stfd f1, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarUninit)
+  store double %x, ptr %0, align 8
+  ret void
+}
+
+define void @storeITLInit(double noundef %x) {
+; SMALL64-LABEL: storeITLInit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C1(r2) # target-flags(ppc-tprel) @IThreadLocalVarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    stfd f1, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: storeITLInit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C1@u(r2)
+; LARGE64-NEXT:    ld r3, L..C1@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    stfd f1, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarInit)
+  store double %x, ptr %0, align 8
+  ret void
+}
+
+define void @storeTLUninit(double noundef %x) {
+; SMALL64-LABEL: storeTLUninit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C2(r2) # target-flags(ppc-tprel) @ThreadLocalVarUninit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    stfd f1, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: storeTLUninit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C2@u(r2)
+; LARGE64-NEXT:    ld r3, L..C2@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    stfd f1, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarUninit)
+  store double %x, ptr %0, align 8
+  ret void
+}
+
+define void @storeTLInit(double noundef %x) {
+; SMALL64-LABEL: storeTLInit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C3(r2) # target-flags(ppc-tprel) @ThreadLocalVarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    stfd f1, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: storeTLInit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C3@u(r2)
+; LARGE64-NEXT:    ld r3, L..C3@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    stfd f1, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarInit)
+  store double %x, ptr %0, align 8
+  ret void
+}
+
+define double @loadITLUninit() {
+; SMALL64-LABEL: loadITLUninit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C0(r2) # target-flags(ppc-tprel) @IThreadLocalVarUninit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lfd f1, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadITLUninit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C0@u(r2)
+; LARGE64-NEXT:    ld r3, L..C0@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lfd f1, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarUninit)
+  %1 = load double, ptr %0, align 8
+  ret double %1
+}
+
+define double @loadITLUninit2() {
+; SMALL64-LABEL: loadITLUninit2:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C0(r2) # target-flags(ppc-tprel) @IThreadLocalVarUninit
+; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lfd f1, 0(r4)
+; SMALL64-NEXT:    lfd f0, 0(r3)
+; SMALL64-NEXT:    xsadddp f1, f0, f1
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadITLUninit2:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C0@u(r2)
+; LARGE64-NEXT:    addis r4, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C0@l(r3)
+; LARGE64-NEXT:    ld r4, L..C4@l(r4)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lfd f1, 0(r4)
+; LARGE64-NEXT:    lfd f0, 0(r3)
+; LARGE64-NEXT:    xsadddp f1, f0, f1
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarUninit)
+  %1 = load double, ptr %0, align 8
+  %2 = load double, ptr @VarInit, align 8
+  %add = fadd double %1, %2
+  ret double %add
+}
+
+define double @loadITLInit() {
+; SMALL64-LABEL: loadITLInit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C1(r2) # target-flags(ppc-tprel) @IThreadLocalVarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lfd f1, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadITLInit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C1@u(r2)
+; LARGE64-NEXT:    ld r3, L..C1@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lfd f1, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarInit)
+  %1 = load double, ptr %0, align 8
+  ret double %1
+}
+
+define double @loadITLInit2() {
+; SMALL64-LABEL: loadITLInit2:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C1(r2) # target-flags(ppc-tprel) @IThreadLocalVarInit
+; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lfd f1, 0(r4)
+; SMALL64-NEXT:    lfd f0, 0(r3)
+; SMALL64-NEXT:    xsadddp f1, f0, f1
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadITLInit2:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C1@u(r2)
+; LARGE64-NEXT:    addis r4, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C1@l(r3)
+; LARGE64-NEXT:    ld r4, L..C4@l(r4)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lfd f1, 0(r4)
+; LARGE64-NEXT:    lfd f0, 0(r3)
+; LARGE64-NEXT:    xsadddp f1, f0, f1
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarInit)
+  %1 = load double, ptr %0, align 8
+  %2 = load double, ptr @VarInit, align 8
+  %add = fadd double %1, %2
+  ret double %add
+}
+
+define double @loadTLUninit() {
+; SMALL64-LABEL: loadTLUninit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C2(r2) # target-flags(ppc-tprel) @ThreadLocalVarUninit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lfd f1, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadTLUninit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C2@u(r2)
+; LARGE64-NEXT:    ld r3, L..C2@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lfd f1, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarUninit)
+  %1 = load double, ptr %0, align 8
+  ret double %1
+}
+
+define double @loadTLUninit2() {
+; SMALL64-LABEL: loadTLUninit2:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C2(r2) # target-flags(ppc-tprel) @ThreadLocalVarUninit
+; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lfd f1, 0(r4)
+; SMALL64-NEXT:    lfd f0, 0(r3)
+; SMALL64-NEXT:    xsadddp f1, f0, f1
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadTLUninit2:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C2@u(r2)
+; LARGE64-NEXT:    addis r4, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C2@l(r3)
+; LARGE64-NEXT:    ld r4, L..C4@l(r4)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lfd f1, 0(r4)
+; LARGE64-NEXT:    lfd f0, 0(r3)
+; LARGE64-NEXT:    xsadddp f1, f0, f1
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarUninit)
+  %1 = load double, ptr %0, align 8
+  %2 = load double, ptr @VarInit, align 8
+  %add = fadd double %1, %2
+  ret double %add
+}
+
+define double @loadTLInit() {
+; SMALL64-LABEL: loadTLInit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C3(r2) # target-flags(ppc-tprel) @ThreadLocalVarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lfd f1, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadTLInit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C3@u(r2)
+; LARGE64-NEXT:    ld r3, L..C3@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lfd f1, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarInit)
+  %1 = load double, ptr %0, align 8
+  ret double %1
+}
+
+define double @loadTLInit2() {
+; SMALL64-LABEL: loadTLInit2:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C3(r2) # target-flags(ppc-tprel) @ThreadLocalVarInit
+; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lfd f1, 0(r4)
+; SMALL64-NEXT:    lfd f0, 0(r3)
+; SMALL64-NEXT:    xsadddp f1, f0, f1
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadTLInit2:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C3@u(r2)
+; LARGE64-NEXT:    addis r4, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C3@l(r3)
+; LARGE64-NEXT:    ld r4, L..C4@l(r4)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lfd f1, 0(r4)
+; LARGE64-NEXT:    lfd f0, 0(r3)
+; LARGE64-NEXT:    xsadddp f1, f0, f1
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarInit)
+  %1 = load double, ptr %0, align 8
+  %2 = load double, ptr @VarInit, align 8
+  %add = fadd double %1, %2
+  ret double %add
+}
+
+; TOC Entry Checks.
+
+; SMALL64-LABEL: .toc
+; SMALL64-LABEL: L..C0:
+; SMALL64-NEXT: .tc IThreadLocalVarUninit[TC],IThreadLocalVarUninit[UL]@le
+; SMALL64-LABEL: L..C1:
+; SMALL64-NEXT: .tc IThreadLocalVarInit[TC],IThreadLocalVarInit[TL]@le
+; SMALL64-LABEL: L..C2:
+; SMALL64-NEXT: .tc ThreadLocalVarUninit[TC],ThreadLocalVarUninit[TL]@le
+; SMALL64-LABEL: L..C3:
+; SMALL64-NEXT: .tc ThreadLocalVarInit[TC],ThreadLocalVarInit[TL]@le
+; SMALL64-LABEL: L..C4:
+; SMALL64-NEXT: .tc VarInit[TC],VarInit[RW]
+
+; LARGE64-LABEL: .toc
+; LARGE64-LABEL: L..C0:
+; LARGE64-NEXT: .tc IThreadLocalVarUninit[TE],IThreadLocalVarUninit[UL]@le
+; LARGE64-LABEL: L..C1:
+; LARGE64-NEXT: .tc IThreadLocalVarInit[TE],IThreadLocalVarInit[TL]@le
+; LARGE64-LABEL: L..C2:
+; LARGE64-NEXT: .tc ThreadLocalVarUninit[TE],ThreadLocalVarUninit[TL]@le
+; LARGE64-LABEL: L..C3:
+; LARGE64-NEXT: .tc ThreadLocalVarInit[TE],ThreadLocalVarInit[TL]@le
+; LARGE64-LABEL: L..C4:
+; LARGE64-NEXT: .tc VarInit[TE],VarInit[RW]

llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-float.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc  -verify-machineinstrs -mcpu=pwr7 -ppc-asm-full-reg-names \
+; RUN:      -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s \
+; RUN:      --check-prefix=SMALL64
+; RUN: llc  -verify-machineinstrs -mcpu=pwr7 -ppc-asm-full-reg-names \
+; RUN:      -mtriple powerpc64-ibm-aix-xcoff --code-model=large < %s \
+; RUN:      | FileCheck %s --check-prefix=LARGE64
+
+@ThreadLocalVarInit = thread_local(localexec) global float 0x401D333340000000, align 4
+@VarInit = global float 0x4021666660000000, align 4
+@IThreadLocalVarUninit = internal thread_local(localexec) global float 0.000000e+00, align 4
+@IThreadLocalVarInit = internal thread_local(localexec) global float 0x4018CCCCC0000000, align 4
+@ThreadLocalVarUninit = thread_local(localexec) global float 0.000000e+00, align 4
+declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) #1
+
+define void @storeITLUninit(float noundef %x) {
+; SMALL64-LABEL: storeITLUninit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C0(r2) # target-flags(ppc-tprel) @IThreadLocalVarUninit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    stfs f1, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: storeITLUninit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C0@u(r2)
+; LARGE64-NEXT:    ld r3, L..C0@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    stfs f1, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @IThreadLocalVarUninit)
+  store float %x, ptr %0, align 4
+  ret void
+}
+
+define void @storeITLInit(float noundef %x) {
+; SMALL64-LABEL: storeITLInit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C1(r2) # target-flags(ppc-tprel) @IThreadLocalVarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    stfs f1, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: storeITLInit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C1@u(r2)
+; LARGE64-NEXT:    ld r3, L..C1@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    stfs f1, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @IThreadLocalVarInit)
+  store float %x, ptr %0, align 4
+  ret void
+}
+
+define void @storeTLUninit(float noundef %x) {
+; SMALL64-LABEL: storeTLUninit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C2(r2) # target-flags(ppc-tprel) @ThreadLocalVarUninit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    stfs f1, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: storeTLUninit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C2@u(r2)
+; LARGE64-NEXT:    ld r3, L..C2@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    stfs f1, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @ThreadLocalVarUninit)
+  store float %x, ptr %0, align 4
+  ret void
+}
+
+define void @storeTLInit(float noundef %x) {
+; SMALL64-LABEL: storeTLInit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C3(r2) # target-flags(ppc-tprel) @ThreadLocalVarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    stfs f1, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: storeTLInit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C3@u(r2)
+; LARGE64-NEXT:    ld r3, L..C3@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    stfs f1, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @ThreadLocalVarInit)
+  store float %x, ptr %0, align 4
+  ret void
+}
+
+define float @loadITLUninit() {
+; SMALL64-LABEL: loadITLUninit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C0(r2) # target-flags(ppc-tprel) @IThreadLocalVarUninit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lfs f1, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadITLUninit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C0@u(r2)
+; LARGE64-NEXT:    ld r3, L..C0@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lfs f1, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @IThreadLocalVarUninit)
+  %1 = load float, ptr %0, align 4
+  ret float %1
+}
+
+define float @loadITLUninit2() {
+; SMALL64-LABEL: loadITLUninit2:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C0(r2) # target-flags(ppc-tprel) @IThreadLocalVarUninit
+; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lfs f1, 0(r4)
+; SMALL64-NEXT:    lfs f0, 0(r3)
+; SMALL64-NEXT:    fadds f1, f0, f1
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadITLUninit2:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C0@u(r2)
+; LARGE64-NEXT:    addis r4, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C0@l(r3)
+; LARGE64-NEXT:    ld r4, L..C4@l(r4)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lfs f1, 0(r4)
+; LARGE64-NEXT:    lfs f0, 0(r3)
+; LARGE64-NEXT:    fadds f1, f0, f1
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @IThreadLocalVarUninit)
+  %1 = load float, ptr %0, align 4
+  %2 = load float, ptr @VarInit, align 4
+  %add = fadd float %1, %2
+  ret float %add
+}
+
+define float @loadITLInit() {
+; SMALL64-LABEL: loadITLInit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C1(r2) # target-flags(ppc-tprel) @IThreadLocalVarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lfs f1, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadITLInit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C1@u(r2)
+; LARGE64-NEXT:    ld r3, L..C1@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lfs f1, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @IThreadLocalVarInit)
+  %1 = load float, ptr %0, align 4
+  ret float %1
+}
+
+define float @loadITLInit2() {
+; SMALL64-LABEL: loadITLInit2:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C1(r2) # target-flags(ppc-tprel) @IThreadLocalVarInit
+; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lfs f1, 0(r4)
+; SMALL64-NEXT:    lfs f0, 0(r3)
+; SMALL64-NEXT:    fadds f1, f0, f1
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadITLInit2:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C1@u(r2)
+; LARGE64-NEXT:    addis r4, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C1@l(r3)
+; LARGE64-NEXT:    ld r4, L..C4@l(r4)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lfs f1, 0(r4)
+; LARGE64-NEXT:    lfs f0, 0(r3)
+; LARGE64-NEXT:    fadds f1, f0, f1
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @IThreadLocalVarInit)
+  %1 = load float, ptr %0, align 4
+  %2 = load float, ptr @VarInit, align 4
+  %add = fadd float %1, %2
+  ret float %add
+}
+
+define float @loadTLUninit() {
+; SMALL64-LABEL: loadTLUninit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C2(r2) # target-flags(ppc-tprel) @ThreadLocalVarUninit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lfs f1, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadTLUninit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C2@u(r2)
+; LARGE64-NEXT:    ld r3, L..C2@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lfs f1, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @ThreadLocalVarUninit)
+  %1 = load float, ptr %0, align 4
+  ret float %1
+}
+
+define float @loadTLUninit2() {
+; SMALL64-LABEL: loadTLUninit2:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C2(r2) # target-flags(ppc-tprel) @ThreadLocalVarUninit
+; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lfs f1, 0(r4)
+; SMALL64-NEXT:    lfs f0, 0(r3)
+; SMALL64-NEXT:    fadds f1, f0, f1
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadTLUninit2:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C2@u(r2)
+; LARGE64-NEXT:    addis r4, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C2@l(r3)
+; LARGE64-NEXT:    ld r4, L..C4@l(r4)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lfs f1, 0(r4)
+; LARGE64-NEXT:    lfs f0, 0(r3)
+; LARGE64-NEXT:    fadds f1, f0, f1
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @ThreadLocalVarUninit)
+  %1 = load float, ptr %0, align 4
+  %2 = load float, ptr @VarInit, align 4
+  %add = fadd float %1, %2
+  ret float %add
+}
+
+define float @loadTLInit() {
+; SMALL64-LABEL: loadTLInit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C3(r2) # target-flags(ppc-tprel) @ThreadLocalVarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lfs f1, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadTLInit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C3@u(r2)
+; LARGE64-NEXT:    ld r3, L..C3@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lfs f1, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @ThreadLocalVarInit)
+  %1 = load float, ptr %0, align 4
+  ret float %1
+}
+
+define float @loadTLInit2() {
+; SMALL64-LABEL: loadTLInit2:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C3(r2) # target-flags(ppc-tprel) @ThreadLocalVarInit
+; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lfs f1, 0(r4)
+; SMALL64-NEXT:    lfs f0, 0(r3)
+; SMALL64-NEXT:    fadds f1, f0, f1
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadTLInit2:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C3@u(r2)
+; LARGE64-NEXT:    addis r4, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C3@l(r3)
+; LARGE64-NEXT:    ld r4, L..C4@l(r4)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lfs f1, 0(r4)
+; LARGE64-NEXT:    lfs f0, 0(r3)
+; LARGE64-NEXT:    fadds f1, f0, f1
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @ThreadLocalVarInit)
+  %1 = load float, ptr %0, align 4
+  %2 = load float, ptr @VarInit, align 4
+  %add = fadd float %1, %2
+  ret float %add
+}
+
+; TOC Entry Checks.
+
+; SMALL64-LABEL: .toc
+; SMALL64-LABEL: L..C0:
+; SMALL64-NEXT: .tc IThreadLocalVarUninit[TC],IThreadLocalVarUninit[UL]@le
+; SMALL64-LABEL: L..C1:
+; SMALL64-NEXT: .tc IThreadLocalVarInit[TC],IThreadLocalVarInit[TL]@le
+; SMALL64-LABEL: L..C2:
+; SMALL64-NEXT: .tc ThreadLocalVarUninit[TC],ThreadLocalVarUninit[TL]@le
+; SMALL64-LABEL: L..C3:
+; SMALL64-NEXT: .tc ThreadLocalVarInit[TC],ThreadLocalVarInit[TL]@le
+; SMALL64-LABEL: L..C4:
+; SMALL64-NEXT: .tc VarInit[TC],VarInit[RW]
+
+; LARGE64-LABEL: .toc
+; LARGE64-LABEL: L..C0:
+; LARGE64-NEXT: .tc IThreadLocalVarUninit[TE],IThreadLocalVarUninit[UL]@le
+; LARGE64-LABEL: L..C1:
+; LARGE64-NEXT: .tc IThreadLocalVarInit[TE],IThreadLocalVarInit[TL]@le
+; LARGE64-LABEL: L..C2:
+; LARGE64-NEXT: .tc ThreadLocalVarUninit[TE],ThreadLocalVarUninit[TL]@le
+; LARGE64-LABEL: L..C3:
+; LARGE64-NEXT: .tc ThreadLocalVarInit[TE],ThreadLocalVarInit[TL]@le
+; LARGE64-LABEL: L..C4:
+; LARGE64-NEXT: .tc VarInit[TE],VarInit[RW]

llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-int.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc  -verify-machineinstrs -mcpu=pwr7 -ppc-asm-full-reg-names \
+; RUN:      -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s \
+; RUN:      --check-prefix=SMALL64
+; RUN: llc  -verify-machineinstrs -mcpu=pwr7 -ppc-asm-full-reg-names \
+; RUN:      -mtriple powerpc64-ibm-aix-xcoff --code-model=large < %s \
+; RUN:      | FileCheck %s --check-prefix=LARGE64
+
+@ThreadLocalVarInit = thread_local(localexec) global i32 1, align 4
+@VarInit = global i32 87, align 4
+@IThreadLocalVarUninit = internal thread_local(localexec) global i32 0, align 4
+@IThreadLocalVarInit = internal thread_local(localexec) global i32 1, align 4
+@ThreadLocalVarUninit = thread_local(localexec) global i32 0, align 4
+declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) #1
+
+define void @storeITLUninit(i32 noundef signext %x) {
+; SMALL64-LABEL: storeITLUninit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r4, L..C0(r2) # target-flags(ppc-tprel) @IThreadLocalVarUninit
+; SMALL64-NEXT:    add r4, r13, r4
+; SMALL64-NEXT:    stw r3, 0(r4)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: storeITLUninit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r4, L..C0@u(r2)
+; LARGE64-NEXT:    ld r4, L..C0@l(r4)
+; LARGE64-NEXT:    add r4, r13, r4
+; LARGE64-NEXT:    stw r3, 0(r4)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @IThreadLocalVarUninit)
+  store i32 %x, ptr %0, align 4
+  ret void
+}
+
+define void @storeITLInit(i32 noundef signext %x) {
+; SMALL64-LABEL: storeITLInit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r4, L..C1(r2) # target-flags(ppc-tprel) @IThreadLocalVarInit
+; SMALL64-NEXT:    add r4, r13, r4
+; SMALL64-NEXT:    stw r3, 0(r4)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: storeITLInit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r4, L..C1@u(r2)
+; LARGE64-NEXT:    ld r4, L..C1@l(r4)
+; LARGE64-NEXT:    add r4, r13, r4
+; LARGE64-NEXT:    stw r3, 0(r4)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @IThreadLocalVarInit)
+  store i32 %x, ptr %0, align 4
+  ret void
+}
+
+define void @storeTLUninit(i32 noundef signext %x) {
+; SMALL64-LABEL: storeTLUninit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r4, L..C2(r2) # target-flags(ppc-tprel) @ThreadLocalVarUninit
+; SMALL64-NEXT:    add r4, r13, r4
+; SMALL64-NEXT:    stw r3, 0(r4)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: storeTLUninit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r4, L..C2@u(r2)
+; LARGE64-NEXT:    ld r4, L..C2@l(r4)
+; LARGE64-NEXT:    add r4, r13, r4
+; LARGE64-NEXT:    stw r3, 0(r4)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @ThreadLocalVarUninit)
+  store i32 %x, ptr %0, align 4
+  ret void
+}
+
+define void @storeTLInit(i32 noundef signext %x) {
+; SMALL64-LABEL: storeTLInit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r4, L..C3(r2) # target-flags(ppc-tprel) @ThreadLocalVarInit
+; SMALL64-NEXT:    add r4, r13, r4
+; SMALL64-NEXT:    stw r3, 0(r4)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: storeTLInit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r4, L..C3@u(r2)
+; LARGE64-NEXT:    ld r4, L..C3@l(r4)
+; LARGE64-NEXT:    add r4, r13, r4
+; LARGE64-NEXT:    stw r3, 0(r4)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @ThreadLocalVarInit)
+  store i32 %x, ptr %0, align 4
+  ret void
+}
+
+define signext i32 @loadITLUninit() {
+; SMALL64-LABEL: loadITLUninit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C0(r2) # target-flags(ppc-tprel) @IThreadLocalVarUninit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lwa r3, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadITLUninit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C0@u(r2)
+; LARGE64-NEXT:    ld r3, L..C0@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lwa r3, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @IThreadLocalVarUninit)
+  %1 = load i32, ptr %0, align 4
+  ret i32 %1
+}
+
+define signext i32 @loadITLUninit2() {
+; SMALL64-LABEL: loadITLUninit2:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C0(r2) # target-flags(ppc-tprel) @IThreadLocalVarUninit
+; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lwz r4, 0(r4)
+; SMALL64-NEXT:    lwz r3, 0(r3)
+; SMALL64-NEXT:    add r3, r4, r3
+; SMALL64-NEXT:    extsw r3, r3
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadITLUninit2:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C0@u(r2)
+; LARGE64-NEXT:    addis r4, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C0@l(r3)
+; LARGE64-NEXT:    ld r4, L..C4@l(r4)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lwz r4, 0(r4)
+; LARGE64-NEXT:    lwz r3, 0(r3)
+; LARGE64-NEXT:    add r3, r4, r3
+; LARGE64-NEXT:    extsw r3, r3
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @IThreadLocalVarUninit)
+  %1 = load i32, ptr %0, align 4
+  %2 = load i32, ptr @VarInit, align 4
+  %add = add nsw i32 %2, %1
+  ret i32 %add
+}
+
+define signext i32 @loadITLInit() {
+; SMALL64-LABEL: loadITLInit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C1(r2) # target-flags(ppc-tprel) @IThreadLocalVarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lwa r3, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadITLInit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C1@u(r2)
+; LARGE64-NEXT:    ld r3, L..C1@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lwa r3, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @IThreadLocalVarInit)
+  %1 = load i32, ptr %0, align 4
+  ret i32 %1
+}
+
+define signext i32 @loadITLInit2() {
+; SMALL64-LABEL: loadITLInit2:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C1(r2) # target-flags(ppc-tprel) @IThreadLocalVarInit
+; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lwz r4, 0(r4)
+; SMALL64-NEXT:    lwz r3, 0(r3)
+; SMALL64-NEXT:    add r3, r4, r3
+; SMALL64-NEXT:    extsw r3, r3
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadITLInit2:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C1@u(r2)
+; LARGE64-NEXT:    addis r4, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C1@l(r3)
+; LARGE64-NEXT:    ld r4, L..C4@l(r4)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lwz r4, 0(r4)
+; LARGE64-NEXT:    lwz r3, 0(r3)
+; LARGE64-NEXT:    add r3, r4, r3
+; LARGE64-NEXT:    extsw r3, r3
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @IThreadLocalVarInit)
+  %1 = load i32, ptr %0, align 4
+  %2 = load i32, ptr @VarInit, align 4
+  %add = add nsw i32 %2, %1
+  ret i32 %add
+}
+
+define signext i32 @loadTLUninit() {
+; SMALL64-LABEL: loadTLUninit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C2(r2) # target-flags(ppc-tprel) @ThreadLocalVarUninit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lwa r3, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadTLUninit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C2@u(r2)
+; LARGE64-NEXT:    ld r3, L..C2@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lwa r3, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @ThreadLocalVarUninit)
+  %1 = load i32, ptr %0, align 4
+  ret i32 %1
+}
+
+define signext i32 @loadTLUninit2() {
+; SMALL64-LABEL: loadTLUninit2:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C2(r2) # target-flags(ppc-tprel) @ThreadLocalVarUninit
+; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lwz r4, 0(r4)
+; SMALL64-NEXT:    lwz r3, 0(r3)
+; SMALL64-NEXT:    add r3, r4, r3
+; SMALL64-NEXT:    extsw r3, r3
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadTLUninit2:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C2@u(r2)
+; LARGE64-NEXT:    addis r4, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C2@l(r3)
+; LARGE64-NEXT:    ld r4, L..C4@l(r4)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lwz r4, 0(r4)
+; LARGE64-NEXT:    lwz r3, 0(r3)
+; LARGE64-NEXT:    add r3, r4, r3
+; LARGE64-NEXT:    extsw r3, r3
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @ThreadLocalVarUninit)
+  %1 = load i32, ptr %0, align 4
+  %2 = load i32, ptr @VarInit, align 4
+  %add = add nsw i32 %2, %1
+  ret i32 %add
+}
+
+define signext i32 @loadTLInit() {
+; SMALL64-LABEL: loadTLInit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C3(r2) # target-flags(ppc-tprel) @ThreadLocalVarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lwa r3, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadTLInit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C3@u(r2)
+; LARGE64-NEXT:    ld r3, L..C3@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lwa r3, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @ThreadLocalVarInit)
+  %1 = load i32, ptr %0, align 4
+  ret i32 %1
+}
+
+define signext i32 @loadTLInit2() {
+; SMALL64-LABEL: loadTLInit2:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C3(r2) # target-flags(ppc-tprel) @ThreadLocalVarInit
+; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    lwz r4, 0(r4)
+; SMALL64-NEXT:    lwz r3, 0(r3)
+; SMALL64-NEXT:    add r3, r4, r3
+; SMALL64-NEXT:    extsw r3, r3
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadTLInit2:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C3@u(r2)
+; LARGE64-NEXT:    addis r4, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C3@l(r3)
+; LARGE64-NEXT:    ld r4, L..C4@l(r4)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    lwz r4, 0(r4)
+; LARGE64-NEXT:    lwz r3, 0(r3)
+; LARGE64-NEXT:    add r3, r4, r3
+; LARGE64-NEXT:    extsw r3, r3
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @ThreadLocalVarInit)
+  %1 = load i32, ptr %0, align 4
+  %2 = load i32, ptr @VarInit, align 4
+  %add = add nsw i32 %2, %1
+  ret i32 %add
+}
+
+; TOC Entry Checks.
+
+; SMALL64-LABEL: .toc
+; SMALL64-LABEL: L..C0:
+; SMALL64-NEXT: .tc IThreadLocalVarUninit[TC],IThreadLocalVarUninit[UL]@le
+; SMALL64-LABEL: L..C1:
+; SMALL64-NEXT: .tc IThreadLocalVarInit[TC],IThreadLocalVarInit[TL]@le
+; SMALL64-LABEL: L..C2:
+; SMALL64-NEXT: .tc ThreadLocalVarUninit[TC],ThreadLocalVarUninit[TL]@le
+; SMALL64-LABEL: L..C3:
+; SMALL64-NEXT: .tc ThreadLocalVarInit[TC],ThreadLocalVarInit[TL]@le
+; SMALL64-LABEL: L..C4:
+; SMALL64-NEXT: .tc VarInit[TC],VarInit[RW]
+
+; LARGE64-LABEL: .toc
+; LARGE64-LABEL: L..C0:
+; LARGE64-NEXT: .tc IThreadLocalVarUninit[TE],IThreadLocalVarUninit[UL]@le
+; LARGE64-LABEL: L..C1:
+; LARGE64-NEXT: .tc IThreadLocalVarInit[TE],IThreadLocalVarInit[TL]@le
+; LARGE64-LABEL: L..C2:
+; LARGE64-NEXT: .tc ThreadLocalVarUninit[TE],ThreadLocalVarUninit[TL]@le
+; LARGE64-LABEL: L..C3:
+; LARGE64-NEXT: .tc ThreadLocalVarInit[TE],ThreadLocalVarInit[TL]@le
+; LARGE64-LABEL: L..C4:
+; LARGE64-NEXT: .tc VarInit[TE],VarInit[RW]

llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-longlong.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc  -verify-machineinstrs -mcpu=pwr7 -ppc-asm-full-reg-names \
+; RUN:      -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s \
+; RUN:      --check-prefix=SMALL64
+; RUN: llc  -verify-machineinstrs -mcpu=pwr7 -ppc-asm-full-reg-names \
+; RUN:      -mtriple powerpc64-ibm-aix-xcoff --code-model=large < %s \
+; RUN:      | FileCheck %s --check-prefix=LARGE64
+
+@ThreadLocalVarInit = thread_local(localexec) global i64 1, align 8
+@VarInit = global i64 87, align 8
+@IThreadLocalVarUninit = internal thread_local(localexec) global i64 0, align 8
+@IThreadLocalVarInit = internal thread_local(localexec) global i64 1, align 8
+@ThreadLocalVarUninit = thread_local(localexec) global i64 0, align 8
+declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) #1
+
+define void @storeITLUninit(i64 noundef %x) {
+; SMALL64-LABEL: storeITLUninit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r4, L..C0(r2) # target-flags(ppc-tprel) @IThreadLocalVarUninit
+; SMALL64-NEXT:    add r4, r13, r4
+; SMALL64-NEXT:    std r3, 0(r4)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: storeITLUninit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r4, L..C0@u(r2)
+; LARGE64-NEXT:    ld r4, L..C0@l(r4)
+; LARGE64-NEXT:    add r4, r13, r4
+; LARGE64-NEXT:    std r3, 0(r4)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarUninit)
+  store i64 %x, ptr %0, align 8
+  ret void
+}
+
+define void @storeITLInit(i64 noundef %x) {
+; SMALL64-LABEL: storeITLInit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r4, L..C1(r2) # target-flags(ppc-tprel) @IThreadLocalVarInit
+; SMALL64-NEXT:    add r4, r13, r4
+; SMALL64-NEXT:    std r3, 0(r4)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: storeITLInit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r4, L..C1@u(r2)
+; LARGE64-NEXT:    ld r4, L..C1@l(r4)
+; LARGE64-NEXT:    add r4, r13, r4
+; LARGE64-NEXT:    std r3, 0(r4)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarInit)
+  store i64 %x, ptr %0, align 8
+  ret void
+}
+
+define void @storeTLUninit(i64 noundef %x) {
+; SMALL64-LABEL: storeTLUninit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r4, L..C2(r2) # target-flags(ppc-tprel) @ThreadLocalVarUninit
+; SMALL64-NEXT:    add r4, r13, r4
+; SMALL64-NEXT:    std r3, 0(r4)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: storeTLUninit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r4, L..C2@u(r2)
+; LARGE64-NEXT:    ld r4, L..C2@l(r4)
+; LARGE64-NEXT:    add r4, r13, r4
+; LARGE64-NEXT:    std r3, 0(r4)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarUninit)
+  store i64 %x, ptr %0, align 8
+  ret void
+}
+
+define void @storeTLInit(i64 noundef %x) {
+; SMALL64-LABEL: storeTLInit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r4, L..C3(r2) # target-flags(ppc-tprel) @ThreadLocalVarInit
+; SMALL64-NEXT:    add r4, r13, r4
+; SMALL64-NEXT:    std r3, 0(r4)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: storeTLInit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r4, L..C3@u(r2)
+; LARGE64-NEXT:    ld r4, L..C3@l(r4)
+; LARGE64-NEXT:    add r4, r13, r4
+; LARGE64-NEXT:    std r3, 0(r4)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarInit)
+  store i64 %x, ptr %0, align 8
+  ret void
+}
+
+define i64 @loadITLUninit() {
+; SMALL64-LABEL: loadITLUninit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C0(r2) # target-flags(ppc-tprel) @IThreadLocalVarUninit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    ld r3, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadITLUninit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C0@u(r2)
+; LARGE64-NEXT:    ld r3, L..C0@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    ld r3, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarUninit)
+  %1 = load i64, ptr %0, align 8
+  ret i64 %1
+}
+
+define i64 @loadITLUninit2() {
+; SMALL64-LABEL: loadITLUninit2:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C0(r2) # target-flags(ppc-tprel) @IThreadLocalVarUninit
+; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    ld r4, 0(r4)
+; SMALL64-NEXT:    ld r3, 0(r3)
+; SMALL64-NEXT:    add r3, r4, r3
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadITLUninit2:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C0@u(r2)
+; LARGE64-NEXT:    addis r4, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C0@l(r3)
+; LARGE64-NEXT:    ld r4, L..C4@l(r4)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    ld r4, 0(r4)
+; LARGE64-NEXT:    ld r3, 0(r3)
+; LARGE64-NEXT:    add r3, r4, r3
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarUninit)
+  %1 = load i64, ptr %0, align 8
+  %2 = load i64, ptr @VarInit, align 8
+  %add = add nsw i64 %2, %1
+  ret i64 %add
+}
+
+define i64 @loadITLInit() {
+; SMALL64-LABEL: loadITLInit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C1(r2) # target-flags(ppc-tprel) @IThreadLocalVarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    ld r3, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadITLInit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C1@u(r2)
+; LARGE64-NEXT:    ld r3, L..C1@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    ld r3, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarInit)
+  %1 = load i64, ptr %0, align 8
+  ret i64 %1
+}
+
+define i64 @loadITLInit2() {
+; SMALL64-LABEL: loadITLInit2:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C1(r2) # target-flags(ppc-tprel) @IThreadLocalVarInit
+; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    ld r4, 0(r4)
+; SMALL64-NEXT:    ld r3, 0(r3)
+; SMALL64-NEXT:    add r3, r4, r3
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadITLInit2:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C1@u(r2)
+; LARGE64-NEXT:    addis r4, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C1@l(r3)
+; LARGE64-NEXT:    ld r4, L..C4@l(r4)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    ld r4, 0(r4)
+; LARGE64-NEXT:    ld r3, 0(r3)
+; LARGE64-NEXT:    add r3, r4, r3
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarInit)
+  %1 = load i64, ptr %0, align 8
+  %2 = load i64, ptr @VarInit, align 8
+  %add = add nsw i64 %2, %1
+  ret i64 %add
+}
+
+define i64 @loadTLUninit() {
+; SMALL64-LABEL: loadTLUninit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C2(r2) # target-flags(ppc-tprel) @ThreadLocalVarUninit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    ld r3, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadTLUninit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C2@u(r2)
+; LARGE64-NEXT:    ld r3, L..C2@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    ld r3, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarUninit)
+  %1 = load i64, ptr %0, align 8
+  ret i64 %1
+}
+
+define i64 @loadTLUninit2() {
+; SMALL64-LABEL: loadTLUninit2:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C2(r2) # target-flags(ppc-tprel) @ThreadLocalVarUninit
+; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    ld r4, 0(r4)
+; SMALL64-NEXT:    ld r3, 0(r3)
+; SMALL64-NEXT:    add r3, r4, r3
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadTLUninit2:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C2@u(r2)
+; LARGE64-NEXT:    addis r4, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C2@l(r3)
+; LARGE64-NEXT:    ld r4, L..C4@l(r4)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    ld r4, 0(r4)
+; LARGE64-NEXT:    ld r3, 0(r3)
+; LARGE64-NEXT:    add r3, r4, r3
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarUninit)
+  %1 = load i64, ptr %0, align 8
+  %2 = load i64, ptr @VarInit, align 8
+  %add = add nsw i64 %2, %1
+  ret i64 %add
+}
+
+define i64 @loadTLInit() {
+; SMALL64-LABEL: loadTLInit:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C3(r2) # target-flags(ppc-tprel) @ThreadLocalVarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    ld r3, 0(r3)
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadTLInit:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C3@u(r2)
+; LARGE64-NEXT:    ld r3, L..C3@l(r3)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    ld r3, 0(r3)
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarInit)
+  %1 = load i64, ptr %0, align 8
+  ret i64 %1
+}
+
+define i64 @loadTLInit2() {
+; SMALL64-LABEL: loadTLInit2:
+; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C3(r2) # target-flags(ppc-tprel) @ThreadLocalVarInit
+; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    add r3, r13, r3
+; SMALL64-NEXT:    ld r4, 0(r4)
+; SMALL64-NEXT:    ld r3, 0(r3)
+; SMALL64-NEXT:    add r3, r4, r3
+; SMALL64-NEXT:    blr
+;
+; LARGE64-LABEL: loadTLInit2:
+; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C3@u(r2)
+; LARGE64-NEXT:    addis r4, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C3@l(r3)
+; LARGE64-NEXT:    ld r4, L..C4@l(r4)
+; LARGE64-NEXT:    add r3, r13, r3
+; LARGE64-NEXT:    ld r4, 0(r4)
+; LARGE64-NEXT:    ld r3, 0(r3)
+; LARGE64-NEXT:    add r3, r4, r3
+; LARGE64-NEXT:    blr
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarInit)
+  %1 = load i64, ptr %0, align 8
+  %2 = load i64, ptr @VarInit, align 8
+  %add = add nsw i64 %2, %1
+  ret i64 %add
+}
+
+; TOC Entry Checks.
+
+; SMALL64-LABEL: .toc
+; SMALL64-LABEL: L..C0:
+; SMALL64-NEXT: .tc IThreadLocalVarUninit[TC],IThreadLocalVarUninit[UL]@le
+; SMALL64-LABEL: L..C1:
+; SMALL64-NEXT: .tc IThreadLocalVarInit[TC],IThreadLocalVarInit[TL]@le
+; SMALL64-LABEL: L..C2:
+; SMALL64-NEXT: .tc ThreadLocalVarUninit[TC],ThreadLocalVarUninit[TL]@le
+; SMALL64-LABEL: L..C3:
+; SMALL64-NEXT: .tc ThreadLocalVarInit[TC],ThreadLocalVarInit[TL]@le
+; SMALL64-LABEL: L..C4:
+; SMALL64-NEXT: .tc VarInit[TC],VarInit[RW]
+
+; LARGE64-LABEL: .toc
+; LARGE64-LABEL: L..C0:
+; LARGE64-NEXT: .tc IThreadLocalVarUninit[TE],IThreadLocalVarUninit[UL]@le
+; LARGE64-LABEL: L..C1:
+; LARGE64-NEXT: .tc IThreadLocalVarInit[TE],IThreadLocalVarInit[TL]@le
+; LARGE64-LABEL: L..C2:
+; LARGE64-NEXT: .tc ThreadLocalVarUninit[TE],ThreadLocalVarUninit[TL]@le
+; LARGE64-LABEL: L..C3:
+; LARGE64-NEXT: .tc ThreadLocalVarInit[TE],ThreadLocalVarInit[TL]@le
+; LARGE64-LABEL: L..C4:
+; LARGE64-NEXT: .tc VarInit[TE],VarInit[RW]

llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large.ll

+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
+; RUN:     -xcoff-traceback-table=false --code-model=large -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=RELOC %s
+; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s
+; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s
+
+@ThreadLocalVarInit = thread_local(localexec) global i64 1, align 8
+@VarInit = global i64 87, align 8
+@IThreadLocalVarUninit = internal thread_local(localexec) global i64 0, align 8
+declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull)
+
+define void @storeITLUninit(i64 noundef %x) {
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarUninit)
+  store i64 %x, ptr %0, align 8
+  ret void
+}
+
+define i64 @loadTLInit() {
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarInit)
+  %1 = load i64, ptr %0, align 8
+  %2 = load i64, ptr @VarInit, align 8
+  %add = add nsw i64 %2, %1
+  ret i64 %add
+}
+
+; RELOC:      File: {{.*}}aix-tls-le-xcoff-reloc-large.ll.tmp.o
+; RELOC-NEXT: Format: aix5coff64-rs6000
+; RELOC-NEXT: Arch: powerpc64
+; RELOC-NEXT: AddressSize: 64bit
+; RELOC-NEXT: Relocations [
+; RELOC:       Virtual Address: 0x2
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (15)
+; RELOC-NEXT:       IsSigned: No
+; RELOC-NEXT:       FixupBitValue: 0
+; RELOC-NEXT:       Length: 16
+; RELOC-NEXT:       Type: R_TOCU (0x30)
+; RELOC-NEXT:     }
+; RELOC:       Virtual Address: 0x6
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (15)
+; RELOC-NEXT:       IsSigned: No
+; RELOC-NEXT:       FixupBitValue: 0
+; RELOC-NEXT:       Length: 16
+; RELOC-NEXT:       Type: R_TOCL (0x31)
+; RELOC-NEXT:     }
+; RELOC:       Virtual Address: 0x22
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (17)
+; RELOC-NEXT:       IsSigned: No
+; RELOC-NEXT:       FixupBitValue: 0
+; RELOC-NEXT:       Length: 16
+; RELOC-NEXT:       Type: R_TOCU (0x30)
+; RELOC-NEXT:     }
+; RELOC:       Virtual Address: 0x2A
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (17)
+; RELOC-NEXT:       IsSigned: No
+; RELOC-NEXT:       FixupBitValue: 0
+; RELOC-NEXT:       Length: 16
+; RELOC-NEXT:       Type: R_TOCL (0x31)
+; RELOC-NEXT:     }
+; RELOC:       Virtual Address: 0x80
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (23)
+; RELOC-NEXT:       IsSigned: No
+; RELOC-NEXT:       FixupBitValue: 0
+; RELOC-NEXT:       Length: 64
+; RELOC-NEXT:       Type: R_TLS_LE (0x23)
+; RELOC-NEXT:     }
+; RELOC:       Virtual Address: 0x88
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (21)
+; RELOC-NEXT:       IsSigned: No
+; RELOC-NEXT:       FixupBitValue: 0
+; RELOC-NEXT:       Length: 64
+; RELOC-NEXT:       Type: R_TLS_LE (0x23)
+; RELOC-NEXT:     }
+
+; SYM:      File: {{.*}}aix-tls-le-xcoff-reloc-large.ll.tmp.o
+; SYM-NEXT: Format: aix5coff64-rs6000
+; SYM-NEXT: Arch: powerpc64
+; SYM-NEXT: AddressSize: 64bit
+; SYM-NEXT: Symbols [
+; SYM:     Index: 15
+; SYM-NEXT:     Name: IThreadLocalVarUninit
+; SYM-NEXT:     Value (RelocatableAddress): 0x80
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 16
+; SYM-NEXT:       SectionLen: 8
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 3
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TE (0x16)
+; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM:     Index: 17
+; SYM-NEXT:     Name: ThreadLocalVarInit
+; SYM-NEXT:     Value (RelocatableAddress): 0x88
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 18
+; SYM-NEXT:       SectionLen: 8
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 3
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TE (0x16)
+; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM:     Index: 21
+; SYM-NEXT:     Name: ThreadLocalVarInit
+; SYM-NEXT:     Value (RelocatableAddress): 0x0
+; SYM-NEXT:     Section: .tdata
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_EXT (0x2)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 22
+; SYM-NEXT:       SectionLen: 8
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 3
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TL (0x14)
+; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM:     Index: 23
+; SYM-NEXT:     Name: IThreadLocalVarUninit
+; SYM-NEXT:     Value (RelocatableAddress): 0x8
+; SYM-NEXT:     Section: .tbss
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 24
+; SYM-NEXT:       SectionLen: 8
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 3
+; SYM-NEXT:       SymbolType: XTY_CM (0x3)
+; SYM-NEXT:       StorageMappingClass: XMC_UL (0x15)
+; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+
+; DIS:      {{.*}}aix-tls-le-xcoff-reloc-large.ll.tmp.o:  file format aix5coff64-rs6000
+; DIS:      Disassembly of section .text:
+; DIS:      0000000000000000 (idx: 3) .storeITLUninit:
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 4, 2, 0
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 15) IThreadLocalVarUninit[TE]
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 4, 0(4)
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 15) IThreadLocalVarUninit[TE]
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                add 4, 13, 4
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                std 3, 0(4)
+; DIS-NEXT:                                       blr
+; DIS:      0000000000000020 (idx: 5) .loadTLInit:
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 3, 2, 0
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 17) ThreadLocalVarInit[TE]
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 4, 2, 0
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 19) VarInit[TE]
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 3, 8(3)
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 17) ThreadLocalVarInit[TE]
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 4, 16(4)
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 19) VarInit[TE]
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                add 3, 13, 3
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 4, 0(4)
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 3, 0(3)
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                add 3, 4, 3
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                blr
+
+; DIS:      Disassembly of section .data:
+; DIS:      0000000000000048 (idx: 7) VarInit[RW]:
+; DIS-NEXT:       48: 00 00 00 00
+; DIS-NEXT:       4c: 00 00 00 57
+; DIS:      0000000000000050 (idx: 9) storeITLUninit[DS]:
+; DIS-NEXT:       50: 00 00 00 00
+; DIS-NEXT: 0000000000000050:  R_POS        (idx: 3) .storeITLUninit
+; DIS-NEXT:       54: 00 00 00 00
+; DIS-NEXT:       58: 00 00 00 00
+; DIS-NEXT: 0000000000000058:  R_POS        (idx: 13) TOC[TC0]
+; DIS-NEXT:       5c: 00 00 00 80
+; DIS:      0000000000000068 (idx: 11) loadTLInit[DS]:
+; DIS-NEXT:       68: 00 00 00 00
+; DIS-NEXT: 0000000000000068:  R_POS        (idx: 5) .loadTLInit
+; DIS-NEXT:       6c: 00 00 00 20
+; DIS-NEXT:       70: 00 00 00 00
+; DIS-NEXT: 0000000000000070:  R_POS        (idx: 13) TOC[TC0]
+; DIS-NEXT:       74: 00 00 00 80
+; DIS:      0000000000000080 (idx: 15) IThreadLocalVarUninit[TE]:
+; DIS-NEXT:       80: 00 00 00 00
+; DIS-NEXT: 0000000000000080:  R_TLS_LE     (idx: 23) IThreadLocalVarUninit[UL]
+; DIS-NEXT:       84: 00 00 00 00
+; DIS:      0000000000000088 (idx: 17) ThreadLocalVarInit[TE]:
+; DIS-NEXT:       88: 00 00 00 00
+; DIS-NEXT: 0000000000000088:  R_TLS_LE     (idx: 21) ThreadLocalVarInit[TL]
+; DIS-NEXT:       8c: 00 00 00 00
+; DIS:      0000000000000090 (idx: 19) VarInit[TE]:
+; DIS-NEXT:       90: 00 00 00 00
+; DIS-NEXT: 0000000000000090:  R_POS        (idx: 7) VarInit[RW]
+; DIS-NEXT:       94: 00 00 00 48
+
+; DIS:      Disassembly of section .tdata:
+; DIS:      0000000000000000 (idx: 21) ThreadLocalVarInit[TL]:
+; DIS-NEXT:        0: 00 00 00 00
+; DIS-NEXT:        4: 00 00 00 01
+
+; DIS:      Disassembly of section .tbss:
+; DIS:      0000000000000008 (idx: 23) IThreadLocalVarUninit[UL]:
+; DIS-NEXT: ...
+

llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll

+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
+; RUN:     -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=RELOC %s
+; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s
+; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s
+
+@ThreadLocalVarInit = thread_local(localexec) global i32 1, align 4
+@VarInit = global i32 87, align 4
+@IThreadLocalVarUninit = internal thread_local(localexec) global i32 0, align 4
+declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull)
+
+define void @storeITLUninit(i32 noundef signext %x) {
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @IThreadLocalVarUninit)
+  store i32 %x, ptr %0, align 4
+  ret void
+}
+
+define signext i32 @loadTLInit() {
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @ThreadLocalVarInit)
+  %1 = load i32, ptr %0, align 4
+  %2 = load i32, ptr @VarInit, align 4
+  %add = add nsw i32 %2, %1
+  ret i32 %add
+}
+
+; RELOC:      File: {{.*}}aix-tls-le-xcoff-reloc.ll.tmp.o
+; RELOC-NEXT: Format: aix5coff64-rs6000
+; RELOC-NEXT: Arch: powerpc64
+; RELOC-NEXT: AddressSize: 64bit
+; RELOC-NEXT: Relocations [
+; RELOC:       Virtual Address: 0x2
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (17)
+; RELOC-NEXT:       IsSigned: No
+; RELOC-NEXT:       FixupBitValue: 0
+; RELOC-NEXT:       Length: 16
+; RELOC-NEXT:       Type: R_TOC (0x3)
+; RELOC-NEXT:     }
+; RELOC:       Virtual Address: 0x12
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (19)
+; RELOC-NEXT:       IsSigned: No
+; RELOC-NEXT:       FixupBitValue: 0
+; RELOC-NEXT:       Length: 16
+; RELOC-NEXT:       Type: R_TOC (0x3)
+; RELOC-NEXT:     }
+; RELOC:       Virtual Address: 0x68
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (27)
+; RELOC-NEXT:       IsSigned: No
+; RELOC-NEXT:       FixupBitValue: 0
+; RELOC-NEXT:       Length: 64
+; RELOC-NEXT:       Type: R_TLS_LE (0x23)
+; RELOC-NEXT:     }
+; RELOC:       Virtual Address: 0x70
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (25)
+; RELOC-NEXT:       IsSigned: No
+; RELOC-NEXT:       FixupBitValue: 0
+; RELOC-NEXT:       Length: 64
+; RELOC-NEXT:       Type: R_TLS_LE (0x23)
+; RELOC-NEXT:     }
+
+; SYM:      File: {{.*}}aix-tls-le-xcoff-reloc.ll.tmp.o
+; SYM-NEXT: Format: aix5coff64-rs6000
+; SYM-NEXT: Arch: powerpc64
+; SYM-NEXT: AddressSize: 64bit
+; SYM-NEXT: Symbols [
+; SYM:     Index: 17
+; SYM-NEXT:     Name: IThreadLocalVarUninit
+; SYM-NEXT:     Value (RelocatableAddress): 0x68
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 18
+; SYM-NEXT:       SectionLen: 8
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 3
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TC (0x3)
+; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM:     Index: 19
+; SYM-NEXT:     Name: ThreadLocalVarInit
+; SYM-NEXT:     Value (RelocatableAddress): 0x70
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 20
+; SYM-NEXT:       SectionLen: 8
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 3
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TC (0x3)
+; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM:     Index: 25
+; SYM-NEXT:     Name: ThreadLocalVarInit
+; SYM-NEXT:     Value (RelocatableAddress): 0x0
+; SYM-NEXT:     Section: .tdata
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_EXT (0x2)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 26
+; SYM-NEXT:       ContainingCsectSymbolIndex: 23
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 0
+; SYM-NEXT:       SymbolType: XTY_LD (0x2)
+; SYM-NEXT:       StorageMappingClass: XMC_TL (0x14)
+; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM:     Index: 27
+; SYM-NEXT:     Name: IThreadLocalVarUninit
+; SYM-NEXT:     Value (RelocatableAddress): 0x4
+; SYM-NEXT:     Section: .tbss
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 28
+; SYM-NEXT:       SectionLen: 4
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_CM (0x3)
+; SYM-NEXT:       StorageMappingClass: XMC_UL (0x15)
+; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+
+; DIS:      {{.*}}aix-tls-le-xcoff-reloc.ll.tmp.o:  file format aix5coff64-rs6000
+; DIS:      Disassembly of section .text:
+; DIS:      0000000000000000 (idx: 3) .storeITLUninit:
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               ld 4, 0(2)
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 17) IThreadLocalVarUninit[TC]
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               add 4, 13, 4
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               stw 3, 0(4)
+; DIS-NEXT:                                      blr
+; DIS:      0000000000000010 (idx: 5) .loadTLInit:
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               ld 3, 8(2)
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 19) ThreadLocalVarInit[TC]
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               ld 4, 16(2)
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 21) VarInit[TC]
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               add 3, 13, 3
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               lwz 4, 0(4)
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               lwz 3, 0(3)
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               add 3, 4, 3
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               extsw 3, 3
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               blr
+
+; DIS:      Disassembly of section .data:
+; DIS:      0000000000000030 (idx: 9) VarInit:
+; DIS-NEXT:       30: 00 00 00 57
+; DIS:      0000000000000038 (idx: 11) storeITLUninit[DS]:
+; DIS-NEXT:       8: 00 00 00 00
+; DIS-NEXT: 0000000000000038:  R_POS        (idx: 3) .storeITLUninit
+; DIS-NEXT:       3c: 00 00 00 00
+; DIS-NEXT:       40: 00 00 00 00
+; DIS-NEXT: 0000000000000040:  R_POS        (idx: 15) TOC[TC0]
+; DIS-NEXT:       44: 00 00 00 68
+; DIS:      0000000000000050 (idx: 13) loadTLInit[DS]:
+; DIS-NEXT:       50: 00 00 00 00
+; DIS-NEXT: 0000000000000050:  R_POS        (idx: 5) .loadTLInit
+; DIS-NEXT:       54: 00 00 00 10
+; DIS-NEXT:       58: 00 00 00 00
+; DIS-NEXT: 0000000000000058:  R_POS        (idx: 15) TOC[TC0]
+; DIS-NEXT:       5c: 00 00 00 68
+; DIS:      0000000000000068 (idx: 17) IThreadLocalVarUninit[TC]:
+; DIS-NEXT:       68: 00 00 00 00
+; DIS-NEXT: 0000000000000068:  R_TLS_LE     (idx: 27) IThreadLocalVarUninit[UL]
+; DIS:      0000000000000070 (idx: 19) ThreadLocalVarInit[TC]:
+; DIS-NEXT:       70: 00 00 00 00
+; DIS-NEXT: 0000000000000070:  R_TLS_LE     (idx: 25) ThreadLocalVarInit
+; DIS:      0000000000000078 (idx: 21) VarInit[TC]:
+; DIS-NEXT:       78: 00 00 00 00
+; DIS-NEXT: 0000000000000078:  R_POS        (idx: 9) VarInit
+
+; DIS:      Disassembly of section .tdata:
+; DIS:      0000000000000000 (idx: 25) ThreadLocalVarInit:
+; DIS-NEXT:        0: 00 00 00 01
+
+; DIS:      Disassembly of section .tbss:
+; DIS:      0000000000000004 (idx: 27) IThreadLocalVarUninit[UL]:
+; DIS-NEXT: ...
+