[AIX][TLS] Generate .extern and .ref references to __tls_get_addr for local-exec accesses.

[amyk]

Summary

Compiling with TLS variables requires -pthread, but if the user omits this option, the
compiler will not show any obvious indication during compilation that -pthread is
needed for programs using TLS variables. Instead, the user will experience a segmentation
fault when running programs with TLS variables in them and without specifying -pthread.

This patch aims to generate .extern/.ref references to __tls_get_addr[DS] for local-exec
accesses, in order to trigger an error from the linker to indicate that there is an undefined
symbol to __tls_get_addr. Doing so will remind the user to compile/link with -pthread.

[amyk]

Rebased patch.

[DiggerLin]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

2822

I do not think it is efficient to put the code here. if there are a lot of thread local variables or the variables are reference in a lot of places, the code run enter as many time as the the number of thread local variable reference place.

and each time do the same thing

MCSymbol *TlsGetAddrDescriptor =
     createMCSymbolForTlsGetAddr(OutContext, XCOFF::XMC_DS);
 ExtSymSDNodeSymbols.insert(TlsGetAddrDescriptor);

can we do it in the function PPCAIXAsmPrinter::doFinalization()

for (auto &I : TOC) {
    // Add a single .ref reference to __tls_get_addr[DS] for the local-exec TLS
    // model on AIX. For TLS models that do not generate calls to TLS functions,
    // this .ref reference to __tls_get_addr helps generate a linker error to
    // an undefined symbol to __tls_get_addr, which indicates to the user that
    // compiling with -pthread is required for programs that use TLS variables.
    if (Subtarget->isPPC64() &&
        (I.first.second == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSLE)) {
      MCSymbol *TlsGetAddrDescriptor =
          createMCSymbolForTlsGetAddr(OutContext, XCOFF::XMC_DS);

      ExtSymSDNodeSymbols.insert(TlsGetAddrDescriptor);

      OutStreamer->emitXCOFFRefDirective(TlsGetAddrDescriptor);
      break;
    }
  }

for (MCSymbol *Sym : ExtSymSDNodeSymbols)
    OutStreamer->emitSymbolAttribute(Sym, MCSA_Extern);

it will run only once.

[DiggerLin]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

2897

if there is not a __thread variable or there is not local exec mode, the loop will go over all the TC entries(the TC entries maybe a large number). if it is not efficient.

can we add a new data number "bool hasRefGetTLSAddr" for PPCAsmPrinter. ?

and set the "hasRefGetTLSAddr" in the lambda function
auto GetVKForMO = [&](const MachineOperand &MO) or other place ?

for example , change your code in the patch D149722 to

auto GetVKForMO = [&](const MachineOperand &MO) {
    // For TLS local-exec accesses on AIX, we have one TOC entry for the symbol
    // (with the variable offset), which is differentiated by MO_TPREL_FLAG.
    if (MO.getTargetFlags() & PPCII::MO_TPREL_FLAG) {
      // TODO: Update the query and the comment above to add a check for initial
      // exec when this TLS model is supported on AIX in the future, as both
      // local-exec and initial-exec can use MO_TPREL_FLAG.
      assert(MO.isGlobal() && "Only expecting a global MachineOperand here!\n");
      TLSModel::Model Model = TM.getTLSModel(MO.getGlobal());
      if (Model == TLSModel::LocalExec) {

        hasRefGetTLSAddr =true;

        return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSLE;
      }
      llvm_unreachable("Only expecting local-exec accesses!");
    }

and change the code here to

if (hasRefGetTLSAddr )  {
   MCSymbol *TlsGetAddrDescriptor =
          createMCSymbolForTlsGetAddr(OutContext, XCOFF::XMC_DS);

  ExtSymSDNodeSymbols.insert(TlsGetAddrDescriptor);
  OutStreamer->emitXCOFFRefDirective(TlsGetAddrDescriptor);
}

for (MCSymbol *Sym : ExtSymSDNodeSymbols)
    OutStreamer->emitSymbolAttribute(Sym, MCSA_Extern);

[amyk]

Address Digger's review comments of adding a boolean HasRefGetTLSAddr to control whether or not to emit the reference.

[amyk]

Rebase patch and update relocation tests after the test case updates in D149722 and D152669.

[amyk]

Rebase patch.

[amyk]

Ping.
@DiggerLin @Esme Do any of you have any comments regarding this patch?

[DiggerLin]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

632

change to

SymName = SMC == XCOFF::XMC_DS  ? "__tls_get_addr" : .__tls_get_addr ;

2887

I know that any value of non PPC::GETtlsTpointer32AIX is OK here
but why it is PPC::LDtoc here ? can we use "PPC::GETtlsADDR" here ?

[DiggerLin]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

2887

use PPC::GETtlsADDR64AIX maybe more specific.

[amyk]

Rebase patch and address review comments from @DiggerLin.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

2887

Yeah, that's a good point. I just needed any other opcode and just chose PPC::LDtoc as that is the instruction that I was adding it to (since we have a load from the TOC in 64-bit local-exec).
That being said, using that opcode also makes sense to me since we're creating a reference to __tls_get_addr to begin with.

[DiggerLin]

LGTM.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

enum TOCEntryType {
     TOCType_GlobalExternal,
     TOCType_GlobalInternal,
     TOCType_JumpTable,
     TOCType_ThreadLocal,
     TOCType_BlockAddress,
     TOCType_EHBlock
   };
 
+  // Controls whether or not to emit a .ref reference to __tls_get_addr.
+  // This is currently used for TLS models that do not generate calls to
+  // TLS functions, such as for the local-exec model on AIX 64-bit.
+  bool HasRefGetTLSAddr = false;
+
   MCSymbol *lookUpOrCreateTOCEntry(const MCSymbol *Sym, TOCEntryType Type,
                                    MCSymbolRefExpr::VariantKind Kind =
                                        MCSymbolRefExpr::VariantKind::VK_None);
 
   bool doInitialization(Module &M) override {
     if (!TOC.empty())
       TOC.clear();
     return AsmPrinter::doInitialization(M);
assert((NumBytes - EncodedBytes) % 4 == 0 &&
          "Invalid number of NOP bytes requested!");
   for (unsigned i = EncodedBytes; i < NumBytes; i += 4)
     EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::NOP));
 }
 
 /// This helper function creates the TlsGetAddr MCSymbol for AIX. We will
 /// create the csect and use the qual-name symbol instead of creating just the
 /// external symbol.
-static MCSymbol *createMCSymbolForTlsGetAddr(MCContext &Ctx, unsigned MIOpc) {
-  StringRef SymName =
-      MIOpc == PPC::GETtlsTpointer32AIX ? ".__get_tpointer" : ".__tls_get_addr";
+static MCSymbol *
+createMCSymbolForTlsGetAddr(MCContext &Ctx, unsigned MIOpc,
+                            XCOFF::StorageMappingClass SMC = XCOFF::XMC_PR) {
+  StringRef SymName;
+  if (MIOpc == PPC::GETtlsTpointer32AIX)
+    SymName = ".__get_tpointer";
+  else
+    SymName = (SMC == XCOFF::XMC_DS) ? "__tls_get_addr" : ".__tls_get_addr";
   return Ctx
       .getXCOFFSection(SymName, SectionKind::getText(),
-                       XCOFF::CsectProperties(XCOFF::XMC_PR, XCOFF::XTY_ER))
+                       XCOFF::CsectProperties(SMC, XCOFF::XTY_ER))
       ->getQualNameSymbol();
 }
 
 void PPCAsmPrinter::EmitAIXTlsCallHelper(const MachineInstr *MI) {
   assert(Subtarget->isAIXABI() &&
          "Only expecting to emit calls to get the thread pointer on AIX!");
 
   MCSymbol *TlsCall = createMCSymbolForTlsGetAddr(OutContext, MI->getOpcode());
#endif
   };
   auto GetVKForMO = [&](const MachineOperand &MO) {
     // For TLS initial-exec and local-exec accesses on AIX, we have one TOC
     // entry for the symbol (with the variable offset), which is differentiated
     // by MO_TPREL_FLAG.
     if (MO.getTargetFlags() & PPCII::MO_TPREL_FLAG) {
       assert(MO.isGlobal() && "Only expecting a global MachineOperand here!\n");
       TLSModel::Model Model = TM.getTLSModel(MO.getGlobal());
-      if (Model == TLSModel::LocalExec)
+      if (Model == TLSModel::LocalExec) {
+        if (IsPPC64)
+          HasRefGetTLSAddr = true;
         return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSLE;
+      }
       if (Model == TLSModel::InitialExec)
         return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSIE;
       llvm_unreachable("Only expecting local-exec or initial-exec accesses!");
     }
     // For GD TLS access on AIX, we have two TOC entries for the symbol (one for
     // the variable offset and the other for the region handle). They are
     // differentiated by MO_TLSGD_FLAG and MO_TLSGDM_FLAG.
     if (MO.getTargetFlags() & PPCII::MO_TLSGDM_FLAG)
case PPC::TDI: {
     OutStreamer->emitXCOFFExceptDirective(CurrentFnSym, TempSym,
                  LangMO.getImm(), ReasonMO.getImm(),
                  Subtarget->isPPC64() ? MI->getMF()->getInstructionCount() * 8 :
                  MI->getMF()->getInstructionCount() * 4,
      MMI->hasDebugInfo());
     break;
   }
   case PPC::GETtlsTpointer32AIX:
   case PPC::GETtlsADDR64AIX:
   case PPC::GETtlsADDR32AIX: {
     // A reference to .__tls_get_addr/.__get_tpointer is unknown to the
     // assembler so we need to emit an external symbol reference.
     MCSymbol *TlsGetAddr =
         createMCSymbolForTlsGetAddr(OutContext, MI->getOpcode());
     ExtSymSDNodeSymbols.insert(TlsGetAddr);
     break;
   }

 }
 
 bool PPCAIXAsmPrinter::doFinalization(Module &M) {
   // Do streamer related finalization for DWARF.
   if (!MAI->usesDwarfFileAndLocDirectives() && MMI->hasDebugInfo())
     OutStreamer->doFinalizationAtSectionEnd(
         OutStreamer->getContext().getObjectFileInfo()->getTextSection());
 
+  // Add a single .ref reference to __tls_get_addr[DS] for the local-exec TLS
+  // model on AIX 64-bit. For TLS models that do not generate calls to TLS
+  // functions, this reference to __tls_get_addr helps generate a linker error
+  // to an undefined symbol to __tls_get_addr, which indicates to the user that
+  // compiling with -pthread is required for programs that use TLS variables.
+  if (HasRefGetTLSAddr) {
+    // Specifically for 64-bit AIX, a load from the TOC is generated to load
+    // the variable offset needed for local-exec accesses.
+    MCSymbol *TlsGetAddrDescriptor =
+        createMCSymbolForTlsGetAddr(OutContext, PPC::GETtlsADDR64AIX,
+                                    XCOFF::XMC_DS);
+
+    ExtSymSDNodeSymbols.insert(TlsGetAddrDescriptor);
+    OutStreamer->emitXCOFFRefDirective(TlsGetAddrDescriptor);
+  }
+
   for (MCSymbol *Sym : ExtSymSDNodeSymbols)
     OutStreamer->emitSymbolAttribute(Sym, MCSA_Extern);
   return PPCAsmPrinter::doFinalization(M);
 }
 
 static unsigned mapToSinitPriority(int P) {
   if (P < 0 || P > 65535)
     report_fatal_error("invalid init priority");
 
   if (P <= 20)
     return P;
 

llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-double.ll

 entry:
   %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarInit)
   %1 = load double, ptr %0, align 8
   %2 = load double, ptr @VarInit, align 8
   %add = fadd double %1, %2
   ret double %add
 }
 
+; (64-bit only) External symbol reference checks for __tls_get_addr[DS]
+
+; SMALL64: .ref __tls_get_addr[DS]
+; SMALL64: .extern __tls_get_addr[DS]
+; LARGE64: .ref __tls_get_addr[DS]
+; LARGE64: .extern __tls_get_addr[DS]
+
 ; TOC Entry Checks.
 
 ; SMALL64-LABEL: .toc
 ; SMALL64-LABEL: L..C0:
 ; SMALL64-NEXT: .tc IThreadLocalVarUninit[TC],IThreadLocalVarUninit[UL]@le
 ; SMALL64-LABEL: L..C1:
 ; SMALL64-NEXT: .tc IThreadLocalVarInit[TC],IThreadLocalVarInit[TL]@le
 ; SMALL64-LABEL: L..C2:

llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-float.ll

 entry:
   %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @ThreadLocalVarInit)
   %1 = load float, ptr %0, align 4
   %2 = load float, ptr @VarInit, align 4
   %add = fadd float %1, %2
   ret float %add
 }
 
+; (64-bit only) External symbol reference checks for __tls_get_addr[DS]
+
+; SMALL64: .ref __tls_get_addr[DS]
+; SMALL64: .extern __tls_get_addr[DS]
+; LARGE64: .ref __tls_get_addr[DS]
+; LARGE64: .extern __tls_get_addr[DS]
+
 ; TOC Entry Checks.
 
 ; SMALL64-LABEL: .toc
 ; SMALL64-LABEL: L..C0:
 ; SMALL64-NEXT: .tc IThreadLocalVarUninit[TC],IThreadLocalVarUninit[UL]@le
 ; SMALL64-LABEL: L..C1:
 ; SMALL64-NEXT: .tc IThreadLocalVarInit[TC],IThreadLocalVarInit[TL]@le
 ; SMALL64-LABEL: L..C2:

llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-int.ll

 entry:
   %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @ThreadLocalVarInit)
   %1 = load i32, ptr %0, align 4
   %2 = load i32, ptr @VarInit, align 4
   %add = add nsw i32 %2, %1
   ret i32 %add
 }
 
+; (64-bit only) External symbol reference checks for __tls_get_addr[DS]
+
+; SMALL64: .ref __tls_get_addr[DS]
+; SMALL64: .extern __tls_get_addr[DS]
+; LARGE64: .ref __tls_get_addr[DS]
+; LARGE64: .extern __tls_get_addr[DS]
+
 ; TOC Entry Checks.
 
 ; SMALL64-LABEL: .toc
 ; SMALL64-LABEL: L..C0:
 ; SMALL64-NEXT: .tc IThreadLocalVarUninit[TC],IThreadLocalVarUninit[UL]@le
 ; SMALL64-LABEL: L..C1:
 ; SMALL64-NEXT: .tc IThreadLocalVarInit[TC],IThreadLocalVarInit[TL]@le
 ; SMALL64-LABEL: L..C2:

llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-longlong.ll

 entry:
   %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarInit)
   %1 = load i64, ptr %0, align 8
   %2 = load i64, ptr @VarInit, align 8
   %add = add nsw i64 %2, %1
   ret i64 %add
 }
 
+; (64-bit only) External symbol reference checks for __tls_get_addr[DS]
+
+; SMALL64: .ref __tls_get_addr[DS]
+; SMALL64: .extern __tls_get_addr[DS]
+; LARGE64: .ref __tls_get_addr[DS]
+; LARGE64: .extern __tls_get_addr[DS]
+
 ; TOC Entry Checks.
 
 ; SMALL64-LABEL: .toc
 ; SMALL64-LABEL: L..C0:
 ; SMALL64-NEXT: .tc IThreadLocalVarUninit[TC],IThreadLocalVarUninit[UL]@le
 ; SMALL64-LABEL: L..C1:
 ; SMALL64-NEXT: .tc IThreadLocalVarInit[TC],IThreadLocalVarInit[TL]@le
 ; SMALL64-LABEL: L..C2:

llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large.ll

 }
 
 ; RELOC:      File: {{.*}}aix-tls-le-xcoff-reloc-large.ll.tmp.o
 ; RELOC-NEXT: Format: aix5coff64-rs6000
 ; RELOC-NEXT: Arch: powerpc64
 ; RELOC-NEXT: AddressSize: 64bit
 ; RELOC-NEXT: Relocations [
 ; RELOC:       Virtual Address: 0x2
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (19)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (21)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOCU (0x30)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x6
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (19)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (21)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOCL (0x31)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x12
-; RELOC-NEXT:       Symbol: ThreadLocalVarInit (21)
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (23)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOCU (0x30)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x1A
-; RELOC-NEXT:       Symbol: ThreadLocalVarInit (21)
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (23)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOCL (0x31)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x36
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (25)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (27)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOCU (0x30)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x42
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (25)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (27)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOCL (0x31)
 ; RELOC-NEXT:     }
+; RELOC:      Virtual Address: 0x0
+; RELOC-NEXT:      Symbol: __tls_get_addr (1)
+; RELOC-NEXT:      IsSigned: No
+; RELOC-NEXT:      FixupBitValue: 0
+; RELOC-NEXT:      Length: 1
+; RELOC-NEXT:      Type: R_REF (0xF)
+; RELOC-NEXT:    }
 ; RELOC:       Virtual Address: 0xA8
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (29)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (31)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 64
 ; RELOC-NEXT:       Type: R_TLS_LE (0x23)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0xB0
-; RELOC-NEXT:       Symbol: ThreadLocalVarInit (27)
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (29)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 64
 ; RELOC-NEXT:       Type: R_TLS_LE (0x23)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0xC0
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (31)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (33)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 64
 ; RELOC-NEXT:       Type: R_TLS_LE (0x23)
 ; RELOC-NEXT:     }
 
 ; SYM:      File: {{.*}}aix-tls-le-xcoff-reloc-large.ll.tmp.o
 ; SYM-NEXT: Format: aix5coff64-rs6000
 ; SYM-NEXT: Arch: powerpc64
 ; SYM-NEXT: AddressSize: 64bit
 ; SYM-NEXT: Symbols [
-; SYM:     Index: 19
+; SYM:    Index: 1
+; SYM-NEXT:    Name: __tls_get_addr
+; SYM-NEXT:    Value (RelocatableAddress): 0x0
+; SYM-NEXT:    Section: N_UNDEF
+; SYM-NEXT:    Type: 0x0
+; SYM-NEXT:    StorageClass: C_EXT (0x2)
+; SYM-NEXT:    NumberOfAuxEntries: 1
+; SYM-NEXT:    CSECT Auxiliary Entry {
+; SYM-NEXT:      Index: 2
+; SYM-NEXT:      SectionLen: 0
+; SYM-NEXT:      ParameterHashIndex: 0x0
+; SYM-NEXT:      TypeChkSectNum: 0x0
+; SYM-NEXT:      SymbolAlignmentLog2: 0
+; SYM-NEXT:      SymbolType: XTY_ER (0x0)
+; SYM-NEXT:      StorageMappingClass: XMC_DS (0xA)
+; SYM-NEXT:      Auxiliary Type: AUX_CSECT (0xFB)
+; SYM-NEXT:    }
+; SYM-NEXT:  }
+; SYM:     Index: 21
 ; SYM-NEXT:     Name: IThreadLocalVarUninit
 ; SYM-NEXT:     Value (RelocatableAddress): 0xA8
 ; SYM-NEXT:     Section: .data
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 20
+; SYM-NEXT:       Index: 22
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 3
 ; SYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; SYM-NEXT:       StorageMappingClass: XMC_TE (0x16)
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 21
+; SYM:     Index: 23
 ; SYM-NEXT:     Name: ThreadLocalVarInit
 ; SYM-NEXT:     Value (RelocatableAddress): 0xB0
 ; SYM-NEXT:     Section: .data
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 22
+; SYM-NEXT:       Index: 24
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 3
 ; SYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; SYM-NEXT:       StorageMappingClass: XMC_TE (0x16)
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
-; SYM:     Index: 25
+; SYM:     Index: 27
 ; SYM-NEXT:     Name: IThreadLocalVarUninit2
 ; SYM-NEXT:     Value (RelocatableAddress): 0xC0
 ; SYM-NEXT:     Section: .data
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 26
+; SYM-NEXT:       Index: 28
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 3
 ; SYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; SYM-NEXT:       StorageMappingClass: XMC_TE (0x16)
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 27
+; SYM:     Index: 29
 ; SYM-NEXT:     Name: ThreadLocalVarInit
 ; SYM-NEXT:     Value (RelocatableAddress): 0x0
 ; SYM-NEXT:     Section: .tdata
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_EXT (0x2)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 28
+; SYM-NEXT:       Index: 30
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 3
 ; SYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; SYM-NEXT:       StorageMappingClass: XMC_TL (0x14)
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 29
+; SYM:     Index: 31
 ; SYM-NEXT:     Name: IThreadLocalVarUninit
 ; SYM-NEXT:     Value (RelocatableAddress): 0x8
 ; SYM-NEXT:     Section: .tbss
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 30
+; SYM-NEXT:       Index: 32
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 3
 ; SYM-NEXT:       SymbolType: XTY_CM (0x3)
 ; SYM-NEXT:       StorageMappingClass: XMC_UL (0x15)
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 31
+; SYM:     Index: 33
 ; SYM-NEXT:     Name: IThreadLocalVarUninit2
 ; SYM-NEXT:     Value (RelocatableAddress): 0x10
 ; SYM-NEXT:     Section: .tbss
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 32
+; SYM-NEXT:       Index: 34
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 3
 ; SYM-NEXT:       SymbolType: XTY_CM (0x3)
 ; SYM-NEXT:       StorageMappingClass: XMC_UL (0x15)
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
 
 ; DIS:      {{.*}}aix-tls-le-xcoff-reloc-large.ll.tmp.o:  file format aix5coff64-rs6000
 ; DIS:      Disassembly of section .text:
-; DIS:      0000000000000000 (idx: 3) .storeITLUninit:
+; DIS:      0000000000000000 (idx: 5) .storeITLUninit:
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 4, 2, 0
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 19) IThreadLocalVarUninit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR]]:     R_REF  (idx: 1)  __tls_get_addr[DS]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 21) IThreadLocalVarUninit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 4, 0(4)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 19) IThreadLocalVarUninit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 21) IThreadLocalVarUninit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                stdx 3, 13, 4
 ; DIS-NEXT:                                       blr
-; DIS:      0000000000000010 (idx: 5) .loadTLInit:
+; DIS:      0000000000000010 (idx: 7) .loadTLInit:
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 3, 2, 0
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 21) ThreadLocalVarInit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 23) ThreadLocalVarInit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 4, 2, 0
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 23) VarInit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 25) VarInit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 3, 8(3)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 21) ThreadLocalVarInit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 23) ThreadLocalVarInit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 4, 16(4)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 23) VarInit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 25) VarInit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ldx 3, 13, 3
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 4, 0(4)
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                add 3, 4, 3
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                blr
-; DIS:      0000000000000030 (idx: 7) .loadTLUninit:
+; DIS:      0000000000000030 (idx: 9) .loadTLUninit:
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 3, 2, 0
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 19) IThreadLocalVarUninit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 21) IThreadLocalVarUninit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 4, 2, 0
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 25) IThreadLocalVarUninit2[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 27) IThreadLocalVarUninit2[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                li 5, 1
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 3, 0(3)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 19) IThreadLocalVarUninit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 21) IThreadLocalVarUninit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 4, 24(4)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 25) IThreadLocalVarUninit2[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 27) IThreadLocalVarUninit2[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                stdx 5, 13, 3
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ldx 3, 13, 4
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addi 3, 3, 1
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                blr
 
 ; DIS:      Disassembly of section .data:
-; DIS:      0000000000000058 (idx: 9) VarInit[RW]:
+; DIS:      0000000000000058 (idx: 11) VarInit[RW]:
 ; DIS-NEXT:       58: 00 00 00 00
 ; DIS-NEXT:       5c: 00 00 00 57
-; DIS:      0000000000000060 (idx: 11) storeITLUninit[DS]:
+; DIS:      0000000000000060 (idx: 13) storeITLUninit[DS]:
 ; DIS-NEXT:       60: 00 00 00 00
-; DIS-NEXT: 0000000000000060:  R_POS        (idx: 3) .storeITLUninit
+; DIS-NEXT: 0000000000000060:  R_POS        (idx: 5) .storeITLUninit
 ; DIS-NEXT:       64: 00 00 00 00
 ; DIS-NEXT:       68: 00 00 00 00
-; DIS-NEXT: 0000000000000068:  R_POS        (idx: 17) TOC[TC0]
+; DIS-NEXT: 0000000000000068:  R_POS        (idx: 19) TOC[TC0]
 ; DIS-NEXT:       6c: 00 00 00 a8
-; DIS:      0000000000000078 (idx: 13) loadTLInit[DS]:
+; DIS:      0000000000000078 (idx: 15) loadTLInit[DS]:
 ; DIS-NEXT:       78: 00 00 00 00
-; DIS-NEXT: 0000000000000078:  R_POS        (idx: 5) .loadTLInit
+; DIS-NEXT: 0000000000000078:  R_POS        (idx: 7) .loadTLInit
 ; DIS-NEXT:       7c: 00 00 00 10
 ; DIS-NEXT:       80: 00 00 00 00
-; DIS-NEXT: 0000000000000080:  R_POS        (idx: 17) TOC[TC0]
+; DIS-NEXT: 0000000000000080:  R_POS        (idx: 19) TOC[TC0]
 ; DIS-NEXT:       84: 00 00 00 a8
-; DIS:      0000000000000090 (idx: 15) loadTLUninit[DS]:
+; DIS:      0000000000000090 (idx: 17) loadTLUninit[DS]:
 ; DIS-NEXT:       90: 00 00 00 00
-; DIS-NEXT: 0000000000000090:  R_POS        (idx: 7) .loadTLUninit
+; DIS-NEXT: 0000000000000090:  R_POS        (idx: 9) .loadTLUninit
 ; DIS-NEXT:       94: 00 00 00 30
 ; DIS-NEXT:       98: 00 00 00 00
-; DIS-NEXT: 0000000000000098:  R_POS        (idx: 17) TOC[TC0]
+; DIS-NEXT: 0000000000000098:  R_POS        (idx: 19) TOC[TC0]
 ; DIS-NEXT:       9c: 00 00 00 a8
-; DIS:      00000000000000a8 (idx: 19) IThreadLocalVarUninit[TE]:
+; DIS:      00000000000000a8 (idx: 21) IThreadLocalVarUninit[TE]:
 ; DIS-NEXT:       a8: 00 00 00 00
-; DIS-NEXT: 00000000000000a8:  R_TLS_LE     (idx: 29) IThreadLocalVarUninit[UL]
+; DIS-NEXT: 00000000000000a8:  R_TLS_LE     (idx: 31) IThreadLocalVarUninit[UL]
 ; DIS-NEXT:       ac: 00 00 00 08
-; DIS:      00000000000000b0 (idx: 21) ThreadLocalVarInit[TE]:
+; DIS:      00000000000000b0 (idx: 23) ThreadLocalVarInit[TE]:
 ; DIS-NEXT:       b0: 00 00 00 00
-; DIS-NEXT: 00000000000000b0:  R_TLS_LE     (idx: 27) ThreadLocalVarInit[TL]
+; DIS-NEXT: 00000000000000b0:  R_TLS_LE     (idx: 29) ThreadLocalVarInit[TL]
 ; DIS-NEXT:       b4: 00 00 00 00
-; DIS:      00000000000000b8 (idx: 23) VarInit[TE]:
+; DIS:      00000000000000b8 (idx: 25) VarInit[TE]:
 ; DIS-NEXT:       b8: 00 00 00 00
-; DIS-NEXT: 00000000000000b8:  R_POS        (idx: 9) VarInit[RW]
+; DIS-NEXT: 00000000000000b8:  R_POS        (idx: 11) VarInit[RW]
 ; DIS-NEXT:       bc: 00 00 00 58
-; DIS:      00000000000000c0 (idx: 25) IThreadLocalVarUninit2[TE]:
+; DIS:      00000000000000c0 (idx: 27) IThreadLocalVarUninit2[TE]:
 ; DIS-NEXT:       c0: 00 00 00 00
-; DIS-NEXT: 00000000000000c0:  R_TLS_LE     (idx: 31) IThreadLocalVarUninit2[UL]
+; DIS-NEXT: 00000000000000c0:  R_TLS_LE     (idx: 33) IThreadLocalVarUninit2[UL]
 ; DIS-NEXT:       c4: 00 00 00 10
 
 ; DIS:      Disassembly of section .tdata:
-; DIS:      0000000000000000 (idx: 27) ThreadLocalVarInit[TL]:
+; DIS:      0000000000000000 (idx: 29) ThreadLocalVarInit[TL]:
 ; DIS-NEXT:        0: 00 00 00 00
 ; DIS-NEXT:        4: 00 00 00 01
 
 ; DIS:      Disassembly of section .tbss:
-; DIS:      0000000000000008 (idx: 29) IThreadLocalVarUninit[UL]:
+; DIS:      0000000000000008 (idx: 31) IThreadLocalVarUninit[UL]:
 ; DIS-NEXT: ...
-; DIS:      0000000000000010 (idx: 31) IThreadLocalVarUninit2[UL]:
+; DIS:      0000000000000010 (idx: 33) IThreadLocalVarUninit2[UL]:
 ; DIS-NEXT: ...
 

llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll

 }
 
 ; RELOC:      File: {{.*}}aix-tls-le-xcoff-reloc.ll.tmp.o
 ; RELOC-NEXT: Format: aix5coff64-rs6000
 ; RELOC-NEXT: Arch: powerpc64
 ; RELOC-NEXT: AddressSize: 64bit
 ; RELOC-NEXT: Relocations [
 ; RELOC:       Virtual Address: 0x2
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (21)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (23)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOC (0x3)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x12
-; RELOC-NEXT:       Symbol: ThreadLocalVarInit (23)
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (25)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOC (0x3)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x36
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (27)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (29)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOC (0x3)
 ; RELOC-NEXT:     }
+; RELOC:      Virtual Address: 0x0
+; RELOC-NEXT:      Symbol: __tls_get_addr (1)
+; RELOC-NEXT:      IsSigned: No
+; RELOC-NEXT:      FixupBitValue: 0
+; RELOC-NEXT:      Length: 1
+; RELOC-NEXT:      Type: R_REF (0xF)
+; RELOC-NEXT:    }
 ; RELOC:       Virtual Address: 0xA0
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (33)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (35)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 64
 ; RELOC-NEXT:       Type: R_TLS_LE (0x23)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0xA8
-; RELOC-NEXT:       Symbol: ThreadLocalVarInit (31)
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (33)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 64
 ; RELOC-NEXT:       Type: R_TLS_LE (0x23)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0xB8
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (35)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (37)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 64
 ; RELOC-NEXT:       Type: R_TLS_LE (0x23)
 ; RELOC-NEXT:     }
 
 ; SYM:      File: {{.*}}aix-tls-le-xcoff-reloc.ll.tmp.o
 ; SYM-NEXT: Format: aix5coff64-rs6000
 ; SYM-NEXT: Arch: powerpc64
 ; SYM-NEXT: AddressSize: 64bit
 ; SYM-NEXT: Symbols [
-; SYM:     Index: 21
+; SYM:    Index: 1
+; SYM-NEXT:    Name: __tls_get_addr
+; SYM-NEXT:    Value (RelocatableAddress): 0x0
+; SYM-NEXT:    Section: N_UNDEF
+; SYM-NEXT:    Type: 0x0
+; SYM-NEXT:    StorageClass: C_EXT (0x2)
+; SYM-NEXT:    NumberOfAuxEntries: 1
+; SYM-NEXT:    CSECT Auxiliary Entry {
+; SYM-NEXT:      Index: 2
+; SYM-NEXT:      SectionLen: 0
+; SYM-NEXT:      ParameterHashIndex: 0x0
+; SYM-NEXT:      TypeChkSectNum: 0x0
+; SYM-NEXT:      SymbolAlignmentLog2: 0
+; SYM-NEXT:      SymbolType: XTY_ER (0x0)
+; SYM-NEXT:      StorageMappingClass: XMC_DS (0xA)
+; SYM-NEXT:      Auxiliary Type: AUX_CSECT (0xFB)
+; SYM-NEXT:    }
+; SYM-NEXT:  }
+; SYM:     Index: 23
 ; SYM-NEXT:     Name: IThreadLocalVarUninit
 ; SYM-NEXT:     Value (RelocatableAddress): 0xA0
 ; SYM-NEXT:     Section: .data
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 22
+; SYM-NEXT:       Index: 24
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 3
 ; SYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; SYM-NEXT:       StorageMappingClass: XMC_TC (0x3)
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 23
+; SYM:     Index: 25
 ; SYM-NEXT:     Name: ThreadLocalVarInit
 ; SYM-NEXT:     Value (RelocatableAddress): 0xA8
 ; SYM-NEXT:     Section: .data
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 24
+; SYM-NEXT:       Index: 26
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 3
 ; SYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; SYM-NEXT:       StorageMappingClass: XMC_TC (0x3)
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 27
+; SYM:     Index: 29
 ; SYM-NEXT:     Name: IThreadLocalVarUninit2
 ; SYM-NEXT:     Value (RelocatableAddress): 0xB8
 ; SYM-NEXT:     Section: .data
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 28
+; SYM-NEXT:       Index: 30
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 3
 ; SYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; SYM-NEXT:       StorageMappingClass: XMC_TC (0x3)
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 31
+; SYM:     Index: 33
 ; SYM-NEXT:     Name: ThreadLocalVarInit
 ; SYM-NEXT:     Value (RelocatableAddress): 0x0
 ; SYM-NEXT:     Section: .tdata
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_EXT (0x2)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 32
-; SYM-NEXT:       ContainingCsectSymbolIndex: 29
+; SYM-NEXT:       Index: 34
+; SYM-NEXT:       ContainingCsectSymbolIndex: 31
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 0
 ; SYM-NEXT:       SymbolType: XTY_LD (0x2)
 ; SYM-NEXT:       StorageMappingClass: XMC_TL (0x14)
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 33
+; SYM:     Index: 35
 ; SYM-NEXT:     Name: IThreadLocalVarUninit
 ; SYM-NEXT:     Value (RelocatableAddress): 0x4
 ; SYM-NEXT:     Section: .tbss
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 34
+; SYM-NEXT:       Index: 36
 ; SYM-NEXT:       SectionLen: 4
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 2
 ; SYM-NEXT:       SymbolType: XTY_CM (0x3)
 ; SYM-NEXT:       StorageMappingClass: XMC_UL (0x15)
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 35
+; SYM:     Index: 37
 ; SYM-NEXT:     Name: IThreadLocalVarUninit2
 ; SYM-NEXT:     Value (RelocatableAddress): 0x8
 ; SYM-NEXT:     Section: .tbss
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 36
+; SYM-NEXT:       Index: 38
 ; SYM-NEXT:       SectionLen: 4
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 2
 ; SYM-NEXT:       SymbolType: XTY_CM (0x3)
 ; SYM-NEXT:       StorageMappingClass: XMC_UL (0x15)
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
 
 ; DIS:      {{.*}}aix-tls-le-xcoff-reloc.ll.tmp.o:  file format aix5coff64-rs6000
 ; DIS:      Disassembly of section .text:
-; DIS:      0000000000000000 (idx: 3) .storeITLUninit:
+; DIS:      0000000000000000 (idx: 5) .storeITLUninit:
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               ld 4, 0(2)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 21) IThreadLocalVarUninit[TC]
+; DIS-NEXT: {{0*}}[[#ADDR]]:     R_REF  (idx: 1)  __tls_get_addr[DS]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 23) IThreadLocalVarUninit[TC]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               stwx 3, 13, 4
 ; DIS-NEXT:                                      blr
-; DIS:      0000000000000010 (idx: 5) .loadTLInit:
+; DIS:      0000000000000010 (idx: 7) .loadTLInit:
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               ld 3, 8(2)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 23) ThreadLocalVarInit[TC]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 25) ThreadLocalVarInit[TC]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               ld 4, 16(2)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 25) VarInit[TC]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 27) VarInit[TC]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               lwzx 3, 13, 3
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               lwz 4, 0(4)
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               add 3, 4, 3
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               extsw 3, 3
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               blr
-; DIS:      0000000000000030 (idx: 7) .loadTLUninit:
+; DIS:      0000000000000030 (idx: 9) .loadTLUninit:
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               ld 3, 0(2)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 21) IThreadLocalVarUninit[TC]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 23) IThreadLocalVarUninit[TC]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               ld 4, 24(2)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 27) IThreadLocalVarUninit2[TC]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 29) IThreadLocalVarUninit2[TC]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               li 5, 1
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               stwx 5, 13, 3
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               lwzx 3, 13, 4
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               addi 3, 3, 1
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               extsw 3, 3
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               blr
 
 ; DIS:      Disassembly of section .data:
-; DIS:      0000000000000050 (idx: 11) VarInit:
+; DIS:      0000000000000050 (idx: 13) VarInit:
 ; DIS-NEXT:       50: 00 00 00 57
-; DIS:      0000000000000058 (idx: 13) storeITLUninit[DS]:
+; DIS:      0000000000000058 (idx: 15) storeITLUninit[DS]:
 ; DIS-NEXT:       58: 00 00 00 00
-; DIS-NEXT: 0000000000000058:  R_POS        (idx: 3) .storeITLUninit
+; DIS-NEXT: 0000000000000058:  R_POS        (idx: 5) .storeITLUninit
 ; DIS-NEXT:       5c: 00 00 00 00
 ; DIS-NEXT:       60: 00 00 00 00
-; DIS-NEXT: 0000000000000060:  R_POS        (idx: 19) TOC[TC0]
+; DIS-NEXT: 0000000000000060:  R_POS        (idx: 21) TOC[TC0]
 ; DIS-NEXT:       64: 00 00 00 a0
-; DIS:      0000000000000070 (idx: 15) loadTLInit[DS]:
+; DIS:      0000000000000070 (idx: 17) loadTLInit[DS]:
 ; DIS-NEXT:       70: 00 00 00 00
-; DIS-NEXT: 0000000000000070:  R_POS        (idx: 5) .loadTLInit
+; DIS-NEXT: 0000000000000070:  R_POS        (idx: 7) .loadTLInit
 ; DIS-NEXT:       74: 00 00 00 10
 ; DIS-NEXT:       78: 00 00 00 00
-; DIS-NEXT: 0000000000000078:  R_POS        (idx: 19) TOC[TC0]
+; DIS-NEXT: 0000000000000078:  R_POS        (idx: 21) TOC[TC0]
 ; DIS-NEXT:       7c: 00 00 00 a0
-; DIS:      0000000000000088 (idx: 17) loadTLUninit[DS]:
+; DIS:      0000000000000088 (idx: 19) loadTLUninit[DS]:
 ; DIS-NEXT:       88: 00 00 00 00
-; DIS-NEXT: 0000000000000088:  R_POS        (idx: 7) .loadTLUninit
+; DIS-NEXT: 0000000000000088:  R_POS        (idx: 9) .loadTLUninit
 ; DIS-NEXT:       8c: 00 00 00 30
 ; DIS-NEXT:       90: 00 00 00 00
-; DIS-NEXT: 0000000000000090:  R_POS        (idx: 19) TOC[TC0]
+; DIS-NEXT: 0000000000000090:  R_POS        (idx: 21) TOC[TC0]
 ; DIS-NEXT:       94: 00 00 00 a0
-; DIS:      00000000000000a0 (idx: 21) IThreadLocalVarUninit[TC]:
+; DIS:      00000000000000a0 (idx: 23) IThreadLocalVarUninit[TC]:
 ; DIS-NEXT:       a0: 00 00 00 00
-; DIS-NEXT: 00000000000000a0:  R_TLS_LE     (idx: 33) IThreadLocalVarUninit[UL]
+; DIS-NEXT: 00000000000000a0:  R_TLS_LE     (idx: 35) IThreadLocalVarUninit[UL]
 ; DIS-NEXT:       a4: 00 00 00 04
-; DIS:      00000000000000a8 (idx: 23) ThreadLocalVarInit[TC]:
+; DIS:      00000000000000a8 (idx: 25) ThreadLocalVarInit[TC]:
 ; DIS-NEXT:       a8: 00 00 00 00
-; DIS-NEXT: 00000000000000a8:  R_TLS_LE     (idx: 31) ThreadLocalVarInit
+; DIS-NEXT: 00000000000000a8:  R_TLS_LE     (idx: 33) ThreadLocalVarInit
 ; DIS-NEXT:       ac: 00 00 00 00
-; DIS:      00000000000000b0 (idx: 25) VarInit[TC]:
+; DIS:      00000000000000b0 (idx: 27) VarInit[TC]:
 ; DIS-NEXT:       b0: 00 00 00 00
-; DIS-NEXT: 00000000000000b0:  R_POS        (idx: 11) VarInit
+; DIS-NEXT: 00000000000000b0:  R_POS        (idx: 13) VarInit
 ; DIS-NEXT:       b4: 00 00 00 50
-; DIS:      00000000000000b8 (idx: 27) IThreadLocalVarUninit2[TC]:
+; DIS:      00000000000000b8 (idx: 29) IThreadLocalVarUninit2[TC]:
 ; DIS-NEXT:       b8: 00 00 00 00
-; DIS-NEXT: 00000000000000b8:  R_TLS_LE     (idx: 35) IThreadLocalVarUninit2[UL]
+; DIS-NEXT: 00000000000000b8:  R_TLS_LE     (idx: 37) IThreadLocalVarUninit2[UL]
 ; DIS-NEXT:       bc: 00 00 00 08
 
 ; DIS:      Disassembly of section .tdata:
-; DIS:      0000000000000000 (idx: 31) ThreadLocalVarInit:
+; DIS:      0000000000000000 (idx: 33) ThreadLocalVarInit:
 ; DIS-NEXT:        0: 00 00 00 01
 
 ; DIS:      Disassembly of section .tbss:
-; DIS:      0000000000000004 (idx: 33) IThreadLocalVarUninit[UL]:
+; DIS:      0000000000000004 (idx: 35) IThreadLocalVarUninit[UL]:
 ; DIS-NEXT: ...
-; DIS:      0000000000000008 (idx: 35) IThreadLocalVarUninit2[UL]:
+; DIS:      0000000000000008 (idx: 37) IThreadLocalVarUninit2[UL]:
 ; DIS-NEXT: ...