[mlir][llvm] Use attributes to store access groups.

[gysit]

Summary

The revision replaces the existing access group operations by
attributes. The access group operations are currently stored in a
global metadata operation. This solution is problematic when inlining
since the access groups cannot be modified in parallel - the
inliner splits the call graph into strongly connected components and
inlines them in parallel - resulting in possible race conditions.

The revision introduces an access group attribute that uses an
integer identifier to model the semantics of distinct metadata.
A distinct sequence attribute is used to generate the unique
identifiers for a specific function. Having a sequence generator
per function ensures deterministic identifiers can be generated
even if functions are manipulated in parallel.

Example:

llvm.metadata @metadata {

llvm.access_group @group
llvm.return

}

llvm.store %0, %ptr { access_groups = [@metadata::@group] }

translates to:

#sequence = #llvm.distinct_sequence<scope = @foo, state = 1>
#group = #llvm.access_group<id = 0, elem_of = #sequence>

llvm.store %0, %ptr { access_groups = [#group] }

Depends on D148007

[zero9178]

mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp

128

Would it maybe be worth commenting that this is threadsafe due to the StorageUniquer using a mutex for mutations? This was non-obvious to me at least (might just be me as well though).

mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp

275

nit: could use accessGroups.getAsRange<AccessGroupAttr>() here to avoid the explicit cast below

[gysit]

Address review comments.

[definelicht]

mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp

259

nit: Doesn't DenseMap have contains?

[definelicht]

mlir/include/mlir/Dialect/LLVMIR/LLVMAttrs.h

73

IIUC you are doing a singleton pattern, maybe add a private constructor?

[gysit]

Address review comments and actually remove the llvm.access_group operation.

[gysit]

mlir/include/mlir/Dialect/LLVMIR/LLVMAttrs.h

73

using Base::Base; actually inherits the base class constructors. I added a comment to clarify this.

[Dinistro]

mlir/include/mlir/Dialect/LLVMIR/LLVMAttrs.h

73

NIT: Maybe changing the name to something like "DistinctHelperAttr" or "DistinctionAttr" to clarify the role of it might be beneficial.

78

Is there a reason why this constructor is public?

[gysit]

Introduce an explicit distinct_sequence attribute.

[definelicht]

mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp

208–218

It would be cleaner if you could pass in scope and state together instead of first and second separately 🤔 Is it possible to pass parser.parseAttribute<SymbolRefAttr> as a function handle directly instead of wrapping the lambda, and then forward the argument?
You could also consider using std::optional instead of the pair with a bool.

255–261

This would be nice to factor into a function getTopLevelSymbolTable or so. This could even exist on SymbolTable directly 🙂

mlir/lib/Target/LLVMIR/ModuleImport.cpp

517–518

Could it be worth to not construct this attribute if it's not actually used?

[Dinistro]

mlir/include/mlir/Dialect/LLVMIR/LLVMAttrs.h

71

78

nvm, that is required for the infra to work.

mlir/lib/Dialect/LLVMIR/IR/LLVMInterfaces.cpp

111

Can a range not be implicitly casted to an ArrayRef instead of converting it to a vector?

[gysit]

Address review comments.

[gysit]

mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp

255–261

I did simplify this code to access the parent module directly using getParentOfType<ModuleOp>. This solution is easier and covers all use cases for now (LLVM dialect is not supposed to support nested builtin module operations). The clean solution for the attribute verification is discussed here https://discourse.llvm.org/t/symbol-user-interface-for-attributes-types/69935.

mlir/lib/Dialect/LLVMIR/IR/LLVMInterfaces.cpp

111

It is necessary unfortunately. I assume since array ref expects a backing memory which is not given for an iterator range.

[gysit]

Minor fixes.

[gysit]

This problem has been solved differently https://reviews.llvm.org/D155285.

mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td

let parameters = (ins
     OptionalParameter<"LoopUnrollAndJamAttr">:$unrollAndJam,
     OptionalParameter<"LoopLICMAttr">:$licm,
     OptionalParameter<"LoopDistributeAttr">:$distribute,
     OptionalParameter<"LoopPipelineAttr">:$pipeline,
     OptionalParameter<"LoopPeeledAttr">:$peeled,
     OptionalParameter<"LoopUnswitchAttr">:$unswitch,
     OptionalParameter<"BoolAttr">:$mustProgress,
     OptionalParameter<"BoolAttr">:$isVectorized,
-    OptionalArrayRefParameter<"SymbolRefAttr">:$parallelAccesses
+    OptionalArrayRefParameter<"AccessGroupAttr">:$parallelAccesses
   );
 
   let assemblyFormat = "`<` struct(params) `>`";
 }
 
 //===----------------------------------------------------------------------===//
 // DebugInfo Attributes
 //===----------------------------------------------------------------------===//
let builders = [
     TypeBuilder<(ins "ArrayRef<DITypeAttr>":$types), [{
       return $_get($_ctxt, /*callingConvention=*/0, types);
     }]>
   ];
   let assemblyFormat = "`<` struct(params) `>`";
 }
 
 //===----------------------------------------------------------------------===//
+// AccessGroupAttr
+//===----------------------------------------------------------------------===//
+
+def LLVM_AccessGroupAttr : LLVM_Attr<"AccessGroup", "access_group"> {
+  let parameters = (ins
+    "int64_t":$id
+  );
+  let builders = [
+    TypeBuilder<(ins), [{ return getDistinct<AccessGroupAttr>($_ctxt); }]>
+  ];
+  let assemblyFormat = "`<` struct(params) `>`";
+}
+
+//===----------------------------------------------------------------------===//
+// AccessGroupArrayAttr
+//===----------------------------------------------------------------------===//
+
+def AccessGroupArrayAttr :
+  TypedArrayAttrBase<LLVM_AccessGroupAttr, "access group array attribute"> {
+  let constBuilderCall = ?;
+}
+
+//===----------------------------------------------------------------------===//
 // MemoryEffectsAttr
 //===----------------------------------------------------------------------===//
 
 def LLVM_MemoryEffectsAttr : LLVM_Attr<"MemoryEffects", "memory_effects"> {
   let parameters = (ins
     "ModRefInfo":$other,
     "ModRefInfo":$argMem,
     "ModRefInfo":$inaccessibleMem

mlir/include/mlir/Dialect/LLVMIR/LLVMAttrs.h

 class DITypeAttr : public DINodeAttr {
 public:
   using DINodeAttr::DINodeAttr;
 
   /// Support LLVM type casting.
   static bool classof(Attribute attr);
 };
 
+namespace detail {
+class GeneratorAttrStorage;
+} // namespace detail
+
+/// This class is a helper attribute that stores a mutable counter which can be
+/// incremented in a thread-safe manner. It serves as a generator for unique
+/// identifiers that enables the creation of multiple distinct attributes
+/// starting from the given base attribute. An example use case is the
+/// representation of distinct metadata nodes. Note: The generator attribute is
+/// only a container for the counter and should not appear in IR directly.
+class GeneratorAttr : public Attribute::AttrBase<GeneratorAttr, Attribute,
+                                                 detail::GeneratorAttrStorage,
+                                                 AttributeTrait::IsMutable> {
+public:
+  using Base::Base;
+
+  /// Returns a generator attribute that can be used to generate unique
+  /// identifiers to produce distinct instances for the given base attribute.
+  static GeneratorAttr get(Attribute attribute);
+
+  /// Returns the next identifier and increments the mutable counter.
+  int64_t getNextID();
+};
+
+/// Returns a distinct attribute of the given type using the given parameters.
+/// Assumes the attributes takes an integer identifier as the first parameter
+/// and uses a generator attribute to set the identifier to a unique value.
+template <typename AttrTy, typename... Args>
+AttrTy getDistinct(MLIRContext *context, Args &&...args) {
+  auto genAttr = GeneratorAttr::get(AttrTy::get(context, 0, args...));
+  return AttrTy::get(context, genAttr.getNextID(), std::forward<Args>(args)...);
+}
+
 // Inline the LLVM generated Linkage enum and utility.
 // This is only necessary to isolate the "enum generated code" from the
 // attribute definition itself.
 // TODO: this shouldn't be needed after we unify the attribute generation, i.e.
 // --gen-attr-* and --gen-attrdef-*.
 using cconv::CConv;
 using linkage::Linkage;
 } // namespace LLVM
 } // namespace mlir
 
 #define GET_ATTRDEF_CLASSES
 #include "mlir/Dialect/LLVMIR/LLVMOpsAttrDefs.h.inc"
 
 #endif // MLIR_DIALECT_LLVMIR_LLVMATTRS_H_

mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.h

 #define MLIR_DIALECT_LLVMIR_LLVMINTERFACES_H_
 
 #include "mlir/Dialect/LLVMIR/LLVMAttrs.h"
 
 namespace mlir {
 namespace LLVM {
 namespace detail {
 
-/// Verifies the access groups attribute of memory operations that implement the
-/// access group interface.
-LogicalResult verifyAccessGroupOpInterface(Operation *op);
-
 /// Verifies the alias analysis attributes of memory operations that implement
 /// the alias analysis interface.
 LogicalResult verifyAliasAnalysisOpInterface(Operation *op);
 
 } // namespace detail
 } // namespace LLVM
 } // namespace mlir
 
 #include "mlir/Dialect/LLVMIR/LLVMInterfaces.h.inc"
 
 #endif // MLIR_DIALECT_LLVMIR_LLVMINTERFACES_H_

mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td

def FastmathFlagsInterface : OpInterface<"FastmathFlagsInterface"> {
   ];
 }
 
 def AccessGroupOpInterface : OpInterface<"AccessGroupOpInterface"> {
   let description = [{
     An interface for memory operations that can carry access groups metadata.
     It provides setters and getters for the operation's access groups attribute.
     The default implementations of the interface methods expect the operation
-    to have an attribute of type ArrayAttr named access_groups.
+    to have an array attribute named access_groups.
   }];
 
   let cppNamespace = "::mlir::LLVM";
-  let verify = [{ return detail::verifyAccessGroupOpInterface($_op); }];
 
   let methods = [
     InterfaceMethod<
       /*desc=*/        "Returns the access groups attribute or nullptr",
       /*returnType=*/  "ArrayAttr",
       /*methodName=*/  "getAccessGroupsOrNull",
       /*args=*/        (ins),
       /*methodBody=*/  [{}],

mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td

 // and alias analysis interfaces. The "aliasAttrs" list contains the arguments
 // required by the access group and alias analysis interfaces. Derived
 // operations should append the "aliasAttrs" to their argument list.
 class LLVM_MemAccessOpBase<string mnemonic, list<Trait> traits = []> :
     LLVM_Op<mnemonic, !listconcat([
       DeclareOpInterfaceMethods<AccessGroupOpInterface>,
       DeclareOpInterfaceMethods<AliasAnalysisOpInterface>], traits)>,
     LLVM_MemOpPatterns {
-  dag aliasAttrs = (ins OptionalAttr<SymbolRefArrayAttr>:$access_groups,
+  dag aliasAttrs = (ins OptionalAttr<AccessGroupArrayAttr>:$access_groups,
                     OptionalAttr<SymbolRefArrayAttr>:$alias_scopes,
                     OptionalAttr<SymbolRefArrayAttr>:$noalias_scopes,
                     OptionalAttr<SymbolRefArrayAttr>:$tbaa);
 }
 
 // Base class for LLVM intrinsics operation. It is similar to LLVM_Op, but
 // provides the "llvmBuilder" field for constructing the intrinsic.
 // The builder relies on the contents of "overloadedResults" and
: LLVM_OpBase<dialect, opName, !listconcat(
             [DeclareOpInterfaceMethods<AliasAnalysisOpInterface>], []),
         !if(!gt(requiresFastmath, 0),
             [DeclareOpInterfaceMethods<FastmathFlagsInterface>], []),
         traits)>,
       LLVM_MemOpPatterns,
       Results<!if(!gt(numResults, 0), (outs LLVM_Type:$res), (outs))> {
   dag aliasAttrs = !con(
         !if(!gt(requiresAccessGroup, 0),
-            (ins OptionalAttr<SymbolRefArrayAttr>:$access_groups),
+            (ins OptionalAttr<AccessGroupArrayAttr>:$access_groups),
             (ins )),
         !if(!gt(requiresAccessGroup, 0),
             (ins OptionalAttr<SymbolRefArrayAttr>:$alias_scopes,
                  OptionalAttr<SymbolRefArrayAttr>:$noalias_scopes,
                  OptionalAttr<SymbolRefArrayAttr>:$tbaa),
             (ins )));
   string resultPattern = !if(!gt(numResults, 1),
                              LLVM_IntrPatterns.structResult,

mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td

let builders = [
     OpBuilder<(ins "Block *":$dest), [{
       build($_builder, $_state, ValueRange(), dest);
     }]>,
     OpBuilder<(ins "ValueRange":$operands, "Block *":$dest), [{
       build($_builder, $_state, operands, /*loop_annotation=*/{}, dest);
     }]>,
     LLVM_TerminatorPassthroughOpBuilder
   ];
-  let hasVerifier = 1;
 }
 def LLVM_CondBrOp : LLVM_TerminatorOp<"cond_br",
     [AttrSizedOperandSegments, DeclareOpInterfaceMethods<BranchOpInterface>,
      Pure]> {
   let arguments = (ins I1:$condition,
                    Variadic<LLVM_Type>:$trueDestOperands,
                    Variadic<LLVM_Type>:$falseDestOperands,
                    OptionalAttr<ElementsAttr>:$branch_weights,
[{
             falseOperands);
   }]>,
   OpBuilder<(ins "Value":$condition, "ValueRange":$trueOperands, "ValueRange":$falseOperands,
     "ElementsAttr":$branchWeights, "Block *":$trueDest, "Block *":$falseDest),
   [{
       build($_builder, $_state, condition, trueOperands, falseOperands, branchWeights,
       {}, trueDest, falseDest);
   }]>, LLVM_TerminatorPassthroughOpBuilder];
-  let hasVerifier = 1;
 }
 
 //===----------------------------------------------------------------------===//
 // ReturnOp
 //===----------------------------------------------------------------------===//
 
 def LLVM_ReturnOp : LLVM_TerminatorOp<"return", [Pure, ReturnLike]> {
   let arguments = (ins Optional<LLVM_Type>:$arg);

mlir/include/mlir/Target/LLVMIR/ModuleImport.h

public:
   LogicalResult convertMetadata();
 
   /// Returns the MLIR symbol reference mapped to the given LLVM TBAA
   /// metadata `node`.
   SymbolRefAttr lookupTBAAAttr(const llvm::MDNode *node) const {
     return tbaaMapping.lookup(node);
   }
 
-  /// Returns the symbol references pointing to the access group operations that
-  /// map to the access group nodes starting from the access group metadata
-  /// `node`. Returns failure, if any of the symbol references cannot be found.
-  FailureOr<SmallVector<SymbolRefAttr>>
+  /// Returns the access group attributes that map to the access group nodes
+  /// starting from the access group metadata `node`. Returns failure if the
+  /// lookup fails for any of the access groups.
+  FailureOr<SmallVector<AccessGroupAttr>>
   lookupAccessGroupAttrs(const llvm::MDNode *node) const;
 
   /// Returns the loop annotation attribute that corresponds to the given LLVM
   /// loop metadata `node`.
   LoopAnnotationAttr translateLoopAnnotationAttr(const llvm::MDNode *node,
                                                  Location loc) const;
 
   /// Returns the symbol references pointing to the alias scope operations that

mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h

private:
 
   /// Converts individual components.
   LogicalResult convertOperation(Operation &op, llvm::IRBuilderBase &builder);
   LogicalResult convertFunctionSignatures();
   LogicalResult convertFunctions();
   LogicalResult convertGlobals();
   LogicalResult convertOneFunction(LLVMFuncOp func);
 
-  /// Process access_group LLVM Metadata operations and create LLVM
-  /// metadata nodes.
-  LogicalResult createAccessGroupMetadata();
-
   /// Process alias.scope LLVM Metadata operations and create LLVM
   /// metadata nodes for them and their domains.
   LogicalResult createAliasScopeMetadata();
 
   /// Returns the LLVM metadata corresponding to a symbol reference to an mlir
   /// LLVM dialect TBAATagOp operation.
   llvm::MDNode *getTBAANode(Operation *op, SymbolRefAttr tagRef) const;
 

mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp

 #define GET_ATTRDEF_CLASSES
 #include "mlir/Dialect/LLVMIR/LLVMOpsAttrDefs.cpp.inc"
 
 //===----------------------------------------------------------------------===//
 // LLVMDialect registration
 //===----------------------------------------------------------------------===//
 
 void LLVMDialect::registerAttributes() {
+  addAttributes<GeneratorAttr>();
   addAttributes<
 #define GET_ATTRDEF_LIST
 #include "mlir/Dialect/LLVMIR/LLVMOpsAttrDefs.cpp.inc"
       >();
 }
 
 //===----------------------------------------------------------------------===//
 // DINodeAttr
bool MemoryEffectsAttr::isReadWrite() {
   if (this->getArgMem() != ModRefInfo::ModRef)
     return false;
   if (this->getInaccessibleMem() != ModRefInfo::ModRef)
     return false;
   if (this->getOther() != ModRefInfo::ModRef)
     return false;
   return true;
 }
+
+//===----------------------------------------------------------------------===//
+// GeneratorAttr
+//===----------------------------------------------------------------------===//
+
+namespace mlir {
+namespace LLVM {
+namespace detail {
+/// Attribute storage for the generator attribute that stores a base attribute
+/// and a mutable counter that can be incremented in a thread-safe manner.
+class GeneratorAttrStorage : public AttributeStorage {
+public:
+  using KeyTy = Attribute;
+
+  GeneratorAttrStorage(Attribute attribute) : attribute(attribute) {}
+
+  static GeneratorAttrStorage *construct(AttributeStorageAllocator &allocator,
+                                         const KeyTy &key) {
+    return new (allocator.allocate<GeneratorAttrStorage>())
+        GeneratorAttrStorage(key);
+  }
+
+  /// Stores the current counter value and increments the counter.
+  LogicalResult mutate(AttributeStorageAllocator &allocator, int64_t *nextID) {
+    *nextID = counter++;
+    return success();
+  }
+
+  bool operator==(const KeyTy &other) const { return attribute == other; }
+
+private:
+  Attribute attribute;
+  int64_t counter = 0;
+};
+} // namespace detail
+} // namespace LLVM
+} // namespace mlir
+
+GeneratorAttr GeneratorAttr::get(Attribute attribute) {
+  return Base::get(attribute.getContext(), attribute);
+}
+
+int64_t GeneratorAttr::getNextID() {
+  int64_t nextID;
+  (void)Base::mutate(&nextID);
+  return nextID;
+}

mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp

LogicalResult AllocaOp::verify() {
   return verifyOpaquePtr(getOperation(), getType().cast<LLVMPointerType>(),
                          getElemType());
 }
 
 //===----------------------------------------------------------------------===//
 // LLVM::BrOp
 //===----------------------------------------------------------------------===//
 
-/// Check if the `loopAttr` references correct symbols.
-static LogicalResult verifyLoopAnnotationAttr(LoopAnnotationAttr loopAttr,
-                                              Operation *op) {
-  if (!loopAttr)
-    return success();
-  // If the `llvm.loop` attribute is present, enforce the following structure,
-  // which the module translation can assume.
-  ArrayRef<SymbolRefAttr> parallelAccesses = loopAttr.getParallelAccesses();
-  if (parallelAccesses.empty())
-    return success();
-  for (SymbolRefAttr accessGroupRef : parallelAccesses) {
-    StringAttr metadataName = accessGroupRef.getRootReference();
-    auto metadataOp = SymbolTable::lookupNearestSymbolFrom<LLVM::MetadataOp>(
-        op->getParentOp(), metadataName);
-    if (!metadataOp)
-      return op->emitOpError() << "expected '" << accessGroupRef
-                               << "' to reference a metadata op";
-    StringAttr accessGroupName = accessGroupRef.getLeafReference();
-    Operation *accessGroupOp =
-        SymbolTable::lookupNearestSymbolFrom(metadataOp, accessGroupName);
-    if (!accessGroupOp)
-      return op->emitOpError() << "expected '" << accessGroupRef
-                               << "' to reference an access_group op";
-  }
-  return success();
-}
-
 SuccessorOperands BrOp::getSuccessorOperands(unsigned index) {
   assert(index == 0 && "invalid successor index");
   return SuccessorOperands(getDestOperandsMutable());
 }
 
-LogicalResult BrOp::verify() {
-  return verifyLoopAnnotationAttr(getLoopAnnotationAttr(), *this);
-}
-
 //===----------------------------------------------------------------------===//
 // LLVM::CondBrOp
 //===----------------------------------------------------------------------===//
 
 SuccessorOperands CondBrOp::getSuccessorOperands(unsigned index) {
   assert(index < getNumSuccessors() && "invalid successor index");
   return SuccessorOperands(index == 0 ? getTrueDestOperandsMutable()
                                       : getFalseDestOperandsMutable());
 }
 
-LogicalResult CondBrOp::verify() {
-  return verifyLoopAnnotationAttr(getLoopAnnotationAttr(), *this);
-}
-
 void CondBrOp::build(OpBuilder &builder, OperationState &result,
                      Value condition, Block *trueDest, ValueRange trueOperands,
                      Block *falseDest, ValueRange falseOperands,
                      std::optional<std::pair<uint32_t, uint32_t>> weights) {
   ElementsAttr weightsAttr;
   if (weights)
     weightsAttr =
         builder.getI32VectorAttr({static_cast<int32_t>(weights->first),

 //===----------------------------------------------------------------------===//
 
 namespace {
 struct LLVMOpAsmDialectInterface : public OpAsmDialectInterface {
   using OpAsmDialectInterface::OpAsmDialectInterface;
 
   AliasResult getAlias(Attribute attr, raw_ostream &os) const override {
     return TypeSwitch<Attribute, AliasResult>(attr)
-        .Case<DIBasicTypeAttr, DICompileUnitAttr, DICompositeTypeAttr,
-              DIDerivedTypeAttr, DIFileAttr, DILexicalBlockAttr,
-              DILexicalBlockFileAttr, DILocalVariableAttr, DINamespaceAttr,
-              DINullTypeAttr, DISubprogramAttr, DISubroutineTypeAttr,
-              LoopAnnotationAttr, LoopVectorizeAttr, LoopInterleaveAttr,
-              LoopUnrollAttr, LoopUnrollAndJamAttr, LoopLICMAttr,
-              LoopDistributeAttr, LoopPipelineAttr, LoopPeeledAttr,
-              LoopUnswitchAttr>([&](auto attr) {
+        .Case<AccessGroupAttr, DIBasicTypeAttr, DICompileUnitAttr,
+              DICompositeTypeAttr, DIDerivedTypeAttr, DIFileAttr,
+              DILexicalBlockAttr, DILexicalBlockFileAttr, DILocalVariableAttr,
+              DINamespaceAttr, DINullTypeAttr, DISubprogramAttr,
+              DISubroutineTypeAttr, LoopAnnotationAttr, LoopVectorizeAttr,
+              LoopInterleaveAttr, LoopUnrollAttr, LoopUnrollAndJamAttr,
+              LoopLICMAttr, LoopDistributeAttr, LoopPipelineAttr,
+              LoopPeeledAttr, LoopUnswitchAttr>([&](auto attr) {
           os << decltype(attr)::getMnemonic();
           return AliasResult::OverridableAlias;
         })
         .Default([](Attribute) { return AliasResult::NoAlias; });
   }
 };
 } // namespace
 

mlir/lib/Dialect/LLVMIR/IR/LLVMInterfaces.cpp

if (!isa<OpTy>(symbolOp)) {
              << OpTy::getOperationName();
     }
     return success();
   };
   return verifySymbolRefs(op, name, symbolRefs, verifySymbolType);
 }
 
 //===----------------------------------------------------------------------===//
-// AccessGroupOpInterface
-//===----------------------------------------------------------------------===//
-
-LogicalResult mlir::LLVM::detail::verifyAccessGroupOpInterface(Operation *op) {
-  auto iface = cast<AccessGroupOpInterface>(op);
-  if (failed(verifySymbolRefsPointTo<LLVM::AccessGroupMetadataOp>(
-          iface, "access groups", iface.getAccessGroupsOrNull())))
-    return failure();
-  return success();
-}
-
-//===----------------------------------------------------------------------===//
 // AliasAnalysisOpInterface
 //===----------------------------------------------------------------------===//
 
 LogicalResult
 mlir::LLVM::detail::verifyAliasAnalysisOpInterface(Operation *op) {
   auto iface = cast<AliasAnalysisOpInterface>(op);
   if (failed(verifySymbolRefsPointTo<LLVM::AliasScopeMetadataOp>(
           iface, "alias scopes", iface.getAliasScopesOrNull())))
     return failure();
   if (failed(verifySymbolRefsPointTo<LLVM::AliasScopeMetadataOp>(
           iface, "noalias scopes", iface.getNoAliasScopesOrNull())))
     return failure();
   if (failed(verifySymbolRefsPointTo<LLVM::TBAATagOp>(
           iface, "tbaa tags", iface.getTBAATagsOrNull())))
     return failure();
   return success();
 }
 
 #include "mlir/Dialect/LLVMIR/LLVMInterfaces.cpp.inc"

mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp

 
 /// Looks up all the symbol references pointing to the access group operations
 /// that map to the access group nodes starting from the access group metadata
 /// `node`, and attaches all of them to the imported operation if the lookups
 /// succeed. Returns failure otherwise.
 static LogicalResult setAccessGroupsAttr(const llvm::MDNode *node,
                                          Operation *op,
                                          LLVM::ModuleImport &moduleImport) {
-  FailureOr<SmallVector<SymbolRefAttr>> accessGroups =
+  FailureOr<SmallVector<AccessGroupAttr>> groups =
       moduleImport.lookupAccessGroupAttrs(node);
-  if (failed(accessGroups))
+  if (failed(groups))
     return failure();
 
   auto iface = dyn_cast<AccessGroupOpInterface>(op);
   if (!iface)
     return failure();
 
-  iface.setAccessGroups(ArrayAttr::get(
-      iface.getContext(),
-      SmallVector<Attribute>{accessGroups->begin(), accessGroups->end()}));
+  iface.setAccessGroups(
+      ArrayAttr::get(iface->getContext(),
+                     SmallVector<Attribute>{groups->begin(), groups->end()}));
   return success();
 }
 
 /// Converts the given loop metadata node to an MLIR loop annotation attribute
 /// and attaches it to the imported operation if the translation succeeds.
 /// Returns failure otherwise.
 static LogicalResult setLoopAttr(const llvm::MDNode *node, Operation *op,
                                  LLVM::ModuleImport &moduleImport) {

mlir/lib/Target/LLVMIR/LoopAnnotationImporter.h

 //===- LoopAnnotationImporter.h ---------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the translation between LLVMIR loop metadata and the
 // corresponding MLIR representation.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef MLIR_LIB_TARGET_LLVMIR_LOOPANNOTATIONIMPORTER_H_
 #define MLIR_LIB_TARGET_LLVMIR_LOOPANNOTATIONIMPORTER_H_
 
+#include "mlir/Dialect/LLVMIR/LLVMAttrs.h"
 #include "mlir/Dialect/LLVMIR/LLVMDialect.h"
 #include "mlir/Target/LLVMIR/ModuleImport.h"
 
 namespace mlir {
 namespace LLVM {
 namespace detail {
 
 /// A helper class that converts llvm.loop metadata nodes into corresponding
 /// LoopAnnotationAttrs and llvm.access.group nodes into
 /// AccessGroupMetadataOps.
 class LoopAnnotationImporter {
 public:
-  explicit LoopAnnotationImporter(OpBuilder &builder) : builder(builder) {}
+  explicit LoopAnnotationImporter(MLIRContext *context) : context(context) {}
   LoopAnnotationAttr translateLoopAnnotation(const llvm::MDNode *node,
                                              Location loc);
 
-  /// Converts all LLVM access groups starting from node to MLIR access group
-  /// operations mested in the region of metadataOp. It stores a mapping from
-  /// every nested access group nod to the symbol pointing to the translated
-  /// operation. Returns success if all conversions succeed and failure
-  /// otherwise.
-  LogicalResult translateAccessGroup(const llvm::MDNode *node, Location loc,
-                                     MetadataOp metadataOp);
-
-  /// Returns the symbol references pointing to the access group operations that
-  /// map to the access group nodes starting from the access group metadata
-  /// node. Returns failure, if any of the symbol references cannot be found.
-  FailureOr<SmallVector<SymbolRefAttr>>
-  lookupAccessGroupAttrs(const llvm::MDNode *node) const;
+  /// Converts all LLVM access groups starting from `node` to MLIR access group
+  /// attributes. It stores a mapping from every nested access group node to the
+  /// translated access group attribute. Returns success if all conversions
+  /// succeed and failure otherwise.
+  LogicalResult translateAccessGroup(const llvm::MDNode *node, Location loc);
+
+  /// Returns the access group attributes that map to the access group nodes
+  /// starting from the access group metadata `node`. Returns failure if the
+  /// lookup fails for any of the access groups.
+  FailureOr<SmallVector<AccessGroupAttr>>
+  lookupAccessGroupsAttr(const llvm::MDNode *node) const;
 
 private:
   /// Returns the LLVM metadata corresponding to a llvm loop metadata attribute.
   LoopAnnotationAttr lookupLoopMetadata(const llvm::MDNode *node) const {
     return loopMetadataMapping.lookup(node);
   }
 
   void mapLoopMetadata(const llvm::MDNode *metadata, LoopAnnotationAttr attr) {
     auto result = loopMetadataMapping.try_emplace(metadata, attr);
     (void)result;
     assert(result.second &&
            "attempting to map loop options that was already mapped");
   }
 
-  OpBuilder &builder;
+  MLIRContext *context;
   DenseMap<const llvm::MDNode *, LoopAnnotationAttr> loopMetadataMapping;
-  /// Mapping between original LLVM access group metadata nodes and the symbol
-  /// references pointing to the imported MLIR access group operations.
-  DenseMap<const llvm::MDNode *, SymbolRefAttr> accessGroupMapping;
+  /// Mapping between original LLVM access group metadata nodes and the
+  /// corresponding MLIR access group attribute.
+  DenseMap<const llvm::MDNode *, AccessGroupAttr> accessGroupMapping;
 };
 
 } // namespace detail
 } // namespace LLVM
 } // namespace mlir
 
 #endif // MLIR_LIB_TARGET_LLVMIR_LOOPANNOTATIONIMPORTER_H_

mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp

struct LoopMetadataConversion {
   /// Converts this structs loop metadata node into a LoopAnnotationAttr.
   LoopAnnotationAttr convert();
 
   LogicalResult initPropertyMap();
 
   /// Helper function to get and erase a property.
   const llvm::MDNode *lookupAndEraseProperty(StringRef name);
 
-  /// Helper functions to lookup and convert MDNodes into a specifc attribute
+  /// Helper functions to lookup and convert MDNodes into a specific attribute
   /// kind. These functions return null-attributes if there is no node with the
   /// specified name, or failure, if the node is ill-formatted.
   FailureOr<BoolAttr> lookupUnitNode(StringRef name);
   FailureOr<BoolAttr> lookupBoolNode(StringRef name, bool negated = false);
   FailureOr<BoolAttr> lookupIntNodeAsBoolAttr(StringRef name);
   FailureOr<IntegerAttr> lookupIntNode(StringRef name);
   FailureOr<llvm::MDNode *> lookupMDNode(StringRef name);
   FailureOr<SmallVector<llvm::MDNode *>> lookupMDNodes(StringRef name);
   FailureOr<LoopAnnotationAttr> lookupFollowupNode(StringRef name);
   FailureOr<BoolAttr> lookupBooleanUnitNode(StringRef enableName,
                                             StringRef disableName,
                                             bool negated = false);
 
   /// Conversion functions for sub-attributes.
   FailureOr<LoopVectorizeAttr> convertVectorizeAttr();
   FailureOr<LoopInterleaveAttr> convertInterleaveAttr();
   FailureOr<LoopUnrollAttr> convertUnrollAttr();
   FailureOr<LoopUnrollAndJamAttr> convertUnrollAndJamAttr();
   FailureOr<LoopLICMAttr> convertLICMAttr();
   FailureOr<LoopDistributeAttr> convertDistributeAttr();
   FailureOr<LoopPipelineAttr> convertPipelineAttr();
   FailureOr<LoopPeeledAttr> convertPeeledAttr();
   FailureOr<LoopUnswitchAttr> convertUnswitchAttr();
-  FailureOr<SmallVector<SymbolRefAttr>> convertParallelAccesses();
+  FailureOr<SmallVector<AccessGroupAttr>> convertParallelAccesses();
 
   llvm::StringMap<const llvm::MDNode *> propertyMap;
   const llvm::MDNode *node;
   Location loc;
   LoopAnnotationImporter &loopAnnotationImporter;
   MLIRContext *ctx;
 };
 } // namespace

 static bool isEmptyOrNull(const Attribute attr) { return !attr; }
 
 template <typename T>
 static bool isEmptyOrNull(const SmallVectorImpl<T> &vec) {
   return vec.empty();
 }
 
 /// Helper function that only creates and attribute of type T if all argument
-/// conversion were successfull and at least one of them holds a non-null value.
+/// conversion were successful and at least one of them holds a non-null value.
 template <typename T, typename... P>
 static T createIfNonNull(MLIRContext *ctx, const P &...args) {
   bool anyFailed = (failed(args) || ...);
   if (anyFailed)
     return {};
 
   bool allEmpty = (isEmptyOrNull(*args) && ...);
   if (allEmpty)

 }
 
 FailureOr<LoopUnswitchAttr> LoopMetadataConversion::convertUnswitchAttr() {
   FailureOr<BoolAttr> partialDisable =
       lookupUnitNode("llvm.loop.unswitch.partial.disable");
   return createIfNonNull<LoopUnswitchAttr>(ctx, partialDisable);
 }
 
-FailureOr<SmallVector<SymbolRefAttr>>
+FailureOr<SmallVector<AccessGroupAttr>>
 LoopMetadataConversion::convertParallelAccesses() {
   FailureOr<SmallVector<llvm::MDNode *>> nodes =
       lookupMDNodes("llvm.loop.parallel_accesses");
   if (failed(nodes))
     return failure();
-  SmallVector<SymbolRefAttr> refs;
+  SmallVector<AccessGroupAttr> accessGroups;
   for (llvm::MDNode *node : *nodes) {
-    FailureOr<SmallVector<SymbolRefAttr>> accessGroups =
-        loopAnnotationImporter.lookupAccessGroupAttrs(node);
-    if (failed(accessGroups))
-      return emitWarning(loc) << "could not lookup access group";
-    llvm::append_range(refs, *accessGroups);
+    FailureOr<SmallVector<AccessGroupAttr>> groups =
+        loopAnnotationImporter.lookupAccessGroupsAttr(node);
+    if (failed(groups))
+      return emitWarning(loc) << "could not lookup access groups";
+    llvm::append_range(accessGroups, *groups);
   }
-  return refs;
+  return accessGroups;
 }
 
 LoopAnnotationAttr LoopMetadataConversion::convert() {
   if (failed(initPropertyMap()))
     return {};
 
   FailureOr<BoolAttr> disableNonForced =
       lookupUnitNode("llvm.loop.disable_nonforced");
   FailureOr<LoopVectorizeAttr> vecAttr = convertVectorizeAttr();
   FailureOr<LoopInterleaveAttr> interleaveAttr = convertInterleaveAttr();
   FailureOr<LoopUnrollAttr> unrollAttr = convertUnrollAttr();
   FailureOr<LoopUnrollAndJamAttr> unrollAndJamAttr = convertUnrollAndJamAttr();
   FailureOr<LoopLICMAttr> licmAttr = convertLICMAttr();
   FailureOr<LoopDistributeAttr> distributeAttr = convertDistributeAttr();
   FailureOr<LoopPipelineAttr> pipelineAttr = convertPipelineAttr();
   FailureOr<LoopPeeledAttr> peeledAttr = convertPeeledAttr();
   FailureOr<LoopUnswitchAttr> unswitchAttr = convertUnswitchAttr();
   FailureOr<BoolAttr> mustProgress = lookupUnitNode("llvm.loop.mustprogress");
   FailureOr<BoolAttr> isVectorized =
       lookupIntNodeAsBoolAttr("llvm.loop.isvectorized");
-  FailureOr<SmallVector<SymbolRefAttr>> parallelAccesses =
+  FailureOr<SmallVector<AccessGroupAttr>> parallelAccesses =
       convertParallelAccesses();
 
   // Drop the metadata if there are parts that cannot be imported.
   if (!propertyMap.empty()) {
     for (auto name : propertyMap.keys())
       emitWarning(loc) << "unknown loop annotation " << name;
     return {};
   }
if (it != loopMetadataMapping.end())
     return it->getSecond();
 
   LoopAnnotationAttr attr = LoopMetadataConversion(node, loc, *this).convert();
 
   mapLoopMetadata(node, attr);
   return attr;
 }
 
-LogicalResult LoopAnnotationImporter::translateAccessGroup(
-    const llvm::MDNode *node, Location loc, MetadataOp metadataOp) {
+LogicalResult
+LoopAnnotationImporter::translateAccessGroup(const llvm::MDNode *node,
+                                             Location loc) {
   SmallVector<const llvm::MDNode *> accessGroups;
   if (!node->getNumOperands())
     accessGroups.push_back(node);
   for (const llvm::MDOperand &operand : node->operands()) {
     auto *childNode = dyn_cast<llvm::MDNode>(operand);
     if (!childNode)
       return failure();
     accessGroups.push_back(cast<llvm::MDNode>(operand.get()));
   }
 
   // Convert all entries of the access group list to access group operations.
   for (const llvm::MDNode *accessGroup : accessGroups) {
     if (accessGroupMapping.count(accessGroup))
       continue;
     // Verify the access group node is distinct and empty.
     if (accessGroup->getNumOperands() != 0 || !accessGroup->isDistinct())
       return emitWarning(loc)
              << "expected an access group node to be empty and distinct";
 
-    OpBuilder::InsertionGuard guard(builder);
-    builder.setInsertionPointToEnd(&metadataOp.getBody().back());
-    auto groupOp = builder.create<AccessGroupMetadataOp>(
-        loc, llvm::formatv("group_{0}", accessGroupMapping.size()).str());
-    // Add a mapping from the access group node to the symbol reference pointing
-    // to the newly created operation.
-    accessGroupMapping[accessGroup] = SymbolRefAttr::get(
-        builder.getContext(), metadataOp.getSymName(),
-        FlatSymbolRefAttr::get(builder.getContext(), groupOp.getSymName()));
+    accessGroupMapping[accessGroup] = getDistinct<AccessGroupAttr>(context);
   }
   return success();
 }
 
-FailureOr<SmallVector<SymbolRefAttr>>
-LoopAnnotationImporter::lookupAccessGroupAttrs(const llvm::MDNode *node) const {
-  // An access group node is either a single access group or an access group
-  // list.
-  SmallVector<SymbolRefAttr> accessGroups;
+FailureOr<SmallVector<AccessGroupAttr>>
+LoopAnnotationImporter::lookupAccessGroupsAttr(const llvm::MDNode *node) const {
+  // An access group node is a single access group or an access group list.
+  SmallVector<AccessGroupAttr> accessGroups;
   if (!node->getNumOperands())
     accessGroups.push_back(accessGroupMapping.lookup(node));
   for (const llvm::MDOperand &operand : node->operands()) {
     auto *node = cast<llvm::MDNode>(operand.get());
     accessGroups.push_back(accessGroupMapping.lookup(node));
   }
   // Exit if one of the access group node lookups failed.
   if (llvm::is_contained(accessGroups, nullptr))
     return failure();
   return accessGroups;
 }

mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.h

 namespace mlir {
 namespace LLVM {
 namespace detail {
 
 /// A helper class that converts LoopAnnotationAttrs and AccessGroupMetadataOps
 /// into a corresponding llvm::MDNodes.
 class LoopAnnotationTranslation {
 public:
-  LoopAnnotationTranslation(Operation *mlirModule, llvm::Module &llvmModule)
-      : mlirModule(mlirModule), llvmModule(llvmModule) {}
+  LoopAnnotationTranslation(llvm::Module &llvmModule)
+      : llvmModule(llvmModule) {}
 
   llvm::MDNode *translateLoopAnnotation(LoopAnnotationAttr attr, Operation *op);
 
-  /// Traverses the global access group metadata operation in the `mlirModule`
-  /// and creates corresponding LLVM metadata nodes.
-  LogicalResult createAccessGroupMetadata();
-
-  /// Returns the LLVM metadata corresponding to a symbol reference to an mlir
-  /// LLVM dialect access group operation.
-  llvm::MDNode *getAccessGroup(Operation *op,
-                               SymbolRefAttr accessGroupRef) const;
+  /// Returns the LLVM metadata corresponding to an MLIR access group attribute.
+  llvm::MDNode *getAccessGroup(AccessGroupAttr group);
 
   /// Returns the LLVM metadata corresponding to the access group operations
   /// referenced by the AccessGroupOpInterface or null if there are none.
-  llvm::MDNode *getAccessGroups(AccessGroupOpInterface op) const;
+  llvm::MDNode *getAccessGroups(AccessGroupOpInterface op);
 
 private:
   /// Returns the LLVM metadata corresponding to a llvm loop metadata attribute.
   llvm::MDNode *lookupLoopMetadata(Attribute options) const {
     return loopMetadataMapping.lookup(options);
   }
 
   void mapLoopMetadata(Attribute options, llvm::MDNode *metadata) {
     auto result = loopMetadataMapping.try_emplace(options, metadata);
     (void)result;
     assert(result.second &&
            "attempting to map loop options that was already mapped");
   }
 
   /// Mapping from an attribute describing loop metadata to its LLVM metadata.
   /// The metadata is attached to Latch block branches with this attribute.
   DenseMap<Attribute, llvm::MDNode *> loopMetadataMapping;
 
-  /// Mapping from an access group metadata operation to its LLVM metadata.
-  /// This map is populated on module entry and is used to annotate loops (as
-  /// identified via their branches) and contained memory accesses.
-  DenseMap<Operation *, llvm::MDNode *> accessGroupMetadataMapping;
+  /// Mapping from an access group attributes to the corresponding LLVM metadata
+  /// nodes. This map is populated on module entry and is used to annotate loops
+  /// (as identified via their branches) and contained memory accesses.
+  DenseMap<AccessGroupAttr, llvm::MDNode *> accessGroupMetadataMapping;
 
-  Operation *mlirModule;
   llvm::Module &llvmModule;
 };
 
 } // namespace detail
 } // namespace LLVM
 } // namespace mlir
 
 #endif // MLIR_LIB_TARGET_LLVMIR_LOOPANNOTATIONTRANSLATION_H_

mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp

 //===- LoopAnnotationTranslation.cpp - Loop annotation export -------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "LoopAnnotationTranslation.h"
+#include "mlir/Dialect/LLVMIR/LLVMAttrs.h"
 
 using namespace mlir;
 using namespace mlir::LLVM;
 using namespace mlir::LLVM::detail;
 
 namespace {
 /// Helper class that keeps the state of one attribute to metadata conversion.
 struct LoopAnnotationConversion {
if (auto options = attr.getDistribute())
     convertLoopOptions(options);
   if (auto options = attr.getPipeline())
     convertLoopOptions(options);
   if (auto options = attr.getPeeled())
     convertLoopOptions(options);
   if (auto options = attr.getUnswitch())
     convertLoopOptions(options);
 
-  ArrayRef<SymbolRefAttr> parallelAccessGroups = attr.getParallelAccesses();
+  ArrayRef<AccessGroupAttr> parallelAccessGroups =
+      attr.getParallelAccesses();
   if (!parallelAccessGroups.empty()) {
     SmallVector<llvm::Metadata *> parallelAccess;
     parallelAccess.push_back(
         llvm::MDString::get(ctx, "llvm.loop.parallel_accesses"));
-    for (SymbolRefAttr accessGroupRef : parallelAccessGroups)
-      parallelAccess.push_back(
-          loopAnnotationTranslation.getAccessGroup(op, accessGroupRef));
+    for (AccessGroupAttr group : parallelAccessGroups)
+      parallelAccess.push_back(loopAnnotationTranslation.getAccessGroup(group));
     metadataNodes.push_back(llvm::MDNode::get(ctx, parallelAccess));
   }
 
   // Create loop options and set the first operand to itself.
   llvm::MDNode *loopMD = llvm::MDNode::get(ctx, metadataNodes);
   loopMD->replaceOperandWith(0, loopMD);
 
   return loopMD;
loopMD =
       LoopAnnotationConversion(attr, op, *this, this->llvmModule.getContext())
           .convert();
   // Store a map from this Attribute to the LLVM metadata in case we
   // encounter it again.
   mapLoopMetadata(attr, loopMD);
   return loopMD;
 }
 
-LogicalResult LoopAnnotationTranslation::createAccessGroupMetadata() {
-  mlirModule->walk([&](LLVM::MetadataOp metadatas) {
-    metadatas.walk([&](LLVM::AccessGroupMetadataOp op) {
-      llvm::MDNode *accessGroup =
-          llvm::MDNode::getDistinct(llvmModule.getContext(), {});
-      accessGroupMetadataMapping.insert({op, accessGroup});
-    });
-  });
-  return success();
-}
-
-llvm::MDNode *
-LoopAnnotationTranslation::getAccessGroup(Operation *op,
-                                          SymbolRefAttr accessGroupRef) const {
-  auto metadataName = accessGroupRef.getRootReference();
-  auto accessGroupName = accessGroupRef.getLeafReference();
-  auto metadataOp = SymbolTable::lookupNearestSymbolFrom<LLVM::MetadataOp>(
-      op->getParentOp(), metadataName);
-  auto *accessGroupOp =
-      SymbolTable::lookupNearestSymbolFrom(metadataOp, accessGroupName);
-  return accessGroupMetadataMapping.lookup(accessGroupOp);
+llvm::MDNode *LoopAnnotationTranslation::getAccessGroup(AccessGroupAttr group) {
+  if (accessGroupMetadataMapping.count(group))
+    return accessGroupMetadataMapping[group];
+
+  accessGroupMetadataMapping.insert({group, accessGroup});
+  return accessGroup;
 }
 
 llvm::MDNode *
-LoopAnnotationTranslation::getAccessGroups(AccessGroupOpInterface op) const {
-  ArrayAttr accessGroupRefs = op.getAccessGroupsOrNull();
-  if (!accessGroupRefs || accessGroupRefs.empty())
+LoopAnnotationTranslation::getAccessGroups(AccessGroupOpInterface op) {
+  ArrayAttr accessGroups = op.getAccessGroupsOrNull();
+  if (!accessGroups || accessGroups.empty())
     return nullptr;
 
   SmallVector<llvm::Metadata *> groupMDs;
-  for (SymbolRefAttr groupRef : accessGroupRefs.getAsRange<SymbolRefAttr>())
-    groupMDs.push_back(getAccessGroup(op, groupRef));
+  for (Attribute group : accessGroups)
+    groupMDs.push_back(getAccessGroup(cast<AccessGroupAttr>(group)));
   if (groupMDs.size() == 1)
     return llvm::cast<llvm::MDNode>(groupMDs.front());
   return llvm::MDNode::get(llvmModule.getContext(), groupMDs);
 }

mlir/lib/Target/LLVMIR/ModuleImport.cpp

 ModuleImport::ModuleImport(ModuleOp mlirModule,
                            std::unique_ptr<llvm::Module> llvmModule)
     : builder(mlirModule->getContext()), context(mlirModule->getContext()),
       mlirModule(mlirModule), llvmModule(std::move(llvmModule)),
       iface(mlirModule->getContext()),
       typeTranslator(*mlirModule->getContext()),
       debugImporter(std::make_unique<DebugImporter>(mlirModule)),
       loopAnnotationImporter(
-          std::make_unique<LoopAnnotationImporter>(builder)) {
+          std::make_unique<LoopAnnotationImporter>(mlirModule.getContext())) {
   builder.setInsertionPointToStart(mlirModule.getBody());
 }
 
 MetadataOp ModuleImport::getGlobalMetadataOp() {
   if (globalMetadataOp)
     return globalMetadataOp;
 
   OpBuilder::InsertionGuard guard(builder);
LogicalResult ModuleImport::processTBAAMetadata(const llvm::MDNode *node) {
   }
 
   return success();
 }
 
 LogicalResult
 ModuleImport::processAccessGroupMetadata(const llvm::MDNode *node) {
   Location loc = mlirModule.getLoc();
-  if (failed(loopAnnotationImporter->translateAccessGroup(
-          node, loc, getGlobalMetadataOp())))
+  if (failed(loopAnnotationImporter->translateAccessGroup(node, loc)))
     return emitError(loc) << "unsupported access group node: "
                           << diagMD(node, llvmModule.get());
   return success();
 }
 
 LogicalResult
 ModuleImport::processAliasScopeMetadata(const llvm::MDNode *node) {
   Location loc = mlirModule.getLoc();
if (llvm::is_contained(aliasScopes, nullptr))
     return failure();
   return aliasScopes;
 }
 
 LogicalResult ModuleImport::convertMetadata() {
   OpBuilder::InsertionGuard guard(builder);
   builder.setInsertionPointToEnd(mlirModule.getBody());
   for (const llvm::Function &func : llvmModule->functions()) {
     for (const llvm::Instruction &inst : llvm::instructions(func)) {
       // Convert access group metadata nodes.
       if (llvm::MDNode *node =
               inst.getMetadata(llvm::LLVMContext::MD_access_group))
         if (failed(processAccessGroupMetadata(node)))
           return failure();
 
       // Convert alias analysis metadata nodes.
       llvm::AAMDNodes aliasAnalysisNodes = inst.getAAMetadata();
       if (!aliasAnalysisNodes)
for (llvm::Instruction &inst : *bb) {
     } else if (inst.getOpcode() != llvm::Instruction::PHI) {
       Location loc = debugImporter->translateLoc(inst.getDebugLoc());
       emitWarning(loc) << "dropped instruction: " << diag(inst);
     }
   }
   return success();
 }
 
-FailureOr<SmallVector<SymbolRefAttr>>
+FailureOr<SmallVector<AccessGroupAttr>>
 ModuleImport::lookupAccessGroupAttrs(const llvm::MDNode *node) const {
-  return loopAnnotationImporter->lookupAccessGroupAttrs(node);
+  return loopAnnotationImporter->lookupAccessGroupsAttr(node);
 }
 
 LoopAnnotationAttr
 ModuleImport::translateLoopAnnotationAttr(const llvm::MDNode *node,
                                           Location loc) const {
   return loopAnnotationImporter->translateLoopAnnotation(node, loc);
 }
 

mlir/lib/Target/LLVMIR/ModuleTranslation.cpp

llvm::Constant *mlir::LLVM::detail::getLLVMConstant(
   return nullptr;
 }
 
 ModuleTranslation::ModuleTranslation(Operation *module,
                                      std::unique_ptr<llvm::Module> llvmModule)
     : mlirModule(module), llvmModule(std::move(llvmModule)),
       debugTranslation(
           std::make_unique<DebugTranslation>(module, *this->llvmModule)),
-      loopAnnotationTranslation(std::make_unique<LoopAnnotationTranslation>(
-          module, *this->llvmModule)),
+      loopAnnotationTranslation(
+          std::make_unique<LoopAnnotationTranslation>(*this->llvmModule)),
       typeTranslator(this->llvmModule->getContext()),
       iface(module->getContext()) {
   assert(satisfiesLLVMModule(mlirModule) &&
          "mlirModule should honor LLVM's module semantics.");
 }
 ModuleTranslation::~ModuleTranslation() {
   if (ompBuilder)
     ompBuilder->finalize();
for (auto function : getModuleBody(mlirModule).getOps<LLVMFuncOp>()) {
 
     if (failed(convertOneFunction(function)))
       return failure();
   }
 
   return success();
 }
 
-LogicalResult ModuleTranslation::createAccessGroupMetadata() {
-  return loopAnnotationTranslation->createAccessGroupMetadata();
-}
-
 void ModuleTranslation::setAccessGroupsMetadata(AccessGroupOpInterface op,
                                                 llvm::Instruction *inst) {
   if (llvm::MDNode *node = loopAnnotationTranslation->getAccessGroups(op))
     inst->setMetadata(llvm::LLVMContext::MD_access_group, node);
 }
 
 LogicalResult ModuleTranslation::createAliasScopeMetadata() {
   mlirModule->walk([&](LLVM::MetadataOp metadatas) {
mlir::translateModuleToLLVMIR(Operation *module, llvm::LLVMContext &llvmContext,
 
   LLVM::ensureDistinctSuccessors(module);
 
   ModuleTranslation translator(module, std::move(llvmModule));
   if (failed(translator.convertFunctionSignatures()))
     return nullptr;
   if (failed(translator.convertGlobals()))
     return nullptr;
-  if (failed(translator.createAccessGroupMetadata()))
-    return nullptr;
   if (failed(translator.createAliasScopeMetadata()))
     return nullptr;
   if (failed(translator.createTBAAMetadata()))
     return nullptr;
   if (failed(translator.convertFunctions()))
     return nullptr;
 
   // Convert other top-level operations if possible.

mlir/test/Dialect/LLVMIR/inlining.mlir

 // CHECK-NEXT: return %[[RES]] : i32
 func.func @test_not_inline() -> i32 {
   %0 = call @inner_func_not_inlinable() : () -> i32
   return %0 : i32
 }
 
 // -----
 
-llvm.metadata @metadata {
-  llvm.access_group @group
-  llvm.return
-}
+#access_group = #llvm.access_group<id = 0>
 
 func.func private @with_mem_attr(%ptr : !llvm.ptr) {
   %0 = llvm.mlir.constant(42 : i32) : i32
   // Do not inline load/store operations that carry attributes requiring
   // handling while inlining, until this is supported by the inliner.
-  llvm.store %0, %ptr { access_groups = [@metadata::@group] }: i32, !llvm.ptr
+  llvm.store %0, %ptr { access_groups = [#access_group] }: i32, !llvm.ptr
   return
 }
 
 // CHECK-LABEL: func.func @test_not_inline
 // CHECK-NEXT: call @with_mem_attr
 // CHECK-NEXT: return
 func.func @test_not_inline(%ptr : !llvm.ptr) {
   call @with_mem_attr(%ptr) : (!llvm.ptr) -> ()

mlir/test/Dialect/LLVMIR/invalid.mlir

 
 // -----
 
 // expected-error@below {{expected array type for 'appending' linkage}}
 llvm.mlir.global appending @non_array_type_global_appending_linkage() : i32
 
 // -----
 
-module {
-  llvm.func @loopOptions() {
-      // expected-error@below {{expected '@func1' to reference a metadata op}}
-      llvm.br ^bb4 {loop_annotation = #llvm.loop_annotation<parallelAccesses = @func1>}
-    ^bb4:
-      llvm.return
-  }
-  llvm.func @func1() {
-    llvm.return
-  }
-}
-
-// -----
-
-module {
-  llvm.func @loopOptions() {
-      // expected-error@below {{expected '@metadata' to reference an access_group op}}
-      llvm.br ^bb4 {loop_annotation = #llvm.loop_annotation<parallelAccesses = @metadata>}
-    ^bb4:
-      llvm.return
-  }
-  llvm.metadata @metadata {
-  }
-}
+    // expected-error@below {{expected '<'}}
+    // expected-error@below {{failed to parse LoopAnnotationAttr parameter 'parallelAccesses' which is to be a `::llvm::ArrayRef<AccessGroupAttr>`}}
+    llvm.br ^bb4 {loop_annotation = #llvm.loop_annotation<parallelAccesses = 42 : i32>}
 
 // -----
 
-module {
-  llvm.func @accessGroups(%arg0 : !llvm.ptr) {
-      // expected-error@below {{expected '@func1' to specify a fully qualified reference}}
-      %0 = llvm.load %arg0 { "access_groups" = [@func1] } : !llvm.ptr -> i32
-      llvm.return
-  }
-  llvm.func @func1() {
-    llvm.return
-  }
-}
-
-// -----
-
-module {
-  llvm.func @accessGroups(%arg0 : i32, %arg1 : !llvm.ptr) {
-      // expected-error@below {{expected '@accessGroups::@group1' to reference a metadata op}}
-      llvm.store %arg0, %arg1 { "access_groups" = [@accessGroups::@group1] } : i32, !llvm.ptr
-      llvm.return
-  }
-  llvm.metadata @metadata {
-  }
-}
-
-// -----
-
-module {
-  llvm.func @accessGroups(%arg0 : !llvm.ptr, %arg1 : f32) {
-      // expected-error@below {{expected '@metadata::@group1' to be a valid reference}}
-      %0 = llvm.atomicrmw fadd %arg0, %arg1 monotonic { "access_groups" = [@metadata::@group1] } : !llvm.ptr, f32
-      llvm.return
-  }
-  llvm.metadata @metadata {
-  }
-}
-
-// -----
-
-module {
-  llvm.func @accessGroups(%arg0 : !llvm.ptr, %arg1 : i32, %arg2 : i32) {
-      // expected-error@below {{expected '@metadata::@scope' to resolve to a llvm.access_group}}
-      %0 = llvm.cmpxchg %arg0, %arg1, %arg2 acq_rel monotonic { "access_groups" = [@metadata::@scope] } : !llvm.ptr, i32
-      llvm.return
-  }
-  llvm.metadata @metadata {
-    llvm.alias_scope_domain @domain
-    llvm.alias_scope @scope { domain = @domain }
-  }
-}
+    // expected-error@below {{attribute 'access_groups' failed to satisfy constraint: access group array attribute}}
+    %0 = llvm.load %arg0 { "access_groups" = [42 : i32] } : !llvm.ptr -> i32
 
 // -----
 
 module {
   llvm.func @aliasScope(%arg0 : !llvm.ptr, %arg1 : i32, %arg2 : i32) {
       // expected-error@below {{attribute 'alias_scopes' failed to satisfy constraint: symbol ref array attribute}}
       %0 = llvm.cmpxchg %arg0, %arg1, %arg2 acq_rel monotonic { "alias_scopes" = "test" } : !llvm.ptr, i32
       llvm.return

mlir/test/Dialect/LLVMIR/loop-metadata.mlir

 #pipeline = #llvm.loop_pipeline<disable = true, initiationinterval = 1 : i32>
 
 // CHECK-DAG: #[[PEELED:.*]] = #llvm.loop_peeled<count = 8 : i32>
 #peeled = #llvm.loop_peeled<count = 8 : i32>
 
 // CHECK-DAG: #[[UNSWITCH:.*]] = #llvm.loop_unswitch<partialDisable = true>
 #unswitch = #llvm.loop_unswitch<partialDisable = true>
 
+// CHECK-DAG: #[[GROUP1:.*]] = #llvm.access_group<id = 1>
+#access_group1 = #llvm.access_group<id = 1>
+// CHECK-DAG: #[[GROUP2:.*]] = #llvm.access_group<id = 2>
+#access_group2 = #llvm.access_group<id = 2>
+
 // CHECK: #[[LOOP_ANNOT:.*]] = #llvm.loop_annotation<
 // CHECK-DAG: disableNonforced = false
 // CHECK-DAG: mustProgress = true
 // CHECK-DAG: unroll = #[[UNROLL]]
 // CHECK-DAG: unrollAndJam = #[[UNROLL_AND_JAM]]
 // CHECK-DAG: licm = #[[LICM]]
 // CHECK-DAG: distribute = #[[DISTRIBUTE]]
 // CHECK-DAG: pipeline = #[[PIPELINE]]
 // CHECK-DAG: peeled = #[[PEELED]]
 // CHECK-DAG: unswitch = #[[UNSWITCH]]
 // CHECK-DAG: isVectorized = false
-// CHECK-DAG: parallelAccesses = @metadata::@group1, @metadata::@group2>
+// CHECK-DAG: parallelAccesses =  #[[GROUP1]], #[[GROUP2]]>
 #loopMD = #llvm.loop_annotation<disableNonforced = false,
         mustProgress = true,
         vectorize = #vectorize,
         interleave = #interleave,
         unroll = #unroll,
         unrollAndJam = #unrollAndJam,
         licm = #licm,
         distribute = #distribute,
         pipeline = #pipeline,
         peeled = #peeled,
         unswitch = #unswitch,
         isVectorized = false,
-        parallelAccesses = @metadata::@group1, @metadata::@group2>
+        parallelAccesses = #access_group1, #access_group2>
 
 // CHECK: llvm.func @loop_annotation
 llvm.func @loop_annotation() {
   // CHECK: llvm.br ^bb1 {llvm.loop = #[[LOOP_ANNOT]]
   llvm.br ^bb1 {llvm.loop = #loopMD}
 ^bb1:
   llvm.return
 }
 
 llvm.metadata @metadata {
   llvm.access_group @group1
   llvm.access_group @group2
 }

mlir/test/Target/LLVMIR/Import/metadata-loop.ll

 ; RUN: mlir-translate -import-llvm -split-input-file %s | FileCheck %s
 
-; CHECK: llvm.metadata @__llvm_global_metadata {
-; CHECK:   llvm.access_group @[[$GROUP0:.*]]
-; CHECK:   llvm.access_group @[[$GROUP1:.*]]
-; CHECK:   llvm.access_group @[[$GROUP2:.*]]
-; CHECK:   llvm.access_group @[[$GROUP3:.*]]
-; CHECK: }
+; CHECK: #[[$GROUP0:.*]] = #llvm.access_group<id = 0>
+; CHECK: #[[$GROUP1:.*]] = #llvm.access_group<id = 1>
+; CHECK: #[[$GROUP2:.*]] = #llvm.access_group<id = 2>
+; CHECK: #[[$GROUP3:.*]] = #llvm.access_group<id = 3>
 
 ; CHECK-LABEL: llvm.func @access_group
 define void @access_group(ptr %arg1) {
-  ; CHECK:  access_groups = [@__llvm_global_metadata::@[[$GROUP0]], @__llvm_global_metadata::@[[$GROUP1]]]
+  ; CHECK:  access_groups = [#[[$GROUP0]], #[[$GROUP1]]]
   %1 = load i32, ptr %arg1, !llvm.access.group !0
-  ; CHECK:  access_groups = [@__llvm_global_metadata::@[[$GROUP2]], @__llvm_global_metadata::@[[$GROUP0]]]
+  ; CHECK:  access_groups = [#[[$GROUP2]], #[[$GROUP0]]]
   %2 = load i32, ptr %arg1, !llvm.access.group !1
-  ; CHECK:  access_groups = [@__llvm_global_metadata::@[[$GROUP3]]]
+  ; CHECK:  access_groups = [#[[$GROUP3]]]
   %3 = load i32, ptr %arg1, !llvm.access.group !2
   ret void
 }
 
 !0 = !{!3, !4}
 !1 = !{!5, !3}
 !2 = distinct !{}
 !3 = distinct !{}
end:
   ret void
 }
 
 !1 = distinct !{!1, !2}
 !2 = !{!"llvm.loop.unswitch.partial.disable"}
 
 ; // -----
 
-; CHECK: #[[$ANNOT_ATTR:.*]] = #llvm.loop_annotation<parallelAccesses = @__llvm_global_metadata::@[[GROUP0:.*]]>
-
-; CHECK: llvm.metadata @__llvm_global_metadata {
-; CHECK:   llvm.access_group @[[GROUP0]]
+; CHECK: #[[GROUP0:.*]] = #llvm.access_group<id = 0>
+; CHECK: #[[$ANNOT_ATTR:.*]] = #llvm.loop_annotation<parallelAccesses = #[[GROUP0]]>
 
 ; CHECK-LABEL: @parallel_accesses
 define void @parallel_accesses(ptr %arg) {
 entry:
   %0 = load i32, ptr %arg, !llvm.access.group !0
 ; CHECK: llvm.br ^{{.*}} {loop_annotation = #[[$ANNOT_ATTR]]}
   br label %end, !llvm.loop !1
 end:
   ret void
 }
 
 !0 = distinct !{}
 !1 = distinct !{!1, !2}
 !2 = !{!"llvm.loop.parallel_accesses", !0}
 
 ; // -----
 
-; CHECK: #[[$ANNOT_ATTR:.*]] = #llvm.loop_annotation<parallelAccesses = @__llvm_global_metadata::@[[GROUP0:.*]], @__llvm_global_metadata::@[[GROUP1:.*]]>
-
-; CHECK: llvm.metadata @__llvm_global_metadata {
-; CHECK:   llvm.access_group @[[GROUP0]]
-; CHECK:   llvm.access_group @[[GROUP1]]
+; CHECK: #[[GROUP0:.*]] = #llvm.access_group<id = 0>
+; CHECK: #[[GROUP1:.*]] = #llvm.access_group<id = 1>
+; CHECK: #[[$ANNOT_ATTR:.*]] = #llvm.loop_annotation<parallelAccesses = #[[GROUP0]], #[[GROUP1]]>
 
 ; CHECK-LABEL: @multiple_parallel_accesses
 define void @multiple_parallel_accesses(ptr %arg) {
 entry:
   %0 = load i32, ptr %arg, !llvm.access.group !0
   %1 = load i32, ptr %arg, !llvm.access.group !3
 ; CHECK: llvm.br ^{{.*}} {loop_annotation = #[[$ANNOT_ATTR]]}
   br label %end, !llvm.loop !1
 end:
   ret void
 }
 
 !0 = distinct !{}
 !1 = distinct !{!1, !2}
 !2 = !{!"llvm.loop.parallel_accesses", !0, !3}
 !3 = distinct !{}

mlir/test/Target/LLVMIR/loop-metadata.mlir

^bb1:
   llvm.return
 }
 
 // CHECK: ![[LOOP_NODE]] = distinct !{![[LOOP_NODE]], !{{[0-9]+}}}
 // CHECK-DAG: ![[VEC_NODE0:[0-9]+]] = !{!"llvm.loop.unswitch.partial.disable"}
 
 // -----
 
+#access_group1 = #llvm.access_group<id = 1>
+#access_group2 = #llvm.access_group<id = 2>
+
 // CHECK-LABEL: @loopOptions
 llvm.func @loopOptions(%arg1 : i32, %arg2 : i32) {
     %0 = llvm.mlir.constant(0 : i32) : i32
     %4 = llvm.alloca %arg1 x i32 : (i32) -> (!llvm.ptr)
     llvm.br ^bb3(%0 : i32)
   ^bb3(%1: i32):
     %2 = llvm.icmp "slt" %1, %arg1 : i32
     // CHECK: br i1 {{.*}} !llvm.loop ![[LOOP_NODE:[0-9]+]]
     llvm.cond_br %2, ^bb4, ^bb5 {loop_annotation = #llvm.loop_annotation<
           licm = <disable = true>,
           interleave = <count = 1>,
           unroll = <disable = true>, pipeline = <disable = true, initiationinterval = 2>,
-          parallelAccesses = @metadata::@group1, @metadata::@group2>}
+          parallelAccesses = #access_group1, #access_group2>}
   ^bb4:
     %3 = llvm.add %1, %arg2  : i32
     // CHECK: = load i32, ptr %{{.*}} !llvm.access.group ![[ACCESS_GROUPS_NODE:[0-9]+]]
-    %5 = llvm.load %4 {access_groups = [@metadata::@group1, @metadata::@group2]} : !llvm.ptr -> i32
+    %5 = llvm.load %4 {access_groups = [#access_group1, #access_group2]} : !llvm.ptr -> i32
     // CHECK: store i32 %{{.*}}, ptr %{{.*}} !llvm.access.group ![[ACCESS_GROUPS_NODE]]
-    llvm.store %5, %4 {access_groups = [@metadata::@group1, @metadata::@group2]} : i32, !llvm.ptr
+    llvm.store %5, %4 {access_groups = [#access_group1, #access_group2]} : i32, !llvm.ptr
     // CHECK: = atomicrmw add ptr %{{.*}}, i32 %{{.*}} !llvm.access.group ![[ACCESS_GROUPS_NODE]]
-    %6 = llvm.atomicrmw add %4, %5 monotonic {access_groups = [@metadata::@group1, @metadata::@group2]} : !llvm.ptr, i32
+    %6 = llvm.atomicrmw add %4, %5 monotonic {access_groups = [#access_group1, #access_group2]} : !llvm.ptr, i32
     // CHECK: = cmpxchg ptr %{{.*}}, i32 %{{.*}}, i32 %{{.*}} !llvm.access.group ![[ACCESS_GROUPS_NODE]]
-    %7 = llvm.cmpxchg %4, %5, %6 acq_rel monotonic {access_groups = [@metadata::@group1, @metadata::@group2]} : !llvm.ptr, i32
+    %7 = llvm.cmpxchg %4, %5, %6 acq_rel monotonic {access_groups = [#access_group1, #access_group2]} : !llvm.ptr, i32
     %8 = llvm.mlir.constant(0 : i1) : i1
     %9 = llvm.mlir.constant(42 : i8) : i8
     // CHECK: llvm.memcpy{{.*}} !llvm.access.group ![[ACCESS_GROUPS_NODE]]
-    "llvm.intr.memcpy"(%4, %4, %0, %8) {access_groups = [@metadata::@group1, @metadata::@group2]} : (!llvm.ptr, !llvm.ptr, i32, i1) -> ()
+    "llvm.intr.memcpy"(%4, %4, %0, %8) {access_groups = [#access_group1, #access_group2]} : (!llvm.ptr, !llvm.ptr, i32, i1) -> ()
     // CHECK: llvm.memset{{.*}} !llvm.access.group ![[ACCESS_GROUPS_NODE]]
-    "llvm.intr.memset"(%4, %9, %0, %8) {access_groups = [@metadata::@group1, @metadata::@group2]} : (!llvm.ptr, i8, i32, i1) -> ()
+    "llvm.intr.memset"(%4, %9, %0, %8) {access_groups = [#access_group1, #access_group2]} : (!llvm.ptr, i8, i32, i1) -> ()
     // CHECK: br label {{.*}} !llvm.loop ![[LOOP_NODE]]
     llvm.br ^bb3(%3 : i32) {loop_annotation = #llvm.loop_annotation<
           licm = <disable = true>,
           interleave = <count = 1>,
           unroll = <disable = true>, pipeline = <disable = true, initiationinterval = 2>,
-          parallelAccesses = @metadata::@group1, @metadata::@group2>}
+          parallelAccesses = #access_group1, #access_group2>}
 
   ^bb5:
     llvm.return
 }
 
-llvm.metadata @metadata {
-  llvm.access_group @group1
-  llvm.access_group @group2
-}
-
 // CHECK: ![[LOOP_NODE]] = distinct !{![[LOOP_NODE]], !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}}
 // CHECK-DAG: ![[PA_NODE:[0-9]+]] = !{!"llvm.loop.parallel_accesses", ![[GROUP_NODE1:[0-9]+]], ![[GROUP_NODE2:[0-9]+]]}
 // CHECK-DAG: ![[GROUP_NODE1:[0-9]+]] = distinct !{}
 // CHECK-DAG: ![[GROUP_NODE2:[0-9]+]] = distinct !{}
 // CHECK-DAG: ![[UNROLL_DISABLE_NODE:[0-9]+]] = !{!"llvm.loop.unroll.disable"}
 // CHECK-DAG: ![[LICM_DISABLE_NODE:[0-9]+]] = !{!"llvm.licm.disable"}
 // CHECK-DAG: ![[INTERLEAVE_NODE:[0-9]+]] = !{!"llvm.loop.interleave.count", i32 1}
 // CHECK-DAG: ![[PIPELINE_DISABLE_NODE:[0-9]+]] = !{!"llvm.loop.pipeline.disable", i1 true}
 // CHECK-DAG: ![[II_NODE:[0-9]+]] = !{!"llvm.loop.pipeline.initiationinterval", i32 2}
 // CHECK-DAG: ![[ACCESS_GROUPS_NODE:[0-9]+]] = !{![[GROUP_NODE1]], ![[GROUP_NODE2]]}

mlir/test/mlir-tblgen/llvm-intrinsics.td

 // GROUPS: [NoMemoryEffect]
 // It has a result.
 // GROUPS: 1,
 // It implements the access group interface.
 // GROUPS: 1,
 // It does not implement the alias analysis interface.
 // GROUPS: 0>
 // It has an access group attribute.
-// GROUPS: OptionalAttr<SymbolRefArrayAttr>:$access_groups
+// GROUPS: OptionalAttr<AccessGroupArrayAttr>:$access_groups
 
 //---------------------------------------------------------------------------//
 
 // This checks that we can define an op that takes in alias analysis metadata.
 //
 // RUN: cat %S/../../../llvm/include/llvm/IR/Intrinsics.td \
 // RUN: | grep -v "llvm/IR/Intrinsics" \
 // RUN: | mlir-tblgen -gen-llvmir-intrinsics -I %S/../../../llvm/include/ --llvmir-intrinsics-filter=ptrmask --llvmir-intrinsics-alias-analysis-regexp=ptrmask \

mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp

if (intr.isCommutative())
     traits.push_back("Commutative");
   if (!intr.hasSideEffects())
     traits.push_back("NoMemoryEffect");
 
   // Prepare strings for operands.
   llvm::SmallVector<llvm::StringRef, 8> operands(intr.getNumOperands(),
                                                  "LLVM_Type");
   if (requiresAccessGroup)
-    operands.push_back("OptionalAttr<SymbolRefArrayAttr>:$access_groups");
+    operands.push_back("OptionalAttr<AccessGroupArrayAttr>:$access_groups");
   if (requiresAliasAnalysis) {
     operands.push_back("OptionalAttr<SymbolRefArrayAttr>:$alias_scopes");
     operands.push_back("OptionalAttr<SymbolRefArrayAttr>:$noalias_scopes");
     operands.push_back("OptionalAttr<SymbolRefArrayAttr>:$tbaa");
   }
 
   // Emit the definition.
   os << "def LLVM_" << intr.getProperRecordName() << " : " << opBaseClass