[X86] Teach computeKnownBitsForTargetNode about MUL_IMM

[kazu]

Summary

This patch teaches computeKnownBitsForTargetNode about MUL_IMM.

MUL_IMM comes up in certain select of constants. Specifically, it is
used to multiply the result of SETCC. Computing the known zero bits
of MUL_IMM allows matchAddressRecursively us to convert some OR into
ADD, which eventually becomes a part of LEA.

This patch fixes:

https://github.com/llvm/llvm-project/issues/61365

[kazu]

Guard against a potential integer overflow.

[craig.topper]

llvm/lib/Target/X86/X86ISelLowering.cpp

38108

Why can't we use KnownBits.mul?

[foad]

llvm/lib/Target/X86/X86ISelLowering.cpp

38105–38106

You can write this as ~Known2.Zero or Known2.getMaxValue(). But I agree with @craig.topper.

[kazu]

Switched to KnownBits::mul.

[kazu]

Please take a look. Thanks!

[RKSimon]

llvm/test/CodeGen/X86/select-constant-lea.ll

20

Please can you confirm what's caused us to use the ORLIke pattern?

[kazu]

llvm/test/CodeGen/X86/select-constant-lea.ll

20

combineSelectOfTwoConstants expands ISD::SELECT as:

// select Cond, TC, FC --> (zext(Cond) * (TC - FC)) + FC

with ISD::ADD. Then DAGCombiner::visitADD does:

// fold (a+b) -> (a|b) iff a and b share no bits.                                                 
if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&
    DAG.haveNoCommonBitsSet(N0, N1))
  return DAG.getNode(ISD::OR, DL, VT, N0, N1);

This is where the ISD::OR comes from.

[RKSimon]

LGTM - cheers