[X86] Teach computeKnownBitsForTargetNode about MUL_IMM

[kazu]

Summary

This patch teaches computeKnownBitsForTargetNode about MUL_IMM.

MUL_IMM comes up in certain select of constants. Specifically, it is
used to multiply the result of SETCC. Computing the known zero bits
of MUL_IMM allows matchAddressRecursively us to convert some OR into
ADD, which eventually becomes a part of LEA.

This patch fixes:

https://github.com/llvm/llvm-project/issues/61365

[kazu]

Guard against a potential integer overflow.

[craig.topper]

llvm/lib/Target/X86/X86ISelLowering.cpp

38108

Why can't we use KnownBits.mul?

[foad]

llvm/lib/Target/X86/X86ISelLowering.cpp

38105–38106

You can write this as ~Known2.Zero or Known2.getMaxValue(). But I agree with @craig.topper.

[kazu]

Switched to KnownBits::mul.

[kazu]

Please take a look. Thanks!

[RKSimon]

llvm/test/CodeGen/X86/select-constant-lea.ll

20

Please can you confirm what's caused us to use the ORLIke pattern?

[kazu]

llvm/test/CodeGen/X86/select-constant-lea.ll

20

combineSelectOfTwoConstants expands ISD::SELECT as:

// select Cond, TC, FC --> (zext(Cond) * (TC - FC)) + FC

with ISD::ADD. Then DAGCombiner::visitADD does:

// fold (a+b) -> (a|b) iff a and b share no bits.                                                 
if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&
    DAG.haveNoCommonBitsSet(N0, N1))
  return DAG.getNode(ISD::OR, DL, VT, N0, N1);

This is where the ISD::OR comes from.

[RKSimon]

LGTM - cheers

llvm/lib/Target/X86/X86ISelLowering.cpp

           Opc == ISD::INTRINSIC_W_CHAIN ||
           Opc == ISD::INTRINSIC_VOID) &&
          "Should use MaskedValueIsZero if you don't know whether Op"
          " is a target node!");
 
   Known.resetAll();
   switch (Opc) {
   default: break;
+  case X86ISD::MUL_IMM: {
+    KnownBits Known2 =
+        DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
+    APInt Val = Known2.Zero;
+    Val.flipAllBits();
+    Val *= cast<ConstantSDNode>(Op.getOperand(1))->getAPIntValue();
+    Known.Zero.setBitsFrom(Val.getActiveBits());
+    break;
+  }
   case X86ISD::SETCC:
     Known.Zero.setBitsFrom(1);
     break;
   case X86ISD::MOVMSK: {
     unsigned NumLoBits = Op.getOperand(0).getValueType().getVectorNumElements();
     Known.Zero.setBitsFrom(NumLoBits);
     break;
   }

llvm/test/CodeGen/X86/select-constant-lea.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown                      | FileCheck %s --check-prefix=BASE
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=slow-3ops-lea | FileCheck %s --check-prefix=SLOWLEA3
 
 define i32 @select_unsigned_lt_10_8_13j(i32 %0) {
 ; BASE-LABEL: select_unsigned_lt_10_8_13j:
 ; BASE:       # %bb.0:
 ; BASE-NEXT:    xorl %eax, %eax
 ; BASE-NEXT:    cmpl $10, %edi
 ; BASE-NEXT:    setae %al
-; BASE-NEXT:    leal (%rax,%rax,4), %eax
-; BASE-NEXT:    orl $8, %eax
+; BASE-NEXT:    leal 8(%rax,%rax,4), %eax
 ; BASE-NEXT:    retq
 ;
 ; SLOWLEA3-LABEL: select_unsigned_lt_10_8_13j:
 ; SLOWLEA3:       # %bb.0:
 ; SLOWLEA3-NEXT:    xorl %eax, %eax
 ; SLOWLEA3-NEXT:    cmpl $10, %edi
 ; SLOWLEA3-NEXT:    setae %al
 ; SLOWLEA3-NEXT:    leal (%rax,%rax,4), %eax
-; SLOWLEA3-NEXT:    orl $8, %eax
+; SLOWLEA3-NEXT:    addl $8, %eax
 ; SLOWLEA3-NEXT:    retq
   %2 = icmp ult i32 %0, 10
   %3 = select i1 %2, i32 8, i32 13
   ret i32 %3
 }