[AArch64] More patterns to generate LD1R vector splats

[SjoerdMeijer]

Summary

We are missing patterns to generate vector splats using LD1R.
A shuffle vector with all 0s is a vector splat:

%lv2i32 = load <2 x i32>, ptr %P
%B = shufflevector <2 x i32> %lv2i32, <2 x i32> undef, <2 x i32> zeroinitializer

for which we can generate a LD1R if the operands are a load and undef. This was inspired by the tests in:

llvm-project/llvm/test/Analysis/CostModel/AArch64/shuffle-load.ll

for which we don't generate LD1Rs.

[dmgreen]

Sounds good. I'm a little surprised that if we have a vector load where only one lane it demanded that we don't change it into a scalar load.

Can you add this as a multi-use test case. Otherwise LGTM:

define <4 x i32> @shuffle2_multiuse(ptr %P) {
; CHECK-LABEL: shuffle2_multiuse:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    dup v1.4s, v0.s[0]
; CHECK-NEXT:    dup v0.4s, v0.s[1]
; CHECK-NEXT:    add v0.4s, v1.4s, v0.4s
; CHECK-NEXT:    ret
  %lv2i32 = load <4 x i32>, ptr %P
  %B = shufflevector <4 x i32> %lv2i32, <4 x i32> undef, <4 x i32> zeroinitializer
  %C = shufflevector <4 x i32> %lv2i32, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
  %D = add <4 x i32> %B, %C
  ret <4 x i32> %D
}

[SjoerdMeijer]

Thanks, also for that case which I will add, that's interesting indeed.

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
           (LD1Rv2s GPR64sp:$Rn)>;
 def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
           (LD1Rv4s GPR64sp:$Rn)>;
 def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
           (LD1Rv2d GPR64sp:$Rn)>;
 def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
           (LD1Rv1d GPR64sp:$Rn)>;
+
+def : Pat<(v8i8 (AArch64duplane8 (v16i8 (insert_subvector undef, (v8i8 (load GPR64sp:$Rn)), (i64 0))), (i64 0))),
+          (LD1Rv8b GPR64sp:$Rn)>;
+def : Pat<(v16i8 (AArch64duplane8 (v16i8 (load GPR64sp:$Rn)), (i64 0))),
+          (LD1Rv16b GPR64sp:$Rn)>;
+def : Pat<(v4i16 (AArch64duplane16 (v8i16 (insert_subvector undef, (v4i16 (load GPR64sp:$Rn)), (i64 0))), (i64 0))),
+          (LD1Rv4h GPR64sp:$Rn)>;
+def : Pat<(v8i16 (AArch64duplane16 (v8i16 (load GPR64sp:$Rn)), (i64 0))),
+          (LD1Rv8h GPR64sp:$Rn)>;
+def : Pat<(v2i32 (AArch64duplane32 (v4i32 (insert_subvector undef, (v2i32 (load GPR64sp:$Rn)), (i64 0))), (i64 0))),
+          (LD1Rv2s GPR64sp:$Rn)>;
+def : Pat<(v4i32 (AArch64duplane32 (v4i32 (load GPR64sp:$Rn)), (i64 0))),
+          (LD1Rv4s GPR64sp:$Rn)>;
+def : Pat<(v2i64 (AArch64duplane64 (v2i64 (load GPR64sp:$Rn)), (i64 0))),
+          (LD1Rv2d GPR64sp:$Rn)>;
+
 // Grab the floating point version too
 def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
           (LD1Rv2s GPR64sp:$Rn)>;
 def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
           (LD1Rv4s GPR64sp:$Rn)>;
 def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
           (LD1Rv2d GPR64sp:$Rn)>;
 def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),

llvm/test/CodeGen/AArch64/neon-vector-splat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu | FileCheck %s
 
 define <2 x i32> @shuffle(ptr %P) {
 ; CHECK-LABEL: shuffle:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr d0, [x0]
-; CHECK-NEXT:    dup v0.2s, v0.s[0]
+; CHECK-NEXT:    ld1r { v0.2s }, [x0]
 ; CHECK-NEXT:    ret
   %lv2i32 = load <2 x i32>, ptr %P
   %B = shufflevector <2 x i32> %lv2i32, <2 x i32> undef, <2 x i32> zeroinitializer
   ret <2 x i32> %B
 }
 
 define <4 x i32> @shuffle2(ptr %P) {
 ; CHECK-LABEL: shuffle2:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr q0, [x0]
-; CHECK-NEXT:    dup v0.4s, v0.s[0]
+; CHECK-NEXT:    ld1r { v0.4s }, [x0]
 ; CHECK-NEXT:    ret
   %lv2i32 = load <4 x i32>, ptr %P
   %B = shufflevector <4 x i32> %lv2i32, <4 x i32> undef, <4 x i32> zeroinitializer
   ret <4 x i32> %B
 }
 
 define <4 x i16> @shuffle3(ptr %P) {
 ; CHECK-LABEL: shuffle3:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr d0, [x0]
-; CHECK-NEXT:    dup v0.4h, v0.h[0]
+; CHECK-NEXT:    ld1r { v0.4h }, [x0]
 ; CHECK-NEXT:    ret
   %lv4i16 = load <4 x i16>, ptr %P
   %sv4i16 = shufflevector <4 x i16> %lv4i16, <4 x i16> undef, <4 x i32> zeroinitializer
   ret <4 x i16> %sv4i16
 }
 
 define <8 x i16> @shuffle4(ptr %P) {
 ; CHECK-LABEL: shuffle4:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr q0, [x0]
-; CHECK-NEXT:    dup v0.8h, v0.h[0]
+; CHECK-NEXT:    ld1r { v0.8h }, [x0]
 ; CHECK-NEXT:    ret
   %lv8i16 = load <8 x i16>, ptr %P
   %sv8i16 = shufflevector <8 x i16> %lv8i16, <8 x i16> undef, <8 x i32> zeroinitializer
   ret <8 x i16> %sv8i16
 }
 
 define <8 x i8> @shuffle5(ptr %P) {
 ; CHECK-LABEL: shuffle5:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr d0, [x0]
-; CHECK-NEXT:    dup v0.8b, v0.b[0]
+; CHECK-NEXT:    ld1r { v0.8b }, [x0]
 ; CHECK-NEXT:    ret
   %lv8i8 = load <8 x i8>, ptr %P
   %sv8i8 = shufflevector <8 x i8> %lv8i8, <8 x i8> undef, <8 x i32> zeroinitializer
   ret <8 x i8> %sv8i8
 }
 
 define <16 x i8> @shuffle6(ptr %P) {
 ; CHECK-LABEL: shuffle6:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr q0, [x0]
-; CHECK-NEXT:    dup v0.16b, v0.b[0]
+; CHECK-NEXT:    ld1r { v0.16b }, [x0]
 ; CHECK-NEXT:    ret
   %lv16i8 = load <16 x i8>, ptr %P
   %sv16i8 = shufflevector <16 x i8> %lv16i8, <16 x i8> undef, <16 x i32> zeroinitializer
   ret <16 x i8> %sv16i8
 }
 
 define <2 x i64> @shuffle7(ptr %P) {
 ; CHECK-LABEL: shuffle7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr q0, [x0]
-; CHECK-NEXT:    dup v0.2d, v0.d[0]
+; CHECK-NEXT:    ld1r { v0.2d }, [x0]
 ; CHECK-NEXT:    ret
   %lv2i64 = load <2 x i64>, ptr %P
   %sv2i64 = shufflevector <2 x i64> %lv2i64, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %sv2i64
 }