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Differential D143279

InstCombine: Handle folding fcmp of 0 into llvm.is.fpclass
ClosedPublic

Authored by arsenm on Feb 3 2023, 9:10 AM.

Details

Reviewers
foad
sepavloff
kpn
jyknight
jcranmer-intel
andrew.w.kaylor
scanon
Summary

This needs to consider the denormal mode.

Diff Detail

Event Timeline

arsenm created this revision.Feb 3 2023, 9:10 AM
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arsenm added parent revisions: D142907: LangRef: Add "dynamic" option to "denormal-fp-math", D139130: InstCombine: Fold and (fcmp), (is.fpclass) into is.fpclass.Feb 3 2023, 9:10 AM
Harbormaster completed remote builds in B211749: Diff 494668.Feb 3 2023, 9:10 AM
foad added inline comments.Feb 6 2023, 2:04 AM
llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
1272

This is done?

1278

Simplify this to ~fcZero & fcAllFlags

1499

You can use getFunction, here and below

arsenm updated this revision to Diff 495197.Feb 6 2023, 10:05 AM
arsenm marked 3 inline comments as done.
Harbormaster completed remote builds in B212156: Diff 495197.Feb 6 2023, 10:07 AM
foad accepted this revision.Feb 6 2023, 12:35 PM

LGTM.

This revision is now accepted and ready to land.Feb 6 2023, 12:35 PM
arsenm closed this revision.Feb 15 2023, 1:21 AM

df78976d023a6b7fcf64bc695261b7b402fcede0

arsenm reopened this revision.Feb 15 2023, 1:28 AM

Pushed wrong patch

This revision is now accepted and ready to land.Feb 15 2023, 1:28 AM
arsenm added a parent revision: D144081: InstCombine: Fold and/or of fcmp into class.Feb 15 2023, 1:32 AM
arsenm closed this revision.EditedMar 15 2023, 4:07 AM

0d18f315d87c52ed08635aaca270c4f0b0d417ec

Revision Contents

PathSize
llvm/
lib/
Transforms/
InstCombine/
26 lines
test/
Transforms/
InstCombine/
48 lines
164 lines

Diff 494668

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

Show First 20 Lines • Show All 1,240 Lines • ▼ Show 20 Linesstatic Value *matchIsFiniteTest(InstCombiner::BuilderTy &Builder, FCmpInst *LHS,
IRBuilder<>::FastMathFlagGuard FMFG(Builder); IRBuilder<>::FastMathFlagGuard FMFG(Builder);
FastMathFlags FMF = LHS->getFastMathFlags(); FastMathFlags FMF = LHS->getFastMathFlags();
FMF &= RHS->getFastMathFlags(); FMF &= RHS->getFastMathFlags();
Builder.setFastMathFlags(FMF); Builder.setFastMathFlags(FMF);
return Builder.CreateFCmp(FCmpInst::getOrderedPredicate(PredR), RHS0, RHS1); return Builder.CreateFCmp(FCmpInst::getOrderedPredicate(PredR), RHS0, RHS1);
} }
/// Return true if it's possible to assume IEEE treatment of input denormals in
/// \p F for \p Val.
static bool inputDenormalIsIEEE(const Function &F, const Value *Val) {
Type *Ty = Val->getType()->getScalarType();
return F.getDenormalMode(Ty->getFltSemantics()).Input == DenormalMode::IEEE;
}
/// Returns a pair of values, which if passed to llvm.is.fpclass, returns the /// Returns a pair of values, which if passed to llvm.is.fpclass, returns the
/// same result as an fcmp with the given operands. /// same result as an fcmp with the given operands.
static std::pair<Value *, unsigned> fcmpToClassTest(FCmpInst::Predicate Pred, static std::pair<Value *, unsigned> fcmpToClassTest(FCmpInst::Predicate Pred,
const Function &F,
Value *LHS, Value *RHS) { Value *LHS, Value *RHS) {
const APFloat *ConstRHS; const APFloat *ConstRHS;
if (!match(RHS, m_APFloat(ConstRHS))) if (!match(RHS, m_APFloat(ConstRHS)))
return {nullptr, 0}; return {nullptr, 0};
if (ConstRHS->isZero()) { if (ConstRHS->isZero()) {
// Compares with 0 are only exactly equal to fcZero if input denormals are
// not flushed.
if (FCmpInst::isEquality(Pred) && !inputDenormalIsIEEE(F, LHS))
return {nullptr, 0};
switch (Pred) { switch (Pred) {
#if 0
// TODO: Compares with 0 depends on the denormal handling mode. // TODO: Compares with 0 depends on the denormal handling mode.
foadUnsubmitted
Done
ReplyInline Actions

This is done?

foad: This is done?
case FCmpInst::FCMP_OEQ: // Match x == 0.0 case FCmpInst::FCMP_OEQ: // Match x == 0.0
return {LHS, fcZero}; return {LHS, fcZero};
case FCmpInst::FCMP_UEQ: // Match isnan(x) || (x == 0.0) case FCmpInst::FCMP_UEQ: // Match isnan(x) || (x == 0.0)
return {LHS, fcZero | fcNan}; return {LHS, fcZero | fcNan};
case FCmpInst::FCMP_UNE: // Match (x != 0.0) case FCmpInst::FCMP_UNE: // Match (x != 0.0)
return {LHS, (~fcZero & fcAllFlags) | fcNan}; return {LHS, (~fcZero & fcAllFlags) | fcNan};
foadUnsubmitted
Done
ReplyInline Actions

Simplify this to ~fcZero & fcAllFlags

foad: Simplify this to `~fcZero & fcAllFlags`
case FCmpInst::FCMP_ONE: // Match !isnan(x) && x != 0.0 case FCmpInst::FCMP_ONE: // Match !isnan(x) && x != 0.0
return {LHS, ~fcNan & ~fcZero & fcAllFlags}; return {LHS, ~fcNan & ~fcZero & fcAllFlags};
#endif
case FCmpInst::FCMP_ORD: case FCmpInst::FCMP_ORD:
// Canonical form of ord/uno is with a zero. We would also handle // Canonical form of ord/uno is with a zero. We would also handle
// non-canonical other non-NaN constants or LHS == RHS. // non-canonical other non-NaN constants or LHS == RHS.
return {LHS, ~fcNan & fcAllFlags}; return {LHS, ~fcNan & fcAllFlags};
case FCmpInst::FCMP_UNO: case FCmpInst::FCMP_UNO:
return {LHS, fcNan}; return {LHS, fcNan};
default: default:
break; break;
▲ Show 20 Lines • Show All 201 Lines • ▼ Show 20 LinesValue *InstCombinerImpl::foldLogicOfFCmps(FCmpInst *LHS, FCmpInst *RHS,
} }
// Turn at least two fcmps with constants into llvm.is.fpclass. // Turn at least two fcmps with constants into llvm.is.fpclass.
// //
// If we can represent a combined value test with one class call, we can // If we can represent a combined value test with one class call, we can
// potentially eliminate 4-6 instructions. If we can represent a test with a // potentially eliminate 4-6 instructions. If we can represent a test with a
// single fcmp with fneg and fabs, that's likely a better canonical form. // single fcmp with fneg and fabs, that's likely a better canonical form.
if (LHS->hasOneUse() && RHS->hasOneUse()) { if (LHS->hasOneUse() && RHS->hasOneUse()) {
auto [ClassValRHS, ClassMaskRHS] = fcmpToClassTest(PredR, RHS0, RHS1); auto [ClassValRHS, ClassMaskRHS] =
fcmpToClassTest(PredR, *RHS->getParent()->getParent(), RHS0, RHS1);
foadUnsubmitted
Done
ReplyInline Actions

You can use getFunction, here and below

foad: You can use getFunction, here and below
if (ClassValRHS) { if (ClassValRHS) {
auto [ClassValLHS, ClassMaskLHS] = fcmpToClassTest(PredL, LHS0, LHS1); auto [ClassValLHS, ClassMaskLHS] =
fcmpToClassTest(PredL, *LHS->getParent()->getParent(), LHS0, LHS1);
if (ClassValLHS == ClassValRHS) { if (ClassValLHS == ClassValRHS) {
unsigned CombinedMask = IsAnd ? (ClassMaskLHS & ClassMaskRHS) unsigned CombinedMask = IsAnd ? (ClassMaskLHS & ClassMaskRHS)
: (ClassMaskLHS | ClassMaskRHS); : (ClassMaskLHS | ClassMaskRHS);
return Builder.CreateIntrinsic( return Builder.CreateIntrinsic(
Intrinsic::is_fpclass, {ClassValLHS->getType()}, Intrinsic::is_fpclass, {ClassValLHS->getType()},
{ClassValLHS, Builder.getInt32(CombinedMask)}); {ClassValLHS, Builder.getInt32(CombinedMask)});
} }
} }
} }
return nullptr; return nullptr;
} }
/// Match an fcmp against a special value that performs a test possible by /// Match an fcmp against a special value that performs a test possible by
/// llvm.is.fpclass. /// llvm.is.fpclass.
static bool matchIsFPClassLikeFCmp(Value *Op, Value *&ClassVal, static bool matchIsFPClassLikeFCmp(Value *Op, Value *&ClassVal,
uint64_t &ClassMask) { uint64_t &ClassMask) {
auto *FCmp = dyn_cast<FCmpInst>(Op); auto *FCmp = dyn_cast<FCmpInst>(Op);
if (!FCmp || !FCmp->hasOneUse()) if (!FCmp || !FCmp->hasOneUse())
return false; return false;
std::tie(ClassVal, ClassMask) = fcmpToClassTest( std::tie(ClassVal, ClassMask) =
FCmp->getPredicate(), FCmp->getOperand(0), FCmp->getOperand(1)); fcmpToClassTest(FCmp->getPredicate(), *FCmp->getParent()->getParent(),
FCmp->getOperand(0), FCmp->getOperand(1));
return ClassVal != nullptr; return ClassVal != nullptr;
} }
/// or (is_fpclass x, mask0), (is_fpclass x, mask1) /// or (is_fpclass x, mask0), (is_fpclass x, mask1)
/// -> is_fpclass x, (mask0 | mask1) /// -> is_fpclass x, (mask0 | mask1)
/// and (is_fpclass x, mask0), (is_fpclass x, mask1) /// and (is_fpclass x, mask0), (is_fpclass x, mask1)
/// -> is_fpclass x, (mask0 & mask1) /// -> is_fpclass x, (mask0 & mask1)
/// xor (is_fpclass x, mask0), (is_fpclass x, mask1) /// xor (is_fpclass x, mask0), (is_fpclass x, mask1)
▲ Show 20 Lines • Show All 3,023 Lines • Show Last 20 Lines

llvm/test/Transforms/InstCombine/combine-is.fpclass-and-fcmp.ll

Show First 20 Lines • Show All 205 Lines • ▼ Show 20 Lines;
%is.subnormal = fcmp olt <2 x half> %fabs, <half 0xH0400, half 0xH0400> %is.subnormal = fcmp olt <2 x half> %fabs, <half 0xH0400, half 0xH0400>
%is.finite.class = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> %x, i32 504) %is.finite.class = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> %x, i32 504)
%or = or <2 x i1> %is.finite.class, %is.subnormal %or = or <2 x i1> %is.finite.class, %is.subnormal
ret <2 x i1> %or ret <2 x i1> %or
} }
define i1 @fcmp_oeq_zero_or_class_normal(half %x) { define i1 @fcmp_oeq_zero_or_class_normal(half %x) {
; CHECK-LABEL: @fcmp_oeq_zero_or_class_normal( ; CHECK-LABEL: @fcmp_oeq_zero_or_class_normal(
; CHECK-NEXT: [[OEQ_INF:%.*]] = fcmp oeq half [[X:%.*]], 0xH0000 ; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 360)
; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264) ; CHECK-NEXT: ret i1 [[CLASS]]
; CHECK-NEXT: [[OR:%.*]] = or i1 [[OEQ_INF]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
; ;
%oeq.inf = fcmp oeq half %x, 0.0 %oeq.inf = fcmp oeq half %x, 0.0
%class = call i1 @llvm.is.fpclass.f16(half %x, i32 264) %class = call i1 @llvm.is.fpclass.f16(half %x, i32 264)
%or = or i1 %oeq.inf, %class %or = or i1 %oeq.inf, %class
ret i1 %or ret i1 %or
} }
define i1 @fcmp_oeq_zero_or_class_normal_daz(half %x) #1 { define i1 @fcmp_oeq_zero_or_class_normal_daz(half %x) #1 {
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines;
%oeq.inf = fcmp oeq <2 x half> %x, zeroinitializer %oeq.inf = fcmp oeq <2 x half> %x, zeroinitializer
%class = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> %x, i32 264) %class = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> %x, i32 264)
%or = or <2 x i1> %oeq.inf, %class %or = or <2 x i1> %oeq.inf, %class
ret <2 x i1> %or ret <2 x i1> %or
} }
define i1 @class_normal_or_fcmp_oeq_zero(half %x) { define i1 @class_normal_or_fcmp_oeq_zero(half %x) {
; CHECK-LABEL: @class_normal_or_fcmp_oeq_zero( ; CHECK-LABEL: @class_normal_or_fcmp_oeq_zero(
; CHECK-NEXT: [[OEQ_INF:%.*]] = fcmp oeq half [[X:%.*]], 0xH0000 ; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 360)
; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264) ; CHECK-NEXT: ret i1 [[CLASS]]
; CHECK-NEXT: [[OR:%.*]] = or i1 [[OEQ_INF]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
; ;
%oeq.inf = fcmp oeq half %x, 0.0 %oeq.inf = fcmp oeq half %x, 0.0
%class = call i1 @llvm.is.fpclass.f16(half %x, i32 264) %class = call i1 @llvm.is.fpclass.f16(half %x, i32 264)
%or = or i1 %oeq.inf, %class %or = or i1 %oeq.inf, %class
ret i1 %or ret i1 %or
} }
define i1 @fcmp_ueq_zero_or_class_normal(half %x) { define i1 @fcmp_ueq_zero_or_class_normal(half %x) {
; CHECK-LABEL: @fcmp_ueq_zero_or_class_normal( ; CHECK-LABEL: @fcmp_ueq_zero_or_class_normal(
; CHECK-NEXT: [[UEQ_INF:%.*]] = fcmp ueq half [[X:%.*]], 0xH0000 ; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 363)
; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264) ; CHECK-NEXT: ret i1 [[CLASS]]
; CHECK-NEXT: [[OR:%.*]] = or i1 [[UEQ_INF]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
; ;
%ueq.inf = fcmp ueq half %x, 0.0 %ueq.inf = fcmp ueq half %x, 0.0
%class = call i1 @llvm.is.fpclass.f16(half %x, i32 264) %class = call i1 @llvm.is.fpclass.f16(half %x, i32 264)
%or = or i1 %ueq.inf, %class %or = or i1 %ueq.inf, %class
ret i1 %or ret i1 %or
} }
define i1 @class_normal_or_fcmp_ueq_zero(half %x) { define i1 @class_normal_or_fcmp_ueq_zero(half %x) {
; CHECK-LABEL: @class_normal_or_fcmp_ueq_zero( ; CHECK-LABEL: @class_normal_or_fcmp_ueq_zero(
; CHECK-NEXT: [[UEQ_INF:%.*]] = fcmp ueq half [[X:%.*]], 0xH0000 ; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 363)
; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264) ; CHECK-NEXT: ret i1 [[CLASS]]
; CHECK-NEXT: [[OR:%.*]] = or i1 [[UEQ_INF]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
; ;
%ueq.inf = fcmp ueq half %x, 0.0 %ueq.inf = fcmp ueq half %x, 0.0
%class = call i1 @llvm.is.fpclass.f16(half %x, i32 264) %class = call i1 @llvm.is.fpclass.f16(half %x, i32 264)
%or = or i1 %ueq.inf, %class %or = or i1 %ueq.inf, %class
ret i1 %or ret i1 %or
} }
define i1 @fcmp_one_zero_or_class_normal(half %x) { define i1 @fcmp_one_zero_or_class_normal(half %x) {
; CHECK-LABEL: @fcmp_one_zero_or_class_normal( ; CHECK-LABEL: @fcmp_one_zero_or_class_normal(
; CHECK-NEXT: [[ONE_INF:%.*]] = fcmp one half [[X:%.*]], 0xH0000 ; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 924)
; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264) ; CHECK-NEXT: ret i1 [[CLASS]]
; CHECK-NEXT: [[OR:%.*]] = or i1 [[ONE_INF]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
; ;
%one.inf = fcmp one half %x, 0.0 %one.inf = fcmp one half %x, 0.0
%class = call i1 @llvm.is.fpclass.f16(half %x, i32 264) %class = call i1 @llvm.is.fpclass.f16(half %x, i32 264)
%or = or i1 %one.inf, %class %or = or i1 %one.inf, %class
ret i1 %or ret i1 %or
} }
define i1 @fcmp_one_zero_or_class_normal_daz(half %x) #1 { define i1 @fcmp_one_zero_or_class_normal_daz(half %x) #1 {
Show All 19 Lines;
%one.inf = fcmp one half %x, 0.0 %one.inf = fcmp one half %x, 0.0
%class = call i1 @llvm.is.fpclass.f16(half %x, i32 264) %class = call i1 @llvm.is.fpclass.f16(half %x, i32 264)
%or = or i1 %one.inf, %class %or = or i1 %one.inf, %class
ret i1 %or ret i1 %or
} }
define i1 @class_normal_or_fcmp_one_zero(half %x) { define i1 @class_normal_or_fcmp_one_zero(half %x) {
; CHECK-LABEL: @class_normal_or_fcmp_one_zero( ; CHECK-LABEL: @class_normal_or_fcmp_one_zero(
; CHECK-NEXT: [[ONE_INF:%.*]] = fcmp one half [[X:%.*]], 0xH0000 ; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 924)
; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264) ; CHECK-NEXT: ret i1 [[CLASS]]
; CHECK-NEXT: [[OR:%.*]] = or i1 [[ONE_INF]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
; ;
%one.inf = fcmp one half %x, 0.0 %one.inf = fcmp one half %x, 0.0
%class = call i1 @llvm.is.fpclass.f16(half %x, i32 264) %class = call i1 @llvm.is.fpclass.f16(half %x, i32 264)
%or = or i1 %one.inf, %class %or = or i1 %one.inf, %class
ret i1 %or ret i1 %or
} }
define i1 @fcmp_une_zero_or_class_normal(half %x) { define i1 @fcmp_une_zero_or_class_normal(half %x) {
; CHECK-LABEL: @fcmp_une_zero_or_class_normal( ; CHECK-LABEL: @fcmp_une_zero_or_class_normal(
; CHECK-NEXT: [[UNE_INF:%.*]] = fcmp une half [[X:%.*]], 0xH0000 ; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 927)
; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264) ; CHECK-NEXT: ret i1 [[CLASS]]
; CHECK-NEXT: [[OR:%.*]] = or i1 [[UNE_INF]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
; ;
%une.inf = fcmp une half %x, 0.0 %une.inf = fcmp une half %x, 0.0
%class = call i1 @llvm.is.fpclass.f16(half %x, i32 264) %class = call i1 @llvm.is.fpclass.f16(half %x, i32 264)
%or = or i1 %une.inf, %class %or = or i1 %une.inf, %class
ret i1 %or ret i1 %or
} }
define i1 @class_normal_or_fcmp_une_zero(half %x) { define i1 @class_normal_or_fcmp_une_zero(half %x) {
; CHECK-LABEL: @class_normal_or_fcmp_une_zero( ; CHECK-LABEL: @class_normal_or_fcmp_une_zero(
; CHECK-NEXT: [[UNE_INF:%.*]] = fcmp une half [[X:%.*]], 0xH0000 ; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 927)
; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264) ; CHECK-NEXT: ret i1 [[CLASS]]
; CHECK-NEXT: [[OR:%.*]] = or i1 [[UNE_INF]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
; ;
%une.inf = fcmp une half %x, 0.0 %une.inf = fcmp une half %x, 0.0
%class = call i1 @llvm.is.fpclass.f16(half %x, i32 264) %class = call i1 @llvm.is.fpclass.f16(half %x, i32 264)
%or = or i1 %une.inf, %class %or = or i1 %une.inf, %class
ret i1 %or ret i1 %or
} }
define i1 @class_normal_or_fcmp_une_zero_daz(half %x) #1 { define i1 @class_normal_or_fcmp_une_zero_daz(half %x) #1 {
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -passes=instcombine < %s | FileCheck %s ; RUN: opt -S -passes=instcombine < %s | FileCheck %s
; Test and/or of fcmps that could be folded to llvm.is.fpclass ; Test and/or of fcmps that could be folded to llvm.is.fpclass
; -------------------------------------------------------------------- ; --------------------------------------------------------------------
; Base pattern, !isfinite(x) || x == 0.0 ; Base pattern, !isfinite(x) || x == 0.0
; -------------------------------------------------------------------- ; --------------------------------------------------------------------
; Base pattern !isfinite(x) || x == 0.0 ; Base pattern !isfinite(x) || x == 0.0
define i1 @not_isfinite_or_zero_f16(half %x) { define i1 @not_isfinite_or_zero_f16(half %x) {
; CHECK-LABEL: @not_isfinite_or_zero_f16( ; CHECK-LABEL: @not_isfinite_or_zero_f16(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) ; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]] ; CHECK-NEXT: ret i1 [[CLASS]]
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%cmpinf = fcmp ueq half %fabs, 0xH7C00 %cmpinf = fcmp ueq half %fabs, 0xH7C00
%cmpzero = fcmp oeq half %x, 0xH0000 %cmpzero = fcmp oeq half %x, 0xH0000
%class = or i1 %cmpzero, %cmpinf %class = or i1 %cmpzero, %cmpinf
ret i1 %class ret i1 %class
} }
; Base pattern x == 0.0 || !isfinite(x) ; Base pattern x == 0.0 || !isfinite(x)
define i1 @not_isfinite_or_zero_f16_commute_or(half %x) { define i1 @not_isfinite_or_zero_f16_commute_or(half %x) {
; CHECK-LABEL: @not_isfinite_or_zero_f16_commute_or( ; CHECK-LABEL: @not_isfinite_or_zero_f16_commute_or(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) ; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMPINF]], [[CMPZERO]]
; CHECK-NEXT: ret i1 [[CLASS]] ; CHECK-NEXT: ret i1 [[CLASS]]
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%cmpinf = fcmp ueq half %fabs, 0xH7C00 %cmpinf = fcmp ueq half %fabs, 0xH7C00
%cmpzero = fcmp oeq half %x, 0xH0000 %cmpzero = fcmp oeq half %x, 0xH0000
%class = or i1 %cmpinf, %cmpzero %class = or i1 %cmpinf, %cmpzero
ret i1 %class ret i1 %class
} }
; Base pattern !isfinite(x) || x == -0.0 ; Base pattern !isfinite(x) || x == -0.0
define i1 @not_isfinite_or_zero_f16_negzero(half %x) { define i1 @not_isfinite_or_zero_f16_negzero(half %x) {
; CHECK-LABEL: @not_isfinite_or_zero_f16_negzero( ; CHECK-LABEL: @not_isfinite_or_zero_f16_negzero(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) ; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]] ; CHECK-NEXT: ret i1 [[CLASS]]
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%cmpinf = fcmp ueq half %fabs, 0xH7C00 %cmpinf = fcmp ueq half %fabs, 0xH7C00
%cmpzero = fcmp oeq half %x, -0.0 %cmpzero = fcmp oeq half %x, -0.0
%class = or i1 %cmpzero, %cmpinf %class = or i1 %cmpzero, %cmpinf
ret i1 %class ret i1 %class
} }
define i1 @not_isfinite_or_fabs_oeq_zero_f16(half %x) { define i1 @not_isfinite_or_fabs_oeq_zero_f16(half %x) {
; CHECK-LABEL: @not_isfinite_or_fabs_oeq_zero_f16( ; CHECK-LABEL: @not_isfinite_or_fabs_oeq_zero_f16(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) ; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]] ; CHECK-NEXT: ret i1 [[CLASS]]
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%cmpinf = fcmp ueq half %fabs, 0xH7C00 %cmpinf = fcmp ueq half %fabs, 0xH7C00
%cmpzero = fcmp oeq half %fabs, 0xH0000 %cmpzero = fcmp oeq half %fabs, 0xH0000
%class = or i1 %cmpzero, %cmpinf %class = or i1 %cmpzero, %cmpinf
ret i1 %class ret i1 %class
} }
; Base pattern !isfinite(x) || x == 0.0 ; Base pattern !isfinite(x) || x == 0.0
define <2 x i1> @not_isfinite_or_zero_v2f16(<2 x half> %x) { define <2 x i1> @not_isfinite_or_zero_v2f16(<2 x half> %x) {
; CHECK-LABEL: @not_isfinite_or_zero_v2f16( ; CHECK-LABEL: @not_isfinite_or_zero_v2f16(
; CHECK-NEXT: [[FABS:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]]) ; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 615)
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq <2 x half> [[FABS]], <half 0xH7C00, half 0xH7C00>
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq <2 x half> [[X]], zeroinitializer
; CHECK-NEXT: [[CLASS:%.*]] = or <2 x i1> [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret <2 x i1> [[CLASS]] ; CHECK-NEXT: ret <2 x i1> [[CLASS]]
; ;
%fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
%cmpinf = fcmp ueq <2 x half> %fabs, <half 0xH7C00, half 0xH7C00> %cmpinf = fcmp ueq <2 x half> %fabs, <half 0xH7C00, half 0xH7C00>
%cmpzero = fcmp oeq <2 x half> %x, zeroinitializer %cmpzero = fcmp oeq <2 x half> %x, zeroinitializer
%class = or <2 x i1> %cmpzero, %cmpinf %class = or <2 x i1> %cmpzero, %cmpinf
ret <2 x i1> %class ret <2 x i1> %class
} }
; Base pattern !isfinite(x) || x == <0.0, -0.0> ; Base pattern !isfinite(x) || x == <0.0, -0.0>
define <2 x i1> @not_isfinite_or_zero_v2f16_pos0_neg0_vec(<2 x half> %x) { define <2 x i1> @not_isfinite_or_zero_v2f16_pos0_neg0_vec(<2 x half> %x) {
; CHECK-LABEL: @not_isfinite_or_zero_v2f16_pos0_neg0_vec( ; CHECK-LABEL: @not_isfinite_or_zero_v2f16_pos0_neg0_vec(
; CHECK-NEXT: [[FABS:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]]) ; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 615)
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq <2 x half> [[FABS]], <half 0xH7C00, half 0xH7C00>
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq <2 x half> [[X]], zeroinitializer
; CHECK-NEXT: [[CLASS:%.*]] = or <2 x i1> [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret <2 x i1> [[CLASS]] ; CHECK-NEXT: ret <2 x i1> [[CLASS]]
; ;
%fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
%cmpinf = fcmp ueq <2 x half> %fabs, <half 0xH7C00, half 0xH7C00> %cmpinf = fcmp ueq <2 x half> %fabs, <half 0xH7C00, half 0xH7C00>
%cmpzero = fcmp oeq <2 x half> %x, <half 0.0, half -0.0> %cmpzero = fcmp oeq <2 x half> %x, <half 0.0, half -0.0>
%class = or <2 x i1> %cmpzero, %cmpinf %class = or <2 x i1> %cmpzero, %cmpinf
ret <2 x i1> %class ret <2 x i1> %class
} }
; Base pattern x == 0.0 || !isfinite(x) ; Base pattern x == 0.0 || !isfinite(x)
define <2 x i1> @not_isfinite_or_zero_v2f16_commute_or(<2 x half> %x) { define <2 x i1> @not_isfinite_or_zero_v2f16_commute_or(<2 x half> %x) {
; CHECK-LABEL: @not_isfinite_or_zero_v2f16_commute_or( ; CHECK-LABEL: @not_isfinite_or_zero_v2f16_commute_or(
; CHECK-NEXT: [[FABS:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]]) ; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 615)
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq <2 x half> [[FABS]], <half 0xH7C00, half 0xH7C00>
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq <2 x half> [[X]], zeroinitializer
; CHECK-NEXT: [[CLASS:%.*]] = or <2 x i1> [[CMPINF]], [[CMPZERO]]
; CHECK-NEXT: ret <2 x i1> [[CLASS]] ; CHECK-NEXT: ret <2 x i1> [[CLASS]]
; ;
%fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
%cmpinf = fcmp ueq <2 x half> %fabs, <half 0xH7C00, half 0xH7C00> %cmpinf = fcmp ueq <2 x half> %fabs, <half 0xH7C00, half 0xH7C00>
%cmpzero = fcmp oeq <2 x half> %x, zeroinitializer %cmpzero = fcmp oeq <2 x half> %x, zeroinitializer
%class = or <2 x i1> %cmpinf, %cmpzero %class = or <2 x i1> %cmpinf, %cmpzero
ret <2 x i1> %class ret <2 x i1> %class
} }
; Positive test ; Positive test
define i1 @oeq_isinf_or_oeq_zero(half %x) { define i1 @oeq_isinf_or_oeq_zero(half %x) {
; CHECK-LABEL: @oeq_isinf_or_oeq_zero( ; CHECK-LABEL: @oeq_isinf_or_oeq_zero(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) ; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 612)
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]] ; CHECK-NEXT: ret i1 [[CLASS]]
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%cmpinf = fcmp oeq half %fabs, 0xH7C00 %cmpinf = fcmp oeq half %fabs, 0xH7C00
%cmpzero = fcmp oeq half %x, 0xH0000 %cmpzero = fcmp oeq half %x, 0xH0000
%class = or i1 %cmpzero, %cmpinf %class = or i1 %cmpzero, %cmpinf
ret i1 %class ret i1 %class
} }
; Missing fabs for infinity check ; Missing fabs for infinity check
define i1 @ueq_inf_or_oeq_zero(half %x) { define i1 @ueq_inf_or_oeq_zero(half %x) {
; CHECK-LABEL: @ueq_inf_or_oeq_zero( ; CHECK-LABEL: @ueq_inf_or_oeq_zero(
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00 ; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 611)
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]] ; CHECK-NEXT: ret i1 [[CLASS]]
; ;
%cmpinf = fcmp ueq half %x, 0xH7C00 %cmpinf = fcmp ueq half %x, 0xH7C00
%cmpzero = fcmp oeq half %x, 0xH0000 %cmpzero = fcmp oeq half %x, 0xH0000
%class = or i1 %cmpzero, %cmpinf %class = or i1 %cmpzero, %cmpinf
ret i1 %class ret i1 %class
} }
; Extra fabs. ; Extra fabs.
define i1 @oeq_isinf_or_fabs_oeq_zero(half %x) { define i1 @oeq_isinf_or_fabs_oeq_zero(half %x) {
; CHECK-LABEL: @oeq_isinf_or_fabs_oeq_zero( ; CHECK-LABEL: @oeq_isinf_or_fabs_oeq_zero(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) ; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 612)
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]] ; CHECK-NEXT: ret i1 [[CLASS]]
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%cmpinf = fcmp oeq half %fabs, 0xH7C00 %cmpinf = fcmp oeq half %fabs, 0xH7C00
%cmpzero = fcmp oeq half %fabs, 0xH0000 %cmpzero = fcmp oeq half %fabs, 0xH0000
%class = or i1 %cmpzero, %cmpinf %class = or i1 %cmpzero, %cmpinf
ret i1 %class ret i1 %class
} }
; Positive test ; Positive test
define i1 @ueq_0_or_oeq_inf(half %x) { define i1 @ueq_0_or_oeq_inf(half %x) {
; CHECK-LABEL: @ueq_0_or_oeq_inf( ; CHECK-LABEL: @ueq_0_or_oeq_inf(
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH0000 ; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 611)
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH7C00
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]] ; CHECK-NEXT: ret i1 [[CLASS]]
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%cmpinf = fcmp ueq half %fabs, 0xH0000 %cmpinf = fcmp ueq half %fabs, 0xH0000
%cmpzero = fcmp oeq half %x, 0xH7C00 %cmpzero = fcmp oeq half %x, 0xH7C00
%class = or i1 %cmpzero, %cmpinf %class = or i1 %cmpzero, %cmpinf
ret i1 %class ret i1 %class
} }
; Positive test ; Positive test
define i1 @not_isfinite_or_zero_f16_not_inf(half %x) { define i1 @not_isfinite_or_zero_f16_not_inf(half %x) {
; CHECK-LABEL: @not_isfinite_or_zero_f16_not_inf( ; CHECK-LABEL: @not_isfinite_or_zero_f16_not_inf(
; CHECK-NEXT: ret i1 true ; CHECK-NEXT: ret i1 true
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%cmpinf = fcmp ueq half %fabs, 0xH7C01 %cmpinf = fcmp ueq half %fabs, 0xH7C01
%cmpzero = fcmp oeq half %x, 0xH0000 %cmpzero = fcmp oeq half %x, 0xH0000
%class = or i1 %cmpzero, %cmpinf %class = or i1 %cmpzero, %cmpinf
ret i1 %class ret i1 %class
} }
; Positive test ; Positive test
define i1 @ueq_inf_or_ueq_zero(half %x) { define i1 @ueq_inf_or_ueq_zero(half %x) {
; CHECK-LABEL: @ueq_inf_or_ueq_zero( ; CHECK-LABEL: @ueq_inf_or_ueq_zero(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) ; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp ueq half [[X]], 0xH0000
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]] ; CHECK-NEXT: ret i1 [[CLASS]]
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%cmpinf = fcmp ueq half %fabs, 0xH7C00 %cmpinf = fcmp ueq half %fabs, 0xH7C00
%cmpzero = fcmp ueq half %x, 0xH0000 %cmpzero = fcmp ueq half %x, 0xH0000
%class = or i1 %cmpzero, %cmpinf %class = or i1 %cmpzero, %cmpinf
ret i1 %class ret i1 %class
} }
; Positive test ; Positive test
define i1 @not_isfinite_and_zero_f16(half %x) { define i1 @not_isfinite_and_zero_f16(half %x) {
; CHECK-LABEL: @not_isfinite_and_zero_f16( ; CHECK-LABEL: @not_isfinite_and_zero_f16(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) ; CHECK-NEXT: ret i1 false
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
; CHECK-NEXT: [[CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]]
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%cmpinf = fcmp ueq half %fabs, 0xH7C00 %cmpinf = fcmp ueq half %fabs, 0xH7C00
%cmpzero = fcmp oeq half %x, 0xH0000 %cmpzero = fcmp oeq half %x, 0xH0000
%class = and i1 %cmpzero, %cmpinf %class = and i1 %cmpzero, %cmpinf
ret i1 %class ret i1 %class
} }
Show All 31 Lines;
store i1 %cmpzero, ptr %ptr store i1 %cmpzero, ptr %ptr
%class = or i1 %cmpzero, %cmpinf %class = or i1 %cmpzero, %cmpinf
ret i1 %class ret i1 %class
} }
; Negative test ; Negative test
define i1 @not_isfinite_or_zero_f16_neg_inf(half %x) { define i1 @not_isfinite_or_zero_f16_neg_inf(half %x) {
; CHECK-LABEL: @not_isfinite_or_zero_f16_neg_inf( ; CHECK-LABEL: @not_isfinite_or_zero_f16_neg_inf(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) ; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 99)
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xHFC00
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]] ; CHECK-NEXT: ret i1 [[CLASS]]
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%cmpinf = fcmp ueq half %fabs, 0xHFC00 %cmpinf = fcmp ueq half %fabs, 0xHFC00
%cmpzero = fcmp oeq half %x, 0xH0000 %cmpzero = fcmp oeq half %x, 0xH0000
%class = or i1 %cmpzero, %cmpinf %class = or i1 %cmpzero, %cmpinf
ret i1 %class ret i1 %class
} }
Show All 12 Lines;
%cmpzero = fcmp olt half %x, 0xH0000 %cmpzero = fcmp olt half %x, 0xH0000
%class = or i1 %cmpzero, %cmpinf %class = or i1 %cmpzero, %cmpinf
ret i1 %class ret i1 %class
} }
; Negative test ; Negative test
define i1 @oeq_0_or_fabs_ult_inf(half %x) { define i1 @oeq_0_or_fabs_ult_inf(half %x) {
; CHECK-LABEL: @oeq_0_or_fabs_ult_inf( ; CHECK-LABEL: @oeq_0_or_fabs_ult_inf(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) ; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 507)
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ult half [[FABS]], 0xH7C00
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[CLASS]] ; CHECK-NEXT: ret i1 [[CLASS]]
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%cmpinf = fcmp ult half %fabs, 0xH7C00 %cmpinf = fcmp ult half %fabs, 0xH7C00
%cmpzero = fcmp oeq half %x, 0xH0000 %cmpzero = fcmp oeq half %x, 0xH0000
%class = or i1 %cmpzero, %cmpinf %class = or i1 %cmpzero, %cmpinf
ret i1 %class ret i1 %class
} }
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; -------------------------------------------------------------------- ; --------------------------------------------------------------------
; Negated pattern, isfinite(x) && !(x == 0.0) ; Negated pattern, isfinite(x) && !(x == 0.0)
; -------------------------------------------------------------------- ; --------------------------------------------------------------------
; Negation of base pattern, isfinite(x) && !(x == 0.0) ; Negation of base pattern, isfinite(x) && !(x == 0.0)
define i1 @negated_isfinite_or_zero_f16(half %x) { define i1 @negated_isfinite_or_zero_f16(half %x) {
; CHECK-LABEL: @negated_isfinite_or_zero_f16( ; CHECK-LABEL: @negated_isfinite_or_zero_f16(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) ; CHECK-NEXT: [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp one half [[FABS]], 0xH7C00
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp une half [[X]], 0xH0000
; CHECK-NEXT: [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[NOT_CLASS]] ; CHECK-NEXT: ret i1 [[NOT_CLASS]]
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%cmpinf = fcmp one half %fabs, 0xH7C00 %cmpinf = fcmp one half %fabs, 0xH7C00
%cmpzero = fcmp une half %x, 0xH0000 %cmpzero = fcmp une half %x, 0xH0000
%not.class = and i1 %cmpzero, %cmpinf %not.class = and i1 %cmpzero, %cmpinf
ret i1 %not.class ret i1 %not.class
} }
; Commuted !(x == 0.0) && isfinite(x) ; Commuted !(x == 0.0) && isfinite(x)
define i1 @negated_isfinite_or_zero_f16_commute_and(half %x) { define i1 @negated_isfinite_or_zero_f16_commute_and(half %x) {
; CHECK-LABEL: @negated_isfinite_or_zero_f16_commute_and( ; CHECK-LABEL: @negated_isfinite_or_zero_f16_commute_and(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) ; CHECK-NEXT: [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp one half [[FABS]], 0xH7C00
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp une half [[X]], 0xH0000
; CHECK-NEXT: [[NOT_CLASS:%.*]] = and i1 [[CMPINF]], [[CMPZERO]]
; CHECK-NEXT: ret i1 [[NOT_CLASS]] ; CHECK-NEXT: ret i1 [[NOT_CLASS]]
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%cmpinf = fcmp one half %fabs, 0xH7C00 %cmpinf = fcmp one half %fabs, 0xH7C00
%cmpzero = fcmp une half %x, 0xH0000 %cmpzero = fcmp une half %x, 0xH0000
%not.class = and i1 %cmpinf, %cmpzero %not.class = and i1 %cmpinf, %cmpzero
ret i1 %not.class ret i1 %not.class
} }
; isfinite(x) && !(x == -0.0) ; isfinite(x) && !(x == -0.0)
define i1 @negated_isfinite_or_zero_f16_negzero(half %x) { define i1 @negated_isfinite_or_zero_f16_negzero(half %x) {
; CHECK-LABEL: @negated_isfinite_or_zero_f16_negzero( ; CHECK-LABEL: @negated_isfinite_or_zero_f16_negzero(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) ; CHECK-NEXT: [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp one half [[FABS]], 0xH7C00
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp une half [[X]], 0xH0000
; CHECK-NEXT: [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[NOT_CLASS]] ; CHECK-NEXT: ret i1 [[NOT_CLASS]]
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%cmpinf = fcmp one half %fabs, 0xH7C00 %cmpinf = fcmp one half %fabs, 0xH7C00
%cmpzero = fcmp une half %x, -0.0 %cmpzero = fcmp une half %x, -0.0
%not.class = and i1 %cmpzero, %cmpinf %not.class = and i1 %cmpzero, %cmpinf
ret i1 %not.class ret i1 %not.class
} }
; Negated pattern ; Negated pattern
define <2 x i1> @negated_isfinite_or_zero_v2f16(<2 x half> %x) { define <2 x i1> @negated_isfinite_or_zero_v2f16(<2 x half> %x) {
; CHECK-LABEL: @negated_isfinite_or_zero_v2f16( ; CHECK-LABEL: @negated_isfinite_or_zero_v2f16(
; CHECK-NEXT: [[FABS:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]]) ; CHECK-NEXT: [[NOT_CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 408)
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp one <2 x half> [[FABS]], <half 0xH7C00, half 0xH7C00>
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp une <2 x half> [[X]], zeroinitializer
; CHECK-NEXT: [[NOT_CLASS:%.*]] = and <2 x i1> [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret <2 x i1> [[NOT_CLASS]] ; CHECK-NEXT: ret <2 x i1> [[NOT_CLASS]]
; ;
%fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
%cmpinf = fcmp one <2 x half> %fabs, <half 0xH7C00, half 0xH7C00> %cmpinf = fcmp one <2 x half> %fabs, <half 0xH7C00, half 0xH7C00>
%cmpzero = fcmp une <2 x half> %x, zeroinitializer %cmpzero = fcmp une <2 x half> %x, zeroinitializer
%not.class = and <2 x i1> %cmpzero, %cmpinf %not.class = and <2 x i1> %cmpzero, %cmpinf
ret <2 x i1> %not.class ret <2 x i1> %not.class
} }
; Negated pattern, commuted vector and ; Negated pattern, commuted vector and
define <2 x i1> @negated_isfinite_or_zero_v2f16_comumte(<2 x half> %x) { define <2 x i1> @negated_isfinite_or_zero_v2f16_comumte(<2 x half> %x) {
; CHECK-LABEL: @negated_isfinite_or_zero_v2f16_comumte( ; CHECK-LABEL: @negated_isfinite_or_zero_v2f16_comumte(
; CHECK-NEXT: [[FABS:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]]) ; CHECK-NEXT: [[NOT_CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 408)
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp one <2 x half> [[FABS]], <half 0xH7C00, half 0xH7C00>
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp une <2 x half> [[X]], zeroinitializer
; CHECK-NEXT: [[NOT_CLASS:%.*]] = and <2 x i1> [[CMPINF]], [[CMPZERO]]
; CHECK-NEXT: ret <2 x i1> [[NOT_CLASS]] ; CHECK-NEXT: ret <2 x i1> [[NOT_CLASS]]
; ;
%fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x) %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
%cmpinf = fcmp one <2 x half> %fabs, <half 0xH7C00, half 0xH7C00> %cmpinf = fcmp one <2 x half> %fabs, <half 0xH7C00, half 0xH7C00>
%cmpzero = fcmp une <2 x half> %x, zeroinitializer %cmpzero = fcmp une <2 x half> %x, zeroinitializer
%not.class = and <2 x i1> %cmpinf, %cmpzero %not.class = and <2 x i1> %cmpinf, %cmpzero
ret <2 x i1> %not.class ret <2 x i1> %not.class
} }
; Positive test ; Positive test
define i1 @negated_isfinite_or_zero_f16_not_une_zero(half %x) { define i1 @negated_isfinite_or_zero_f16_not_une_zero(half %x) {
; CHECK-LABEL: @negated_isfinite_or_zero_f16_not_une_zero( ; CHECK-LABEL: @negated_isfinite_or_zero_f16_not_une_zero(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) ; CHECK-NEXT: [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp one half [[FABS]], 0xH7C00
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp one half [[X]], 0xH0000
; CHECK-NEXT: [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[NOT_CLASS]] ; CHECK-NEXT: ret i1 [[NOT_CLASS]]
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%cmpinf = fcmp one half %fabs, 0xH7C00 %cmpinf = fcmp one half %fabs, 0xH7C00
%cmpzero = fcmp one half %x, 0xH0000 %cmpzero = fcmp one half %x, 0xH0000
%not.class = and i1 %cmpzero, %cmpinf %not.class = and i1 %cmpzero, %cmpinf
ret i1 %not.class ret i1 %not.class
} }
; Positive test ; Positive test
define i1 @negated_isfinite_and_zero_f16(half %x) { define i1 @negated_isfinite_and_zero_f16(half %x) {
; CHECK-LABEL: @negated_isfinite_and_zero_f16( ; CHECK-LABEL: @negated_isfinite_and_zero_f16(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) ; CHECK-NEXT: ret i1 true
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp one half [[FABS]], 0xH7C00
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp une half [[X]], 0xH0000
; CHECK-NEXT: [[NOT_CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[NOT_CLASS]]
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%cmpinf = fcmp one half %fabs, 0xH7C00 %cmpinf = fcmp one half %fabs, 0xH7C00
%cmpzero = fcmp une half %x, 0xH0000 %cmpzero = fcmp une half %x, 0xH0000
%not.class = or i1 %cmpzero, %cmpinf %not.class = or i1 %cmpzero, %cmpinf
ret i1 %not.class ret i1 %not.class
} }
; Negative test ; Negative test
define i1 @negated_isfinite_or_zero_f16_swapped_constants(half %x) { define i1 @negated_isfinite_or_zero_f16_swapped_constants(half %x) {
; CHECK-LABEL: @negated_isfinite_or_zero_f16_swapped_constants( ; CHECK-LABEL: @negated_isfinite_or_zero_f16_swapped_constants(
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp one half [[X:%.*]], 0xH0000 ; CHECK-NEXT: [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 412)
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp une half [[X]], 0xH7C00
; CHECK-NEXT: [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[NOT_CLASS]] ; CHECK-NEXT: ret i1 [[NOT_CLASS]]
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%cmpzero = fcmp one half %fabs, 0xH0000 %cmpzero = fcmp one half %fabs, 0xH0000
%cmpinf = fcmp une half %x, 0xH7C00 %cmpinf = fcmp une half %x, 0xH7C00
%not.class = and i1 %cmpzero, %cmpinf %not.class = and i1 %cmpzero, %cmpinf
ret i1 %not.class ret i1 %not.class
} }
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store i1 %cmpzero, ptr %ptr store i1 %cmpzero, ptr %ptr
%not.class = and i1 %cmpzero, %cmpinf %not.class = and i1 %cmpzero, %cmpinf
ret i1 %not.class ret i1 %not.class
} }
; Negative test ; Negative test
define i1 @negated_isfinite_or_zero_f16_multi_use_cmp0_not_one_inf(half %x) { define i1 @negated_isfinite_or_zero_f16_multi_use_cmp0_not_one_inf(half %x) {
; CHECK-LABEL: @negated_isfinite_or_zero_f16_multi_use_cmp0_not_one_inf( ; CHECK-LABEL: @negated_isfinite_or_zero_f16_multi_use_cmp0_not_one_inf(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) ; CHECK-NEXT: [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 411)
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp une half [[FABS]], 0xH7C00
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp une half [[X]], 0xH0000
; CHECK-NEXT: [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[NOT_CLASS]] ; CHECK-NEXT: ret i1 [[NOT_CLASS]]
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%cmpinf = fcmp une half %fabs, 0xH7C00 %cmpinf = fcmp une half %fabs, 0xH7C00
%cmpzero = fcmp une half %x, 0xH0000 %cmpzero = fcmp une half %x, 0xH0000
%not.class = and i1 %cmpzero, %cmpinf %not.class = and i1 %cmpzero, %cmpinf
ret i1 %not.class ret i1 %not.class
} }
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} }
; -------------------------------------------------------------------- ; --------------------------------------------------------------------
; Other fcmp to class recognition ; Other fcmp to class recognition
; -------------------------------------------------------------------- ; --------------------------------------------------------------------
define i1 @fcmp_une_0_or_fcmp_une_inf(half %x) { define i1 @fcmp_une_0_or_fcmp_une_inf(half %x) {
; CHECK-LABEL: @fcmp_une_0_or_fcmp_une_inf( ; CHECK-LABEL: @fcmp_une_0_or_fcmp_une_inf(
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp une half [[X:%.*]], 0xH0000 ; CHECK-NEXT: ret i1 true
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp une half [[X]], 0xH7C00
; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[OR]]
; ;
%cmpzero = fcmp une half %x, 0.0 %cmpzero = fcmp une half %x, 0.0
%cmpinf = fcmp une half %x, 0xH7C00 %cmpinf = fcmp une half %x, 0xH7C00
%or = or i1 %cmpzero, %cmpinf %or = or i1 %cmpzero, %cmpinf
ret i1 %or ret i1 %or
} }
define i1 @fcmp_one_0_and_fcmp_une_fabs_inf(half %x) { define i1 @fcmp_one_0_and_fcmp_une_fabs_inf(half %x) {
; CHECK-LABEL: @fcmp_one_0_and_fcmp_une_fabs_inf( ; CHECK-LABEL: @fcmp_one_0_and_fcmp_une_fabs_inf(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) ; CHECK-NEXT: [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp one half [[X]], 0xH0000
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp une half [[FABS]], 0xH7C00
; CHECK-NEXT: [[AND:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[AND]] ; CHECK-NEXT: ret i1 [[AND]]
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%cmpzero = fcmp one half %x, 0.0 %cmpzero = fcmp one half %x, 0.0
%cmpinf = fcmp une half %fabs, 0xH7C00 %cmpinf = fcmp une half %fabs, 0xH7C00
%and = and i1 %cmpzero, %cmpinf %and = and i1 %cmpzero, %cmpinf
ret i1 %and ret i1 %and
} }
define i1 @fcmp_une_0_and_fcmp_une_fabs_inf(half %x) { define i1 @fcmp_une_0_and_fcmp_une_fabs_inf(half %x) {
; CHECK-LABEL: @fcmp_une_0_and_fcmp_une_fabs_inf( ; CHECK-LABEL: @fcmp_une_0_and_fcmp_une_fabs_inf(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) ; CHECK-NEXT: [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 411)
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp une half [[X]], 0xH0000
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp une half [[FABS]], 0xH7C00
; CHECK-NEXT: [[AND:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[AND]] ; CHECK-NEXT: ret i1 [[AND]]
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%cmpzero = fcmp une half %x, 0.0 %cmpzero = fcmp une half %x, 0.0
%cmpinf = fcmp une half %fabs, 0xH7C00 %cmpinf = fcmp une half %fabs, 0xH7C00
%and = and i1 %cmpzero, %cmpinf %and = and i1 %cmpzero, %cmpinf
ret i1 %and ret i1 %and
} }
define i1 @fcmp_une_0_and_fcmp_une_neginf(half %x) { define i1 @fcmp_une_0_and_fcmp_une_neginf(half %x) {
; CHECK-LABEL: @fcmp_une_0_and_fcmp_une_neginf( ; CHECK-LABEL: @fcmp_une_0_and_fcmp_une_neginf(
; CHECK-NEXT: [[CMPZERO:%.*]] = fcmp une half [[X:%.*]], 0xH0000 ; CHECK-NEXT: ret i1 true
; CHECK-NEXT: [[CMPINF:%.*]] = fcmp une half [[X]], 0xHFC00
; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
; CHECK-NEXT: ret i1 [[OR]]
; ;
%cmpzero = fcmp une half %x, 0.0 %cmpzero = fcmp une half %x, 0.0
%cmpinf = fcmp une half %x, 0xHFC00 %cmpinf = fcmp une half %x, 0xHFC00
%or = or i1 %cmpzero, %cmpinf %or = or i1 %cmpzero, %cmpinf
ret i1 %or ret i1 %or
} }
define i1 @issubnormal_or_inf(half %x) { define i1 @issubnormal_or_inf(half %x) {
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%cmpinf = fcmp olt half %fabs, 0xH7C00 %cmpinf = fcmp olt half %fabs, 0xH7C00
%cmp.smallest.normal = fcmp olt half %fabs, 0xH0400 %cmp.smallest.normal = fcmp olt half %fabs, 0xH0400
%and = and i1 %cmp.smallest.normal, %cmpinf %and = and i1 %cmp.smallest.normal, %cmpinf
ret i1 %and ret i1 %and
} }
define i1 @not_zero_and_subnormal(half %x) { define i1 @not_zero_and_subnormal(half %x) {
; CHECK-LABEL: @not_zero_and_subnormal( ; CHECK-LABEL: @not_zero_and_subnormal(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) ; CHECK-NEXT: [[OR:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
; CHECK-NEXT: [[CMP_ZERO:%.*]] = fcmp one half [[X]], 0xH0000
; CHECK-NEXT: [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMP_ZERO]]
; CHECK-NEXT: ret i1 [[OR]] ; CHECK-NEXT: ret i1 [[OR]]
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%cmp.zero = fcmp one half %fabs, 0.0 %cmp.zero = fcmp one half %fabs, 0.0
%cmp.smallest.normal = fcmp olt half %fabs, 0xH0400 %cmp.smallest.normal = fcmp olt half %fabs, 0xH0400
%or = or i1 %cmp.smallest.normal, %cmp.zero %or = or i1 %cmp.smallest.normal, %cmp.zero
ret i1 %or ret i1 %or
} }
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; -------------------------------------------------------------------- ; --------------------------------------------------------------------
; isnormal(x) || x == 0.0 ; isnormal(x) || x == 0.0
; -------------------------------------------------------------------- ; --------------------------------------------------------------------
define i1 @isnormal_or_zero(half %x) #0 { define i1 @isnormal_or_zero(half %x) #0 {
; CHECK-LABEL: @isnormal_or_zero( ; CHECK-LABEL: @isnormal_or_zero(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[AND1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 264) ; CHECK-NEXT: [[AND1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 360)
; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq half [[X]], 0xH0000 ; CHECK-NEXT: ret i1 [[AND1]]
; CHECK-NEXT: [[SPEC_SELECT:%.*]] = or i1 [[CMP]], [[AND1]]
; CHECK-NEXT: ret i1 [[SPEC_SELECT]]
; ;
entry: entry:
%iseq = fcmp ord half %x, 0xH0000 %iseq = fcmp ord half %x, 0xH0000
%fabs = tail call half @llvm.fabs.f16(half %x) %fabs = tail call half @llvm.fabs.f16(half %x)
%isinf = fcmp ult half %fabs, 0xH7C00 %isinf = fcmp ult half %fabs, 0xH7C00
%isnormal = fcmp uge half %fabs, 0xH0400 %isnormal = fcmp uge half %fabs, 0xH0400
%and = and i1 %iseq, %isinf %and = and i1 %iseq, %isinf
%and1 = and i1 %isnormal, %and %and1 = and i1 %isnormal, %and
%cmp = fcmp oeq half %x, 0xH0000 %cmp = fcmp oeq half %x, 0xH0000
%spec.select = or i1 %cmp, %and1 %spec.select = or i1 %cmp, %and1
ret i1 %spec.select ret i1 %spec.select
} }
define i1 @isnormal_uge_or_zero_oeq(half %x) #0 { define i1 @isnormal_uge_or_zero_oeq(half %x) #0 {
; CHECK-LABEL: @isnormal_uge_or_zero_oeq( ; CHECK-LABEL: @isnormal_uge_or_zero_oeq(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[FABS:%.*]] = tail call half @llvm.fabs.f16(half [[X:%.*]]) ; CHECK-NEXT: [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 879)
; CHECK-NEXT: [[IS_NORMAL:%.*]] = fcmp uge half [[FABS]], 0xH0400
; CHECK-NEXT: [[IS_ZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
; CHECK-NEXT: [[OR:%.*]] = or i1 [[IS_NORMAL]], [[IS_ZERO]]
; CHECK-NEXT: ret i1 [[OR]] ; CHECK-NEXT: ret i1 [[OR]]
; ;
entry: entry:
%fabs = tail call half @llvm.fabs.f16(half %x) %fabs = tail call half @llvm.fabs.f16(half %x)
%is.normal = fcmp uge half %fabs, 0xH0400 %is.normal = fcmp uge half %fabs, 0xH0400
%is.zero = fcmp oeq half %x, 0xH0000 %is.zero = fcmp oeq half %x, 0xH0000
%or = or i1 %is.normal, %is.zero %or = or i1 %is.normal, %is.zero
ret i1 %or ret i1 %or
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%or = or i1 %is.ord, %is.normal.inf %or = or i1 %is.ord, %is.normal.inf
ret i1 %or ret i1 %or
} }
; No fabs ; No fabs
; -> iszero ; -> iszero
define i1 @une_or_oge_smallest_normal(half %x) #0 { define i1 @une_or_oge_smallest_normal(half %x) #0 {
; CHECK-LABEL: @une_or_oge_smallest_normal( ; CHECK-LABEL: @une_or_oge_smallest_normal(
; CHECK-NEXT: [[IS_NORMAL_INF:%.*]] = fcmp oge half [[X:%.*]], 0xH0400 ; CHECK-NEXT: [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 927)
; CHECK-NEXT: [[IS_UNE:%.*]] = fcmp une half [[X]], 0xH0000
; CHECK-NEXT: [[OR:%.*]] = or i1 [[IS_UNE]], [[IS_NORMAL_INF]]
; CHECK-NEXT: ret i1 [[OR]] ; CHECK-NEXT: ret i1 [[OR]]
; ;
%is.normal.inf = fcmp oge half %x, 0xH0400 %is.normal.inf = fcmp oge half %x, 0xH0400
%is.une = fcmp une half %x, 0xH0000 %is.une = fcmp une half %x, 0xH0000
%or = or i1 %is.une, %is.normal.inf %or = or i1 %is.une, %is.normal.inf
ret i1 %or ret i1 %or
} }
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%cmp.smallest.normal = fcmp olt half %fabs, 0xH0400 %cmp.smallest.normal = fcmp olt half %fabs, 0xH0400
%or = or i1 %cmp.smallest.normal, %cmp.zero %or = or i1 %cmp.smallest.normal, %cmp.zero
ret i1 %or ret i1 %or
} }
; TODO: This could fold to just fcmp olt half %fabs, 0xH0400 ; TODO: This could fold to just fcmp olt half %fabs, 0xH0400
define i1 @subnormal_or_zero_ieee(half %x) #0 { define i1 @subnormal_or_zero_ieee(half %x) #0 {
; CHECK-LABEL: @subnormal_or_zero_ieee( ; CHECK-LABEL: @subnormal_or_zero_ieee(
; CHECK-NEXT: [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) ; CHECK-NEXT: [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 240)
; CHECK-NEXT: [[IS_SUBNORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
; CHECK-NEXT: [[IS_ZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
; CHECK-NEXT: [[AND:%.*]] = or i1 [[IS_SUBNORMAL]], [[IS_ZERO]]
; CHECK-NEXT: ret i1 [[AND]] ; CHECK-NEXT: ret i1 [[AND]]
; ;
%fabs = call half @llvm.fabs.f16(half %x) %fabs = call half @llvm.fabs.f16(half %x)
%is.subnormal = fcmp olt half %fabs, 0xH0400 %is.subnormal = fcmp olt half %fabs, 0xH0400
%is.zero = fcmp oeq half %x, 0xH0000 %is.zero = fcmp oeq half %x, 0xH0000
%and = or i1 %is.subnormal, %is.zero %and = or i1 %is.subnormal, %is.zero
ret i1 %and ret i1 %and
} }
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