Codegen support for 128-bit atomicrmw (and|or|xchg).
- store atomic -> swpp
- atomicrmw xchg -> swpp
- atomicrmw and -> ldclrp
- atomicrmw or -> ldsetp
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| Differential D141406
[AArch64] Codegen for FEAT_LSE128 ClosedPublic Authored by tmatheson on Jan 10 2023, 9:16 AM.
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Summary Codegen support for 128-bit atomicrmw (and|or|xchg).
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Right now, GlobalISel falls back to SelectionDAG for many atomics, including those above (the -O0 case is the globalisel case, but it has fallen back). I think GlobalISel work for these atomics can come in a later patch, to be honest. This revision is now accepted and ready to land.Jan 25 2023, 3:51 AM This revision was landed with ongoing or failed builds.Jan 25 2023, 4:02 AM Closed by commit rGf1f583347d00: [AArch64] Codegen for FEAT_LSE128 (authored by tmatheson). · Explain Why This revision was automatically updated to reflect the committed changes. Comment Actions
In that case, can you add a few tests to show what happens on targets that have both lse2 and lse128? I assume lse2 "wins", but it would be nice to make that explicit.
Revision Contents
Diff 487841 llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-lse128.ll
llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse128.ll
llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-store-lse128.ll
llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse128.ll
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I am also confused about this assert message.