[RISCV] Teach RISCVMergeBaseOffset to handle constant pools.

[craig.topper]

Summary

Primarily this allows us to fold the addi from PseudoLLA expansion
into a load.

If the linker is able to GP relax the constant pool access we'll
end up with a GP relative load.

[asb]

LGTM!

llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp

 //===----- RISCVMergeBaseOffset.cpp - Optimise address calculations  ------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 // 2. (medany pattern):
 // .Lpcrel_hi1:
 //   auipc vreg1, %pcrel_hi(s)
 //   addi  vreg2, vreg1, %pcrel_lo(.Lpcrel_hi1)
 //
 // The pattern is only accepted if:
 //    1) The first instruction has only one use, which is the ADDI.
 //    2) The address operands have the appropriate type, reflecting the
-//       lowering of a global address using medlow or medany.
-//    3) The offset value in the Global Address is 0.
+//       lowering of a global address or constant pool using medlow or medany.
+//    3) The offset value in the Global Address or Constant Pool is 0.
 bool RISCVMergeBaseOffsetOpt::detectFoldable(MachineInstr &Hi,
                                              MachineInstr *&Lo) {
   if (Hi.getOpcode() == RISCV::LUI) {
     Register HiDestReg = Hi.getOperand(0).getReg();
     const MachineOperand &HiOp1 = Hi.getOperand(1);
-    if (HiOp1.getTargetFlags() != RISCVII::MO_HI || !HiOp1.isGlobal() ||
-        HiOp1.getOffset() != 0 || !MRI->hasOneUse(HiDestReg))
+    if (HiOp1.getTargetFlags() != RISCVII::MO_HI ||
+        !(HiOp1.isGlobal() || HiOp1.isCPI()) || HiOp1.getOffset() != 0 ||
+        !MRI->hasOneUse(HiDestReg))
       return false;
     Lo = &*MRI->use_instr_begin(HiDestReg);
     if (Lo->getOpcode() != RISCV::ADDI)
       return false;
     const MachineOperand &LoOp2 = Lo->getOperand(2);
-    if (LoOp2.getTargetFlags() != RISCVII::MO_LO || !LoOp2.isGlobal() ||
-        LoOp2.getOffset() != 0)
+    if (LoOp2.getTargetFlags() != RISCVII::MO_LO ||
+        !(LoOp2.isGlobal() || LoOp2.isCPI()) || LoOp2.getOffset() != 0)
       return false;
     return true;
   }
 
   if (Hi.getOpcode() == RISCV::AUIPC) {
     Register HiDestReg = Hi.getOperand(0).getReg();
     const MachineOperand &HiOp1 = Hi.getOperand(1);
-    if (HiOp1.getTargetFlags() != RISCVII::MO_PCREL_HI || !HiOp1.isGlobal() ||
-        HiOp1.getOffset() != 0 || !MRI->hasOneUse(HiDestReg))
+    if (HiOp1.getTargetFlags() != RISCVII::MO_PCREL_HI ||
+        !(HiOp1.isGlobal() || HiOp1.isCPI()) || HiOp1.getOffset() != 0 ||
+        !MRI->hasOneUse(HiDestReg))
       return false;
     Lo = &*MRI->use_instr_begin(HiDestReg);
     if (Lo->getOpcode() != RISCV::ADDI)
       return false;
     const MachineOperand &LoOp2 = Lo->getOperand(2);
     if (LoOp2.getTargetFlags() != RISCVII::MO_PCREL_LO ||
         LoOp2.getType() != MachineOperand::MO_MCSymbol)
       return false;
bool RISCVMergeBaseOffsetOpt::runOnMachineFunction(MachineFunction &Fn) {
   bool MadeChange = false;
   MRI = &Fn.getRegInfo();
   for (MachineBasicBlock &MBB : Fn) {
     LLVM_DEBUG(dbgs() << "MBB: " << MBB.getName() << "\n");
     for (MachineInstr &Hi : MBB) {
       MachineInstr *Lo = nullptr;
       if (!detectFoldable(Hi, Lo))
         continue;
+      if (Hi.getOperand(1).isGlobal()) {
         LLVM_DEBUG(dbgs() << "  Found lowered global address: "
                           << *Hi.getOperand(1).getGlobal() << "\n");
+      } else {
+        assert(Hi.getOperand(1).isCPI());
+        LLVM_DEBUG(dbgs() << "  Found lowered constant pool: "
+                          << Hi.getOperand(1).getIndex() << "\n");
+      }
       MadeChange |= detectAndFoldOffset(Hi, *Lo);
       MadeChange |= foldIntoMemoryOps(Hi, *Lo);
     }
   }
 
   return MadeChange;
 }
 
 /// Returns an instance of the Merge Base Offset Optimization pass.
 FunctionPass *llvm::createRISCVMergeBaseOffsetOptPass() {
   return new RISCVMergeBaseOffsetOpt();
 }

llvm/test/CodeGen/RISCV/codemodel-lowering.ll

 ; RV32I-SMALL-NEXT:    flw ft0, %lo(.LCPI3_0)(a0)
 ; RV32I-SMALL-NEXT:    fadd.s fa0, fa0, ft0
 ; RV32I-SMALL-NEXT:    ret
 ;
 ; RV32I-MEDIUM-LABEL: lower_constantpool:
 ; RV32I-MEDIUM:       # %bb.0:
 ; RV32I-MEDIUM-NEXT:  .Lpcrel_hi3:
 ; RV32I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(.LCPI3_0)
-; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi3)
-; RV32I-MEDIUM-NEXT:    flw ft0, 0(a0)
+; RV32I-MEDIUM-NEXT:    flw ft0, %pcrel_lo(.Lpcrel_hi3)(a0)
 ; RV32I-MEDIUM-NEXT:    fadd.s fa0, fa0, ft0
 ; RV32I-MEDIUM-NEXT:    ret
   %1 = fadd float %a, 1.0
   ret float %1
 }