[AArch64] Add FP16 instructions to isAssociativeAndCommutative

[kawashima-fj]

Summary

This is one of patch series split from D138107.

-mcpu= in llvm/test/CodeGen/AArch64/machine-combiner.ll is changed
to neoverse-n2 to use FP16 and SVE/SVE2 instructions. By this, the
register allocation and/or instruction scheduling are slightly changed
and some existing CHECK lines need to be updated.

[dmgreen]

Sorry for the delay. FP16 instructions sound good.

llvm/test/CodeGen/AArch64/machine-combiner.ll

2–3

It may be better to pick neoverse-n2, as that is the scheduling model that will be used for cortex-a710.

[kawashima-fj]

As per @dmgreen's comment, change -mcpu=cortex-a710 to -mcpu=neoverse-n2.

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

 //       3. Other forms of the same operation (intrinsics and other variants)
 bool AArch64InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst,
                                                    bool Invert) const {
   if (Invert)
     return false;
   switch (Inst.getOpcode()) {
   // == Floating-point types ==
   // -- Floating-point instructions --
+  case AArch64::FADDHrr:
   case AArch64::FADDSrr:
   case AArch64::FADDDrr:
+  case AArch64::FMULHrr:
   case AArch64::FMULSrr:
   case AArch64::FMULDrr:
+  case AArch64::FMULX16:
   case AArch64::FMULX32:
   case AArch64::FMULX64:
   // -- Advanced SIMD instructions --
+  case AArch64::FADDv4f16:
+  case AArch64::FADDv8f16:
   case AArch64::FADDv2f32:
   case AArch64::FADDv4f32:
   case AArch64::FADDv2f64:
+  case AArch64::FMULv4f16:
+  case AArch64::FMULv8f16:
   case AArch64::FMULv2f32:
   case AArch64::FMULv4f32:
   case AArch64::FMULv2f64:
+  case AArch64::FMULXv4f16:
+  case AArch64::FMULXv8f16:
   case AArch64::FMULXv2f32:
   case AArch64::FMULXv4f32:
   case AArch64::FMULXv2f64:
     return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath ||
            (Inst.getFlag(MachineInstr::MIFlag::FmReassoc) &&
             Inst.getFlag(MachineInstr::MIFlag::FmNsz));
 
   // == Integer types ==

llvm/test/CodeGen/AArch64/machine-combiner.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=cortex-a57 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-STD
-; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=cortex-a57 -enable-unsafe-fp-math < %s | FileCheck %s --check-prefixes=CHECK,CHECK-UNSAFE
+; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=neoverse-n2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-STD
+; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=neoverse-n2 -enable-unsafe-fp-math < %s | FileCheck %s --check-prefixes=CHECK,CHECK-UNSAFE
 
 ; Incremental updates of the instruction depths should be enough for this test
 ; case.
-; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=cortex-a57 -enable-unsafe-fp-math \
+; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=neoverse-n2 -enable-unsafe-fp-math \
 ; RUN:     -machine-combiner-inc-threshold=0 -machine-combiner-verify-pattern-order=true < %s | FileCheck %s --check-prefixes=CHECK,CHECK-UNSAFE
 
 ; Verify that the first two adds are independent regardless of how the inputs are
 ; commuted. The destination registers are used as source registers for the third add.
 
 define float @reassociate_adds1(float %x0, float %x1, float %x2, float %x3) {
 ; CHECK-STD-LABEL: reassociate_adds1:
 ; CHECK-STD:       // %bb.0:

 }
 
 ; Verify that scalar single-precision multiplies are reassociated.
 
 define float @reassociate_muls1(float %x0, float %x1, float %x2, float %x3) {
 ; CHECK-STD-LABEL: reassociate_muls1:
 ; CHECK-STD:       // %bb.0:
 ; CHECK-STD-NEXT:    fdiv s0, s0, s1
-; CHECK-STD-NEXT:    fmul s1, s2, s0
-; CHECK-STD-NEXT:    fmul s0, s3, s1
+; CHECK-STD-NEXT:    fmul s0, s2, s0
+; CHECK-STD-NEXT:    fmul s0, s3, s0
 ; CHECK-STD-NEXT:    ret
 ;
 ; CHECK-UNSAFE-LABEL: reassociate_muls1:
 ; CHECK-UNSAFE:       // %bb.0:
 ; CHECK-UNSAFE-NEXT:    fdiv s0, s0, s1
 ; CHECK-UNSAFE-NEXT:    fmul s1, s3, s2
 ; CHECK-UNSAFE-NEXT:    fmul s0, s1, s0
 ; CHECK-UNSAFE-NEXT:    ret

 }
 
 ; Verify that scalar double-precision multiplies are reassociated.
 
 define double @reassociate_muls_double(double %x0, double %x1, double %x2, double %x3) {
 ; CHECK-STD-LABEL: reassociate_muls_double:
 ; CHECK-STD:       // %bb.0:
 ; CHECK-STD-NEXT:    fdiv d0, d0, d1
-; CHECK-STD-NEXT:    fmul d1, d2, d0
-; CHECK-STD-NEXT:    fmul d0, d3, d1
+; CHECK-STD-NEXT:    fmul d0, d2, d0
+; CHECK-STD-NEXT:    fmul d0, d3, d0
 ; CHECK-STD-NEXT:    ret
 ;
 ; CHECK-UNSAFE-LABEL: reassociate_muls_double:
 ; CHECK-UNSAFE:       // %bb.0:
 ; CHECK-UNSAFE-NEXT:    fdiv d0, d0, d1
 ; CHECK-UNSAFE-NEXT:    fmul d1, d3, d2
 ; CHECK-UNSAFE-NEXT:    fmul d0, d1, d0
 ; CHECK-UNSAFE-NEXT:    ret
   %t0 = fdiv double %x0, %x1
   %t1 = fmul double %x2, %t0
   %t2 = fmul double %x3, %t1
   ret double %t2
 }
 
+; Verify that scalar half-precision adds are reassociated.
+
+define half @reassociate_adds_half(half %x0, half %x1, half %x2, half %x3) {
+; CHECK-STD-LABEL: reassociate_adds_half:
+; CHECK-STD:       // %bb.0:
+; CHECK-STD-NEXT:    fdiv h0, h0, h1
+; CHECK-STD-NEXT:    fadd h0, h2, h0
+; CHECK-STD-NEXT:    fadd h0, h3, h0
+; CHECK-STD-NEXT:    ret
+;
+; CHECK-UNSAFE-LABEL: reassociate_adds_half:
+; CHECK-UNSAFE:       // %bb.0:
+; CHECK-UNSAFE-NEXT:    fdiv h0, h0, h1
+; CHECK-UNSAFE-NEXT:    fadd h1, h3, h2
+; CHECK-UNSAFE-NEXT:    fadd h0, h1, h0
+; CHECK-UNSAFE-NEXT:    ret
+  %t0 = fdiv half %x0, %x1
+  %t1 = fadd half %x2, %t0
+  %t2 = fadd half %x3, %t1
+  ret half %t2
+}
+
+; Verify that scalar half-precision multiplies are reassociated.
+
+define half @reassociate_muls_half(half %x0, half %x1, half %x2, half %x3) {
+; CHECK-STD-LABEL: reassociate_muls_half:
+; CHECK-STD:       // %bb.0:
+; CHECK-STD-NEXT:    fdiv h0, h0, h1
+; CHECK-STD-NEXT:    fmul h0, h2, h0
+; CHECK-STD-NEXT:    fmul h0, h3, h0
+; CHECK-STD-NEXT:    ret
+;
+; CHECK-UNSAFE-LABEL: reassociate_muls_half:
+; CHECK-UNSAFE:       // %bb.0:
+; CHECK-UNSAFE-NEXT:    fdiv h0, h0, h1
+; CHECK-UNSAFE-NEXT:    fmul h1, h3, h2
+; CHECK-UNSAFE-NEXT:    fmul h0, h1, h0
+; CHECK-UNSAFE-NEXT:    ret
+  %t0 = fdiv half %x0, %x1
+  %t1 = fmul half %x2, %t0
+  %t2 = fmul half %x3, %t1
+  ret half %t2
+}
+
 ; Verify that scalar integer adds are reassociated.
 
 define i32 @reassociate_adds_i32(i32 %x0, i32 %x1, i32 %x2, i32 %x3) {
 ; CHECK-LABEL: reassociate_adds_i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    udiv w8, w0, w1
 ; CHECK-NEXT:    add w9, w3, w2
 ; CHECK-NEXT:    add w0, w9, w8

 ; CHECK-UNSAFE-NEXT:    fadd v1.4s, v3.4s, v2.4s
 ; CHECK-UNSAFE-NEXT:    fadd v0.4s, v1.4s, v0.4s
 ; CHECK-UNSAFE-NEXT:    ret
   %t0 = fadd <4 x float> %x0, %x1
   %t1 = fadd <4 x float> %x2, %t0
   %t2 = fadd <4 x float> %x3, %t1
   ret <4 x float> %t2
 }
+
+; Verify that 64-bit vector half-precision adds are reassociated.
+
+define <4 x half> @reassociate_adds_v4f16(<4 x half> %x0, <4 x half> %x1, <4 x half> %x2, <4 x half> %x3) {
+; CHECK-STD-LABEL: reassociate_adds_v4f16:
+; CHECK-STD:       // %bb.0:
+; CHECK-STD-NEXT:    fadd v0.4h, v0.4h, v1.4h
+; CHECK-STD-NEXT:    fadd v0.4h, v2.4h, v0.4h
+; CHECK-STD-NEXT:    fadd v0.4h, v3.4h, v0.4h
+; CHECK-STD-NEXT:    ret
+;
+; CHECK-UNSAFE-LABEL: reassociate_adds_v4f16:
+; CHECK-UNSAFE:       // %bb.0:
+; CHECK-UNSAFE-NEXT:    fadd v0.4h, v0.4h, v1.4h
+; CHECK-UNSAFE-NEXT:    fadd v1.4h, v3.4h, v2.4h
+; CHECK-UNSAFE-NEXT:    fadd v0.4h, v1.4h, v0.4h
+; CHECK-UNSAFE-NEXT:    ret
+  %t0 = fadd <4 x half> %x0, %x1
+  %t1 = fadd <4 x half> %x2, %t0
+  %t2 = fadd <4 x half> %x3, %t1
+  ret <4 x half> %t2
+}
+
+; Verify that 128-bit vector half-precision multiplies are reassociated.
+
+define <8 x half> @reassociate_muls_v8f16(<8 x half> %x0, <8 x half> %x1, <8 x half> %x2, <8 x half> %x3) {
+; CHECK-STD-LABEL: reassociate_muls_v8f16:
+; CHECK-STD:       // %bb.0:
+; CHECK-STD-NEXT:    fadd v0.8h, v0.8h, v1.8h
+; CHECK-STD-NEXT:    fmul v0.8h, v2.8h, v0.8h
+; CHECK-STD-NEXT:    fmul v0.8h, v3.8h, v0.8h
+; CHECK-STD-NEXT:    ret
+;
+; CHECK-UNSAFE-LABEL: reassociate_muls_v8f16:
+; CHECK-UNSAFE:       // %bb.0:
+; CHECK-UNSAFE-NEXT:    fadd v0.8h, v0.8h, v1.8h
+; CHECK-UNSAFE-NEXT:    fmul v1.8h, v3.8h, v2.8h
+; CHECK-UNSAFE-NEXT:    fmul v0.8h, v1.8h, v0.8h
+; CHECK-UNSAFE-NEXT:    ret
+  %t0 = fadd <8 x half> %x0, %x1
+  %t1 = fmul <8 x half> %x2, %t0
+  %t2 = fmul <8 x half> %x3, %t1
+  ret <8 x half> %t2
+}
+
 ; Verify that 128-bit vector single-precision multiplies are reassociated.
 
 define <4 x float> @reassociate_muls_v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
 ; CHECK-STD-LABEL: reassociate_muls_v4f32:
 ; CHECK-STD:       // %bb.0:
 ; CHECK-STD-NEXT:    fadd v0.4s, v0.4s, v1.4s
 ; CHECK-STD-NEXT:    fmul v0.4s, v2.4s, v0.4s
 ; CHECK-STD-NEXT:    fmul v0.4s, v3.4s, v0.4s

 ; CHECK-UNSAFE-NEXT:    bl bar
 ; CHECK-UNSAFE-NEXT:    fmov d8, d0
 ; CHECK-UNSAFE-NEXT:    bl bar
 ; CHECK-UNSAFE-NEXT:    fmov d9, d0
 ; CHECK-UNSAFE-NEXT:    bl bar
 ; CHECK-UNSAFE-NEXT:    fmov d10, d0
 ; CHECK-UNSAFE-NEXT:    bl bar
 ; CHECK-UNSAFE-NEXT:    fadd d1, d8, d9
-; CHECK-UNSAFE-NEXT:    fadd d0, d10, d0
-; CHECK-UNSAFE-NEXT:    ldr x30, [sp, #24] // 8-byte Folded Reload
 ; CHECK-UNSAFE-NEXT:    ldp d9, d8, [sp, #8] // 16-byte Folded Reload
+; CHECK-UNSAFE-NEXT:    ldr x30, [sp, #24] // 8-byte Folded Reload
+; CHECK-UNSAFE-NEXT:    fadd d0, d10, d0
 ; CHECK-UNSAFE-NEXT:    fadd d0, d1, d0
 ; CHECK-UNSAFE-NEXT:    ldr d10, [sp], #32 // 8-byte Folded Reload
 ; CHECK-UNSAFE-NEXT:    ret
   %x0 = call double @bar()
   %x1 = call double @bar()
   %x2 = call double @bar()
   %x3 = call double @bar()
   %t0 = fadd double %x0, %x1

 ; CHECK-NEXT:    bl bar
 ; CHECK-NEXT:    fmov d8, d0
 ; CHECK-NEXT:    bl bar
 ; CHECK-NEXT:    fmov d9, d0
 ; CHECK-NEXT:    bl bar
 ; CHECK-NEXT:    fmov d10, d0
 ; CHECK-NEXT:    bl bar
 ; CHECK-NEXT:    fadd d1, d8, d9
-; CHECK-NEXT:    fadd d0, d10, d0
-; CHECK-NEXT:    ldr x30, [sp, #24] // 8-byte Folded Reload
 ; CHECK-NEXT:    ldp d9, d8, [sp, #8] // 16-byte Folded Reload
+; CHECK-NEXT:    ldr x30, [sp, #24] // 8-byte Folded Reload
+; CHECK-NEXT:    fadd d0, d10, d0
 ; CHECK-NEXT:    fadd d0, d1, d0
 ; CHECK-NEXT:    ldr d10, [sp], #32 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %x0 = call double @bar()
   %x1 = call double @bar()
   %x2 = call double @bar()
   %x3 = call double @bar()
   %t0 = fadd double %x0, %x1
   %t1 = fadd double %x2, %x3
   %t2 = fadd double %t0, %t1
   ret double %t2
 }