[RISCV] Implement assembler support for XTHeadVdot

[JojoR]

Summary

This patch implements the T-Head vendor extensions (XTHeadVdot),
which is documented here, it's based on standard vector extension v1.0:

https://github.com/T-head-Semi/thead-extension-spec

[jrtc27]

Aside from the maintainability question of having two similar but conflicting scalable vector extensions in the backend, this needs splitting up into separate MC, CodeGen and Clang patches like any other extension.

clang/include/clang/Basic/riscvTHEAD_vector.td

1 ↗

(On Diff #480309)

You have a lot of files with a blank first line and no header

clang/include/clang/Basic/riscv_vector.td

65 ↗

(On Diff #480309)

Maybe this "only" has some clear meaning to those familiar to V but I have no clue from reading this how it differs from "q". From reading the code it seems to just be q without affecting LMUL; maybe that should be a non-primitive type transformer or something so we don't end up expanding out the whole orthogonal space.

2396 ↗

(On Diff #480309)

riscv_thead_vector maybe? This is really ugly

clang/test/CodeGen/RISCV/Vendor/THEAD/vdot-intrinsics-overloaded/vmaqa.c

3 ↗

(On Diff #480309)

These tests are using +v not +xtheadvdot and demonstrates that your intrinsics aren't predicted on the right thing, since this should give an error

5 ↗

(On Diff #480309)

I don't think T-Head intrinsics belong in riscv_vector.h, that's for V

llvm/include/llvm/IR/IntrinsicsRISCVxTHEAD.td

1 ↗

(On Diff #480309)

Xthead is the standard capitalisation for extensions when not doing lowercase

4 ↗

(On Diff #480309)

TH_ given it's "th."

llvm/lib/Target/RISCV/CMakeLists.txt

74 ↗

(On Diff #480309)

Do we really need this? It's only a handful of TableGen files, all of which should have the extension (or family) name in them. Hopefully we're not going to have so many that we'll need this...

llvm/lib/Target/RISCV/RISCV.td

539

We already have a block in this file for vendor extensions

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

1715 ↗

(On Diff #480309)

Put this at the top level, don't tie it to V

1717 ↗

(On Diff #480309)

Include this in the InstrInfo file

llvm/lib/Target/RISCV/RISCVSubtarget.h

36 ↗

(On Diff #480309)

... no

llvm/lib/Target/RISCV/Vendor/CMakeLists.txt

2 ↗

(On Diff #480309)

As for the Vendor directory itself... seems wholly unnecessary

llvm/lib/Target/RISCV/Vendor/THEAD/THEAD.td

2 ↗

(On Diff #480309)

VDot seems more natural

llvm/lib/Target/RISCV/Vendor/THEAD/THEADInstrInfoV.td

1 ↗

(On Diff #480309)

This isn't V, don't call it V

5 ↗

(On Diff #480309)

Unclear if it should be tied to V or use its own classes

llvm/lib/Target/RISCV/Vendor/THEAD/THEADSubtarget.h

6 ↗

(On Diff #480309)

Fix

llvm/test/CodeGen/RISCV/Vendor/THEAD/attributes.ll

5 ↗

(On Diff #480309)

xventanacondops is being tested in the normal attributes.ll

llvm/test/CodeGen/RISCV/Vendor/THEAD/vdot/vmaqa.ll

3

+v should be incompatible

[craig.topper]

llvm/lib/Target/RISCV/Vendor/THEAD/THEADInstrInfoV.td

5 ↗

(On Diff #480309)

Need a DecoderNamespace

[craig.topper]

llvm/lib/Target/RISCV/Vendor/THEAD/THEAD.td

3 ↗

(On Diff #480309)

Probably need to imply at least Zve32x. Here and in RISCVISAInfo.cpp

[reames]

I have not looked at the change at all (yet), but a couple of high level points.

1. Please link not to the repository, but a specific version of the PDF. We need to know exactly what version of the specification is being implemented. For instance, I was looking at https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.0/xthead-2022-12-04-2.2.0.pdf. Please update RISCVUsage.rst to contain the same information. This will form the user focused documentation.

2. Can you clarify whether the extension is based on v1.0 or a prior vector specification revision? From the document, it looks like this might be based on v1.0. Getting an extension based off v1.0 into tree will be much easier than one based on v0.7, so being clear is in your interest here. Ideally, you'd revise the specification document to be explicit here as well.

3. Please split the patch. The first patch for review should add the MC (assembly) part only.

4. I very strongly encourage you to attend the riscv sync up call happening on Thursday of this week. This will be a likely topic of discussion.

[JojoR]

clang/test/CodeGen/RISCV/Vendor/THEAD/vdot-intrinsics-overloaded/vmaqa.c

5 ↗

(On Diff #480309)

Thanks for your comments :)

from our ISAs spec if you have seen it, they are designed based on vector v1.0,
and most rules of that like mc or intrinsic derive from RVV code, so I could copy whole from that,
but I think RISCV is base code for vendor's function if they want to reuse them like llvm code is base code for all backend. we should encourage vendor to reuse RISCV base code if they are stable and help vendor construct function easily or quickly, alright ?

What header file should we supply for this ? any suggestion ?

llvm/lib/Target/RISCV/CMakeLists.txt

74 ↗

(On Diff #480309)

Thanks for your comments :)

We should make the long term planning because of RISCV ISAs allow vendor to extend their personal ISAs, alright ? :)

And for another hand, we should also help or guide vendor put their code in the the individual root space, I think it's convenience for vendor and RISCV, you can say one step to create customer's extension: "just copy a skeleton from Vendor sub-directory" :)

I believe that RISCV is open and most of vendors want to put their ISAs into community :)
you think about if there are more than 20 vendors ? is it possible ?

llvm/lib/Target/RISCV/RISCV.td

539

Like my consideration is described above, there will be much more vendors ?
they should maintain their stuffs in some one root place ?

llvm/lib/Target/RISCV/RISCVSubtarget.h

36 ↗

(On Diff #480309)

Like my consideration is described above, there will be much more vendors ?
they should maintain their stuffs in some one root place ?

llvm/lib/Target/RISCV/Vendor/THEAD/THEADInstrInfoV.td

1 ↗

(On Diff #480309)

I think I explain reason clearly above, do you agree ?

[JojoR]

In D139386#3974689, @reames wrote:

I have not looked at the change at all (yet), but a couple of high level points.

1. Please link not to the repository, but a specific version of the PDF. We need to know exactly what version of the specification is being implemented. For instance, I was looking at https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.0/xthead-2022-12-04-2.2.0.pdf. Please update RISCVUsage.rst to contain the same information. This will form the user focused documentation.

2. Can you clarify whether the extension is based on v1.0 or a prior vector specification revision? From the document, it looks like this might be based on v1.0. Getting an extension based off v1.0 into tree will be much easier than one based on v0.7, so being clear is in your interest here. Ideally, you'd revise the specification document to be explicit here as well.

3. Please split the patch. The first patch for review should add the MC (assembly) part only.

4. I very strongly encourage you to attend the riscv sync up call happening on Thursday of this week. This will be a likely topic of discussion.

Thanks for your comments and I will attend if I am free at that time :)

[asb]

Just to document the discussion we had in the RISC-V sync call yesterday, my understanding is that we concluded there aren't objections to reviewing and merging support for this extension once reviewers are happy with code quality, on the basis that the extension is relatively small, there are people willing to support it, and it's based on v1.0 vector ISA rather than 0.7 (which would trigger a much larger discussion).

[craig.topper]

llvm/lib/Target/RISCV/Vendor/THEAD/THEADSubtarget.h

1 ↗

(On Diff #481241)

I have a patch up to auto generate this from tablegen.

https://reviews.llvm.org/D139746

[craig.topper]

llvm/lib/Target/RISCV/RISCV.td

539

Line 438 already created a section called "Vendor extensions" that contains vendor subtarget features.

[JojoR]

llvm/test/CodeGen/RISCV/Vendor/THEAD/vdot/vmaqa.ll

3

Where is the incompatibility ?

[craig.topper]

llvm/lib/Target/RISCV/RISCV.td

450

I think THEAD should be T-Head in the description since that is user visible?

[JojoR]

llvm/lib/Target/RISCV/RISCV.td

450

Good point, I will refine this in the next version, thanks :)

[JojoR]

I am confused about the failures of CI testing and checked that is AddressSanitizer-Unit of x86,
it looks there is no relation between AddressSanitizer and this patch,
could anyone give me some hints for the failures ? thanks :)

[• pcwang-thead]

In D139386#3993766, @JojoR wrote:

I am confused about the failures of CI testing and checked that is AddressSanitizer-Unit of x86,
it looks there is no relation between AddressSanitizer and this patch,
could anyone give me some hints for the failures ? thanks :)

If these failures are apparently irrelevant to your changes, you can just ignore them since they may be caused by other landed patches.
A rebasing on main branch may help.

[jrtc27]

If this is some new T-Head extension based on the ratified V 1.0 rather than the 0.7.1 draft implemented in existing T-Head hardware then the compatibility points I made can be ignored. I would prefer that llvm/test remain flatter though and not have Vendor/THEAD/vdot, just use a single level with xtheadvdot as the name. In the case of MC I'd go one step further and say, given it's just a single file (that should conform to the -(in)valid.s convention that already exists there) it should be xtheadvdot-valid.s or whatever (just copy the Ventana approach).

[jrtc27]

llvm/include/llvm/IR/IntrinsicsRISCV.td

1589

IntrinsicsRISCVXThead?

[• pcwang-thead]

It seems we have split Clang changes off, but this patch still mix MC and CodeGen changes.
I think we can do further splitting to make it easier to review (separate MC and CodeGen). :-)

llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td

2

RISCVInstrInfoXTHeadV.td -> RISCVInstrInfoXTHeadVdot.td?

llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudo.td

2

RISCVInstrInfoXTHeadVPseudo.td -> RISCVInstrInfoXTHeadVdotPseudo.td?

[• pcwang-thead]

llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudo.td

2

Pseudo->Pseudos

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td

30

Missing DecoderNamespace?

62

Merge these into a single let?

llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudo.td

22

Quadenable -> QuadWidenable.

60

indent this 4 more spaces

73

indent this 4 more spaces

[reames]

Next step to make progress here is to strip out everything which isn't related to MC (assembler and disassembler). The intrinsic codegen changes should be a separate patch.

llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

2

Minor: Splitting this off into three different files seems to have little value to me. I would merge all the contents of XTHead* into the root file. If we add further extensions where the division becomes worthwhile, we can split at that time.

llvm/test/CodeGen/RISCV/xtheadvdot/vmaqa.ll

1 ↗

(On Diff #482717)

Minor: These dependent on vector, so they should be in the rvv subtree.

Naming wise, I'd stop the xtheadvdot directory, and just prefix the paths.

Ex: test/CodeGen/RISCV/rvv/xtheadvdot-vmaqa.ll

[• pcwang-thead]

llvm/test/MC/RISCV/XTHeadVdot-valid.s

1 ↗

(On Diff #483866)

Change the file name to lower case?

[JojoR]

llvm/test/MC/RISCV/XTHeadVdot-valid.s

1 ↗

(On Diff #483866)

We would like this could be align with other vendors like Ventana,
you can see "XVentanaCondOps-valid.s"

[eopXD]

Looks good to me.

[asb]

Reverse ping on this - @JojoR are there outstanding changes you have planned for this, or is it ready to go on from your perspective. I _think_ the review comments were all addressed and of course it got a LGTM from eop.

llvm/docs/RISCVUsage.rst

164 ↗

(On Diff #483866)

riscv-toolchai-convention => riscv-toolchain-convention

[craig.topper]

I think this was committed at 54752f3ff6d50944f17c260a6dc47a4758a026fc

llvm/include/llvm/IR/IntrinsicsRISCV.td

 // Zksed
 def int_riscv_sm4ks      : ScalarCryptoByteSelectAny;
 def int_riscv_sm4ed      : ScalarCryptoByteSelectAny;
 
 // Zksh
 def int_riscv_sm3p0      : ScalarCryptoGprIntrinsicAny;
 def int_riscv_sm3p1      : ScalarCryptoGprIntrinsicAny;
 } // TargetPrefix = "riscv"
+
+//===----------------------------------------------------------------------===//
+// Vendor extensions
+//===----------------------------------------------------------------------===//
+include "llvm/IR/IntrinsicsRISCV_THEAD.td"

llvm/include/llvm/IR/IntrinsicsRISCV_THEAD.td

+let TargetPrefix = "riscv" in {
+
+  class TH_VdotTernaryWideMasked
+        : Intrinsic< [llvm_anyvector_ty],
+                     [LLVMMatchType<0>, llvm_any_ty, llvm_anyvector_ty,
+                      LLVMScalarOrSameVectorWidth<2, llvm_i1_ty>,
+                      llvm_anyint_ty, LLVMMatchType<3>],
+                     [ImmArg<ArgIndex<5>>, IntrNoMem]>, RISCVVIntrinsic {
+    let ScalarOperand = 1;
+    let VLOperand = 4;
+  }
+
+  multiclass TH_VdotTernaryWide {
+    def "int_riscv_" # NAME : RISCVTernaryWideUnMasked;
+    def "int_riscv_" # NAME # "_mask" : TH_VdotTernaryWideMasked;
+  }
+
+  defm th_vmaqa    : TH_VdotTernaryWide;
+  defm th_vmaqau   : TH_VdotTernaryWide;
+  defm th_vmaqasu  : TH_VdotTernaryWide;
+  defm th_vmaqaus  : TH_VdotTernaryWide;
+}

llvm/lib/Support/RISCVISAInfo.cpp

static const RISCVSupportedExtension SupportedExtensions[] = {
 
     {"zicbom", RISCVExtensionVersion{1, 0}},
     {"zicboz", RISCVExtensionVersion{1, 0}},
     {"zicbop", RISCVExtensionVersion{1, 0}},
 
     {"svnapot", RISCVExtensionVersion{1, 0}},
     {"svinval", RISCVExtensionVersion{1, 0}},
     {"xventanacondops", RISCVExtensionVersion{1, 0}},
+    {"xtheadvdot", RISCVExtensionVersion{1, 0}},
 };
 
 static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
     {"zihintntl", RISCVExtensionVersion{0, 2}},
 
     {"zca", RISCVExtensionVersion{0, 70}},
     {"zcd", RISCVExtensionVersion{0, 70}},
     {"zcf", RISCVExtensionVersion{0, 70}},

 static const char *ImpliedExtsZvl512b[] = {"zvl256b"};
 static const char *ImpliedExtsZvl256b[] = {"zvl128b"};
 static const char *ImpliedExtsZvl128b[] = {"zvl64b"};
 static const char *ImpliedExtsZvl64b[] = {"zvl32b"};
 static const char *ImpliedExtsZk[] = {"zkn", "zkt", "zkr"};
 static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"};
 static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
 static const char *ImpliedExtsZvfh[] = {"zve32f"};
+static const char *ImpliedExtsXTHeadVdot[] = {"v"};
 
 struct ImpliedExtsEntry {
   StringLiteral Name;
   ArrayRef<const char *> Exts;
 
   bool operator<(const ImpliedExtsEntry &Other) const {
     return Name < Other.Name;
   }
 
   bool operator<(StringRef Other) const { return Name < Other; }
 };
 
 // Note: The table needs to be sorted by name.
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
     {{"v"}, {ImpliedExtsV}},
+    {{"xtheadvdot"}, {ImpliedExtsXTHeadVdot}},
     {{"zdinx"}, {ImpliedExtsZdinx}},
     {{"zfh"}, {ImpliedExtsZfh}},
     {{"zfhmin"}, {ImpliedExtsZfhmin}},
     {{"zhinx"}, {ImpliedExtsZhinx}},
     {{"zhinxmin"}, {ImpliedExtsZhinxmin}},
     {{"zk"}, {ImpliedExtsZk}},
     {{"zkn"}, {ImpliedExtsZkn}},
     {{"zks"}, {ImpliedExtsZks}},

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

if (STI.getFeatureBits()[RISCV::FeatureVendorXVentanaCondOps]) {
       LLVM_DEBUG(dbgs() << "Trying Ventana custom opcode table:\n");
       Result = decodeInstruction(DecoderTableVentana32, MI, Insn, Address, this,
                                  STI);
       if (Result != MCDisassembler::Fail) {
         Size = 4;
         return Result;
       }
     }
+    if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadVdot]) {
+      LLVM_DEBUG(dbgs() << "Trying T-Head custom opcode table:\n");
+      Result = decodeInstruction(DecoderTableTHeadV32, MI, Insn, Address, this,
+                                 STI);
+      if (Result != MCDisassembler::Fail) {
+        Size = 4;
+        return Result;
+      }
+    }
 
     LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n");
     Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
     Size = 4;
   } else {
     if (Bytes.size() < 2) {
       Size = 0;
       return MCDisassembler::Fail;

llvm/lib/Target/RISCV/RISCV.td

 
 def FeatureVendorXVentanaCondOps
     : SubtargetFeature<"xventanacondops", "HasVendorXVentanaCondOps", "true",
                        "'XVentanaCondOps' (Ventana Conditional Ops)">;
 def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()">,
                                 AssemblerPredicate<(all_of FeatureVendorXVentanaCondOps),
                                 "'XVentanaCondOps' (Ventana Conditional Ops)">;
 
+def FeatureVendorXTHeadVdot
+    : SubtargetFeature<"xtheadvdot", "HasVendorXTHeadVdot", "true",
+                       "'xtheadvdot' (T-Head Vector Extensions for Dot)",
+                       [FeatureStdExtV]>;
+def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">,
+                                    AssemblerPredicate<(all_of FeatureVendorXTHeadVdot),
+                                    "'xtheadvdot' (T-Head Vector Extensions for Dot)">;
+
 //===----------------------------------------------------------------------===//
 // LLVM specific features and extensions
 //===----------------------------------------------------------------------===//
 
 // Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
 // tuning CPU names.
 def Feature32Bit
     : SubtargetFeature<"32bit", "HasRV32", "true", "Implements RV32">;
def FeatureForcedAtomics : SubtargetFeature<
     "forced-atomics", "HasForcedAtomics", "true",
     "Assume that lock-free native-width atomics are available">;
 def HasAtomicLdSt
     : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics()">;
 
 //===----------------------------------------------------------------------===//
 // Named operands for CSR instructions.
 //===----------------------------------------------------------------------===//
 
 include "RISCVSystemOperands.td"
 
 //===----------------------------------------------------------------------===//
 // Registers, calling conventions, instruction descriptions.
 //===----------------------------------------------------------------------===//
 
 include "RISCVSchedule.td"
 include "RISCVRegisterInfo.td"

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 include "RISCVInstrInfoZfh.td"
 include "RISCVInstrInfoZicbo.td"
 
 //===----------------------------------------------------------------------===//
 // Vendor extensions
 //===----------------------------------------------------------------------===//
 
 include "RISCVInstrInfoXVentana.td"
+include "RISCVInstrInfoXTHead.td"

llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

+//===-- RISCVInstrInfoXTHead.td ----------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the vendor extensions defined by T-Head of Alibaba.
+//
+//===----------------------------------------------------------------------===//
+
+include "RISCVInstrInfoXTHeadV.td"

llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadV.td

+//===-- RISCVInstrInfoXTHeadV.td ---------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the vendor extensions defined by T-Head of Alibaba.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+class THInstVdotVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
+                   string opcodestr, string argstr>
+    : RVInstVV<funct6, opv, outs, ins, opcodestr, argstr> {
+  let Inst{26} = 0;
+  let Opcode = OPC_CUSTOM_0.Value;
+  let DecoderNamespace = "THeadV";
+}
+
+class THInstVdotVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
+                   string opcodestr, string argstr>
+    : RVInstVX<funct6, opv, outs, ins, opcodestr, argstr> {
+  let Inst{26} = 1;
+  let Opcode = OPC_CUSTOM_0.Value;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+// op vd, vs1, vs2, vm (reverse the order of vs1 and vs2)
+class THVdotALUrVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+    : THInstVdotVV<funct6, opv, (outs VR:$vd),
+                   (ins VR:$vs1, VR:$vs2, VMaskOp:$vm),
+                   opcodestr, "$vd, $vs1, $vs2$vm">;
+
+// op vd, rs1, vs2, vm (reverse the order of rs1 and vs2)
+class THVdotALUrVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+    : THInstVdotVX<funct6, opv, (outs VR:$vd),
+                   (ins GPR:$rs1, VR:$vs2, VMaskOp:$vm),
+                   opcodestr, "$vd, $rs1, $vs2$vm">;
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+//===----------------------------------------------------------------------===//
+// Combination of instruction classes.
+// Use these multiclasses to define instructions more easily.
+//===----------------------------------------------------------------------===//
+multiclass THVdotVMAQA_VX<string opcodestr, bits<6> funct6> {
+  def _VX : THVdotALUrVX<funct6, OPMVX, opcodestr # ".vx">;
+}
+
+multiclass THVdotVMAQA<string opcodestr, bits<6> funct6> {
+  def _VV   : THVdotALUrVV<funct6, OPMVX, opcodestr # ".vv">;
+  defm ""   : THVdotVMAQA_VX<opcodestr, funct6>;
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+let Predicates = [HasVendorXTHeadVdot] in {
+let Constraints = "@earlyclobber $vd" in {
+let RVVConstraint = WidenV in {
+defm THVdotVMAQA      : THVdotVMAQA<"th.vmaqa",     0b100000>;
+defm THVdotVMAQAU     : THVdotVMAQA<"th.vmaqau",    0b100010>;
+defm THVdotVMAQASU    : THVdotVMAQA<"th.vmaqasu",   0b100100>;
+defm THVdotVMAQAUS    : THVdotVMAQA_VX<"th.vmaqaus",0b100110>;
+} // RVVConstraint = WidenV
+} // Constraints = "@earlyclobber $vd"
+} // Predicates = [HasVendorXTHeadVdot]
+
+include "RISCVInstrInfoXTHeadVPseudo.td"

llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudo.td

+//===-- RISCVInstrInfoXTHeadVPseudo.td ---------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the vendor extensions defined by T-Head of Alibaba.
+//
+//===----------------------------------------------------------------------===//
+
+// Associate LMUL with tablegen records of register classes.
+def THVdotV_M1  : LMULInfo<0b000,  8,   VR, VR,   VR,   VR,   VR, "M1">;
+def THVdotV_M2  : LMULInfo<0b001, 16, VRM2, VRM2, VR,   VR,   VR, "M2">;
+def THVdotV_M4  : LMULInfo<0b010, 32, VRM4, VRM4, VRM2, VR,   VR, "M4">;
+def THVdotV_M8  : LMULInfo<0b011, 64, VRM8, VRM8, VRM4, VRM2, VR, "M8">;
+
+defvar MxListTHVdot = [V_MF2, THVdotV_M1, THVdotV_M2, THVdotV_M4, THVdotV_M8];
+
+defset list<VTypeInfoToWide> AllQuadenableInt8NoVLMulVectors = {
+  def : VTypeInfoToWide<VI8MF2,  VI32MF2>;
+  def : VTypeInfoToWide<VI8M1,   VI32M1>;
+  def : VTypeInfoToWide<VI8M2,   VI32M2>;
+  def : VTypeInfoToWide<VI8M4,   VI32M4>;
+  def : VTypeInfoToWide<VI8M8,   VI32M8>;
+}
+
+//===----------------------------------------------------------------------===//
+// Combination of instruction classes.
+// Use these multiclasses to define instructions more easily.
+//===----------------------------------------------------------------------===//
+multiclass VPseudoVMAQA_VV_VX {
+  foreach m = MxListTHVdot in {
+    defm "" : VPseudoTernaryW_VV<m>;
+    defm "" : VPseudoTernaryW_VX<m>;
+  }
+}
+
+multiclass VPseudoVMAQA_VX {
+  foreach m = MxListTHVdot in {
+    defm "" : VPseudoTernaryW_VX<m>;
+  }
+}
+
+multiclass VPatTernaryVMAQA_VV<string intrinsic, string instruction,
+                           list<VTypeInfoToWide> vtilist> {
+  foreach vtiToWti = vtilist in {
+    defvar vti = vtiToWti.Vti;
+    defvar wti = vtiToWti.Wti;
+    defm : VPatTernaryWithPolicy<intrinsic, instruction, "VV",
+                                 wti.Vector, vti.Vector, vti.Vector,
+                                 vti.Mask, wti.Log2SEW, vti.LMul,
+                                 wti.RegClass, vti.RegClass, vti.RegClass>;
+  }
+}
+
+multiclass VPatTernaryVMAQA_VX<string intrinsic, string instruction,
+                           list<VTypeInfoToWide> vtilist> {
+  foreach vtiToWti = vtilist in {
+    defvar vti = vtiToWti.Vti;
+    defvar wti = vtiToWti.Wti;
+    defm : VPatTernaryWithPolicy<intrinsic, instruction,
+                                 "V"#vti.ScalarSuffix,
+                                 wti.Vector, vti.Scalar, vti.Vector,
+                                 vti.Mask, wti.Log2SEW, vti.LMul,
+                                 wti.RegClass, vti.ScalarRegClass, vti.RegClass>;
+  }
+}
+
+multiclass VPatTernaryVMAQA_VV_VX<string intrinsic, string instruction,
+                              list<VTypeInfoToWide> vtilist>
+    : VPatTernaryVMAQA_VV<intrinsic, instruction, vtilist>,
+      VPatTernaryVMAQA_VX<intrinsic, instruction, vtilist>;
+
+//===----------------------------------------------------------------------===//
+// Pseudo-instructions and codegen patterns
+//===----------------------------------------------------------------------===//
+defm PseudoTHVdotVMAQA      : VPseudoVMAQA_VV_VX;
+defm PseudoTHVdotVMAQAU     : VPseudoVMAQA_VV_VX;
+defm PseudoTHVdotVMAQASU    : VPseudoVMAQA_VV_VX;
+defm PseudoTHVdotVMAQAUS    : VPseudoVMAQA_VX;
+
+let Predicates = [HasVendorXTHeadVdot] in {
+defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqa",  "PseudoTHVdotVMAQA",  AllQuadenableInt8NoVLMulVectors>;
+defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqau", "PseudoTHVdotVMAQAU", AllQuadenableInt8NoVLMulVectors>;
+defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqasu","PseudoTHVdotVMAQASU",AllQuadenableInt8NoVLMulVectors>;
+defm : VPatTernaryVMAQA_VX<"int_riscv_th_vmaqaus",   "PseudoTHVdotVMAQAUS",AllQuadenableInt8NoVLMulVectors>;
+}

llvm/test/CodeGen/RISCV/Vendor/THEAD/vdot/vmaqa.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvdot \
+; RUN:   -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvdot \
+; RUN:   -verify-machineinstrs | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.th.vmaqa.nxv1i32.nxv4i8(
+  <vscale x 1 x i32>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 1 x i32>  @intrinsic_th_vmaqa_vv_nxv1i32_nxv4i8_nxv4i8(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqa_vv_nxv1i32_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, ma
+; CHECK-NEXT:    th.vmaqa.vv v8, v9, v10
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.nxv1i32.nxv4i8(
+    <vscale x 1 x i32> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.th.vmaqa.mask.nxv1i32.nxv4i8(
+  <vscale x 1 x i32>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 1 x i32>  @intrinsic_th_vmaqa_mask_vv_nxv1i32_nxv4i8_nxv4i8(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqa_mask_vv_nxv1i32_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, mu
+; CHECK-NEXT:    th.vmaqa.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.mask.nxv1i32.nxv4i8(
+    <vscale x 1 x i32> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.th.vmaqa.nxv2i32.nxv8i8(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 2 x i32>  @intrinsic_th_vmaqa_vv_nxv2i32_nxv8i8_nxv8i8(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqa_vv_nxv2i32_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma
+; CHECK-NEXT:    th.vmaqa.vv v8, v9, v10
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.nxv2i32.nxv8i8(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.th.vmaqa.mask.nxv2i32.nxv8i8(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 2 x i32>  @intrinsic_th_vmaqa_mask_vv_nxv2i32_nxv8i8_nxv8i8(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqa_mask_vv_nxv2i32_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, mu
+; CHECK-NEXT:    th.vmaqa.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.mask.nxv2i32.nxv8i8(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.th.vmaqa.nxv4i32.nxv16i8(
+  <vscale x 4 x i32>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 4 x i32>  @intrinsic_th_vmaqa_vv_nxv4i32_nxv16i8_nxv16i8(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqa_vv_nxv4i32_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma
+; CHECK-NEXT:    th.vmaqa.vv v8, v10, v12
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.nxv4i32.nxv16i8(
+    <vscale x 4 x i32> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.th.vmaqa.mask.nxv4i32.nxv16i8(
+  <vscale x 4 x i32>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 4 x i32>  @intrinsic_th_vmaqa_mask_vv_nxv4i32_nxv16i8_nxv16i8(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqa_mask_vv_nxv4i32_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, mu
+; CHECK-NEXT:    th.vmaqa.vv v8, v10, v12, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.mask.nxv4i32.nxv16i8(
+    <vscale x 4 x i32> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.th.vmaqa.nxv8i32.nxv32i8(
+  <vscale x 8 x i32>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 8 x i32>  @intrinsic_th_vmaqa_vv_nxv8i32_nxv32i8_nxv32i8(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqa_vv_nxv8i32_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, ma
+; CHECK-NEXT:    th.vmaqa.vv v8, v12, v16
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.nxv8i32.nxv32i8(
+    <vscale x 8 x i32> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.th.vmaqa.mask.nxv8i32.nxv32i8(
+  <vscale x 8 x i32>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 8 x i32>  @intrinsic_th_vmaqa_mask_vv_nxv8i32_nxv32i8_nxv32i8(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqa_mask_vv_nxv8i32_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, mu
+; CHECK-NEXT:    th.vmaqa.vv v8, v12, v16, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.mask.nxv8i32.nxv32i8(
+    <vscale x 8 x i32> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 8 x i32> %a
+}
+
+
+declare <vscale x 1 x i32> @llvm.riscv.th.vmaqa.nxv1i32.i8(
+  <vscale x 1 x i32>,
+  i8,
+  <vscale x 4 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 1 x i32>  @intrinsic_th_vmaqa_vx_nxv1i32_i8_nxv4i8(<vscale x 1 x i32> %0, i8 %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqa_vx_nxv1i32_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, tu, ma
+; CHECK-NEXT:    th.vmaqa.vx v8, a0, v9
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.nxv1i32.i8(
+    <vscale x 1 x i32> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.th.vmaqa.mask.nxv1i32.i8(
+  <vscale x 1 x i32>,
+  i8,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 1 x i32> @intrinsic_th_vmaqa_mask_vx_nxv1i32_i8_nxv4i8(<vscale x 1 x i32> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqa_mask_vx_nxv1i32_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, tu, mu
+; CHECK-NEXT:    th.vmaqa.vx v8, a0, v9, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.th.vmaqa.mask.nxv1i32.i8(
+    <vscale x 1 x i32> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.th.vmaqa.nxv2i32.i8(
+  <vscale x 2 x i32>,
+  i8,
+  <vscale x 8 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 2 x i32>  @intrinsic_th_vmaqa_vx_nxv2i32_i8_nxv8i8(<vscale x 2 x i32> %0, i8 %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqa_vx_nxv2i32_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m1, tu, ma
+; CHECK-NEXT:    th.vmaqa.vx v8, a0, v9
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.nxv2i32.i8(
+    <vscale x 2 x i32> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.th.vmaqa.mask.nxv2i32.i8(
+  <vscale x 2 x i32>,
+  i8,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 2 x i32> @intrinsic_th_vmaqa_mask_vx_nxv2i32_i8_nxv8i8(<vscale x 2 x i32> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqa_mask_vx_nxv2i32_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m1, tu, mu
+; CHECK-NEXT:    th.vmaqa.vx v8, a0, v9, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.th.vmaqa.mask.nxv2i32.i8(
+    <vscale x 2 x i32> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.th.vmaqa.nxv4i32.i8(
+  <vscale x 4 x i32>,
+  i8,
+  <vscale x 16 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 4 x i32>  @intrinsic_th_vmaqa_vx_nxv4i32_i8_nxv16i8(<vscale x 4 x i32> %0, i8 %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqa_vx_nxv4i32_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, ma
+; CHECK-NEXT:    th.vmaqa.vx v8, a0, v10
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.nxv4i32.i8(
+    <vscale x 4 x i32> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.th.vmaqa.mask.nxv4i32.i8(
+  <vscale x 4 x i32>,
+  i8,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 4 x i32> @intrinsic_th_vmaqa_mask_vx_nxv4i32_i8_nxv16i8(<vscale x 4 x i32> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqa_mask_vx_nxv4i32_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, mu
+; CHECK-NEXT:    th.vmaqa.vx v8, a0, v10, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.th.vmaqa.mask.nxv4i32.i8(
+    <vscale x 4 x i32> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.th.vmaqa.nxv8i32.i8(
+  <vscale x 8 x i32>,
+  i8,
+  <vscale x 32 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 8 x i32>  @intrinsic_th_vmaqa_vx_nxv8i32_i8_nxv32i8(<vscale x 8 x i32> %0, i8 %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqa_vx_nxv8i32_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m4, tu, ma
+; CHECK-NEXT:    th.vmaqa.vx v8, a0, v12
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.nxv8i32.i8(
+    <vscale x 8 x i32> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.th.vmaqa.mask.nxv8i32.i8(
+  <vscale x 8 x i32>,
+  i8,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 8 x i32> @intrinsic_th_vmaqa_mask_vx_nxv8i32_i8_nxv32i8(<vscale x 8 x i32> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqa_mask_vx_nxv8i32_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m4, tu, mu
+; CHECK-NEXT:    th.vmaqa.vx v8, a0, v12, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.th.vmaqa.mask.nxv8i32.i8(
+    <vscale x 8 x i32> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 8 x i32> %a
+}

llvm/test/CodeGen/RISCV/Vendor/THEAD/vdot/vmaqasu.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvdot \
+; RUN:   -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvdot \
+; RUN:   -verify-machineinstrs | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.nxv1i32.nxv4i8(
+  <vscale x 1 x i32>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 1 x i32>  @intrinsic_th_vmaqasu_vv_nxv1i32_nxv4i8_nxv4i8(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqasu_vv_nxv1i32_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, ma
+; CHECK-NEXT:    th.vmaqasu.vv v8, v9, v10
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.nxv1i32.nxv4i8(
+    <vscale x 1 x i32> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.mask.nxv1i32.nxv4i8(
+  <vscale x 1 x i32>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 1 x i32>  @intrinsic_th_vmaqasu_mask_vv_nxv1i32_nxv4i8_nxv4i8(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqasu_mask_vv_nxv1i32_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, mu
+; CHECK-NEXT:    th.vmaqasu.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.mask.nxv1i32.nxv4i8(
+    <vscale x 1 x i32> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.nxv2i32.nxv8i8(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 2 x i32>  @intrinsic_th_vmaqasu_vv_nxv2i32_nxv8i8_nxv8i8(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqasu_vv_nxv2i32_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma
+; CHECK-NEXT:    th.vmaqasu.vv v8, v9, v10
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.nxv2i32.nxv8i8(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.mask.nxv2i32.nxv8i8(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 2 x i32>  @intrinsic_th_vmaqasu_mask_vv_nxv2i32_nxv8i8_nxv8i8(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqasu_mask_vv_nxv2i32_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, mu
+; CHECK-NEXT:    th.vmaqasu.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.mask.nxv2i32.nxv8i8(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.nxv4i32.nxv16i8(
+  <vscale x 4 x i32>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 4 x i32>  @intrinsic_th_vmaqasu_vv_nxv4i32_nxv16i8_nxv16i8(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqasu_vv_nxv4i32_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma
+; CHECK-NEXT:    th.vmaqasu.vv v8, v10, v12
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.nxv4i32.nxv16i8(
+    <vscale x 4 x i32> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.mask.nxv4i32.nxv16i8(
+  <vscale x 4 x i32>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 4 x i32>  @intrinsic_th_vmaqasu_mask_vv_nxv4i32_nxv16i8_nxv16i8(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqasu_mask_vv_nxv4i32_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, mu
+; CHECK-NEXT:    th.vmaqasu.vv v8, v10, v12, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.mask.nxv4i32.nxv16i8(
+    <vscale x 4 x i32> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.nxv8i32.nxv32i8(
+  <vscale x 8 x i32>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 8 x i32>  @intrinsic_th_vmaqasu_vv_nxv8i32_nxv32i8_nxv32i8(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqasu_vv_nxv8i32_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, ma
+; CHECK-NEXT:    th.vmaqasu.vv v8, v12, v16
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.nxv8i32.nxv32i8(
+    <vscale x 8 x i32> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.mask.nxv8i32.nxv32i8(
+  <vscale x 8 x i32>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 8 x i32>  @intrinsic_th_vmaqasu_mask_vv_nxv8i32_nxv32i8_nxv32i8(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqasu_mask_vv_nxv8i32_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, mu
+; CHECK-NEXT:    th.vmaqasu.vv v8, v12, v16, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.mask.nxv8i32.nxv32i8(
+    <vscale x 8 x i32> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 8 x i32> %a
+}
+
+
+declare <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.nxv1i32.i8(
+  <vscale x 1 x i32>,
+  i8,
+  <vscale x 4 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 1 x i32>  @intrinsic_th_vmaqasu_vx_nxv1i32_i8_nxv4i8(<vscale x 1 x i32> %0, i8 %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqasu_vx_nxv1i32_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, tu, ma
+; CHECK-NEXT:    th.vmaqasu.vx v8, a0, v9
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.nxv1i32.i8(
+    <vscale x 1 x i32> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.mask.nxv1i32.i8(
+  <vscale x 1 x i32>,
+  i8,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 1 x i32> @intrinsic_th_vmaqasu_mask_vx_nxv1i32_i8_nxv4i8(<vscale x 1 x i32> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqasu_mask_vx_nxv1i32_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, tu, mu
+; CHECK-NEXT:    th.vmaqasu.vx v8, a0, v9, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.th.vmaqasu.mask.nxv1i32.i8(
+    <vscale x 1 x i32> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.nxv2i32.i8(
+  <vscale x 2 x i32>,
+  i8,
+  <vscale x 8 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 2 x i32>  @intrinsic_th_vmaqasu_vx_nxv2i32_i8_nxv8i8(<vscale x 2 x i32> %0, i8 %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqasu_vx_nxv2i32_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m1, tu, ma
+; CHECK-NEXT:    th.vmaqasu.vx v8, a0, v9
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.nxv2i32.i8(
+    <vscale x 2 x i32> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.mask.nxv2i32.i8(
+  <vscale x 2 x i32>,
+  i8,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 2 x i32> @intrinsic_th_vmaqasu_mask_vx_nxv2i32_i8_nxv8i8(<vscale x 2 x i32> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqasu_mask_vx_nxv2i32_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m1, tu, mu
+; CHECK-NEXT:    th.vmaqasu.vx v8, a0, v9, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.th.vmaqasu.mask.nxv2i32.i8(
+    <vscale x 2 x i32> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.nxv4i32.i8(
+  <vscale x 4 x i32>,
+  i8,
+  <vscale x 16 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 4 x i32>  @intrinsic_th_vmaqasu_vx_nxv4i32_i8_nxv16i8(<vscale x 4 x i32> %0, i8 %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqasu_vx_nxv4i32_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, ma
+; CHECK-NEXT:    th.vmaqasu.vx v8, a0, v10
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.nxv4i32.i8(
+    <vscale x 4 x i32> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.mask.nxv4i32.i8(
+  <vscale x 4 x i32>,
+  i8,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 4 x i32> @intrinsic_th_vmaqasu_mask_vx_nxv4i32_i8_nxv16i8(<vscale x 4 x i32> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqasu_mask_vx_nxv4i32_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, mu
+; CHECK-NEXT:    th.vmaqasu.vx v8, a0, v10, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.th.vmaqasu.mask.nxv4i32.i8(
+    <vscale x 4 x i32> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.nxv8i32.i8(
+  <vscale x 8 x i32>,
+  i8,
+  <vscale x 32 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 8 x i32>  @intrinsic_th_vmaqasu_vx_nxv8i32_i8_nxv32i8(<vscale x 8 x i32> %0, i8 %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqasu_vx_nxv8i32_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m4, tu, ma
+; CHECK-NEXT:    th.vmaqasu.vx v8, a0, v12
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.nxv8i32.i8(
+    <vscale x 8 x i32> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.mask.nxv8i32.i8(
+  <vscale x 8 x i32>,
+  i8,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 8 x i32> @intrinsic_th_vmaqasu_mask_vx_nxv8i32_i8_nxv32i8(<vscale x 8 x i32> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqasu_mask_vx_nxv8i32_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m4, tu, mu
+; CHECK-NEXT:    th.vmaqasu.vx v8, a0, v12, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.th.vmaqasu.mask.nxv8i32.i8(
+    <vscale x 8 x i32> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 8 x i32> %a
+}

llvm/test/CodeGen/RISCV/Vendor/THEAD/vdot/vmaqau.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvdot \
+; RUN:   -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvdot \
+; RUN:   -verify-machineinstrs | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.th.vmaqau.nxv1i32.nxv4i8(
+  <vscale x 1 x i32>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 1 x i32>  @intrinsic_th_vmaqau_vv_nxv1i32_nxv4i8_nxv4i8(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqau_vv_nxv1i32_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, ma
+; CHECK-NEXT:    th.vmaqau.vv v8, v9, v10
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.th.vmaqau.nxv1i32.nxv4i8(
+    <vscale x 1 x i32> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.th.vmaqau.mask.nxv1i32.nxv4i8(
+  <vscale x 1 x i32>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 1 x i32>  @intrinsic_th_vmaqau_mask_vv_nxv1i32_nxv4i8_nxv4i8(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqau_mask_vv_nxv1i32_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, mu
+; CHECK-NEXT:    th.vmaqau.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.th.vmaqau.mask.nxv1i32.nxv4i8(
+    <vscale x 1 x i32> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.th.vmaqau.nxv2i32.nxv8i8(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 2 x i32>  @intrinsic_th_vmaqau_vv_nxv2i32_nxv8i8_nxv8i8(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqau_vv_nxv2i32_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma
+; CHECK-NEXT:    th.vmaqau.vv v8, v9, v10
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.th.vmaqau.nxv2i32.nxv8i8(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.th.vmaqau.mask.nxv2i32.nxv8i8(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 2 x i32>  @intrinsic_th_vmaqau_mask_vv_nxv2i32_nxv8i8_nxv8i8(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqau_mask_vv_nxv2i32_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, mu
+; CHECK-NEXT:    th.vmaqau.vv v8, v9, v10, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.th.vmaqau.mask.nxv2i32.nxv8i8(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.th.vmaqau.nxv4i32.nxv16i8(
+  <vscale x 4 x i32>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 4 x i32>  @intrinsic_th_vmaqau_vv_nxv4i32_nxv16i8_nxv16i8(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqau_vv_nxv4i32_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma
+; CHECK-NEXT:    th.vmaqau.vv v8, v10, v12
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.th.vmaqau.nxv4i32.nxv16i8(
+    <vscale x 4 x i32> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.th.vmaqau.mask.nxv4i32.nxv16i8(
+  <vscale x 4 x i32>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 4 x i32>  @intrinsic_th_vmaqau_mask_vv_nxv4i32_nxv16i8_nxv16i8(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqau_mask_vv_nxv4i32_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, mu
+; CHECK-NEXT:    th.vmaqau.vv v8, v10, v12, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.th.vmaqau.mask.nxv4i32.nxv16i8(
+    <vscale x 4 x i32> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.th.vmaqau.nxv8i32.nxv32i8(
+  <vscale x 8 x i32>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 8 x i32>  @intrinsic_th_vmaqau_vv_nxv8i32_nxv32i8_nxv32i8(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqau_vv_nxv8i32_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, ma
+; CHECK-NEXT:    th.vmaqau.vv v8, v12, v16
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.th.vmaqau.nxv8i32.nxv32i8(
+    <vscale x 8 x i32> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.th.vmaqau.mask.nxv8i32.nxv32i8(
+  <vscale x 8 x i32>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 8 x i32>  @intrinsic_th_vmaqau_mask_vv_nxv8i32_nxv32i8_nxv32i8(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqau_mask_vv_nxv8i32_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, mu
+; CHECK-NEXT:    th.vmaqau.vv v8, v12, v16, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.th.vmaqau.mask.nxv8i32.nxv32i8(
+    <vscale x 8 x i32> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 8 x i32> %a
+}
+
+
+declare <vscale x 1 x i32> @llvm.riscv.th.vmaqau.nxv1i32.i8(
+  <vscale x 1 x i32>,
+  i8,
+  <vscale x 4 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 1 x i32>  @intrinsic_th_vmaqau_vx_nxv1i32_i8_nxv4i8(<vscale x 1 x i32> %0, i8 %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqau_vx_nxv1i32_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, tu, ma
+; CHECK-NEXT:    th.vmaqau.vx v8, a0, v9
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.th.vmaqau.nxv1i32.i8(
+    <vscale x 1 x i32> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.th.vmaqau.mask.nxv1i32.i8(
+  <vscale x 1 x i32>,
+  i8,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 1 x i32> @intrinsic_th_vmaqau_mask_vx_nxv1i32_i8_nxv4i8(<vscale x 1 x i32> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqau_mask_vx_nxv1i32_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, tu, mu
+; CHECK-NEXT:    th.vmaqau.vx v8, a0, v9, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.th.vmaqau.mask.nxv1i32.i8(
+    <vscale x 1 x i32> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.th.vmaqau.nxv2i32.i8(
+  <vscale x 2 x i32>,
+  i8,
+  <vscale x 8 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 2 x i32>  @intrinsic_th_vmaqau_vx_nxv2i32_i8_nxv8i8(<vscale x 2 x i32> %0, i8 %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqau_vx_nxv2i32_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m1, tu, ma
+; CHECK-NEXT:    th.vmaqau.vx v8, a0, v9
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.th.vmaqau.nxv2i32.i8(
+    <vscale x 2 x i32> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.th.vmaqau.mask.nxv2i32.i8(
+  <vscale x 2 x i32>,
+  i8,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 2 x i32> @intrinsic_th_vmaqau_mask_vx_nxv2i32_i8_nxv8i8(<vscale x 2 x i32> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqau_mask_vx_nxv2i32_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m1, tu, mu
+; CHECK-NEXT:    th.vmaqau.vx v8, a0, v9, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.th.vmaqau.mask.nxv2i32.i8(
+    <vscale x 2 x i32> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.th.vmaqau.nxv4i32.i8(
+  <vscale x 4 x i32>,
+  i8,
+  <vscale x 16 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 4 x i32>  @intrinsic_th_vmaqau_vx_nxv4i32_i8_nxv16i8(<vscale x 4 x i32> %0, i8 %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqau_vx_nxv4i32_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, ma
+; CHECK-NEXT:    th.vmaqau.vx v8, a0, v10
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.th.vmaqau.nxv4i32.i8(
+    <vscale x 4 x i32> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.th.vmaqau.mask.nxv4i32.i8(
+  <vscale x 4 x i32>,
+  i8,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 4 x i32> @intrinsic_th_vmaqau_mask_vx_nxv4i32_i8_nxv16i8(<vscale x 4 x i32> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqau_mask_vx_nxv4i32_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, mu
+; CHECK-NEXT:    th.vmaqau.vx v8, a0, v10, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.th.vmaqau.mask.nxv4i32.i8(
+    <vscale x 4 x i32> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.th.vmaqau.nxv8i32.i8(
+  <vscale x 8 x i32>,
+  i8,
+  <vscale x 32 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 8 x i32>  @intrinsic_th_vmaqau_vx_nxv8i32_i8_nxv32i8(<vscale x 8 x i32> %0, i8 %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqau_vx_nxv8i32_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m4, tu, ma
+; CHECK-NEXT:    th.vmaqau.vx v8, a0, v12
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.th.vmaqau.nxv8i32.i8(
+    <vscale x 8 x i32> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.th.vmaqau.mask.nxv8i32.i8(
+  <vscale x 8 x i32>,
+  i8,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 8 x i32> @intrinsic_th_vmaqau_mask_vx_nxv8i32_i8_nxv32i8(<vscale x 8 x i32> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqau_mask_vx_nxv8i32_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m4, tu, mu
+; CHECK-NEXT:    th.vmaqau.vx v8, a0, v12, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.th.vmaqau.mask.nxv8i32.i8(
+    <vscale x 8 x i32> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 8 x i32> %a
+}

llvm/test/CodeGen/RISCV/Vendor/THEAD/vdot/vmaqaus.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvdot \
+; RUN:   -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvdot \
+; RUN:   -verify-machineinstrs | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.th.vmaqaus.nxv1i32.i8(
+  <vscale x 1 x i32>,
+  i8,
+  <vscale x 4 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 1 x i32>  @intrinsic_th_vmaqaus_vx_nxv1i32_i8_nxv4i8(<vscale x 1 x i32> %0, i8 %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqaus_vx_nxv1i32_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, tu, ma
+; CHECK-NEXT:    th.vmaqaus.vx v8, a0, v9
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.th.vmaqaus.nxv1i32.i8(
+    <vscale x 1 x i32> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.th.vmaqaus.mask.nxv1i32.i8(
+  <vscale x 1 x i32>,
+  i8,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 1 x i32> @intrinsic_th_vmaqaus_mask_vx_nxv1i32_i8_nxv4i8(<vscale x 1 x i32> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqaus_mask_vx_nxv1i32_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, tu, mu
+; CHECK-NEXT:    th.vmaqaus.vx v8, a0, v9, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.th.vmaqaus.mask.nxv1i32.i8(
+    <vscale x 1 x i32> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.th.vmaqaus.nxv2i32.i8(
+  <vscale x 2 x i32>,
+  i8,
+  <vscale x 8 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 2 x i32>  @intrinsic_th_vmaqaus_vx_nxv2i32_i8_nxv8i8(<vscale x 2 x i32> %0, i8 %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqaus_vx_nxv2i32_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m1, tu, ma
+; CHECK-NEXT:    th.vmaqaus.vx v8, a0, v9
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.th.vmaqaus.nxv2i32.i8(
+    <vscale x 2 x i32> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.th.vmaqaus.mask.nxv2i32.i8(
+  <vscale x 2 x i32>,
+  i8,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 2 x i32> @intrinsic_th_vmaqaus_mask_vx_nxv2i32_i8_nxv8i8(<vscale x 2 x i32> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqaus_mask_vx_nxv2i32_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m1, tu, mu
+; CHECK-NEXT:    th.vmaqaus.vx v8, a0, v9, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.th.vmaqaus.mask.nxv2i32.i8(
+    <vscale x 2 x i32> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.th.vmaqaus.nxv4i32.i8(
+  <vscale x 4 x i32>,
+  i8,
+  <vscale x 16 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 4 x i32>  @intrinsic_th_vmaqaus_vx_nxv4i32_i8_nxv16i8(<vscale x 4 x i32> %0, i8 %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqaus_vx_nxv4i32_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, ma
+; CHECK-NEXT:    th.vmaqaus.vx v8, a0, v10
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.th.vmaqaus.nxv4i32.i8(
+    <vscale x 4 x i32> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.th.vmaqaus.mask.nxv4i32.i8(
+  <vscale x 4 x i32>,
+  i8,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 4 x i32> @intrinsic_th_vmaqaus_mask_vx_nxv4i32_i8_nxv16i8(<vscale x 4 x i32> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqaus_mask_vx_nxv4i32_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, mu
+; CHECK-NEXT:    th.vmaqaus.vx v8, a0, v10, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.th.vmaqaus.mask.nxv4i32.i8(
+    <vscale x 4 x i32> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.th.vmaqaus.nxv8i32.i8(
+  <vscale x 8 x i32>,
+  i8,
+  <vscale x 32 x i8>,
+  iXLen,
+  iXLen);
+
+define <vscale x 8 x i32>  @intrinsic_th_vmaqaus_vx_nxv8i32_i8_nxv32i8(<vscale x 8 x i32> %0, i8 %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqaus_vx_nxv8i32_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m4, tu, ma
+; CHECK-NEXT:    th.vmaqaus.vx v8, a0, v12
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.th.vmaqaus.nxv8i32.i8(
+    <vscale x 8 x i32> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.th.vmaqaus.mask.nxv8i32.i8(
+  <vscale x 8 x i32>,
+  i8,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 8 x i32> @intrinsic_th_vmaqaus_mask_vx_nxv8i32_i8_nxv32i8(<vscale x 8 x i32> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_th_vmaqaus_mask_vx_nxv8i32_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m4, tu, mu
+; CHECK-NEXT:    th.vmaqaus.vx v8, a0, v12, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.th.vmaqaus.mask.nxv8i32.i8(
+    <vscale x 8 x i32> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    iXLen %4, iXLen 0)
+
+  ret <vscale x 8 x i32> %a
+}

llvm/test/CodeGen/RISCV/attributes.ll

 ; RUN: llc -mtriple=riscv64 -mattr=+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh %s -o - | FileCheck --check-prefix=RV64COMBINEINTOZKN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zbkb,+zbkc,+zbkx,+zksed,+zksh %s -o - | FileCheck --check-prefix=RV64COMBINEINTOZKS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV64ZICBOM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefix=RV64XVENTANACONDOPS %s
+; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck --check-prefix=RV64XTHEADVDOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV64ZCA %s
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
 ; RV32ZMMUL: .attribute 5, "rv32i2p0_zmmul1p0"
 ; RV32MZMMUL: .attribute 5, "rv32i2p0_m2p0_zmmul1p0"
 ; RV32A: .attribute 5, "rv32i2p0_a2p0"

 ; RV64COMBINEINTOZKS: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
 ; RV64ZICBOM: .attribute 5, "rv64i2p0_zicbom1p0"
 ; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0"
 ; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
 ; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
 ; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
 ; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
+; RV64XTHEADVDOT: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 ; RV64ZCA: .attribute 5, "rv64i2p0_zca0p70"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
   ret i32 %1
 }

llvm/test/MC/RISCV/Vendor/THEAD/vdot/vmaqa.s

+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xtheadvdot %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvdot %s \
+# RUN:        | llvm-objdump -d --mattr=+xtheadvdot - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xtheadvdot %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+th.vmaqau.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vmaqau.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x0b,0x64,0x4a,0x88]
+# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-UNKNOWN: 0b 64 4a 88 <unknown>
+
+th.vmaqau.vv v8, v20, v4
+# CHECK-INST: th.vmaqau.vv v8, v20, v4
+# CHECK-ENCODING: [0x0b,0x64,0x4a,0x8a]
+# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-UNKNOWN: 0b 64 4a 8a <unknown>
+
+th.vmaqau.vx v8, a0, v4, v0.t
+# CHECK-INST: th.vmaqau.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x0b,0x64,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-UNKNOWN: 0b 64 45 8c <unknown>
+
+th.vmaqau.vx v8, a0, v4
+# CHECK-INST: th.vmaqau.vx v8, a0, v4
+# CHECK-ENCODING: [0x0b,0x64,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-UNKNOWN: 0b 64 45 8e <unknown>
+
+th.vmaqa.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vmaqa.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x0b,0x64,0x4a,0x80]
+# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-UNKNOWN: 0b 64 4a 80 <unknown>
+
+th.vmaqa.vv v8, v20, v4
+# CHECK-INST: th.vmaqa.vv v8, v20, v4
+# CHECK-ENCODING: [0x0b,0x64,0x4a,0x82]
+# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-UNKNOWN: 0b 64 4a 82 <unknown>
+
+th.vmaqa.vx v8, a0, v4, v0.t
+# CHECK-INST: th.vmaqa.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x0b,0x64,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-UNKNOWN: 0b 64 45 84 <unknown>
+
+th.vmaqa.vx v8, a0, v4
+# CHECK-INST: th.vmaqa.vx v8, a0, v4
+# CHECK-ENCODING: [0x0b,0x64,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-UNKNOWN: 0b 64 45 86 <unknown>
+
+th.vmaqasu.vv v8, v20, v4, v0.t
+# CHECK-INST: th.vmaqasu.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x0b,0x64,0x4a,0x90]
+# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-UNKNOWN: 0b 64 4a 90 <unknown>
+
+th.vmaqasu.vv v8, v20, v4
+# CHECK-INST: th.vmaqasu.vv v8, v20, v4
+# CHECK-ENCODING: [0x0b,0x64,0x4a,0x92]
+# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-UNKNOWN: 0b 64 4a 92 <unknown>
+
+th.vmaqasu.vx v8, a0, v4, v0.t
+# CHECK-INST: th.vmaqasu.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x0b,0x64,0x45,0x94]
+# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-UNKNOWN: 0b 64 45 94 <unknown>
+
+th.vmaqasu.vx v8, a0, v4
+# CHECK-INST: th.vmaqasu.vx v8, a0, v4
+# CHECK-ENCODING: [0x0b,0x64,0x45,0x96]
+# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-UNKNOWN: 0b 64 45 96 <unknown>
+
+th.vmaqaus.vx v8, a0, v4, v0.t
+# CHECK-INST: th.vmaqaus.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x0b,0x64,0x45,0x9c]
+# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-UNKNOWN: 0b 64 45 9c <unknown>
+
+th.vmaqaus.vx v8, a0, v4
+# CHECK-INST: th.vmaqaus.vx v8, a0, v4
+# CHECK-ENCODING: [0x0b,0x64,0x45,0x9e]
+# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-UNKNOWN: 0b 64 45 9e <unknown>