[RISCV] Add Syntacore SCR1 CPU model

[dnpetrov-sc]

Summary

[RISCV] Add Syntacore SCR1 CPU model

SCR1 is available at https://github.com/syntacore/scr1

'scr1-base' corresponds to SCR1_CFG_RV32IC_BASE,
'scr1-max' corresponds to SCR1_CFG_RV32IMC_MAX.

SCR1_CFG_RV32EC_MIN is RV32EC, which is currently unsupported.

[craig.topper]

llvm/lib/Target/RISCV/RISCV.td

638

Shouldn't this also need Feature32Bit?

llvm/lib/Target/RISCV/RISCVSchedSCR1.td

208 ↗

(On Diff #480019)

Add new line

[dnpetrov-sc]

llvm/lib/Target/RISCV/RISCV.td

638

Now, that's somewhat funny. Indeed, RISCVSubtarget has HasRV32 field, but it is never queried. IsRV32 predicate in RISCV.td is mapped to !Subtarget->is64Bit() in C++ code.

Code generation for RV32E is not implemented yet, though (and would error out in RISCVTargetLowering). I'll drop scr1-min for now.

[dnpetrov-sc]

• fixed new line at end-of-file in RISCVSchedSCR1.td;
• dropped scr1-min (RV32E unsupported).

[craig.topper]

llvm/lib/Target/RISCV/RISCV.td

638

It is queried from the MC layer using something like FeatureBits[RISCV::Feature32Bit].

It’s only there to distinquish mtune CPU names from real CPU names. The mtune CPU names don’t have 32Bit or 64Bit and generate an error if they are used with -mcpu

[jrtc27]

llvm/include/llvm/Support/RISCVTargetParser.def

22

Alphabetise (with the exception of INVALID)?

[craig.topper]

Should the names be prefixed with "syntacore-". I assume there could be an SCR2, etc. in the future?

[anton-afanasyev]

llvm/lib/Target/RISCV/RISCVSchedSCR1.td

14 ↗

(On Diff #480352)

SCR1_CFG_RV32EC_MIN (scr1-min) -- this should be removed from comment as well since patch doesn't cover scr1-min

[dnpetrov-sc]

• Added syntacore prefix

[dnpetrov-sc]

• Fixes

[craig.topper]

LGTM

clang/test/Driver/riscv-cpus.c

 // Check target CPUs are correctly passed.
 
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=rocket-rv32 | FileCheck -check-prefix=MCPU-ROCKET32 %s
 // MCPU-ROCKET32: "-nostdsysteminc" "-target-cpu" "rocket-rv32"
 
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=rocket-rv64 | FileCheck -check-prefix=MCPU-ROCKET64 %s
 // MCPU-ROCKET64: "-nostdsysteminc" "-target-cpu" "rocket-rv64"
 // MCPU-ROCKET64: "-target-feature" "+64bit"
 
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr1-base | FileCheck -check-prefix=MCPU-SYNTACORE-SCR1-BASE %s
+// MCPU-SYNTACORE-SCR1-BASE: "-target-cpu" "syntacore-scr1-base"
+// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "+c" "-target-feature" "-64bit"
+// MCPU-SYNTACORE-SCR1-BASE: "-target-abi" "ilp32"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr1-max | FileCheck -check-prefix=MCPU-SYNTACORE-SCR1-MAX %s
+// MCPU-SYNTACORE-SCR1-MAX: "-target-cpu" "syntacore-scr1-max"
+// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+m" "-target-feature" "+c" "-target-feature" "-64bit"
+// MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
+
 // We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string.
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=native | FileCheck -check-prefix=MCPU-NATIVE %s
 // MCPU-NATIVE-NOT: "-target-cpu" "native"
 
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=rocket-rv32 | FileCheck -check-prefix=MTUNE-ROCKET32 %s
 // MTUNE-ROCKET32: "-tune-cpu" "rocket-rv32"
 
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=rocket-rv64 | FileCheck -check-prefix=MTUNE-ROCKET64 %s
 // MTUNE-ROCKET64: "-tune-cpu" "rocket-rv64"
 
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-base | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-BASE %s
+// MTUNE-SYNTACORE-SCR1-BASE: "-tune-cpu" "syntacore-scr1-base"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-max | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-MAX %s
+// MTUNE-SYNTACORE-SCR1-MAX: "-tune-cpu" "syntacore-scr1-max"
+
 // Check mtune alias CPU has resolved to the right CPU according XLEN.
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck -check-prefix=MTUNE-GENERIC-32 %s
 // MTUNE-GENERIC-32: "-tune-cpu" "generic"
 
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=generic | FileCheck -check-prefix=MTUNE-GENERIC-64 %s
 // MTUNE-GENERIC-64: "-tune-cpu" "generic"
 
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=rocket | FileCheck -check-prefix=MTUNE-ROCKET-32 %s

clang/test/Misc/target-invalid-cpu-note.c

 // BPF-NEXT: note: valid target CPU values are: generic, v1, v2, v3, probe{{$}}
 
 // RUN: not %clang_cc1 -triple avr--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AVR
 // AVR: error: unknown target CPU 'not-a-cpu'
 // AVR-NEXT: note: valid target CPU values are: avr1, at90s1200, attiny11, attiny12, attiny15, attiny28, avr2, at90s2313, at90s2323, at90s2333, at90s2343, attiny22, attiny26, at86rf401, at90s4414, at90s4433, at90s4434, at90s8515, at90c8534, at90s8535, avr25, ata5272, ata6616c, attiny13, attiny13a, attiny2313, attiny2313a, attiny24, attiny24a, attiny4313, attiny44, attiny44a, attiny84, attiny84a, attiny25, attiny45, attiny85, attiny261, attiny261a, attiny441, attiny461, attiny461a, attiny841, attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88, attiny828, avr3, at43usb355, at76c711, avr31, atmega103, at43usb320, avr35, attiny167, at90usb82, at90usb162, ata5505, ata6617c, ata664251, atmega8u2, atmega16u2, atmega32u2, attiny1634, avr4, atmega8, ata6289, atmega8a, ata6285, ata6286, ata6612c, atmega48, atmega48a, atmega48pa, atmega48pb, atmega48p, atmega88, atmega88a, atmega88p, atmega88pa, atmega88pb, atmega8515, atmega8535, atmega8hva, at90pwm1, at90pwm2, at90pwm2b, at90pwm3, at90pwm3b, at90pwm81, avr5, ata5702m322, ata5782, ata5790, ata5790n, ata5791, ata5795, ata5831, ata6613c, ata6614q, ata8210, ata8510, atmega16, atmega16a, atmega161, atmega162, atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a, atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa, atmega168pb, atmega169, atmega169a, atmega169p, atmega169pa, atmega32, atmega32a, atmega323, atmega324a, atmega324p, atmega324pa, atmega324pb, atmega325, atmega325a, atmega325p, atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328, atmega328p, atmega328pb, atmega329, atmega329a, atmega329p, atmega329pa, atmega3290, atmega3290a, atmega3290p, atmega3290pa, atmega406, atmega64, atmega64a, atmega640, atmega644, atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, atmega645p, atmega649, atmega649a, atmega649p, atmega6450, atmega6450a, atmega6450p, atmega6490, atmega6490a, atmega6490p, atmega64rfr2, atmega644rfr2, atmega16hva, atmega16hva2, atmega16hvb, atmega16hvbrevb, atmega32hvb, atmega32hvbrevb, atmega64hve, atmega64hve2, at90can32, at90can64, at90pwm161, at90pwm216, at90pwm316, atmega32c1, atmega64c1, atmega16m1, atmega32m1, atmega64m1, atmega16u4, atmega32u4, atmega32u6, at90usb646, at90usb647, at90scr100, at94k, m3000, avr51, atmega128, atmega128a, atmega1280, atmega1281, atmega1284, atmega1284p, atmega128rfa1, atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286, at90usb1287, avr6, atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2, avrxmega2, atxmega16a4, atxmega16a4u, atxmega16c4, atxmega16d4, atxmega32a4, atxmega32a4u, atxmega32c3, atxmega32c4, atxmega32d3, atxmega32d4, atxmega32e5, atxmega16e5, atxmega8e5, avrxmega4, atxmega64a3, atxmega64a3u, atxmega64a4u, atxmega64b1, atxmega64b3, atxmega64c3, atxmega64d3, atxmega64d4, avrxmega5, atxmega64a1, atxmega64a1u, avrxmega6, atxmega128a3, atxmega128a3u, atxmega128b1, atxmega128b3, atxmega128c3, atxmega128d3, atxmega128d4, atxmega192a3, atxmega192a3u, atxmega192c3, atxmega192d3, atxmega256a3, atxmega256a3u, atxmega256a3b, atxmega256a3bu, atxmega256c3, atxmega256d3, atxmega384c3, atxmega384d3, avrxmega7, atxmega128a1, atxmega128a1u, atxmega128a4u, avrtiny, attiny4, attiny5, attiny9, attiny10, attiny20, attiny40, attiny102, attiny104, avrxmega3, attiny202, attiny402, attiny204, attiny404, attiny804, attiny1604, attiny406, attiny806, attiny1606, attiny807, attiny1607, attiny212, attiny412, attiny214, attiny414, attiny814, attiny1614, attiny416, attiny816, attiny1616, attiny3216, attiny417, attiny817, attiny1617, attiny3217, attiny1624, attiny1626, attiny1627, atmega808, atmega809, atmega1608, atmega1609, atmega3208, atmega3209, atmega4808, atmega4809
 
 // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
 // RISCV32: error: unknown target CPU 'not-a-cpu'
-// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76{{$}}
+// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max{{$}}
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
 // RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, generic, rocket, sifive-7-series{{$}}
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
 // TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, generic, rocket, sifive-7-series{{$}}

llvm/include/llvm/Support/RISCVTargetParser.def

 PROC(SIFIVE_E34, {"sifive-e34"}, FK_NONE, {"rv32imafc"})
 PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})
 PROC(SIFIVE_S21, {"sifive-s21"}, FK_64BIT, {"rv64imac"})
 PROC(SIFIVE_S51, {"sifive-s51"}, FK_64BIT, {"rv64imac"})
 PROC(SIFIVE_S54, {"sifive-s54"}, FK_64BIT, {"rv64gc"})
 PROC(SIFIVE_S76, {"sifive-s76"}, FK_64BIT, {"rv64gc"})
 PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
 PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
+PROC(SYNTACORE_SCR1_BASE, {"syntacore-scr1-base"}, FK_NONE, {"rv32ic"})
+PROC(SYNTACORE_SCR1_MAX, {"syntacore-scr1-max"}, FK_NONE, {"rv32imc"})
 
 #undef PROC
 
 #ifndef TUNE_PROC
 #define TUNE_PROC(ENUM, NAME)
 #endif
 
 TUNE_PROC(GENERIC, "generic")
 TUNE_PROC(ROCKET, "rocket")
 TUNE_PROC(SIFIVE_7, "sifive-7-series")
 
 #undef TUNE_PROC

llvm/lib/Target/RISCV/RISCV.td

 
 include "RISCVSchedule.td"
 include "RISCVRegisterInfo.td"
 include "RISCVCallingConv.td"
 include "RISCVInstrInfo.td"
 include "GISel/RISCVRegisterBanks.td"
 include "RISCVSchedRocket.td"
 include "RISCVSchedSiFive7.td"
+include "RISCVSchedSyntacoreSCR1.td"
 
 //===----------------------------------------------------------------------===//
 // RISC-V processors supported.
 //===----------------------------------------------------------------------===//
 
 def : ProcessorModel<"generic-rv32", NoSchedModel, [Feature32Bit]>;
 def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
 // Support generic for compatibility with other targets. The triple will be used

 def : ProcessorModel<"sifive-u74", SiFive7Model, [Feature64Bit,
                                                   FeatureStdExtM,
                                                   FeatureStdExtA,
                                                   FeatureStdExtF,
                                                   FeatureStdExtD,
                                                   FeatureStdExtC],
                      [TuneSiFive7]>;
 
+def : ProcessorModel<"syntacore-scr1-base", SyntacoreSCR1Model,
+                     [Feature32Bit, FeatureStdExtC],
+                     [TuneNoDefaultUnroll]>;
+
+def : ProcessorModel<"syntacore-scr1-max", SyntacoreSCR1Model,
+                     [Feature32Bit, FeatureStdExtM, FeatureStdExtC],
+                     [TuneNoDefaultUnroll]>;
+
 //===----------------------------------------------------------------------===//
 // Define the RISC-V target.
 //===----------------------------------------------------------------------===//
 
 def RISCVInstrInfo : InstrInfo {
   let guessInstructionProperties = 0;
 }
 

llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td

+//==- RISCVSchedSyntacoreSCR1.td - Syntacore SCR1 Scheduling Definitions --------*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+
+// SCR1: https://github.com/syntacore/scr1
+
+// This model covers SYNTACORE_SCR1_CFG_RV32IMC_MAX configuration (syntacore-scr1-max).
+// SYNTACORE_SCR1_CFG_RV32IC_BASE (syntacore-scr1-base) configuration has essentially
+// same scheduling characteristics.
+
+// SCR1 is single-issue in-order processor
+def SyntacoreSCR1Model : SchedMachineModel {
+  let MicroOpBufferSize = 0;
+  let IssueWidth = 1;
+  let LoadLatency = 2;
+  let MispredictPenalty = 3;
+  let CompleteModel = 0;
+  let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
+                             HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
+                             HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
+                             HasVInstructions];
+}
+
+let SchedModel = SyntacoreSCR1Model in {
+
+let BufferSize = 0 in {
+def SCR1_ALU : ProcResource<1>;
+def SCR1_LSU : ProcResource<1>;
+def SCR1_MUL : ProcResource<1>;
+def SCR1_DIV : ProcResource<1>;
+def SCR1_CFU : ProcResource<1>;
+}
+
+// Branching
+def : WriteRes<WriteJmp, [SCR1_CFU]>;
+def : WriteRes<WriteJal, [SCR1_CFU]>;
+def : WriteRes<WriteJalr, [SCR1_CFU]>;
+def : WriteRes<WriteJmpReg, [SCR1_CFU]>;
+
+// Integer arithmetic and logic
+def : WriteRes<WriteIALU32, [SCR1_ALU]>;
+def : WriteRes<WriteIALU, [SCR1_ALU]>;
+def : WriteRes<WriteShiftImm32, [SCR1_ALU]>;
+def : WriteRes<WriteShiftImm, [SCR1_ALU]>;
+def : WriteRes<WriteShiftReg32, [SCR1_ALU]>;
+def : WriteRes<WriteShiftReg, [SCR1_ALU]>;
+
+// Integer multiplication: single-cycle multiplier in SCR1_CFG_RV32IMC_MAX
+def : WriteRes<WriteIMul, [SCR1_MUL]>;
+def : WriteRes<WriteIMul32, [SCR1_MUL]>;
+
+// Integer division: latency 33, inverse throughput 33
+let Latency = 33, ResourceCycles = [33] in {
+def : WriteRes<WriteIDiv32, [SCR1_DIV]>;
+def : WriteRes<WriteIDiv, [SCR1_DIV]>;
+}
+
+// Load/store instructions on SCR1 have latency 2 and inverse throughput 2
+// (SCR1_CFG_RV32IMC_MAX includes TCM)
+let Latency = 2, ResourceCycles=[2] in {
+// Memory
+def : WriteRes<WriteSTB, [SCR1_LSU]>;
+def : WriteRes<WriteSTH, [SCR1_LSU]>;
+def : WriteRes<WriteSTW, [SCR1_LSU]>;
+def : WriteRes<WriteSTD, [SCR1_LSU]>;
+def : WriteRes<WriteLDB, [SCR1_LSU]>;
+def : WriteRes<WriteLDH, [SCR1_LSU]>;
+def : WriteRes<WriteLDW, [SCR1_LSU]>;
+def : WriteRes<WriteLDD, [SCR1_LSU]>;
+}
+
+let Unsupported = true in {
+// Atomic memory
+def : WriteRes<WriteAtomicW, [SCR1_LSU]>;
+def : WriteRes<WriteAtomicD, [SCR1_LSU]>;
+def : WriteRes<WriteAtomicLDW, [SCR1_LSU]>;
+def : WriteRes<WriteAtomicLDD, [SCR1_LSU]>;
+def : WriteRes<WriteAtomicSTW, [SCR1_LSU]>;
+def : WriteRes<WriteAtomicSTD, [SCR1_LSU]>;
+
+// FP load/store
+def : WriteRes<WriteFST32, [SCR1_LSU]>;
+def : WriteRes<WriteFST64, [SCR1_LSU]>;
+def : WriteRes<WriteFLD32, [SCR1_LSU]>;
+def : WriteRes<WriteFLD64, [SCR1_LSU]>;
+
+// FP instructions
+def : WriteRes<WriteFAdd32, []>;
+def : WriteRes<WriteFSGNJ32, []>;
+def : WriteRes<WriteFMinMax32, []>;
+def : WriteRes<WriteFAdd64, []>;
+def : WriteRes<WriteFSGNJ64, []>;
+def : WriteRes<WriteFMinMax64, []>;
+def : WriteRes<WriteFCvtI32ToF32, []>;
+def : WriteRes<WriteFCvtI32ToF64, []>;
+def : WriteRes<WriteFCvtI64ToF32, []>;
+def : WriteRes<WriteFCvtI64ToF64, []>;
+def : WriteRes<WriteFCvtF32ToI32, []>;
+def : WriteRes<WriteFCvtF32ToI64, []>;
+def : WriteRes<WriteFCvtF64ToI32, []>;
+def : WriteRes<WriteFCvtF64ToI64, []>;
+def : WriteRes<WriteFCvtF32ToF64, []>;
+def : WriteRes<WriteFCvtF64ToF32, []>;
+def : WriteRes<WriteFClass32, []>;
+def : WriteRes<WriteFClass64, []>;
+def : WriteRes<WriteFCmp32, []>;
+def : WriteRes<WriteFCmp64, []>;
+def : WriteRes<WriteFMovF32ToI32, []>;
+def : WriteRes<WriteFMovI32ToF32, []>;
+def : WriteRes<WriteFMovF64ToI64, []>;
+def : WriteRes<WriteFMovI64ToF64, []>;
+def : WriteRes<WriteFMul32, []>;
+def : WriteRes<WriteFMA32, []>;
+def : WriteRes<WriteFMul64, []>;
+def : WriteRes<WriteFMA64, []>;
+def : WriteRes<WriteFDiv32, []>;
+def : WriteRes<WriteFDiv64, []>;
+def : WriteRes<WriteFSqrt32, []>;
+def : WriteRes<WriteFSqrt64, []>;
+
+def : WriteRes<WriteSFB, []>;
+}
+
+// Others
+def : WriteRes<WriteCSR, []>;
+def : WriteRes<WriteNop, []>;
+
+def : InstRW<[WriteIALU], (instrs COPY)>;
+
+//===----------------------------------------------------------------------===//
+// Bypasses (none)
+def : ReadAdvance<ReadJmp, 0>;
+def : ReadAdvance<ReadJalr, 0>;
+def : ReadAdvance<ReadCSR, 0>;
+def : ReadAdvance<ReadStoreData, 0>;
+def : ReadAdvance<ReadMemBase, 0>;
+def : ReadAdvance<ReadIALU, 0>;
+def : ReadAdvance<ReadIALU32, 0>;
+def : ReadAdvance<ReadShiftImm, 0>;
+def : ReadAdvance<ReadShiftImm32, 0>;
+def : ReadAdvance<ReadShiftReg, 0>;
+def : ReadAdvance<ReadShiftReg32, 0>;
+def : ReadAdvance<ReadIDiv, 0>;
+def : ReadAdvance<ReadIDiv32, 0>;
+def : ReadAdvance<ReadIMul, 0>;
+def : ReadAdvance<ReadIMul32, 0>;
+def : ReadAdvance<ReadAtomicWA, 0>;
+def : ReadAdvance<ReadAtomicWD, 0>;
+def : ReadAdvance<ReadAtomicDA, 0>;
+def : ReadAdvance<ReadAtomicDD, 0>;
+def : ReadAdvance<ReadAtomicLDW, 0>;
+def : ReadAdvance<ReadAtomicLDD, 0>;
+def : ReadAdvance<ReadAtomicSTW, 0>;
+def : ReadAdvance<ReadAtomicSTD, 0>;
+def : ReadAdvance<ReadFStoreData, 0>;
+def : ReadAdvance<ReadFMemBase, 0>;
+def : ReadAdvance<ReadFAdd32, 0>;
+def : ReadAdvance<ReadFAdd64, 0>;
+def : ReadAdvance<ReadFMul32, 0>;
+def : ReadAdvance<ReadFMul64, 0>;
+def : ReadAdvance<ReadFMA32, 0>;
+def : ReadAdvance<ReadFMA64, 0>;
+def : ReadAdvance<ReadFDiv32, 0>;
+def : ReadAdvance<ReadFDiv64, 0>;
+def : ReadAdvance<ReadFSqrt32, 0>;
+def : ReadAdvance<ReadFSqrt64, 0>;
+def : ReadAdvance<ReadFCmp32, 0>;
+def : ReadAdvance<ReadFCmp64, 0>;
+def : ReadAdvance<ReadFSGNJ32, 0>;
+def : ReadAdvance<ReadFSGNJ64, 0>;
+def : ReadAdvance<ReadFMinMax32, 0>;
+def : ReadAdvance<ReadFMinMax64, 0>;
+def : ReadAdvance<ReadFCvtF32ToI32, 0>;
+def : ReadAdvance<ReadFCvtF32ToI64, 0>;
+def : ReadAdvance<ReadFCvtF64ToI32, 0>;
+def : ReadAdvance<ReadFCvtF64ToI64, 0>;
+def : ReadAdvance<ReadFCvtI32ToF32, 0>;
+def : ReadAdvance<ReadFCvtI32ToF64, 0>;
+def : ReadAdvance<ReadFCvtI64ToF32, 0>;
+def : ReadAdvance<ReadFCvtI64ToF64, 0>;
+def : ReadAdvance<ReadFCvtF32ToF64, 0>;
+def : ReadAdvance<ReadFCvtF64ToF32, 0>;
+def : ReadAdvance<ReadFMovF32ToI32, 0>;
+def : ReadAdvance<ReadFMovI32ToF32, 0>;
+def : ReadAdvance<ReadFMovF64ToI64, 0>;
+def : ReadAdvance<ReadFMovI64ToF64, 0>;
+def : ReadAdvance<ReadFClass32, 0>;
+def : ReadAdvance<ReadFClass64, 0>;
+def : ReadAdvance<ReadSFB, 0>;
+
+//===----------------------------------------------------------------------===//
+// Unsupported extensions
+defm : UnsupportedSchedV;
+defm : UnsupportedSchedZba;
+defm : UnsupportedSchedZbb;
+defm : UnsupportedSchedZbc;
+defm : UnsupportedSchedZbs;
+defm : UnsupportedSchedZbkb;
+defm : UnsupportedSchedZbkx;
+defm : UnsupportedSchedZfh;
+}