User Details
User Details
- User Since
- Jun 1 2022, 2:32 AM (69 w, 1 d)
Dec 13 2022
Dec 13 2022
dnpetrov-sc updated the diff for D139302: [RISCV] Add Syntacore SCR1 CPU model.
- Fixes
dnpetrov-sc updated the diff for D139302: [RISCV] Add Syntacore SCR1 CPU model.
- Added syntacore prefix
Dec 6 2022
Dec 6 2022
dnpetrov-sc updated the diff for D139302: [RISCV] Add Syntacore SCR1 CPU model.
- fixed new line at end-of-file in RISCVSchedSCR1.td;
- dropped scr1-min (RV32E unsupported).
Dec 5 2022
Dec 5 2022
dnpetrov-sc added inline comments to D139302: [RISCV] Add Syntacore SCR1 CPU model.
dnpetrov-sc requested review of D139302: [RISCV] Add Syntacore SCR1 CPU model.
Nov 18 2022
Nov 18 2022
dnpetrov-sc added a comment to D98101: [RISCV] Enable the LocalStackSlotAllocation pass support.
Jun 16 2022
Jun 16 2022
dnpetrov-sc added a comment to D127842: [RuntimeDyld][RISCV] Minimal riscv64 support.
Jun 15 2022
Jun 15 2022
dnpetrov-sc updated the summary of D127842: [RuntimeDyld][RISCV] Minimal riscv64 support.
dnpetrov-sc requested review of D127842: [RuntimeDyld][RISCV] Minimal riscv64 support.