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[RISCV] Add Syntacore SCR1 CPU model

Authored by dnpetrov-sc on Dec 5 2022, 1:53 AM.



[RISCV] Add Syntacore SCR1 CPU model

SCR1 is available at

'scr1-base' corresponds to SCR1_CFG_RV32IC_BASE,
'scr1-max' corresponds to SCR1_CFG_RV32IMC_MAX.

SCR1_CFG_RV32EC_MIN is RV32EC, which is currently unsupported.

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dnpetrov-sc created this revision.Dec 5 2022, 1:53 AM
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dnpetrov-sc requested review of this revision.Dec 5 2022, 1:53 AM
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craig.topper added inline comments.Dec 5 2022, 3:47 PM

Shouldn't this also need Feature32Bit?

208 ↗(On Diff #480019)

Add new line

dnpetrov-sc added inline comments.Dec 5 2022, 11:47 PM

Now, that's somewhat funny. Indeed, RISCVSubtarget has HasRV32 field, but it is never queried. IsRV32 predicate in is mapped to !Subtarget->is64Bit() in C++ code.

Code generation for RV32E is not implemented yet, though (and would error out in RISCVTargetLowering). I'll drop scr1-min for now.

dnpetrov-sc edited the summary of this revision. (Show Details)
  • fixed new line at end-of-file in;
  • dropped scr1-min (RV32E unsupported).
craig.topper added inline comments.Dec 6 2022, 12:27 AM

It is queried from the MC layer using something like FeatureBits[RISCV::Feature32Bit].

It’s only there to distinquish mtune CPU names from real CPU names. The mtune CPU names don’t have 32Bit or 64Bit and generate an error if they are used with -mcpu

jrtc27 added inline comments.Dec 8 2022, 9:06 AM

Alphabetise (with the exception of INVALID)?

Should the names be prefixed with "syntacore-". I assume there could be an SCR2, etc. in the future?

14 ↗(On Diff #480352)

SCR1_CFG_RV32EC_MIN (scr1-min) -- this should be removed from comment as well since patch doesn't cover scr1-min

dnpetrov-sc marked an inline comment as done.
  • Added syntacore prefix
This revision is now accepted and ready to land.Dec 13 2022, 1:18 PM
This revision was landed with ongoing or failed builds.Dec 14 2022, 12:50 AM
This revision was automatically updated to reflect the committed changes.