[RISCV] Teach RISCVMatInt to prefer li+slli over lui+addi(w) for compressibility.

[craig.topper]

Summary

With C extension, li with a 6 bit immediate followed by slli is 4 bytes.
The lui+addi(w) sequence is at least 6 bytes.

The two sequences probably have similar execution latency. The exception
being if the target supports lui+addi(w) macrofusion.

Since the execution latency is probably the same I didn't restrict
this to C extension.

[jrtc27]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

192

This is confusing, LI is a pseudo implemented using this function but here you mean it to be what C.LI expands to. Though it doesn’t help there’s the LI alias that’s deemed canonical (which I don’t like but came from binutils).

[reames]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

197

I think we could phrase this comparison in terms of getInstSeqCost, and abstract away the details of the compression cost here. It would use a different default for when compression isn't enabled, but not sure we care about that point?

[craig.topper]

Address @jrtc27's comment

I didn't use the getInstSeqCost because I think it would make the code harder to reason about.

[reames]

LGTM

JFYI, Craig and I talked about this one a bit offline. My prior proposal (to use the cost metric) doesn't simplify this code - I tried locally - and Craig has landed some cleanups to the surrounding code which makes it easier to read anyways.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

 //===- RISCVMatInt.cpp - Immediate materialisation -------------*- C++ -*--===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 

 namespace llvm::RISCVMatInt {
 InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
   RISCVMatInt::InstSeq Res;
   generateInstSeqImpl(Val, ActiveFeatures, Res);
 
   // If the low 12 bits are non-zero, the first expansion may end with an ADDI
   // or ADDIW. If there are trailing zeros, try generating a sign extended
   // constant with no trailing zeros and use a final SLLI to restore them.
-  if ((Val & 0xfff) != 0 && (Val & 1) == 0 && Res.size() > 2) {
+  if ((Val & 0xfff) != 0 && (Val & 1) == 0 && Res.size() >= 2) {
     unsigned TrailingZeros = countTrailingZeros((uint64_t)Val);
     int64_t ShiftedVal = Val >> TrailingZeros;
+    // If we can use C.LI+C.SLLI instead of LUI+ADDI(W) prefer that since
+    // its more compressible. But only if LUI+ADDI(W) isn't fusable.
+    // NOTE: We don't check for C extension to minimize differences in generated
+    // code.
+    bool IsShiftedCompressible =
+              isInt<6>(ShiftedVal) && !ActiveFeatures[RISCV::TuneLUIADDIFusion];
     RISCVMatInt::InstSeq TmpSeq;
     generateInstSeqImpl(ShiftedVal, ActiveFeatures, TmpSeq);
     TmpSeq.emplace_back(RISCV::SLLI, TrailingZeros);
 
     // Keep the new sequence if it is an improvement.
-    if (TmpSeq.size() < Res.size())
+    if (TmpSeq.size() < Res.size() || IsShiftedCompressible)
       Res = TmpSeq;
   }
 
   // If the constant is positive we might be able to generate a shifted constant
   // with no leading zeros and use a final SRLI to restore them.
   if (Val > 0 && Res.size() > 2) {
     assert(ActiveFeatures[RISCV::Feature64Bit] &&
            "Expected RV32 to only need 2 instructions");
     unsigned LeadingZeros = countLeadingZeros((uint64_t)Val);
     uint64_t ShiftedVal = (uint64_t)Val << LeadingZeros;

llvm/test/CodeGen/RISCV/calling-conv-half.ll

 ; RV64-LP64ZFHMIN-NEXT:    ret
   %1 = call i32 @callee_half_on_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, half 10.0)
   ret i32 %1
 }
 
 define half @callee_half_ret() nounwind {
 ; RV32I-LABEL: callee_half_ret:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a0, 4
-; RV32I-NEXT:    addi a0, a0, -1024
+; RV32I-NEXT:    li a0, 15
+; RV32I-NEXT:    slli a0, a0, 10
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: callee_half_ret:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a0, 4
-; RV64I-NEXT:    addiw a0, a0, -1024
+; RV64I-NEXT:    li a0, 15
+; RV64I-NEXT:    slli a0, a0, 10
 ; RV64I-NEXT:    ret
 ;
 ; RV32IF-LABEL: callee_half_ret:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    lui a0, 1048564
 ; RV32IF-NEXT:    addi a0, a0, -1024
 ; RV32IF-NEXT:    ret
 ;

llvm/test/CodeGen/RISCV/i32-icmp.ll

; RV32I-NEXT:    ret
   %1 = icmp slt i32 %a, 2047
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @icmp_slt_constant_2048(i32 %a) nounwind {
 ; RV32I-LABEL: icmp_slt_constant_2048:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a1, 1
-; RV32I-NEXT:    addi a1, a1, -2048
+; RV32I-NEXT:    li a1, 1
+; RV32I-NEXT:    slli a1, a1, 11
 ; RV32I-NEXT:    slt a0, a0, a1
 ; RV32I-NEXT:    ret
   %1 = icmp slt i32 %a, 2048
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @icmp_slt_constant_neg_2048(i32 %a) nounwind {
; RV32I-NEXT:    ret
   %1 = icmp sle i32 %a, 2046
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @icmp_sle_constant_2047(i32 %a) nounwind {
 ; RV32I-LABEL: icmp_sle_constant_2047:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a1, 1
-; RV32I-NEXT:    addi a1, a1, -2048
+; RV32I-NEXT:    li a1, 1
+; RV32I-NEXT:    slli a1, a1, 11
 ; RV32I-NEXT:    slt a0, a0, a1
 ; RV32I-NEXT:    ret
   %1 = icmp sle i32 %a, 2047
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @icmp_sle_constant_neg_2049(i32 %a) nounwind {

llvm/test/CodeGen/RISCV/i64-icmp.ll

; RV64I-NEXT:    ret
   %1 = icmp slt i64 %a, 2047
   %2 = zext i1 %1 to i64
   ret i64 %2
 }
 
 define i64 @icmp_slt_constant_2048(i64 %a) nounwind {
 ; RV64I-LABEL: icmp_slt_constant_2048:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 1
-; RV64I-NEXT:    addiw a1, a1, -2048
+; RV64I-NEXT:    li a1, 1
+; RV64I-NEXT:    slli a1, a1, 11
 ; RV64I-NEXT:    slt a0, a0, a1
 ; RV64I-NEXT:    ret
   %1 = icmp slt i64 %a, 2048
   %2 = zext i1 %1 to i64
   ret i64 %2
 }
 
 define i64 @icmp_slt_constant_neg_2048(i64 %a) nounwind {
; RV64I-NEXT:    ret
   %1 = icmp sle i64 %a, 2046
   %2 = zext i1 %1 to i64
   ret i64 %2
 }
 
 define i64 @icmp_sle_constant_2047(i64 %a) nounwind {
 ; RV64I-LABEL: icmp_sle_constant_2047:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 1
-; RV64I-NEXT:    addiw a1, a1, -2048
+; RV64I-NEXT:    li a1, 1
+; RV64I-NEXT:    slli a1, a1, 11
 ; RV64I-NEXT:    slt a0, a0, a1
 ; RV64I-NEXT:    ret
   %1 = icmp sle i64 %a, 2047
   %2 = zext i1 %1 to i64
   ret i64 %2
 }
 
 define i64 @icmp_sle_constant_neg_2049(i64 %a) nounwind {

llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll

 ; FUSION-NEXT:    addi a0, a0, %lo(.L.str)
 ; FUSION-NEXT:    tail bar@plt
   %3 = sitofp i32 %1 to float
   tail call void @bar(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), float %3)
   ret void
 }
 
 declare void @bar(i8*, float)
+
+; Test that we prefer lui+addiw over li+slli.
+define i32 @test_matint() {
+; NOFUSION-LABEL: test_matint:
+; NOFUSION:       # %bb.0:
+; NOFUSION-NEXT:    li a0, 1
+; NOFUSION-NEXT:    slli a0, a0, 11
+; NOFUSION-NEXT:    ret
+;
+; FUSION-LABEL: test_matint:
+; FUSION:       # %bb.0:
+; FUSION-NEXT:    lui a0, 1
+; FUSION-NEXT:    addiw a0, a0, -2048
+; FUSION-NEXT:    ret
+  ret i32 2048
+}

llvm/test/CodeGen/RISCV/mul.ll

 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a1, a0, 8
 ; RV32I-NEXT:    slli a0, a0, 12
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: muli32_p4352:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    lui a1, 1
-; RV32IM-NEXT:    addi a1, a1, 256
+; RV32IM-NEXT:    li a1, 17
+; RV32IM-NEXT:    slli a1, a1, 8
 ; RV32IM-NEXT:    mul a0, a0, a1
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: muli32_p4352:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slliw a1, a0, 8
 ; RV64I-NEXT:    slliw a0, a0, 12
 ; RV64I-NEXT:    addw a0, a0, a1

 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a1, a0, 8
 ; RV32I-NEXT:    slli a0, a0, 12
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: muli32_p3840:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    lui a1, 1
-; RV32IM-NEXT:    addi a1, a1, -256
+; RV32IM-NEXT:    li a1, 15
+; RV32IM-NEXT:    slli a1, a1, 8
 ; RV32IM-NEXT:    mul a0, a0, a1
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: muli32_p3840:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slliw a1, a0, 8
 ; RV64I-NEXT:    slliw a0, a0, 12
 ; RV64I-NEXT:    subw a0, a0, a1

 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a1, a0, 12
 ; RV32I-NEXT:    slli a0, a0, 8
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: muli32_m3840:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    lui a1, 1048575
-; RV32IM-NEXT:    addi a1, a1, 256
+; RV32IM-NEXT:    li a1, -15
+; RV32IM-NEXT:    slli a1, a1, 8
 ; RV32IM-NEXT:    mul a0, a0, a1
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: muli32_m3840:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slliw a1, a0, 12
 ; RV64I-NEXT:    slliw a0, a0, 8
 ; RV64I-NEXT:    subw a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: muli32_m3840:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    slliw a1, a0, 12
 ; RV64IM-NEXT:    slliw a0, a0, 8
 ; RV64IM-NEXT:    subw a0, a0, a1
 ; RV64IM-NEXT:    ret
   %1 = mul i32 %a, -3840
   ret i32 %1
 }
 
 define i32 @muli32_m4352(i32 %a) nounwind {
 ; RV32I-LABEL: muli32_m4352:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a1, 1048575
-; RV32I-NEXT:    addi a1, a1, -256
+; RV32I-NEXT:    li a1, -17
+; RV32I-NEXT:    slli a1, a1, 8
 ; RV32I-NEXT:    tail __mulsi3@plt
 ;
 ; RV32IM-LABEL: muli32_m4352:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    lui a1, 1048575
-; RV32IM-NEXT:    addi a1, a1, -256
+; RV32IM-NEXT:    li a1, -17
+; RV32IM-NEXT:    slli a1, a1, 8
 ; RV32IM-NEXT:    mul a0, a0, a1
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: muli32_m4352:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    lui a1, 1048575
-; RV64I-NEXT:    addiw a1, a1, -256
+; RV64I-NEXT:    li a1, -17
+; RV64I-NEXT:    slli a1, a1, 8
 ; RV64I-NEXT:    call __muldi3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: muli32_m4352:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    lui a1, 1048575
-; RV64IM-NEXT:    addiw a1, a1, -256
+; RV64IM-NEXT:    li a1, -17
+; RV64IM-NEXT:    slli a1, a1, 8
 ; RV64IM-NEXT:    mulw a0, a0, a1
 ; RV64IM-NEXT:    ret
   %1 = mul i32 %a, -4352
   ret i32 %1
 }
 
 define i64 @muli64_p4352(i64 %a) nounwind {
 ; RV32I-LABEL: muli64_p4352:

 ; RV32I-NEXT:    slli a3, a0, 12
 ; RV32I-NEXT:    add a0, a3, a2
 ; RV32I-NEXT:    sltu a2, a0, a3
 ; RV32I-NEXT:    add a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: muli64_p4352:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    lui a2, 1
-; RV32IM-NEXT:    addi a2, a2, 256
+; RV32IM-NEXT:    li a2, 17
+; RV32IM-NEXT:    slli a2, a2, 8
 ; RV32IM-NEXT:    mul a1, a1, a2
 ; RV32IM-NEXT:    mulhu a3, a0, a2
 ; RV32IM-NEXT:    add a1, a3, a1
 ; RV32IM-NEXT:    mul a0, a0, a2
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: muli64_p4352:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a0, 8
 ; RV64I-NEXT:    slli a0, a0, 12
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: muli64_p4352:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    lui a1, 1
-; RV64IM-NEXT:    addiw a1, a1, 256
+; RV64IM-NEXT:    li a1, 17
+; RV64IM-NEXT:    slli a1, a1, 8
 ; RV64IM-NEXT:    mul a0, a0, a1
 ; RV64IM-NEXT:    ret
   %1 = mul i64 %a, 4352
   ret i64 %1
 }
 
 define i64 @muli64_p3840(i64 %a) nounwind {
 ; RV32I-LABEL: muli64_p3840:

 ; RV32I-NEXT:    slli a0, a0, 12
 ; RV32I-NEXT:    sltu a3, a0, a2
 ; RV32I-NEXT:    sub a1, a1, a3
 ; RV32I-NEXT:    sub a0, a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: muli64_p3840:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    lui a2, 1
-; RV32IM-NEXT:    addi a2, a2, -256
+; RV32IM-NEXT:    li a2, 15
+; RV32IM-NEXT:    slli a2, a2, 8
 ; RV32IM-NEXT:    mul a1, a1, a2
 ; RV32IM-NEXT:    mulhu a3, a0, a2
 ; RV32IM-NEXT:    add a1, a3, a1
 ; RV32IM-NEXT:    mul a0, a0, a2
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: muli64_p3840:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a0, 8
 ; RV64I-NEXT:    slli a0, a0, 12
 ; RV64I-NEXT:    sub a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: muli64_p3840:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    lui a1, 1
-; RV64IM-NEXT:    addiw a1, a1, -256
+; RV64IM-NEXT:    li a1, 15
+; RV64IM-NEXT:    slli a1, a1, 8
 ; RV64IM-NEXT:    mul a0, a0, a1
 ; RV64IM-NEXT:    ret
   %1 = mul i64 %a, 3840
   ret i64 %1
 }
 
 define i64 @muli64_m4352(i64 %a) nounwind {
 ; RV32I-LABEL: muli64_m4352:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    lui a2, 1048575
-; RV32I-NEXT:    addi a2, a2, -256
+; RV32I-NEXT:    li a2, -17
+; RV32I-NEXT:    slli a2, a2, 8
 ; RV32I-NEXT:    li a3, -1
 ; RV32I-NEXT:    call __muldi3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: muli64_m4352:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    lui a2, 1048575
-; RV32IM-NEXT:    addi a2, a2, -256
+; RV32IM-NEXT:    li a2, -17
+; RV32IM-NEXT:    slli a2, a2, 8
 ; RV32IM-NEXT:    mul a1, a1, a2
 ; RV32IM-NEXT:    mulhu a3, a0, a2
 ; RV32IM-NEXT:    sub a3, a3, a0
 ; RV32IM-NEXT:    add a1, a3, a1
 ; RV32IM-NEXT:    mul a0, a0, a2
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: muli64_m4352:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 1048575
-; RV64I-NEXT:    addiw a1, a1, -256
+; RV64I-NEXT:    li a1, -17
+; RV64I-NEXT:    slli a1, a1, 8
 ; RV64I-NEXT:    tail __muldi3@plt
 ;
 ; RV64IM-LABEL: muli64_m4352:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    lui a1, 1048575
-; RV64IM-NEXT:    addiw a1, a1, -256
+; RV64IM-NEXT:    li a1, -17
+; RV64IM-NEXT:    slli a1, a1, 8
 ; RV64IM-NEXT:    mul a0, a0, a1
 ; RV64IM-NEXT:    ret
   %1 = mul i64 %a, -4352
   ret i64 %1
 }
 
 define i64 @muli64_m3840(i64 %a) nounwind {
 ; RV32I-LABEL: muli64_m3840:

 ; RV32I-NEXT:    slli a0, a0, 8
 ; RV32I-NEXT:    sltu a3, a0, a2
 ; RV32I-NEXT:    sub a1, a1, a3
 ; RV32I-NEXT:    sub a0, a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: muli64_m3840:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    lui a2, 1048575
-; RV32IM-NEXT:    addi a2, a2, 256
+; RV32IM-NEXT:    li a2, -15
+; RV32IM-NEXT:    slli a2, a2, 8
 ; RV32IM-NEXT:    mul a1, a1, a2
 ; RV32IM-NEXT:    mulhu a3, a0, a2
 ; RV32IM-NEXT:    sub a3, a3, a0
 ; RV32IM-NEXT:    add a1, a3, a1
 ; RV32IM-NEXT:    mul a0, a0, a2
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: muli64_m3840:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a0, 12
 ; RV64I-NEXT:    slli a0, a0, 8
 ; RV64I-NEXT:    sub a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: muli64_m3840:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    lui a1, 1048575
-; RV64IM-NEXT:    addiw a1, a1, 256
+; RV64IM-NEXT:    li a1, -15
+; RV64IM-NEXT:    slli a1, a1, 8
 ; RV64IM-NEXT:    mul a0, a0, a1
 ; RV64IM-NEXT:    ret
   %1 = mul i64 %a, -3840
   ret i64 %1
 }
 
 define i128 @muli128_m3840(i128 %a) nounwind {
 ; RV32I-LABEL: muli128_m3840:

 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    addi sp, sp, -16
 ; RV32IM-NEXT:    sw s0, 12(sp) # 4-byte Folded Spill
 ; RV32IM-NEXT:    sw s1, 8(sp) # 4-byte Folded Spill
 ; RV32IM-NEXT:    lw a2, 12(a1)
 ; RV32IM-NEXT:    lw a3, 8(a1)
 ; RV32IM-NEXT:    lw a4, 0(a1)
 ; RV32IM-NEXT:    lw a1, 4(a1)
-; RV32IM-NEXT:    lui a5, 1048575
-; RV32IM-NEXT:    addi a5, a5, 256
+; RV32IM-NEXT:    li a5, -15
+; RV32IM-NEXT:    slli a5, a5, 8
 ; RV32IM-NEXT:    mulhu a6, a4, a5
 ; RV32IM-NEXT:    mul a7, a1, a5
 ; RV32IM-NEXT:    add a6, a7, a6
 ; RV32IM-NEXT:    sltu a7, a6, a7
 ; RV32IM-NEXT:    mulhu t0, a1, a5
 ; RV32IM-NEXT:    add a7, t0, a7
 ; RV32IM-NEXT:    sub a6, a6, a4
 ; RV32IM-NEXT:    neg t0, a4

 ; RV64I-NEXT:    slli a0, a0, 8
 ; RV64I-NEXT:    sltu a3, a0, a2
 ; RV64I-NEXT:    sub a1, a1, a3
 ; RV64I-NEXT:    sub a0, a0, a2
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: muli128_m3840:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    lui a2, 1048575
-; RV64IM-NEXT:    addiw a2, a2, 256
+; RV64IM-NEXT:    li a2, -15
+; RV64IM-NEXT:    slli a2, a2, 8
 ; RV64IM-NEXT:    mul a1, a1, a2
 ; RV64IM-NEXT:    mulhu a3, a0, a2
 ; RV64IM-NEXT:    sub a3, a3, a0
 ; RV64IM-NEXT:    add a1, a3, a1
 ; RV64IM-NEXT:    mul a0, a0, a2
 ; RV64IM-NEXT:    ret
   %1 = mul i128 %a, -3840
   ret i128 %1

llvm/test/CodeGen/RISCV/pr58511.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
 
 define i32 @f(i1 %0, i32 %1, ptr %2) {
 ; CHECK-LABEL: f:
 ; CHECK:       # %bb.0: # %BB
 ; CHECK-NEXT:    slliw a3, a1, 11
 ; CHECK-NEXT:    slliw a1, a1, 12
 ; CHECK-NEXT:    subw a1, a1, a3
 ; CHECK-NEXT:    andi a0, a0, 1
 ; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    lui a3, 1
-; CHECK-NEXT:    addiw a3, a3, -2048
+; CHECK-NEXT:    li a3, 1
+; CHECK-NEXT:    slli a3, a3, 11
 ; CHECK-NEXT:    or a0, a0, a3
 ; CHECK-NEXT:    sw a1, 0(a2)
 ; CHECK-NEXT:    ret
 BB:
   %I = select i1 %0, i32 -1, i32 0
   %I1 = mul i32 %1, 2048
   %I2 = or i32 2048, %I
   store i32 %I1, ptr %2
   ret i32 %I2
 }
 
 define i32 @g(i1 %0, i32 %1, ptr %2) {
 ; CHECK-LABEL: g:
 ; CHECK:       # %bb.0: # %BB
 ; CHECK-NEXT:    slliw a3, a1, 11
 ; CHECK-NEXT:    slliw a1, a1, 12
 ; CHECK-NEXT:    subw a1, a1, a3
 ; CHECK-NEXT:    andi a0, a0, 1
 ; CHECK-NEXT:    addi a0, a0, -1
-; CHECK-NEXT:    lui a3, 1
-; CHECK-NEXT:    addiw a3, a3, -2048
+; CHECK-NEXT:    li a3, 1
+; CHECK-NEXT:    slli a3, a3, 11
 ; CHECK-NEXT:    or a0, a0, a3
 ; CHECK-NEXT:    sw a1, 0(a2)
 ; CHECK-NEXT:    ret
 BB:
   %I = select i1 %0, i32 0, i32 -1
   %I1 = mul i32 %1, 2048
   %I2 = or i32 2048, %I
   store i32 %I1, ptr %2

 define i32 @i(i1 %0, i32 %1, ptr %2) {
 ; CHECK-LABEL: i:
 ; CHECK:       # %bb.0: # %BB
 ; CHECK-NEXT:    andi a0, a0, 1
 ; CHECK-NEXT:    slliw a3, a1, 11
 ; CHECK-NEXT:    slliw a1, a1, 12
 ; CHECK-NEXT:    subw a1, a1, a3
 ; CHECK-NEXT:    addi a0, a0, -1
-; CHECK-NEXT:    lui a3, 1
-; CHECK-NEXT:    addiw a3, a3, -2048
+; CHECK-NEXT:    li a3, 1
+; CHECK-NEXT:    slli a3, a3, 11
 ; CHECK-NEXT:    and a0, a0, a3
 ; CHECK-NEXT:    sw a1, 0(a2)
 ; CHECK-NEXT:    ret
 BB:
   %I = select i1 %0, i32 0, i32 -1
   %I1 = mul i32 %1, 2048
   %I2 = and i32 2048, %I
   store i32 %I1, ptr %2
   ret i32 %I2
 }

llvm/test/CodeGen/RISCV/rv32zbs.ll

 ; CHECK-NEXT:    ret
   %or = or i32 %a, 1024
   ret i32 %or
 }
 
 define i32 @bseti_i32_11(i32 %a) nounwind {
 ; RV32I-LABEL: bseti_i32_11:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a1, 1
-; RV32I-NEXT:    addi a1, a1, -2048
+; RV32I-NEXT:    li a1, 1
+; RV32I-NEXT:    slli a1, a1, 11
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBS-LABEL: bseti_i32_11:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    bseti a0, a0, 11
 ; RV32ZBS-NEXT:    ret
   %or = or i32 %a, 2048

 ; CHECK-NEXT:    ret
   %xor = xor i32 %a, 1024
   ret i32 %xor
 }
 
 define i32 @binvi_i32_11(i32 %a) nounwind {
 ; RV32I-LABEL: binvi_i32_11:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a1, 1
-; RV32I-NEXT:    addi a1, a1, -2048
+; RV32I-NEXT:    li a1, 1
+; RV32I-NEXT:    slli a1, a1, 11
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBS-LABEL: binvi_i32_11:
 ; RV32ZBS:       # %bb.0:
 ; RV32ZBS-NEXT:    binvi a0, a0, 11
 ; RV32ZBS-NEXT:    ret
   %xor = xor i32 %a, 2048

llvm/test/CodeGen/RISCV/rv64zbs.ll

 ; CHECK-NEXT:    ret
   %or = or i32 %a, 1024
   ret i32 %or
 }
 
 define signext i32 @bseti_i32_11(i32 signext %a) nounwind {
 ; RV64I-LABEL: bseti_i32_11:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 1
-; RV64I-NEXT:    addiw a1, a1, -2048
+; RV64I-NEXT:    li a1, 1
+; RV64I-NEXT:    slli a1, a1, 11
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bseti_i32_11:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bseti a0, a0, 11
 ; RV64ZBS-NEXT:    ret
   %or = or i32 %a, 2048

 ; CHECK-NEXT:    ret
   %or = or i64 %a, 1024
   ret i64 %or
 }
 
 define i64 @bseti_i64_11(i64 %a) nounwind {
 ; RV64I-LABEL: bseti_i64_11:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 1
-; RV64I-NEXT:    addiw a1, a1, -2048
+; RV64I-NEXT:    li a1, 1
+; RV64I-NEXT:    slli a1, a1, 11
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bseti_i64_11:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bseti a0, a0, 11
 ; RV64ZBS-NEXT:    ret
   %or = or i64 %a, 2048

 ; CHECK-NEXT:    ret
   %xor = xor i32 %a, 1024
   ret i32 %xor
 }
 
 define signext i32 @binvi_i32_11(i32 signext %a) nounwind {
 ; RV64I-LABEL: binvi_i32_11:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 1
-; RV64I-NEXT:    addiw a1, a1, -2048
+; RV64I-NEXT:    li a1, 1
+; RV64I-NEXT:    slli a1, a1, 11
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: binvi_i32_11:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    binvi a0, a0, 11
 ; RV64ZBS-NEXT:    ret
   %xor = xor i32 %a, 2048

 ; CHECK-NEXT:    ret
   %xor = xor i64 %a, 1024
   ret i64 %xor
 }
 
 define i64 @binvi_i64_11(i64 %a) nounwind {
 ; RV64I-LABEL: binvi_i64_11:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 1
-; RV64I-NEXT:    addiw a1, a1, -2048
+; RV64I-NEXT:    li a1, 1
+; RV64I-NEXT:    slli a1, a1, 11
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: binvi_i64_11:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    binvi a0, a0, 11
 ; RV64ZBS-NEXT:    ret
   %xor = xor i64 %a, 2048

llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll

 }
 
 ; Architectural max VLEN=64k, so result is "as-if" TC=1024
 define <vscale x 1 x i1> @above_maxvl(ptr %p) {
 ; CHECK-LABEL: above_maxvl:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
 ; CHECK-NEXT:    vid.v v8
-; CHECK-NEXT:    lui a0, 1
-; CHECK-NEXT:    addiw a0, a0, -2048
+; CHECK-NEXT:    li a0, 1
+; CHECK-NEXT:    slli a0, a0, 11
 ; CHECK-NEXT:    vmsltu.vx v0, v8, a0
 ; CHECK-NEXT:    ret
   %mask = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i64(i64 0, i64 2048)
   ret <vscale x 1 x i1> %mask
 }
 
 define <2 x i1> @fv2(ptr %p, i64 %index, i64 %tc) {
 ; CHECK-LABEL: fv2:

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

 ; RV64-NEXT:    vid.v v8
 ; RV64-NEXT:    vadd.vv v8, v8, v8
 ; RV64-NEXT:    vadd.vi v9, v8, 4
 ; RV64-NEXT:    ret
   ret <4 x i64> <i64 0, i64 2, i64 4, i64 6>
 }
 
 define void @buildvec_no_vid_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x i8>* %z2, <4 x i8>* %z3, <4 x i8>* %z4, <4 x i8>* %z5) {
-; RV32-LABEL: buildvec_no_vid_v4i8:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a6, %hi(.LCPI14_0)
-; RV32-NEXT:    addi a6, a6, %lo(.LCPI14_0)
-; RV32-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
-; RV32-NEXT:    vle8.v v8, (a6)
-; RV32-NEXT:    lui a6, %hi(.LCPI14_1)
-; RV32-NEXT:    addi a6, a6, %lo(.LCPI14_1)
-; RV32-NEXT:    vle8.v v9, (a6)
-; RV32-NEXT:    vse8.v v8, (a0)
-; RV32-NEXT:    vse8.v v9, (a1)
-; RV32-NEXT:    lui a0, 1
-; RV32-NEXT:    addi a0, a0, -2048
-; RV32-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; RV32-NEXT:    vmv.v.x v8, a0
-; RV32-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
-; RV32-NEXT:    vse8.v v8, (a2)
-; RV32-NEXT:    li a0, 2047
-; RV32-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; RV32-NEXT:    vmv.v.x v8, a0
-; RV32-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
-; RV32-NEXT:    lui a0, %hi(.LCPI14_2)
-; RV32-NEXT:    addi a0, a0, %lo(.LCPI14_2)
-; RV32-NEXT:    vle8.v v9, (a0)
-; RV32-NEXT:    vse8.v v8, (a3)
-; RV32-NEXT:    vmv.v.i v8, -2
-; RV32-NEXT:    vse8.v v8, (a4)
-; RV32-NEXT:    vse8.v v9, (a5)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: buildvec_no_vid_v4i8:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a6, %hi(.LCPI14_0)
-; RV64-NEXT:    addi a6, a6, %lo(.LCPI14_0)
-; RV64-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
-; RV64-NEXT:    vle8.v v8, (a6)
-; RV64-NEXT:    lui a6, %hi(.LCPI14_1)
-; RV64-NEXT:    addi a6, a6, %lo(.LCPI14_1)
-; RV64-NEXT:    vle8.v v9, (a6)
-; RV64-NEXT:    vse8.v v8, (a0)
-; RV64-NEXT:    vse8.v v9, (a1)
-; RV64-NEXT:    lui a0, 1
-; RV64-NEXT:    addiw a0, a0, -2048
-; RV64-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; RV64-NEXT:    vmv.v.x v8, a0
-; RV64-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
-; RV64-NEXT:    vse8.v v8, (a2)
-; RV64-NEXT:    li a0, 2047
-; RV64-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; RV64-NEXT:    vmv.v.x v8, a0
-; RV64-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
-; RV64-NEXT:    lui a0, %hi(.LCPI14_2)
-; RV64-NEXT:    addi a0, a0, %lo(.LCPI14_2)
-; RV64-NEXT:    vle8.v v9, (a0)
-; RV64-NEXT:    vse8.v v8, (a3)
-; RV64-NEXT:    vmv.v.i v8, -2
-; RV64-NEXT:    vse8.v v8, (a4)
-; RV64-NEXT:    vse8.v v9, (a5)
-; RV64-NEXT:    ret
+; CHECK-LABEL: buildvec_no_vid_v4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a6, %hi(.LCPI14_0)
+; CHECK-NEXT:    addi a6, a6, %lo(.LCPI14_0)
+; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT:    vle8.v v8, (a6)
+; CHECK-NEXT:    lui a6, %hi(.LCPI14_1)
+; CHECK-NEXT:    addi a6, a6, %lo(.LCPI14_1)
+; CHECK-NEXT:    vle8.v v9, (a6)
+; CHECK-NEXT:    vse8.v v8, (a0)
+; CHECK-NEXT:    vse8.v v9, (a1)
+; CHECK-NEXT:    li a0, 1
+; CHECK-NEXT:    slli a0, a0, 11
+; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT:    vse8.v v8, (a2)
+; CHECK-NEXT:    li a0, 2047
+; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT:    lui a0, %hi(.LCPI14_2)
+; CHECK-NEXT:    addi a0, a0, %lo(.LCPI14_2)
+; CHECK-NEXT:    vle8.v v9, (a0)
+; CHECK-NEXT:    vse8.v v8, (a3)
+; CHECK-NEXT:    vmv.v.i v8, -2
+; CHECK-NEXT:    vse8.v v8, (a4)
+; CHECK-NEXT:    vse8.v v9, (a5)
+; CHECK-NEXT:    ret
   store <4 x i8> <i8 1, i8 3, i8 6, i8 7>, <4 x i8>* %z0
   store <4 x i8> <i8 undef, i8 2, i8 5, i8 7>, <4 x i8>* %z1
   store <4 x i8> <i8 0, i8 undef, i8 undef, i8 8>, <4 x i8>* %z2
   store <4 x i8> <i8 -1, i8 undef, i8 undef, i8 7>, <4 x i8>* %z3
   store <4 x i8> <i8 -2, i8 undef, i8 undef, i8 undef>, <4 x i8>* %z4
   store <4 x i8> <i8 -1, i8 -2, i8 -4, i8 -5>, <4 x i8>* %z5
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir

--- |
   ; CHECK-NEXT:    .cfi_offset ra, -8
   ; CHECK-NEXT:    .cfi_offset s0, -16
   ; CHECK-NEXT:    addi s0, sp, 2032
   ; CHECK-NEXT:    .cfi_def_cfa s0, 0
   ; CHECK-NEXT:    addi sp, sp, -272
   ; CHECK-NEXT:    sd a0, 8(sp)
   ; CHECK-NEXT:    csrr a0, vlenb
   ; CHECK-NEXT:    sd a1, 0(sp)
-  ; CHECK-NEXT:    lui a1, 1
-  ; CHECK-NEXT:    addiw a1, a1, -1024
+  ; CHECK-NEXT:    li a1, 3
+  ; CHECK-NEXT:    slli a1, a1, 10
   ; CHECK-NEXT:    mul a0, a0, a1
   ; CHECK-NEXT:    ld a1, 0(sp)
   ; CHECK-NEXT:    sub sp, sp, a0
   ; CHECK-NEXT:    ld a0, 8(sp)
   ; CHECK-NEXT:    andi sp, sp, -128
   ; CHECK-NEXT:    sd a0, 8(sp)
   ; CHECK-NEXT:    addi a0, sp, 2047
   ; CHECK-NEXT:    addi a0, a0, 241

llvm/test/CodeGen/RISCV/rvv/vscale-power-of-two.ll

 ; Maximum VLEN=64k implies Maximum vscale=1024.
 ; TODO: This should fold to 2048
 define i64 @con2048_minus_rem() {
 ; CHECK-LABEL: con2048_minus_rem:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    srli a0, a0, 3
 ; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    lui a1, 1
-; CHECK-NEXT:    addiw a1, a1, -2048
+; CHECK-NEXT:    li a1, 1
+; CHECK-NEXT:    slli a1, a1, 11
 ; CHECK-NEXT:    and a0, a0, a1
 ; CHECK-NEXT:    ret
   %vscale = call i64 @llvm.vscale.i64()
   %urem = urem i64 2048, %vscale
   %VTC = sub i64 2048, %urem
   ret i64 %VTC
 }

llvm/test/MC/RISCV/rv32c-aliases-valid.s

 # CHECK-EXPAND: c.li a0, 1
 li x10, 1
 # CHECK-EXPAND: c.li a0, -1
 li x10, -1
 # CHECK-EXPAND: addi a0, zero, 2047
 li x10, 2047
 # CHECK-EXPAND: addi a0, zero, -2047
 li x10, -2047
-# CHECK-EXPAND: c.lui a1, 1
-# CHECK-EXPAND: addi a1, a1, -2048
+# CHECK-EXPAND: c.li a1, 1
+# CHECK-EXPAND: c.slli a1, 11
 li x11, 2048
 # CHECK-EXPAND: addi a1, zero, -2048
 li x11, -2048
 # CHECK-EXPAND: c.lui a1, 1
 # CHECK-EXPAND: addi a1, a1, -2047
 li x11, 2049
 # CHECK-EXPAND: lui a1, 1048575
 # CHECK-EXPAND: addi a1, a1, 2047

llvm/test/MC/RISCV/rv32i-aliases-valid.s

 # CHECK-ALIAS: li a0, -1
 li x10, -1
 # CHECK-INST: addi a0, zero, 2047
 # CHECK-ALIAS: li a0, 2047
 li x10, 2047
 # CHECK-INST: addi a0, zero, -2047
 # CHECK-ALIAS: li a0, -2047
 li x10, -2047
-# CHECK-EXPAND: lui a1, 1
-# CHECK-EXPAND: addi a1, a1, -2048
+# CHECK-INST: addi a1, zero, 1
+# CHECK-INST: slli a1, a1, 11
+# CHECK-ALIAS: li a1, 1
+# CHECK-ALIAS: slli a1, a1, 11
 li x11, 2048
 # CHECK-INST: addi a1, zero, -2048
 # CHECK-ALIAS: li a1, -2048
 li x11, -2048
 # CHECK-EXPAND: lui a1, 1
 # CHECK-EXPAND: addi a1, a1, -2047
 li x11, 2049
 # CHECK-EXPAND: lui a1, 1048575

llvm/test/MC/RISCV/rv64c-aliases-valid.s

 # CHECK-EXPAND: c.li a0, 1
 li x10, 1
 # CHECK-EXPAND: c.li a0, -1
 li x10, -1
 # CHECK-EXPAND: addi a0, zero, 2047
 li x10, 2047
 # CHECK-EXPAND: addi a0, zero, -2047
 li x10, -2047
-# CHECK-EXPAND: c.lui a1, 1
-# CHECK-EXPAND: addiw a1, a1, -2048
+# CHECK-EXPAND: c.li a1, 1
+# CHECK-EXPAND: c.slli a1, 11
 li x11, 2048
 # CHECK-EXPAND: addi a1, zero, -2048
 li x11, -2048
 # CHECK-EXPAND: c.lui a1, 1
 # CHECK-EXPAND: addiw a1, a1, -2047
 li x11, 2049
 # CHECK-EXPAND: c.lui a1, 1048575
 # CHECK-EXPAND: addiw a1, a1, 2047

llvm/test/MC/RISCV/rv64i-aliases-valid.s

 # CHECK-ALIAS: li a0, -1
 li x10, -1
 # CHECK-INST: addi a0, zero, 2047
 # CHECK-ALIAS: li a0, 2047
 li x10, 2047
 # CHECK-INST: addi a0, zero, -2047
 # CHECK-ALIAS: li a0, -2047
 li x10, -2047
-# CHECK-EXPAND: lui a1, 1
-# CHECK-EXPAND: addiw a1, a1, -2048
+# CHECK-INST: addi a1, zero, 1
+# CHECK-INST: slli a1, a1, 11
+# CHECK-ALIAS: li a1, 1
+# CHECK-ALIAS: slli a1, a1, 11
 li x11, 2048
 # CHECK-INST: addi a1, zero, -2048
 # CHECK-ALIAS: li a1, -2048
 li x11, -2048
 # CHECK-EXPAND: lui a1, 1
 # CHECK-EXPAND: addiw a1, a1, -2047
 li x11, 2049
 # CHECK-EXPAND: lui a1, 1048575