[X86] AMD Zen 4 Initial enablement

[GGanesh]

Summary

This patch has the initial skeleton that enables AMD znver4!

AMD znver4 belongs to Family 19h with model numbers as below
Models 0x10 to 0x1f
Models 0x60 to 0x74
Models 0x78 to 0x7b
Models 0xA0 to 0xAf

The patch

1. Includes ISAs that already have target descriptions are added.
2. Uses no scheduler model as of now. (We have an update to this)
3. Updates few tests as per the initial enablement.
4. ISAs that are added are

avx512f,
avx512dq,
avx512ifma,
avx512cd,
avx512bw,
avx512vl,
avx512_bf16,
avx512vbmi,
avx512vbmi2,
avx512vl,
avx512_vnni,
avx512_bitalg,
avx512_vpopcntdq/vl

[RKSimon]

Thank you @GGanesh I thought you'd forgotten about LLVM :)

Please add znver4 test coverage to:

llvm/test/CodeGen/X86/cpus-amd.ll
llvm/test/CodeGen/X86/slow-unaligned-mem.ll

llvm/lib/Target/X86/X86.td

1619

This might sound strange - but its probably better to use either the IceLake or SkylakeServer model initially - as they have AVX512 instruction coverage, the znver3 model will assert in llvm-mca etc when it encounters an unsupported instruction (any of the Z sched classes).

[RKSimon]

@GGanesh reverse-ping

llvm/lib/Target/X86/X86.td

1619

If the use of an Intel model isn't acceptable, using the Proc<> macro (no model) would be the most straightforward - but if you wish to use the znver3 model as a stopgap then I don't want to stop you, just bear in mind that it will cause breaks, particularly where the models are used for codegen analysis etc.

[GGanesh]

In D139073#3995741, @RKSimon wrote:

@GGanesh reverse-ping

@RKSimon Thanks a lot! We were trying to get the libpfm patch posted and subsequently enabling the zen4 scheduler model. Probably a week or two from there. The intel model isn't approved for obvious reasons. Yes I will post a stopgap patch!

[GGanesh]

Update to use 'no' processor model.
Fixed the below tests
tools/llvm-mca/X86/cpus.s
tools/llvm-mca/X86/read-after-ld-1.s
tools/llvm-mca/X86/register-file-statistics.s
tools/llvm-mca/X86/scheduler-queue-usage.s

Addressed comments from @RKSimon

[RKSimon]

Thanks @GGanesh - LGTM with one minor - the orphan ZNVER4 checks from the llvm-mca tests need removing

[GGanesh]

In D139073#3997418, @RKSimon wrote:

Thanks @GGanesh - LGTM with one minor - the orphan ZNVER4 checks from the llvm-mca tests need removing

Thank you! I left them intentionally as this is a stop-gap patch. Agreed! Will remove them.

[GGanesh]

Fixed the tests

tools/llvm-mca/X86/cpus.s
tools/llvm-mca/X86/read-after-ld-1.s
tools/llvm-mca/X86/register-file-statistics.s
tools/llvm-mca/X86/scheduler-queue-usage.s

[RKSimon]

cheers

clang/lib/Basic/Targets/X86.cpp

case CK_ZNVER1:
     defineCPUMacros(Builder, "znver1");
     break;
   case CK_ZNVER2:
     defineCPUMacros(Builder, "znver2");
     break;
   case CK_ZNVER3:
     defineCPUMacros(Builder, "znver3");
     break;
+  case CK_ZNVER4:
+    defineCPUMacros(Builder, "znver4");
+    break;
   case CK_Geode:
     defineCPUMacros(Builder, "geode");
     break;
   }
 
   // Target properties.
   Builder.defineMacro("__REGISTER_PREFIX__", "");
 
switch (CPU) {
     case CK_BDVER1:
     case CK_BDVER2:
     case CK_BDVER3:
     case CK_BDVER4:
     // Zen
     case CK_ZNVER1:
     case CK_ZNVER2:
     case CK_ZNVER3:
+    case CK_ZNVER4:
     // Deprecated
     case CK_x86_64:
     case CK_x86_64_v2:
     case CK_x86_64_v3:
     case CK_x86_64_v4:
     case CK_Yonah:
     case CK_Penryn:
     case CK_Core2:

clang/test/CodeGen/target-builtin-noerror.c

void verifycpustrings(void) {
   (void)__builtin_cpu_is("slm");
   (void)__builtin_cpu_is("tigerlake");
   (void)__builtin_cpu_is("sapphirerapids");
   (void)__builtin_cpu_is("tremont");
   (void)__builtin_cpu_is("westmere");
   (void)__builtin_cpu_is("znver1");
   (void)__builtin_cpu_is("znver2");
   (void)__builtin_cpu_is("znver3");
+  (void)__builtin_cpu_is("znver4");
 }

clang/test/Driver/x86-march.c

 //
 // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=znver2 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=znver2
 // znver2: "-target-cpu" "znver2"
 //
 // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=znver3 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=znver3
 // znver3: "-target-cpu" "znver3"
+//
+// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=znver4 2>&1 \
+// RUN:   | FileCheck %s -check-prefix=znver4
+// znver4: "-target-cpu" "znver4"
 
 // RUN: %clang -target x86_64 -c -### %s -march=x86-64 2>&1 | FileCheck %s --check-prefix=x86-64
 // x86-64: "-target-cpu" "x86-64"
 // RUN: %clang -target x86_64 -c -### %s -march=x86-64-v2 2>&1 | FileCheck %s --check-prefix=x86-64-v2
 // x86-64-v2: "-target-cpu" "x86-64-v2"
 // RUN: %clang -target x86_64 -c -### %s -march=x86-64-v3 2>&1 | FileCheck %s --check-prefix=x86-64-v3
 // x86-64-v3: "-target-cpu" "x86-64-v3"
 // RUN: %clang -target x86_64 -c -### %s -march=x86-64-v4 2>&1 | FileCheck %s --check-prefix=x86-64-v4
 // x86-64-v4: "-target-cpu" "x86-64-v4"

clang/test/Frontend/x86-target-cpu.c

 // RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu bdver2 -verify %s
 // RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu bdver3 -verify %s
 // RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu bdver4 -verify %s
 // RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu btver1 -verify %s
 // RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu btver2 -verify %s
 // RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver1 -verify %s
 // RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver2 -verify %s
 // RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver3 -verify %s
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver4 -verify %s
 //
 // expected-no-diagnostics

clang/test/Misc/target-invalid-cpu-note.c

 // Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if there is anything extra in the output.
 // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix ARM
 // ARM: error: unknown target CPU 'not-a-cpu'
 // ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, cortex-r52, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, cortex-m35p, cortex-m55, cortex-m85, cortex-a32, cortex-a35, cortex-a53, cortex-a55, cortex-a57, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-x1, cortex-x1c, neoverse-n1, neoverse-n2, neoverse-v1, cyclone, exynos-m3, exynos-m4, exynos-m5, kryo, iwmmxt, xscale, swift{{$}}
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
 // AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, grace{{$}}
 
 // RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64
 // TUNE_AARCH64: error: unknown target CPU 'not-a-cpu'
 // TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16,  apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, grace{{$}}
 
 // RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86
 // X86: error: unknown target CPU 'not-a-cpu'
-// X86-NEXT: note: valid target CPU values are: i386, i486, winchip-c6, winchip2, c3, i586, pentium, pentium-mmx, pentiumpro, i686, pentium2, pentium3, pentium3m, pentium-m, c3-2, yonah, pentium4, pentium4m, prescott, nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, raptorlake, meteorlake, sierraforest, grandridge, graniterapids, knl, knm, lakemont, k6, k6-2, k6-3, athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, x86-64, x86-64-v2, x86-64-v3, x86-64-v4, geode{{$}}
+// X86-NEXT: note: valid target CPU values are: i386, i486, winchip-c6, winchip2, c3, i586, pentium, pentium-mmx, pentiumpro, i686, pentium2, pentium3, pentium3m, pentium-m, c3-2, yonah, pentium4, pentium4m, prescott, nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, raptorlake, meteorlake, sierraforest, grandridge, graniterapids, knl, knm, lakemont, k6, k6-2, k6-3, athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, znver4, x86-64, x86-64-v2, x86-64-v3, x86-64-v4, geode{{$}}
 
 // RUN: not %clang_cc1 -triple x86_64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86_64
 // X86_64: error: unknown target CPU 'not-a-cpu'
-// X86_64-NEXT: note: valid target CPU values are: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, raptorlake, meteorlake, sierraforest, grandridge, graniterapids, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, x86-64, x86-64-v2, x86-64-v3, x86-64-v4{{$}}
+// X86_64-NEXT: note: valid target CPU values are: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, raptorlake, meteorlake, sierraforest, grandridge, graniterapids, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, znver4, x86-64, x86-64-v2, x86-64-v3, x86-64-v4{{$}}
 
 // RUN: not %clang_cc1 -triple i386--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_X86
 // TUNE_X86: error: unknown target CPU 'not-a-cpu'
-// TUNE_X86-NEXT: note: valid target CPU values are: i386, i486, winchip-c6, winchip2, c3, i586, pentium, pentium-mmx, pentiumpro, i686, pentium2, pentium3, pentium3m, pentium-m, c3-2, yonah, pentium4, pentium4m, prescott, nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, raptorlake, meteorlake, sierraforest, grandridge, graniterapids, knl, knm, lakemont, k6, k6-2, k6-3, athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, x86-64, geode{{$}}
+// TUNE_X86-NEXT: note: valid target CPU values are: i386, i486, winchip-c6, winchip2, c3, i586, pentium, pentium-mmx, pentiumpro, i686, pentium2, pentium3, pentium3m, pentium-m, c3-2, yonah, pentium4, pentium4m, prescott, nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, raptorlake, meteorlake, sierraforest, grandridge, graniterapids, knl, knm, lakemont, k6, k6-2, k6-3, athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, znver4, x86-64, geode{{$}}
 
 // RUN: not %clang_cc1 -triple x86_64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_X86_64
 // TUNE_X86_64: error: unknown target CPU 'not-a-cpu'
-// TUNE_X86_64-NEXT: note: valid target CPU values are: i386, i486, winchip-c6, winchip2, c3, i586, pentium, pentium-mmx, pentiumpro, i686, pentium2, pentium3, pentium3m, pentium-m, c3-2, yonah, pentium4, pentium4m, prescott, nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, raptorlake, meteorlake, sierraforest, grandridge, graniterapids, knl, knm, lakemont, k6, k6-2, k6-3, athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, x86-64, geode{{$}}
+// TUNE_X86_64-NEXT: note: valid target CPU values are: i386, i486, winchip-c6, winchip2, c3, i586, pentium, pentium-mmx, pentiumpro, i686, pentium2, pentium3, pentium3m, pentium-m, c3-2, yonah, pentium4, pentium4m, prescott, nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, raptorlake, meteorlake, sierraforest, grandridge, graniterapids, knl, knm, lakemont, k6, k6-2, k6-3, athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, znver4, x86-64, geode{{$}}
 
 // RUN: not %clang_cc1 -triple nvptx--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix NVPTX
 // NVPTX: error: unknown target CPU 'not-a-cpu'
 // NVPTX-NEXT: note: valid target CPU values are: sm_20, sm_21, sm_30, sm_32, sm_35, sm_37, sm_50, sm_52, sm_53, sm_60, sm_61, sm_62, sm_70, sm_72, sm_75, sm_80, sm_86, sm_87, sm_89, sm_90, gfx600, gfx601, gfx602, gfx700, gfx701, gfx702, gfx703, gfx704, gfx705, gfx801, gfx802, gfx803, gfx805, gfx810, gfx900, gfx902, gfx904, gfx906, gfx908, gfx909, gfx90a, gfx90c, gfx940, gfx1010, gfx1011, gfx1012, gfx1013, gfx1030, gfx1031, gfx1032, gfx1033, gfx1034, gfx1035, gfx1036, gfx1100, gfx1101, gfx1102, gfx1103{{$}}
 
 // RUN: not %clang_cc1 -triple r600--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix R600
 // R600: error: unknown target CPU 'not-a-cpu'
 // R600-NEXT: note: valid target CPU values are: r600, rv630, rv635, r630, rs780, rs880, rv610, rv620, rv670, rv710, rv730, rv740, rv770, cedar, palm, cypress, hemlock, juniper, redwood, sumo, sumo2, barts, caicos, aruba, cayman, turks{{$}}

clang/test/Preprocessor/predefined-arch-macros.c

 // CHECK_ZNVER3_M64: #define __amd64 1
 // CHECK_ZNVER3_M64: #define __amd64__ 1
 // CHECK_ZNVER3_M64: #define __tune_znver3__ 1
 // CHECK_ZNVER3_M64: #define __x86_64 1
 // CHECK_ZNVER3_M64: #define __x86_64__ 1
 // CHECK_ZNVER3_M64: #define __znver3 1
 // CHECK_ZNVER3_M64: #define __znver3__ 1
 
+// RUN: %clang -march=znver4 -m32 -E -dM %s -o - 2>&1 \
+// RUN:     -target i386-unknown-linux \
+// RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER4_M32
+// CHECK_ZNVER4_M32-NOT: #define __3dNOW_A__ 1
+// CHECK_ZNVER4_M32-NOT: #define __3dNOW__ 1
+// CHECK_ZNVER4_M32: #define __ADX__ 1
+// CHECK_ZNVER4_M32: #define __AES__ 1
+// CHECK_ZNVER4_M32: #define __AVX2__ 1
+// CHECK_ZNVER4_M32: #define __AVX512BF16__ 1
+// CHECK_ZNVER4_M32: #define __AVX512BITALG__ 1
+// CHECK_ZNVER4_M32: #define __AVX512BW__ 1
+// CHECK_ZNVER4_M32: #define __AVX512CD__ 1
+// CHECK_ZNVER4_M32: #define __AVX512DQ__ 1
+// CHECK_ZNVER4_M32: #define __AVX512F__ 1
+// CHECK_ZNVER4_M32: #define __AVX512IFMA__ 1
+// CHECK_ZNVER4_M32: #define __AVX512VBMI2__ 1
+// CHECK_ZNVER4_M32: #define __AVX512VBMI__ 1
+// CHECK_ZNVER4_M32: #define __AVX512VL__ 1
+// CHECK_ZNVER4_M32: #define __AVX512VNNI__ 1
+// CHECK_ZNVER4_M32: #define __AVX512VPOPCNTDQ__ 1
+// CHECK_ZNVER4_M32: #define __AVX__ 1
+// CHECK_ZNVER4_M32: #define __BMI2__ 1
+// CHECK_ZNVER4_M32: #define __BMI__ 1
+// CHECK_ZNVER4_M32: #define __CLFLUSHOPT__ 1
+// CHECK_ZNVER4_M32: #define __CLWB__ 1
+// CHECK_ZNVER4_M32: #define __CLZERO__ 1
+// CHECK_ZNVER4_M32: #define __F16C__ 1
+// CHECK_ZNVER4_M32-NOT: #define __FMA4__ 1
+// CHECK_ZNVER4_M32: #define __FMA__ 1
+// CHECK_ZNVER4_M32: #define __FSGSBASE__ 1
+// CHECK_ZNVER4_M32: #define __GFNI__ 1
+// CHECK_ZNVER4_M32: #define __LZCNT__ 1
+// CHECK_ZNVER4_M32: #define __MMX__ 1
+// CHECK_ZNVER4_M32: #define __PCLMUL__ 1
+// CHECK_ZNVER4_M32: #define __PKU__ 1
+// CHECK_ZNVER4_M32: #define __POPCNT__ 1
+// CHECK_ZNVER4_M32: #define __PRFCHW__ 1
+// CHECK_ZNVER4_M32: #define __RDPID__ 1
+// CHECK_ZNVER4_M32: #define __RDPRU__ 1
+// CHECK_ZNVER4_M32: #define __RDRND__ 1
+// CHECK_ZNVER4_M32: #define __RDSEED__ 1
+// CHECK_ZNVER4_M32: #define __SHA__ 1
+// CHECK_ZNVER4_M32: #define __SSE2_MATH__ 1
+// CHECK_ZNVER4_M32: #define __SSE2__ 1
+// CHECK_ZNVER4_M32: #define __SSE3__ 1
+// CHECK_ZNVER4_M32: #define __SSE4A__ 1
+// CHECK_ZNVER4_M32: #define __SSE4_1__ 1
+// CHECK_ZNVER4_M32: #define __SSE4_2__ 1
+// CHECK_ZNVER4_M32: #define __SSE_MATH__ 1
+// CHECK_ZNVER4_M32: #define __SSE__ 1
+// CHECK_ZNVER4_M32: #define __SSSE3__ 1
+// CHECK_ZNVER4_M32-NOT: #define __TBM__ 1
+// CHECK_ZNVER4_M32: #define __WBNOINVD__ 1
+// CHECK_ZNVER4_M32-NOT: #define __XOP__ 1
+// CHECK_ZNVER4_M32: #define __XSAVEC__ 1
+// CHECK_ZNVER4_M32: #define __XSAVEOPT__ 1
+// CHECK_ZNVER4_M32: #define __XSAVES__ 1
+// CHECK_ZNVER4_M32: #define __XSAVE__ 1
+// CHECK_ZNVER4_M32: #define __i386 1
+// CHECK_ZNVER4_M32: #define __i386__ 1
+// CHECK_ZNVER4_M32: #define __tune_znver4__ 1
+// CHECK_ZNVER4_M32: #define __znver4 1
+// CHECK_ZNVER4_M32: #define __znver4__ 1
+
+// RUN: %clang -march=znver4 -m64 -E -dM %s -o - 2>&1 \
+// RUN:     -target i386-unknown-linux \
+// RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER4_M64
+// CHECK_ZNVER4_M64-NOT: #define __3dNOW_A__ 1
+// CHECK_ZNVER4_M64-NOT: #define __3dNOW__ 1
+// CHECK_ZNVER4_M64: #define __ADX__ 1
+// CHECK_ZNVER4_M64: #define __AES__ 1
+// CHECK_ZNVER4_M64: #define __AVX2__ 1
+// CHECK_ZNVER4_M64: #define __AVX512BF16__ 1
+// CHECK_ZNVER4_M64: #define __AVX512BITALG__ 1
+// CHECK_ZNVER4_M64: #define __AVX512BW__ 1
+// CHECK_ZNVER4_M64: #define __AVX512CD__ 1
+// CHECK_ZNVER4_M64: #define __AVX512DQ__ 1
+// CHECK_ZNVER4_M64: #define __AVX512F__ 1
+// CHECK_ZNVER4_M64: #define __AVX512IFMA__ 1
+// CHECK_ZNVER4_M64: #define __AVX512VBMI2__ 1
+// CHECK_ZNVER4_M64: #define __AVX512VBMI__ 1
+// CHECK_ZNVER4_M64: #define __AVX512VL__ 1
+// CHECK_ZNVER4_M64: #define __AVX512VNNI__ 1
+// CHECK_ZNVER4_M64: #define __AVX512VPOPCNTDQ__ 1
+// CHECK_ZNVER4_M64: #define __AVX__ 1
+// CHECK_ZNVER4_M64: #define __BMI2__ 1
+// CHECK_ZNVER4_M64: #define __BMI__ 1
+// CHECK_ZNVER4_M64: #define __CLFLUSHOPT__ 1
+// CHECK_ZNVER4_M64: #define __CLWB__ 1
+// CHECK_ZNVER4_M64: #define __CLZERO__ 1
+// CHECK_ZNVER4_M64: #define __F16C__ 1
+// CHECK_ZNVER4_M64-NOT: #define __FMA4__ 1
+// CHECK_ZNVER4_M64: #define __FMA__ 1
+// CHECK_ZNVER4_M64: #define __FSGSBASE__ 1
+// CHECK_ZNVER4_M64: #define __GFNI__ 1
+// CHECK_ZNVER4_M64: #define __LZCNT__ 1
+// CHECK_ZNVER4_M64: #define __MMX__ 1
+// CHECK_ZNVER4_M64: #define __PCLMUL__ 1
+// CHECK_ZNVER4_M64: #define __PKU__ 1
+// CHECK_ZNVER4_M64: #define __POPCNT__ 1
+// CHECK_ZNVER4_M64: #define __PRFCHW__ 1
+// CHECK_ZNVER4_M64: #define __RDPID__ 1
+// CHECK_ZNVER4_M64: #define __RDPRU__ 1
+// CHECK_ZNVER4_M64: #define __RDRND__ 1
+// CHECK_ZNVER4_M64: #define __RDSEED__ 1
+// CHECK_ZNVER4_M64: #define __SHA__ 1
+// CHECK_ZNVER4_M64: #define __SSE2_MATH__ 1
+// CHECK_ZNVER4_M64: #define __SSE2__ 1
+// CHECK_ZNVER4_M64: #define __SSE3__ 1
+// CHECK_ZNVER4_M64: #define __SSE4A__ 1
+// CHECK_ZNVER4_M64: #define __SSE4_1__ 1
+// CHECK_ZNVER4_M64: #define __SSE4_2__ 1
+// CHECK_ZNVER4_M64: #define __SSE_MATH__ 1
+// CHECK_ZNVER4_M64: #define __SSE__ 1
+// CHECK_ZNVER4_M64: #define __SSSE3__ 1
+// CHECK_ZNVER4_M64-NOT: #define __TBM__ 1
+// CHECK_ZNVER4_M64: #define __VAES__ 1
+// CHECK_ZNVER4_M64: #define __VPCLMULQDQ__ 1
+// CHECK_ZNVER4_M64: #define __WBNOINVD__ 1
+// CHECK_ZNVER4_M64-NOT: #define __XOP__ 1
+// CHECK_ZNVER4_M64: #define __XSAVEC__ 1
+// CHECK_ZNVER4_M64: #define __XSAVEOPT__ 1
+// CHECK_ZNVER4_M64: #define __XSAVES__ 1
+// CHECK_ZNVER4_M64: #define __XSAVE__ 1
+// CHECK_ZNVER4_M64: #define __amd64 1
+// CHECK_ZNVER4_M64: #define __amd64__ 1
+// CHECK_ZNVER4_M64: #define __tune_znver4__ 1
+// CHECK_ZNVER4_M64: #define __x86_64 1
+// CHECK_ZNVER4_M64: #define __x86_64__ 1
+// CHECK_ZNVER4_M64: #define __znver4 1
+// CHECK_ZNVER4_M64: #define __znver4__ 1
+
 // End X86/GCC/Linux tests ------------------
 
 // Begin PPC/GCC/Linux tests ----------------
 // Check that VSX also turns on altivec.
 // RUN: %clang -mvsx -E -dM %s -o - 2>&1 \
 // RUN:     -target powerpc-unknown-linux \
 // RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_VSX_M32
 // CHECK_PPC_VSX_M32: #define __ALTIVEC__ 1

compiler-rt/lib/builtins/cpu_model.c

if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x5f)) {
       // Family 19h Models 00h-0Fh - Zen3
       // Family 19h Models 20h-2Fh - Zen3
       // Family 19h Models 30h-3Fh - Zen3
       // Family 19h Models 40h-4Fh - Zen3+
       // Family 19h Models 50h-5Fh - Zen3+
       *Subtype = AMDFAM19H_ZNVER3;
       break;
     }
+    if ((Model >= 0x10 && Model <= 0x1f) ||
+        (Model >= 0x60 && Model <= 0x74) ||
+        (Model >= 0x78 && Model <= 0x7b) ||
+        (Model >= 0xA0 && Model <= 0xAf)) {
+      CPU = "znver4";
+      *Subtype = AMDFAM19H_ZNVER4;
+      break; //  "znver4"
+    }
     break;
   default:
     break; // Unknown AMD CPU.
   }
 
   return CPU;
 }
 

llvm/include/llvm/Support/X86TargetParser.h

enum CPUKind {
   CK_BTVER2,
   CK_BDVER1,
   CK_BDVER2,
   CK_BDVER3,
   CK_BDVER4,
   CK_ZNVER1,
   CK_ZNVER2,
   CK_ZNVER3,
+  CK_ZNVER4,
   CK_x86_64,
   CK_x86_64_v2,
   CK_x86_64_v3,
   CK_x86_64_v4,
   CK_Geode,
 };
 
 /// Parse \p CPU string into a CPUKind. Will only accept 64-bit capable CPUs if

llvm/lib/Support/Host.cpp

if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x5f)) {
       // Family 19h Models 00h-0Fh - Zen3
       // Family 19h Models 20h-2Fh - Zen3
       // Family 19h Models 30h-3Fh - Zen3
       // Family 19h Models 40h-4Fh - Zen3+
       // Family 19h Models 50h-5Fh - Zen3+
       *Subtype = X86::AMDFAM19H_ZNVER3;
       break;
     }
-    break;
+    if ((Model >= 0x10 && Model <= 0x1f) ||
+        (Model >= 0x60 && Model <= 0x74) ||
+        (Model >= 0x78 && Model <= 0x7b) ||
+        (Model >= 0xA0 && Model <= 0xAf)) {
+      CPU = "znver4";
+      *Subtype = X86::AMDFAM19H_ZNVER4;
+      break; //  "znver4"
+    }
+    break; // family 19h 
   default:
     break; // Unknown AMD CPU.
   }
 
   return CPU;
 }
 
 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,

llvm/lib/Support/X86TargetParser.cpp

constexpr FeatureBitset FeaturesZNVER1 =
     FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
     FeatureXSAVEOPT | FeatureXSAVES;
 constexpr FeatureBitset FeaturesZNVER2 = FeaturesZNVER1 | FeatureCLWB |
                                          FeatureRDPID | FeatureRDPRU |
                                          FeatureWBNOINVD;
 static constexpr FeatureBitset FeaturesZNVER3 = FeaturesZNVER2 |
                                                 FeatureINVPCID | FeaturePKU |
                                                 FeatureVAES | FeatureVPCLMULQDQ;
+static constexpr FeatureBitset FeaturesZNVER4 =
+    FeaturesZNVER3 | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
+    FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
+    FeatureAVX512VBMI2 | FeatureAVX512VNNI | FeatureAVX512BITALG |
+    FeatureAVX512VPOPCNTDQ | FeatureAVX512BF16 | FeatureGFNI |
+    FeatureSHSTK;
 
 constexpr ProcInfo Processors[] = {
   // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
   { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B },
   // i386-generation processors.
   { {"i386"}, CK_i386, ~0U, FeatureX87 },
   // i486-generation processors.
   { {"i486"}, CK_i486, ~0U, FeatureX87 },
constexpr ProcInfo Processors[] = {
   { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 },
   { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 },
   { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 },
   { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 },
   // Zen architecture processors.
   { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 },
   { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 },
   { {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3 },
+  { {"znver4"}, CK_ZNVER4, FEATURE_AVX512VBMI2, FeaturesZNVER4 },
   // Generic 64-bit processor.
   { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 },
   { {"x86-64-v2"}, CK_x86_64_v2, ~0U, FeaturesX86_64_V2 },
   { {"x86-64-v3"}, CK_x86_64_v3, ~0U, FeaturesX86_64_V3 },
   { {"x86-64-v4"}, CK_x86_64_v4, ~0U, FeaturesX86_64_V4 },
   // Geode processors.
   { {"geode"}, CK_Geode, ~0U, FeaturesGeode },
 };

llvm/lib/Target/X86/X86.td

list<SubtargetFeature> ZN3AdditionalFeatures = [FeatureFSRM,
                                                   FeaturePKU,
                                                   FeatureVAES,
                                                   FeatureVPCLMULQDQ];
   list<SubtargetFeature> ZN3AdditionalTuning = [TuningMacroFusion];
   list<SubtargetFeature> ZN3Tuning =
     !listconcat(ZN2Tuning, ZN3AdditionalTuning);
   list<SubtargetFeature> ZN3Features =
     !listconcat(ZN2Features, ZN3AdditionalFeatures);
+  list<SubtargetFeature> ZN4Tuning = ZN3Tuning;
+  list<SubtargetFeature> ZN4AdditionalFeatures = [FeatureAVX512,
+                                                  FeatureCDI,
+                                                  FeatureDQI,
+                                                  FeatureBWI,
+                                                  FeatureVLX,
+                                                  FeatureVBMI,
+                                                  FeatureVBMI2,
+                                                  FeatureIFMA,
+                                                  FeatureVNNI,
+                                                  FeatureBITALG,
+                                                  FeatureGFNI,
+                                                  FeatureBF16,
+                                                  FeatureSHSTK,
+                                                  FeatureVPOPCNTDQ];
+  list<SubtargetFeature> ZN4Features =
+    !listconcat(ZN3Features, ZN4AdditionalFeatures);
 }
 
 //===----------------------------------------------------------------------===//
 // X86 processors supported.
 //===----------------------------------------------------------------------===//
 
 class Proc<string Name, list<SubtargetFeature> Features,
            list<SubtargetFeature> TuneFeatures>
def : Proc<"bdver4", ProcessorFeatures.BdVer4Features,
            ProcessorFeatures.BdVer4Tuning>;
 
 def : ProcModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures,
                 ProcessorFeatures.ZNTuning>;
 def : ProcModel<"znver2", Znver2Model, ProcessorFeatures.ZN2Features,
                 ProcessorFeatures.ZN2Tuning>;
 def : ProcModel<"znver3", Znver3Model, ProcessorFeatures.ZN3Features,
                 ProcessorFeatures.ZN3Tuning>;
+def : Proc<"znver4",ProcessorFeatures.ZN4Features,
+           ProcessorFeatures.ZN4Tuning>;
 
 def : Proc<"geode",           [FeatureX87, FeatureCX8, Feature3DNowA],
                               [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
 
 def : Proc<"winchip-c6",      [FeatureX87, FeatureMMX],
                               [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
 def : Proc<"winchip2",        [FeatureX87, Feature3DNow],
                               [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;

llvm/lib/Target/X86/X86PfmCounters.td

let IssueCounters = [
     PfmIssueCounter<"Zn3Int", "ops_type_dispatched_from_decoder:int_disp_retire_mode">,
     PfmIssueCounter<"Zn3FPU", "ops_type_dispatched_from_decoder:fp_disp_retire_mode">,
     PfmIssueCounter<"Zn3Load", "ls_dispatch:ld_dispatch">,
     PfmIssueCounter<"Zn3Store", "ls_dispatch:store_dispatch">,
     PfmIssueCounter<"Zn3Divider", "div_op_count">
   ];
 }
 def : PfmCountersBinding<"znver3", ZnVer3PfmCounters>;
+def : PfmCountersBinding<"znver4", ZnVer3PfmCounters>;

llvm/test/CodeGen/X86/cpus-amd.ll

 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bdver2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bdver3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bdver4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=btver1 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=btver2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver1 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 define void @foo() {
   ret void
 }

llvm/test/CodeGen/X86/rdpru.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-- -mattr=+rdpru | FileCheck %s --check-prefix=X86
 ; RUN: llc < %s -mtriple=i686-- -mattr=+rdpru -fast-isel | FileCheck %s --check-prefix=X86
 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+rdpru | FileCheck %s --check-prefix=X64
 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+rdpru -fast-isel | FileCheck %s --check-prefix=X64
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver2 | FileCheck %s --check-prefix=X64
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 -fast-isel | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 -fast-isel | FileCheck %s --check-prefix=X64
 
 define void @rdpru_asm() {
 ; X86-LABEL: rdpru_asm:
 ; X86:       # %bb.0: # %entry
 ; X86-NEXT:    #APP
 ; X86-NEXT:    rdpru
 ; X86-NEXT:    #NO_APP
 ; X86-NEXT:    retl

llvm/test/CodeGen/X86/slow-unaligned-mem.ll

 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=btver2        2>&1 | FileCheck %s --check-prefix=FAST
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver1        2>&1 | FileCheck %s --check-prefix=FAST
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver2        2>&1 | FileCheck %s --check-prefix=FAST
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver3        2>&1 | FileCheck %s --check-prefix=FAST
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver4        2>&1 | FileCheck %s --check-prefix=FAST
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver1        2>&1 | FileCheck %s --check-prefix=FAST
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver2        2>&1 | FileCheck %s --check-prefix=FAST
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver3        2>&1 | FileCheck %s --check-prefix=FAST
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver4        2>&1 | FileCheck %s --check-prefix=FAST
 
 ; Other chips with slow unaligned memory accesses
 
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=c3-2          2>&1 | FileCheck %s --check-prefix=SLOW
 
 ; Verify that the slow/fast unaligned memory attribute is set correctly for each CPU model.
 ; Slow chips use 4-byte stores. Fast chips with SSE or later use something other than 4-byte stores.
 ; Chips that don't have SSE use 4-byte stores either way, so they're not tested.

llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=nehalem     | FileCheck %s --check-prefixes=NHM
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=sandybridge | FileCheck %s --check-prefixes=FAST-SCALAR,SNB
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=broadwell   | FileCheck %s --check-prefixes=FAST-SCALAR,BDW
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=skylake     | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1      | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3      | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4      | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64      | FileCheck %s --check-prefixes=X86-64
 
 define float @f32_no_daz(float %f) #0 {
 ; NHM-LABEL: f32_no_daz:
 ; NHM:       # %bb.0:
 ; NHM-NEXT:    rsqrtss %xmm0, %xmm1
 ; NHM-NEXT:    movaps %xmm0, %xmm2
 ; NHM-NEXT:    mulss %xmm1, %xmm2

llvm/test/CodeGen/X86/vector-shuffle-fast-per-lane.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=SLOW
 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=SLOW
 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=FAST
 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=FAST
 ;
 ; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=znver1 | FileCheck %s --check-prefixes=FAST
 ; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=znver2 | FileCheck %s --check-prefixes=FAST
 ; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=znver3 | FileCheck %s --check-prefixes=FAST
+; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=znver4 | FileCheck %s --check-prefixes=FAST
 ; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=haswell | FileCheck %s --check-prefixes=FAST
 ; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=skx | FileCheck %s --check-prefixes=FAST
 
 define <32 x i8> @PR44795(<32 x i8> %a0) {
 ; SLOW-LABEL: PR44795:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    vpshuflw {{.*#+}} ymm0 = ymm0[0,0,2,2,4,5,6,7,8,8,10,10,12,13,14,15]
 ; SLOW-NEXT:    vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,4,6,6,8,9,10,11,12,12,14,14]

llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll

 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=btver2 | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver1 | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver2 | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver3 | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver4 | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1 | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver2 | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s
 
 ; Verify that for the X86_64 processors that are known to have poor latency
 ; double precision shift instructions we do not generate 'shld' or 'shrd'
 ; instructions.
 
 ;uint64_t lshift(uint64_t a, uint64_t b, int c)
 ;{
 ;    return (a << c) | (b >> (64-c));

llvm/test/MC/X86/x86_long_nop.s

 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=btver2 %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=btver2 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=znver1 %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=znver1 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=znver2 %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=znver2 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=znver3 %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=znver3 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=znver4 %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=znver4 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=nehalem %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP10 %s
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=westmere %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP10 %s
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=sandybridge %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP15 %s
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=ivybridge %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP15 %s
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=haswell %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP15 %s
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=broadwell %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP15 %s
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=skylake %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP15 %s
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=skx %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP15 %s

llvm/test/tools/llvm-mca/X86/cpus.s

 # ZNVER2-NEXT:      uOps Per Cycle:    0.97
 # ZNVER2-NEXT:      IPC:               0.97
 # ZNVER2-NEXT:      Block RThroughput: 0.3
 
 # ZNVER3:           Dispatch Width:    6
 # ZNVER3-NEXT:      uOps Per Cycle:    0.97
 # ZNVER3-NEXT:      IPC:               0.97
 # ZNVER3-NEXT:      Block RThroughput: 0.3
+
+# ZNVER4:           Dispatch Width:    6
+# ZNVER4-NEXT:      uOps Per Cycle:    0.97
+# ZNVER4-NEXT:      IPC:               0.97
+# ZNVER4-NEXT:      Block RThroughput: 0.3

llvm/test/tools/llvm-mca/X86/read-after-ld-1.s

 # ZNVER1-NEXT:    Total uOps:        2
 
 # ZNVER2-NEXT:    Total Cycles:      16
 # ZNVER2-NEXT:    Total uOps:        2
 
 # ZNVER3-NEXT:    Total Cycles:      17
 # ZNVER3-NEXT:    Total uOps:        2
 
+# ZNVER4-NEXT:    Total Cycles:      17
+# ZNVER4-NEXT:    Total uOps:        2
+
 # BARCELONA:      Dispatch Width:    4
 # BARCELONA-NEXT: uOps Per Cycle:    0.15
 # BARCELONA-NEXT: IPC:               0.10
 # BARCELONA-NEXT: Block RThroughput: 14.0
 
 # BDVER2:         Dispatch Width:    4
 # BDVER2-NEXT:    uOps Per Cycle:    0.12
 # BDVER2-NEXT:    IPC:               0.12

 # ZNVER2-NEXT:    IPC:               0.13
 # ZNVER2-NEXT:    Block RThroughput: 5.0
 
 # ZNVER3:         Dispatch Width:    6
 # ZNVER3-NEXT:    uOps Per Cycle:    0.12
 # ZNVER3-NEXT:    IPC:               0.12
 # ZNVER3-NEXT:    Block RThroughput: 3.0
 
+# ZNVER4:         Dispatch Width:    6
+# ZNVER4-NEXT:    uOps Per Cycle:    0.12
+# ZNVER4-NEXT:    IPC:               0.12
+# ZNVER4-NEXT:    Block RThroughput: 3.0
+
 # ALL:            Timeline view:
 
 # BARCELONA-NEXT:                     0123456789
 # BARCELONA-NEXT: Index     0123456789
 
 # BDVER2-NEXT:                        0123456
 # BDVER2-NEXT:    Index     0123456789
 

 # ZNVER1-NEXT:    Index     0123456789
 
 # ZNVER2-NEXT:                        012345
 # ZNVER2-NEXT:    Index     0123456789
 
 # ZNVER3-NEXT:                        0123456
 # ZNVER3-NEXT:    Index     0123456789
 
+# ZNVER4-NEXT:                        0123456
+# ZNVER4-NEXT:    Index     0123456789
+
 # BARCELONA:      [0,0]     DeeeeeeeeeeeeeeER  .   vdivps %xmm0, %xmm1, %xmm1
 # BARCELONA-NEXT: [0,1]     D========eeeeeeeeeER   vaddps (%rax), %xmm1, %xmm1
 
 # BDVER2:         [0,0]     DeeeeeeeeeER   ..   vdivps  %xmm0, %xmm1, %xmm1
 # BDVER2-NEXT:    [0,1]     D====eeeeeeeeeeER   vaddps  (%rax), %xmm1, %xmm1
 
 # BDWELL:         [0,0]     DeeeeeeeeeeeER ..   vdivps  %xmm0, %xmm1, %xmm1
 # BDWELL-NEXT:    [0,1]     D======eeeeeeeeER   vaddps  (%rax), %xmm1, %xmm1

 # ZNVER1-NEXT:    [0,1]     D==eeeeeeeeeeER   vaddps  (%rax), %xmm1, %xmm1
 
 # ZNVER2:         [0,0]     DeeeeeeeeeeER  .   vdivps %xmm0, %xmm1, %xmm1
 # ZNVER2-NEXT:    [0,1]     D===eeeeeeeeeeER   vaddps (%rax), %xmm1, %xmm1
 
 # ZNVER3:         [0,0]     DeeeeeeeeeeeER ..   vdivps  %xmm0, %xmm1, %xmm1
 # ZNVER3-NEXT:    [0,1]     D====eeeeeeeeeeER   vaddps  (%rax), %xmm1, %xmm1
 
+# ZNVER4:         [0,0]     DeeeeeeeeeeeER ..   vdivps  %xmm0, %xmm1, %xmm1
+# ZNVER4-NEXT:    [0,1]     D====eeeeeeeeeeER   vaddps  (%rax), %xmm1, %xmm1
+
 # ALL:            Average Wait times (based on the timeline view):
 # ALL-NEXT:       [0]: Executions
 # ALL-NEXT:       [1]: Average time spent waiting in a scheduler's queue
 # ALL-NEXT:       [2]: Average time spent waiting in a scheduler's queue while ready
 # ALL-NEXT:       [3]: Average time elapsed from WB until retire stage
 
 # ALL:                  [0]    [1]    [2]    [3]
 # ALL-NEXT:       0.     1     1.0    1.0    0.0       vdivps %xmm0, %xmm1, %xmm1

 # ZNVER1-NEXT:    1.     1     3.0    0.0    0.0       vaddps (%rax), %xmm1, %xmm1
 # ZNVER1-NEXT:           1     2.0    0.5    0.0       <total>
 
 # ZNVER2-NEXT:    1.     1     4.0    0.0    0.0       vaddps (%rax), %xmm1, %xmm1
 # ZNVER2-NEXT:           1     2.5    0.5    0.0       <total>
 
 # ZNVER3-NEXT:    1.     1     5.0    0.0    0.0       vaddps (%rax), %xmm1, %xmm1
 # ZNVER3-NEXT:           1     3.0    0.5    0.0       <total>
+
+# ZNVER4-NEXT:    1.     1     5.0    0.0    0.0       vaddps (%rax), %xmm1, %xmm1
+# ZNVER4-NEXT:           1     3.0    0.5    0.0       <total>

llvm/test/tools/llvm-mca/X86/register-file-statistics.s

 # ZNVER2-NEXT:       Total number of mappings created: 0
 # ZNVER2-NEXT:       Max number of mappings used:      0
 
 # ZNVER3:         *  Register File #1 -- Zn3FpPRF:
 # ZNVER3-NEXT:       Number of physical registers:     160
 # ZNVER3-NEXT:       Total number of mappings created: 0
 # ZNVER3-NEXT:       Max number of mappings used:      0
 
+# ZNVER4:         *  Register File #1 -- Zn3FpPRF:
+# ZNVER4-NEXT:       Number of physical registers:     160
+# ZNVER4-NEXT:       Total number of mappings created: 0
+# ZNVER4-NEXT:       Max number of mappings used:      0
+
 # BDVER2:         *  Register File #2 -- PdIntegerPRF:
 # BDVER2-NEXT:       Number of physical registers:     96
 # BDVER2-NEXT:       Total number of mappings created: 2
 # BDVER2-NEXT:       Max number of mappings used:      2
 
 # BTVER2:         *  Register File #2 -- JIntegerPRF:
 # BTVER2-NEXT:       Number of physical registers:     64
 # BTVER2-NEXT:       Total number of mappings created: 2
 # BTVER2-NEXT:       Max number of mappings used:      2
 
 # ZNVER1:         *  Register File #2 -- ZnIntegerPRF:
 # ZNVER1-NEXT:       Number of physical registers:     168
 # ZNVER1-NEXT:       Total number of mappings created: 2
 # ZNVER1-NEXT:       Max number of mappings used:      2
 
 # ZNVER2:         *  Register File #2 -- Zn2IntegerPRF:
 # ZNVER2-NEXT:       Number of physical registers:     168
 # ZNVER2-NEXT:       Total number of mappings created: 2
 # ZNVER2-NEXT:       Max number of mappings used:      2
 
 # ZNVER3:         *  Register File #2 -- Zn3IntegerPRF:
 # ZNVER3-NEXT:       Number of physical registers:     192
 # ZNVER3-NEXT:       Total number of mappings created: 2
 # ZNVER3-NEXT:       Max number of mappings used:      2
+
+# ZNVER4:         *  Register File #2 -- Zn3IntegerPRF:
+# ZNVER4-NEXT:       Number of physical registers:     192
+# ZNVER4-NEXT:       Total number of mappings created: 2
+# ZNVER4-NEXT:       Max number of mappings used:      2

llvm/test/tools/llvm-mca/X86/scheduler-queue-usage.s

 # ZNVER2-NEXT:     [4] Total number of buffer entries.
 
 # ZNVER3:          Scheduler's queue usage:
 # ZNVER3-NEXT:     [1] Resource name.
 # ZNVER3-NEXT:     [2] Average number of used buffer entries.
 # ZNVER3-NEXT:     [3] Maximum number of used buffer entries.
 # ZNVER3-NEXT:     [4] Total number of buffer entries.
 
+# ZNVER4:          Scheduler's queue usage:
+# ZNVER4-NEXT:     [1] Resource name.
+# ZNVER4-NEXT:     [2] Average number of used buffer entries.
+# ZNVER4-NEXT:     [3] Maximum number of used buffer entries.
+# ZNVER4-NEXT:     [4] Total number of buffer entries.
+
 # BARCELONA:        [1]            [2]        [3]        [4]
 # BARCELONA-NEXT:  SBPortAny        0          1          54
 
 # BDVER2:           [1]            [2]        [3]        [4]
 # BDVER2-NEXT:     PdEX             0          1          40
 # BDVER2-NEXT:     PdFPU            0          0          64
 # BDVER2-NEXT:     PdLoad           0          0          40
 # BDVER2-NEXT:     PdStore          0          0          24

 # ZNVER2-NEXT:     Zn2ALU           0          1          64
 # ZNVER2-NEXT:     Zn2FPU           0          0          36
 
 # ZNVER3:           [1]            [2]        [3]        [4]
 # ZNVER3-NEXT:     Zn3FP            0          0          64
 # ZNVER3-NEXT:     Zn3Int           0          1          96
 # ZNVER3-NEXT:     Zn3Load          0          0          72
 # ZNVER3-NEXT:     Zn3Store         0          0          64
+
+# ZNVER4:           [1]            [2]        [3]        [4]
+# ZNVER4-NEXT:     Zn3FP            0          0          64
+# ZNVER4-NEXT:     Zn3Int           0          1          96
+# ZNVER4-NEXT:     Zn3Load          0          0          72
+# ZNVER4-NEXT:     Zn3Store         0          0          64