jbhateja (Jatin Bhateja)
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Apr 23 2017, 9:51 AM (74 w, 2 d)

Recent Activity

Aug 8 2018

jbhateja updated the summary of D49966: [X86] Performing DAG pruning before selection of LEA instructions..
Aug 8 2018, 9:54 AM

Aug 6 2018

jbhateja added a comment to D49966: [X86] Performing DAG pruning before selection of LEA instructions..

Ping reviewers, can put this under Size oriented optimization.

Aug 6 2018, 10:06 AM

Aug 2 2018

jbhateja added inline comments to D49966: [X86] Performing DAG pruning before selection of LEA instructions..
Aug 2 2018, 10:15 AM
jbhateja updated the diff for D49966: [X86] Performing DAG pruning before selection of LEA instructions..
  • [X86] Limiting optimization to i32 and i64 types
Aug 2 2018, 9:59 AM

Aug 1 2018

jbhateja updated the summary of D49966: [X86] Performing DAG pruning before selection of LEA instructions..
Aug 1 2018, 3:26 AM

Jul 31 2018

jbhateja updated the diff for D49966: [X86] Performing DAG pruning before selection of LEA instructions..
  • [X86] Review comments resolution for patch D49966
  • Patch rebase.
Jul 31 2018, 9:23 PM
jbhateja committed rL338483: [X86] Adding more test patterns for lea-opt (PR37939).
[X86] Adding more test patterns for lea-opt (PR37939)
Jul 31 2018, 8:54 PM
jbhateja closed D50128: [X86] Adding more test patterns for lea-opt (PR37939).
Jul 31 2018, 8:53 PM
jbhateja accepted D50128: [X86] Adding more test patterns for lea-opt (PR37939).
Jul 31 2018, 8:40 PM
jbhateja created D50128: [X86] Adding more test patterns for lea-opt (PR37939).
Jul 31 2018, 8:39 PM

Jul 30 2018

jbhateja updated the diff for D49966: [X86] Performing DAG pruning before selection of LEA instructions..
  • [X86] Review comments incorporation for patch D49966
Jul 30 2018, 11:30 AM

Jul 29 2018

jbhateja updated the diff for D49966: [X86] Performing DAG pruning before selection of LEA instructions..
  • [X86] Review comment resolutions for patch D49966
Jul 29 2018, 8:43 PM
jbhateja updated the diff for D49966: [X86] Performing DAG pruning before selection of LEA instructions..
  • [X86] Correcting a comment in patch D49966
Jul 29 2018, 12:56 PM
jbhateja added reviewers for D49966: [X86] Performing DAG pruning before selection of LEA instructions.: craig.topper, lebedev.ri.
Jul 29 2018, 12:48 PM
jbhateja updated the diff for D49966: [X86] Performing DAG pruning before selection of LEA instructions..
  • [X86] Review comments incorporation for patch D49966
Jul 29 2018, 12:45 PM
jbhateja added inline comments to D49966: [X86] Performing DAG pruning before selection of LEA instructions..
Jul 29 2018, 11:10 AM
jbhateja added reviewers for D49966: [X86] Performing DAG pruning before selection of LEA instructions.: RKSimon, spatel.
Jul 29 2018, 10:52 AM
jbhateja created D49966: [X86] Performing DAG pruning before selection of LEA instructions..
Jul 29 2018, 10:46 AM

Apr 15 2018

jbhateja accepted D45674: Test commit access..
Apr 15 2018, 10:00 AM
jbhateja created D45674: Test commit access..
Apr 15 2018, 9:59 AM

Dec 1 2017

jbhateja committed rL319543: [X86] Improvement in CodeGen instruction selection for LEAs..
[X86] Improvement in CodeGen instruction selection for LEAs.
Dec 1 2017, 6:08 AM
jbhateja closed D35014: [X86] Improvement in CodeGen instruction selection for LEAs. by committing rL319543: [X86] Improvement in CodeGen instruction selection for LEAs..
Dec 1 2017, 6:08 AM

Nov 29 2017

jbhateja updated the diff for D35014: [X86] Improvement in CodeGen instruction selection for LEAs..
  • Register name case changes due to rebase.
Nov 29 2017, 8:17 AM

Nov 28 2017

jbhateja added inline comments to D35014: [X86] Improvement in CodeGen instruction selection for LEAs..
Nov 28 2017, 11:25 PM
jbhateja updated the diff for D35014: [X86] Improvement in CodeGen instruction selection for LEAs..
  • Rebasing to resolve incorrect overrideing of register names in kill statements.
Nov 28 2017, 11:22 PM
jbhateja updated the diff for D35014: [X86] Improvement in CodeGen instruction selection for LEAs..
  • Reivew comment resolution.
  • Rebasing patch.
Nov 28 2017, 11:02 PM

Nov 26 2017

jbhateja committed rL318997: [SCEV] Adding a check on outgoing branches of a terminator instr for….
[SCEV] Adding a check on outgoing branches of a terminator instr for…
Nov 26 2017, 7:09 AM
jbhateja closed D40460: [SCEV] Adding a check on outgoing branches of a terminator instr for SCEVBackedgeConditionFolder, NFC. by committing rL318997: [SCEV] Adding a check on outgoing branches of a terminator instr for….
Nov 26 2017, 7:09 AM
jbhateja retitled D40460: [SCEV] Adding a check on outgoing branches of a terminator instr for SCEVBackedgeConditionFolder, NFC. from [SCEV] NFC : Removing unnecessary check on outgoing branches of a branch instr. to [SCEV] Adding a check on outgoing branches of a terminator instr for SCEVBackedgeConditionFolder, NFC..
Nov 26 2017, 6:40 AM
jbhateja updated the diff for D40460: [SCEV] Adding a check on outgoing branches of a terminator instr for SCEVBackedgeConditionFolder, NFC..

Few more minor changes , mostly NFCs.

Nov 26 2017, 6:29 AM
jbhateja reopened D40460: [SCEV] Adding a check on outgoing branches of a terminator instr for SCEVBackedgeConditionFolder, NFC..
Nov 26 2017, 5:04 AM

Nov 25 2017

jbhateja added inline comments to D40460: [SCEV] Adding a check on outgoing branches of a terminator instr for SCEVBackedgeConditionFolder, NFC..
Nov 25 2017, 8:33 PM
jbhateja committed rL318991: [SCEV] NFC : Removing unnecessary check on outgoing branches of a branch instr..
[SCEV] NFC : Removing unnecessary check on outgoing branches of a branch instr.
Nov 25 2017, 6:01 PM
jbhateja closed D40460: [SCEV] Adding a check on outgoing branches of a terminator instr for SCEVBackedgeConditionFolder, NFC. by committing rL318991: [SCEV] NFC : Removing unnecessary check on outgoing branches of a branch instr..
Nov 25 2017, 6:01 PM
jbhateja accepted D40460: [SCEV] Adding a check on outgoing branches of a terminator instr for SCEVBackedgeConditionFolder, NFC..
Nov 25 2017, 5:57 PM
jbhateja created D40460: [SCEV] Adding a check on outgoing branches of a terminator instr for SCEVBackedgeConditionFolder, NFC..
Nov 25 2017, 5:56 PM

Nov 13 2017

jbhateja added inline comments to D38494: [SCEV] Handling for ICmp occuring in the evolution chain..
Nov 13 2017, 9:54 AM
jbhateja committed rL318050: [SCEV] Handling for ICmp occuring in the evolution chain..
[SCEV] Handling for ICmp occuring in the evolution chain.
Nov 13 2017, 8:44 AM
jbhateja closed D38494: [SCEV] Handling for ICmp occuring in the evolution chain. by committing rL318050: [SCEV] Handling for ICmp occuring in the evolution chain..
Nov 13 2017, 8:44 AM
jbhateja updated the diff for D38494: [SCEV] Handling for ICmp occuring in the evolution chain..
  • Formatting change.
  • Rebasing for commit.
Nov 13 2017, 8:33 AM
jbhateja added inline comments to D38494: [SCEV] Handling for ICmp occuring in the evolution chain..
Nov 13 2017, 8:13 AM

Nov 12 2017

jbhateja added a comment to D38494: [SCEV] Handling for ICmp occuring in the evolution chain..

ping @reviewers

Nov 12 2017, 6:47 AM

Nov 10 2017

jbhateja committed rL317895: [WebAssembly] Fix stack offsets of return values from call lowering..
[WebAssembly] Fix stack offsets of return values from call lowering.
Nov 10 2017, 8:26 AM
jbhateja closed D39866: [WebAssembly] Fix stack offsets of return values from call lowering. by committing rL317895: [WebAssembly] Fix stack offsets of return values from call lowering..
Nov 10 2017, 8:26 AM
jbhateja added a reviewer for D39866: [WebAssembly] Fix stack offsets of return values from call lowering.: alexcrichton.
Nov 10 2017, 5:18 AM

Nov 9 2017

jbhateja added a reviewer for D39866: [WebAssembly] Fix stack offsets of return values from call lowering.: vadimcn.
Nov 9 2017, 1:19 PM
jbhateja created D39866: [WebAssembly] Fix stack offsets of return values from call lowering..
Nov 9 2017, 1:17 PM
jbhateja updated the diff for D38494: [SCEV] Handling for ICmp occuring in the evolution chain..
Nov 9 2017, 12:56 PM

Nov 8 2017

jbhateja accepted D39529: [WebAssembly] Call signExtend to get sign extended register [NFCI].
Nov 8 2017, 11:00 AM
jbhateja added a comment to D35014: [X86] Improvement in CodeGen instruction selection for LEAs..

@RKSimon, @lsaba , @jmolly , all your comments have been addressed. Kindly verify so that I can land this into trunk.

Nov 8 2017, 10:57 AM
jbhateja added inline comments to D38494: [SCEV] Handling for ICmp occuring in the evolution chain..
Nov 8 2017, 10:53 AM

Nov 5 2017

jbhateja added inline comments to D38494: [SCEV] Handling for ICmp occuring in the evolution chain..
Nov 5 2017, 8:28 PM

Nov 4 2017

jbhateja updated the diff for D39529: [WebAssembly] Call signExtend to get sign extended register [NFCI].
  • Adding a test for signext of function arguments.
Nov 4 2017, 11:32 AM

Nov 3 2017

jbhateja updated the diff for D35014: [X86] Improvement in CodeGen instruction selection for LEAs..

1/ Making the factorization alog iterative. This was earlier commited with

Diff : https://reviews.llvm.org/D35014?id=116144
but some how got removed in successive commits.

2/ Rebasing again. All comments are resolved.

Nov 3 2017, 3:11 AM

Nov 1 2017

jbhateja added a reviewer for D39529: [WebAssembly] Call signExtend to get sign extended register [NFCI]: sunfish.
Nov 1 2017, 11:39 PM
jbhateja created D39529: [WebAssembly] Call signExtend to get sign extended register [NFCI].
Nov 1 2017, 11:36 PM
jbhateja added a comment to D39252: [WebAssembly] Handle errors in getRegFor{Uns,S}ignedValue..

ConstantExpr are not handled by FastISel.

Nov 1 2017, 6:16 AM

Oct 31 2017

jbhateja added a comment to D38494: [SCEV] Handling for ICmp occuring in the evolution chain..

The problem is, if under ICmp's operand node has a ICmp can evolutable? (or any other conditional expressions).
This only can be solved by registering this chain into getSCEV.

; RUN: opt -analyze -scalar-evolution < %s | FileCheck %s --check-prefix=CHECK-ANALYSIS

define i32 @foo() {
  br label %do_start

do_start:
  %inc = phi i32 [ 0, %0 ], [ %add, %do_start ]
  %cmp = icmp slt i32 %inc, 10000
  %add_cond = add nsw i32 %inc, 2
  %sel = select i1 %cmp, i32 %add_cond, i32 %inc
  %add = add nsw i32 %sel, 1
  br i1 %cmp, label %do_start, label %do_end

; CHECK-ANALYSIS: Loop %do_start: backedge-taken count is 3334
; CHECK-ANALYSIS: Loop %do_start: max backedge-taken count is 3334
; CHECK-ANALYSIS: Loop %do_start: Predicated backedge-taken count is 3334

do_end:
  ret i32 0
}

This case is "actaully" generated from Clang executable using -O3 -S -emit-llvm option.
that mean this case can be "always" appear.

To fix this case, we need to create SCEVConditional. that I commented here.

Okay, just we need to make sure we are evoluting conditional instructions or just checking that instructions are true or false for now.

first one.
If we are "actaully" evoluting a conditional instructions. better creating SCEVConditonal, checking that is true or false when is computing backedge taken count on each AddRec step.
I think this is a correct way for handling conditional instructions.
but, this will cause SCEV jobs MUUUUCHHH SLOWER.

second one.
If we are just checking that instructions are true or false. we do not need to rewrite it, rewriting value means that we handle that value as that "actual" SCEV. (register SCEV on SCEVCallbackVH)
this mean, this is same to write this chain on to createSCEV that we did at first.
so we have to handle it as a "except" of SCEV chain. better inlining code into createAddRecFromPHI.

and just note this issue CANNOT be solved just by checking ICmp has conditional instruction.

Just try pulling out earlier diff : https://reviews.llvm.org/D38494?id=120193 , this was fixing your new case.
You shuld attempt an incremental fix once this patch goes through.

That isn't a POINT, Please read the point that I commented.
Only that handling each test case dosn't means fixing a "point" of problem.

Is the point of this problem is handling the problem just by CHECKING that ICmp is true, or false?
OR are we REALLY wants to handle condtional instructions.
The point of problem is, current SCEV chain cannot handle conditonal expressions.
NOT only a clang, clang emits PHI node when its conditional, LLVM is a toolchain that we can create a compiler.

so I wanted to listen the opinion that "how about handling condtional variables by just creating SCEVCondtional, and comparing at computing backedge-count by visiting each step."

Oct 31 2017, 1:59 AM

Oct 30 2017

jbhateja added a comment to D38494: [SCEV] Handling for ICmp occuring in the evolution chain..

The problem is, if under ICmp's operand node has a ICmp can evolutable? (or any other conditional expressions).
This only can be solved by registering this chain into getSCEV.

; RUN: opt -analyze -scalar-evolution < %s | FileCheck %s --check-prefix=CHECK-ANALYSIS

define i32 @foo() {
  br label %do_start

do_start:
  %inc = phi i32 [ 0, %0 ], [ %add, %do_start ]
  %cmp = icmp slt i32 %inc, 10000
  %add_cond = add nsw i32 %inc, 2
  %sel = select i1 %cmp, i32 %add_cond, i32 %inc
  %add = add nsw i32 %sel, 1
  br i1 %cmp, label %do_start, label %do_end

; CHECK-ANALYSIS: Loop %do_start: backedge-taken count is 3334
; CHECK-ANALYSIS: Loop %do_start: max backedge-taken count is 3334
; CHECK-ANALYSIS: Loop %do_start: Predicated backedge-taken count is 3334

do_end:
  ret i32 0
}

This case is "actaully" generated from Clang executable using -O3 -S -emit-llvm option.
that mean this case can be "always" appear.

To fix this case, we need to create SCEVConditional. that I commented here.

Okay, just we need to make sure we are evoluting conditional instructions or just checking that instructions are true or false for now.

first one.
If we are "actaully" evoluting a conditional instructions. better creating SCEVConditonal, checking that is true or false when is computing backedge taken count on each AddRec step.
I think this is a correct way for handling conditional instructions.
but, this will cause SCEV jobs MUUUUCHHH SLOWER.

second one.
If we are just checking that instructions are true or false. we do not need to rewrite it, rewriting value means that we handle that value as that "actual" SCEV. (register SCEV on SCEVCallbackVH)
this mean, this is same to write this chain on to createSCEV that we did at first.
so we have to handle it as a "except" of SCEV chain. better inlining code into createAddRecFromPHI.

and just note this issue CANNOT be solved just by checking ICmp has conditional instruction.

Oct 30 2017, 10:42 PM
jbhateja added inline comments to D38494: [SCEV] Handling for ICmp occuring in the evolution chain..
Oct 30 2017, 10:32 PM
jbhateja updated the diff for D38494: [SCEV] Handling for ICmp occuring in the evolution chain..
  • Review comments resolution.
Oct 30 2017, 10:32 PM
jbhateja added a comment to D38494: [SCEV] Handling for ICmp occuring in the evolution chain..

:( that I commented didn't reviewed. this is why I wanted to make other reversion.

Are you saying that you had made the same comments as I did above? If so, that wasn't clear from what you wrote. You can help authors by:

  • Adding inline comments instead of a top level comment, knowing which part of the patch you're referring to helps comprehension
  • Being specific; instead of saying "this is very general" say "use cast instead of switch"

No, I wanted to say all that we are missing a very important point.

Okay, just we need to make sure we are evoluting conditional instructions or just checking that instructions are true or false for now.

first one.
If we are "actaully" evoluting a conditional instructions. better creating SCEVConditonal, checking that is true or false when is computing backedge taken count on each AddRec step.
I think this is a correct way for handling conditional instructions.
but, this will cause SCEV jobs MUUUUCHHH SLOWER.

second one.
If we are just checking that instructions are true or false. we do not need to rewrite it, rewriting value means that we handle that value as that "actual" SCEV. (register SCEV on SCEVCallbackVH)
this mean, this is same to write this chain on to createSCEV that we did at first.
so we have to handle it as a "except" of SCEV chain. better inlining code into createAddRecFromPHI.

This is the actual point. not only fixing a ICmp, this will not fix a "point" that bug reported.
and this will cause same bug, but from littlely different code.
It just fixing only that "specific" IR assembles in a very narrow range.

Oct 30 2017, 7:47 PM
jbhateja added a comment to D35014: [X86] Improvement in CodeGen instruction selection for LEAs..

@RKSimon, requested revision changes have been made as per your comments. Can you please validate.

Oct 30 2017, 7:27 PM
jbhateja updated the diff for D38494: [SCEV] Handling for ICmp occuring in the evolution chain..
  • Review comments resolution.
Oct 30 2017, 1:09 PM

Oct 29 2017

jbhateja updated the diff for D35014: [X86] Improvement in CodeGen instruction selection for LEAs..
  • Rebasing
  • Review comments resolution.
Oct 29 2017, 10:12 AM
jbhateja added inline comments to D35014: [X86] Improvement in CodeGen instruction selection for LEAs..
Oct 29 2017, 9:55 AM
jbhateja retitled D35014: [X86] Improvement in CodeGen instruction selection for LEAs. from [X86] PR32755 : Improvement in CodeGen instruction selection for LEAs. to [X86] Improvement in CodeGen instruction selection for LEAs..
Oct 29 2017, 8:36 AM

Oct 28 2017

jbhateja updated the diff for D38494: [SCEV] Handling for ICmp occuring in the evolution chain..
  • Review comment resolutions.
Oct 28 2017, 4:19 AM

Oct 24 2017

jbhateja updated the diff for D38494: [SCEV] Handling for ICmp occuring in the evolution chain..
  • Review comments resolutions.
Oct 24 2017, 11:54 PM
jbhateja retitled D38494: [SCEV] Handling for ICmp occuring in the evolution chain. from [ScalarEvolution] Handling for ICmp occuring in the evolution chain. to [SCEV] Handling for ICmp occuring in the evolution chain..
Oct 24 2017, 1:59 AM
jbhateja added a comment to D38494: [SCEV] Handling for ICmp occuring in the evolution chain..

@reviewers, kindly let me know if any other comments.

I hope just understand that I can be rude a bit, please understand I'm not really good at english. ( I'm just a korean highschool student. )

Oct 24 2017, 1:44 AM

Oct 23 2017

jbhateja added a comment to D38494: [SCEV] Handling for ICmp occuring in the evolution chain..

@reviewers, kindly let me know if any other comments.

Oct 23 2017, 7:57 AM
jbhateja added a comment to D37660: [ScalarEvolution] Handling Conditional Instruction in SCEV chain..

Few general concerns.

1/  Always submit patch with few test cases (valid for any patch).
2/  Patch https://reviews.llvm.org/D38494 is taking care of this problem. I don't see what is your point in duplicating the efforts.

You are on the review list also.

Oct 23 2017, 3:40 AM

Oct 21 2017

jbhateja updated the diff for D38494: [SCEV] Handling for ICmp occuring in the evolution chain..
Oct 21 2017, 10:37 AM

Oct 18 2017

jbhateja reopened D38494: [SCEV] Handling for ICmp occuring in the evolution chain..

[llvm] r316129 - Revert "[ScalarEvolution] Handling for ICmp occuring in the evolution chain."

Oct 18 2017, 7:49 PM
jbhateja added a comment to D35014: [X86] Improvement in CodeGen instruction selection for LEAs..

Patch has been regressed through chrome test sweet.
No issues reported. Thanks to Hans Wennborg (hans@chromium.org) for validating it.

Oct 18 2017, 11:42 AM

Oct 17 2017

jbhateja added a comment to D37660: [ScalarEvolution] Handling Conditional Instruction in SCEV chain..
Oct 17 2017, 7:15 PM
jbhateja committed rL316054: [ScalarEvolution] Handling for ICmp occuring in the evolution chain..
[ScalarEvolution] Handling for ICmp occuring in the evolution chain.
Oct 17 2017, 6:36 PM
jbhateja closed D38494: [SCEV] Handling for ICmp occuring in the evolution chain. by committing rL316054: [ScalarEvolution] Handling for ICmp occuring in the evolution chain..
Oct 17 2017, 6:36 PM
jbhateja updated the diff for D38494: [SCEV] Handling for ICmp occuring in the evolution chain..

If a compare instruction is same or inverse of the compare in the
branch of the loop latch, then return a constant evolution node.
Currently scope of evaluation is limited to SCEV computation for
PHI nodes.

Oct 17 2017, 6:29 PM
jbhateja updated the diff for D38494: [SCEV] Handling for ICmp occuring in the evolution chain..

Formatting changes.
Test case extension from .txt to .ll

Oct 17 2017, 9:01 AM
jbhateja added a comment to D38494: [SCEV] Handling for ICmp occuring in the evolution chain..

Go to diff history, and download diff. and re upload it.

Oct 17 2017, 6:17 AM
jbhateja updated the diff for D38494: [SCEV] Handling for ICmp occuring in the evolution chain..

Removing unrelated changes uploaded by mistake in previous diff.

Oct 17 2017, 6:15 AM
jbhateja added a comment to D38494: [SCEV] Handling for ICmp occuring in the evolution chain..

I don't understand why is there are CG commits here....

Oct 17 2017, 5:59 AM
jbhateja updated the diff for D38494: [SCEV] Handling for ICmp occuring in the evolution chain..
  • Updating for a review comment.
Oct 17 2017, 5:21 AM
jbhateja added inline comments to D38494: [SCEV] Handling for ICmp occuring in the evolution chain..
Oct 17 2017, 3:10 AM
jbhateja added a comment to D37660: [ScalarEvolution] Handling Conditional Instruction in SCEV chain..

Hi Jun Ryoung Ju,

Oct 17 2017, 3:03 AM

Oct 16 2017

jbhateja added a comment to D38494: [SCEV] Handling for ICmp occuring in the evolution chain..

With this IR:

define void @f() {
entry:
  br label %loop

loop:
  %iv = phi i32 [ 0, %entry ], [ %iv.inc, %loop ]
  %iv.inc = add i32 %iv, 1
  %cmp = icmp ne i32 %iv.inc, 10
  %cmp.zext = zext i1 %cmp to i32
  br i1 %cmp, label %loop, label %leave

leave:
  ret void
}

and opt -analyze -scalar-evolution , on master:

Printing analysis 'Scalar Evolution Analysis' for function 'f':
Classifying expressions for: @f
  %iv = phi i32 [ 0, %entry ], [ %iv.inc, %loop ]
  -->  {0,+,1}<%loop> U: [0,10) S: [0,10)               Exits: 9                LoopDispositions: { %loop: Computable }
  %iv.inc = add i32 %iv, 1
  -->  {1,+,1}<%loop> U: [1,11) S: [1,11)               Exits: 10               LoopDispositions: { %loop: Computable }
  %cmp.zext = zext i1 %cmp to i32
  -->  (zext i1 %cmp to i32) U: [0,2) S: [0,2)          Exits: 0                LoopDispositions: { %loop: Variant }
Determining loop execution counts for: @f
Loop %loop: backedge-taken count is 9
Loop %loop: max backedge-taken count is 9
Loop %loop: Predicated backedge-taken count is 9
 Predicates:

Loop %loop: Trip multiple is 10

and with your patch:

Printing analysis 'Scalar Evolution Analysis' for function 'f':
Classifying expressions for: @f
  %iv = phi i32 [ 0, %entry ], [ %iv.inc, %loop ]
  -->  {0,+,1}<%loop> U: [0,10) S: [0,10)               Exits: 9                LoopDispositions: { %loop: Computable }
  %iv.inc = add i32 %iv, 1
  -->  {1,+,1}<%loop> U: [1,11) S: [1,11)               Exits: 10               LoopDispositions: { %loop: Computable }
  %cmp.zext = zext i1 %cmp to i32
  -->  1 U: [1,2) S: [1,2)              Exits: 1                LoopDispositions: { %loop: Invariant }
Determining loop execution counts for: @f
Loop %loop: backedge-taken count is 9
Loop %loop: max backedge-taken count is 9
Loop %loop: Predicated backedge-taken count is 9
 Predicates:

Loop %loop: Trip multiple is 10

Note that the SCEV for %cmp.zext is different. I'm not sure how you got a
different answer on your end, since this should basically be the same as the IR
from Hal's example. Perhaps in the example you tried the icmp feeding in to the
latch was a different llvm::Instruction than the icmp feeding into the zext? If
so, that's a missing-CSE bug.

Oct 16 2017, 7:33 PM
jbhateja updated the diff for D38494: [SCEV] Handling for ICmp occuring in the evolution chain..
  • Limiting the evaluation of ICmp to computation of SCEV of PHI nodes.
Oct 16 2017, 7:28 PM

Oct 14 2017

jbhateja updated the diff for D35014: [X86] Improvement in CodeGen instruction selection for LEAs..
  • Operands of LEA must be of same register class, this constraint is as per Intel's architecture manual.
  • Remove map entry from LEAs map if value list becomes empty.
  • Rebase.
Oct 14 2017, 1:17 AM
jbhateja updated the diff for D35014: [X86] Improvement in CodeGen instruction selection for LEAs..
  • D35014 : Review comments resolution
  • Removing 2 tests, pulled their latest renamed versions from trunk.
  • [X86] : Factorize LEA, handling for patterns involing SUBREG_TO_REG as LEA operands.
  • Few more changes for LEA factorization.
  • Updating test lea-opt-cse3.ll
  • Formatting changes.
  • Formatting changes
  • Changes to avoid creating costly LEAs in loops, strength reduction for simple LEAs with unit scale
  • Updating test.
  • [X86] Limiting the scope of DAG operands folding while AM based instruction selection to LEAs.
  • Merge from trunk.
  • Extending aggressive AM based folding for LEAs to cover more cases.
  • Updating test post rebase.
  • Formatting changes + fine tuning pattern matching condition.
  • Adding a check for subtarget feature Slow3OpLEA in pattern matching.
  • Few synthetic changes.
  • Undefining result operand of factored statement to preserve SSA nature of Machine IR.
  • Merge branch 'master' of https://github.com/llvm-mirror/llvm
  • Merge branch 'master' of https://github.com/llvm-mirror/llvm
  • Updating tests for reported PRs for initial patch.
  • Merge branch 'master' of https://github.com/llvm-mirror/llvm
  • Pull from trunk.
  • Operands of LEAs must be of same register class.
  • Revert "Operands of LEAs must be of same register class."
Oct 14 2017, 1:06 AM

Oct 13 2017

jbhateja updated the diff for D35014: [X86] Improvement in CodeGen instruction selection for LEAs..
  • Operands of factored LEA must belong to same register class as per Intel's Architecture Manual.
  • Some code reorganization + rebase.
Oct 13 2017, 11:37 AM

Oct 12 2017

jbhateja added inline comments to D37660: [ScalarEvolution] Handling Conditional Instruction in SCEV chain..
Oct 12 2017, 8:11 AM

Oct 4 2017

jbhateja added inline comments to D38494: [SCEV] Handling for ICmp occuring in the evolution chain..
Oct 4 2017, 2:26 AM
jbhateja added a comment to D38494: [SCEV] Handling for ICmp occuring in the evolution chain..

can you explain me why? (I may I didn't understood why do we need to process without loop latch)
I thought without latch cannot be evoluted from ICmp evolution.

without latch loop have to me evoluted from previous SCEV operation. isn't it?

I don't understand your statement.

The point is that, in the last loop iteration, latch condition is not true, so replacing it with true is incorrect. If you have:

int values[11];
int i = 0;
do {

values[i] = i != 10;

} while (i++ != 10);

After the loop, values should be { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0 }. In the 11th iteration, the comparison will be false. With this patch, we'd store 1 into the values array, even for the last iteration.

Oct 4 2017, 2:21 AM
jbhateja committed rL314886: [X86] Improvement in CodeGen instruction selection for LEAs (re-applying post….
[X86] Improvement in CodeGen instruction selection for LEAs (re-applying post…
Oct 4 2017, 2:04 AM

Oct 3 2017

jbhateja added a comment to D38494: [SCEV] Handling for ICmp occuring in the evolution chain..

For following C and IR references.

Oct 3 2017, 8:32 PM
jbhateja retitled D38494: [SCEV] Handling for ICmp occuring in the evolution chain. from [ScalarEvolution] Handling for ICmp occuring in then evolution chain. to [ScalarEvolution] Handling for ICmp occuring in the evolution chain..
Oct 3 2017, 1:53 AM
jbhateja accepted D35014: [X86] Improvement in CodeGen instruction selection for LEAs..

@reviewers, if no more comment I shall be landing this into trunk since required revision changes post acceptance are through.

Oct 3 2017, 1:46 AM
jbhateja edited reviewers for D38494: [SCEV] Handling for ICmp occuring in the evolution chain., added: sanjoy, hfinkel, junryoungju; removed: llvm-commits.
Oct 3 2017, 12:40 AM