[LoongArch] Add remaining intrinsics for CRC check instructions

[gonglingqin]

Summary

After D137316 implements the intrinsics of the first crc check instruction
and related diagnosis, this patch implements the intrinsics of all remaining
crc check instructions.

[SixWeining]

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

953–961

Can we define a marco but not repeating similar codes?
For example:

#define CRC_CASE(NAME, ISD) \
    case Intrinsic::loongarch_#NAME: { \
      Results.push_back(DAG.getNode( \
          ISD::TRUNCATE, DL, VT, \
          DAG.getNode(LoongArchISD::#ISD, DL, MVT::i64, \
                      DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2), \
                      DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op3)))); \
      Results.push_back(N->getOperand(0)); \
      break; \
    }

Then

CRC_CASE(crc_w_b_w, CRC_W_B_W)

[gonglingqin]

Address @SixWeining's comments.

[SixWeining]

LGTM.

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

953–980

You could use uppercase to keep consistency.

[gonglingqin]

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

953–980

Thanks, I will modify it.

[gonglingqin]

Address @SixWeining's comments.

[xen0n]

otherwise LGTM

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

953–980

What's a "two op", are you meaning "binary op" instead?

970

Similarly, is this actually "unary op"?

[gonglingqin]

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

953–980

Yes, thank you for your correction!

970

Thanks a lot! I will modify it.

[gonglingqin]

Address @xen0n's comments.

[SixWeining]

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

953–980

Seems the difference is not binary op or unar op. They are both binary ops. The difference is that the former uses 2 ISD::ANY_EXTEND while the latter only use one.

[SixWeining]

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

953–980

@xen0n What do you think?

clang/include/clang/Basic/BuiltinsLoongArch.def

 
 // TODO: Support more builtins.
 // TODO: Added feature constraints.
 TARGET_BUILTIN(__builtin_loongarch_dbar, "vIUi", "nc", "")
 TARGET_BUILTIN(__builtin_loongarch_ibar, "vIUi", "nc", "")
 TARGET_BUILTIN(__builtin_loongarch_break, "vIUi", "nc", "")
 TARGET_BUILTIN(__builtin_loongarch_syscall, "vIUi", "nc", "")
 
+TARGET_BUILTIN(__builtin_loongarch_crc_w_b_w, "iii", "nc", "64bit")
+TARGET_BUILTIN(__builtin_loongarch_crc_w_h_w, "iii", "nc", "64bit")
+TARGET_BUILTIN(__builtin_loongarch_crc_w_w_w, "iii", "nc", "64bit")
 TARGET_BUILTIN(__builtin_loongarch_crc_w_d_w, "iLii", "nc", "64bit")
+TARGET_BUILTIN(__builtin_loongarch_crcc_w_b_w, "iii", "nc", "64bit")
+TARGET_BUILTIN(__builtin_loongarch_crcc_w_h_w, "iii", "nc", "64bit")
+TARGET_BUILTIN(__builtin_loongarch_crcc_w_w_w, "iii", "nc", "64bit")
+TARGET_BUILTIN(__builtin_loongarch_crcc_w_d_w, "iLii", "nc", "64bit")
 
 #undef BUILTIN
 #undef TARGET_BUILTIN

clang/lib/CodeGen/CGBuiltin.cpp

Value *CodeGenFunction::EmitLoongArchBuiltinExpr(unsigned BuiltinID,
   Intrinsic::ID ID = Intrinsic::not_intrinsic;
 
   switch (BuiltinID) {
   default:
     llvm_unreachable("unexpected builtin ID.");
   case LoongArch::BI__builtin_loongarch_dbar:
     ID = Intrinsic::loongarch_dbar;
     break;
-  case LoongArch::BI__builtin_loongarch_crc_w_d_w:
-    ID = Intrinsic::loongarch_crc_w_d_w;
-    break;
   case LoongArch::BI__builtin_loongarch_break:
     ID = Intrinsic::loongarch_break;
     break;
   case LoongArch::BI__builtin_loongarch_ibar:
     ID = Intrinsic::loongarch_ibar;
     break;
   case LoongArch::BI__builtin_loongarch_syscall:
     ID = Intrinsic::loongarch_syscall;
     break;
+  case LoongArch::BI__builtin_loongarch_crc_w_b_w:
+    ID = Intrinsic::loongarch_crc_w_b_w;
+    break;
+  case LoongArch::BI__builtin_loongarch_crc_w_h_w:
+    ID = Intrinsic::loongarch_crc_w_h_w;
+    break;
+  case LoongArch::BI__builtin_loongarch_crc_w_w_w:
+    ID = Intrinsic::loongarch_crc_w_w_w;
+    break;
+  case LoongArch::BI__builtin_loongarch_crc_w_d_w:
+    ID = Intrinsic::loongarch_crc_w_d_w;
+    break;
+  case LoongArch::BI__builtin_loongarch_crcc_w_b_w:
+    ID = Intrinsic::loongarch_crcc_w_b_w;
+    break;
+  case LoongArch::BI__builtin_loongarch_crcc_w_h_w:
+    ID = Intrinsic::loongarch_crcc_w_h_w;
+    break;
+  case LoongArch::BI__builtin_loongarch_crcc_w_w_w:
+    ID = Intrinsic::loongarch_crcc_w_w_w;
+    break;
+  case LoongArch::BI__builtin_loongarch_crcc_w_d_w:
+    ID = Intrinsic::loongarch_crcc_w_d_w;
+    break;
     // TODO: Support more Intrinsics.
   }
 
   assert(ID != Intrinsic::not_intrinsic);
 
   llvm::Function *F = CGM.getIntrinsic(ID);
   return Builder.CreateCall(F, Ops);
 }

clang/lib/Headers/larchintrin.h

 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 #if __loongarch_grlen == 64
 extern __inline int
     __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+    __crc_w_b_w(char _1, int _2) {
+  return (int)__builtin_loongarch_crc_w_b_w((char)_1, (int)_2);
+}
+
+extern __inline int
+    __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+    __crc_w_h_w(short _1, int _2) {
+  return (int)__builtin_loongarch_crc_w_h_w((short)_1, (int)_2);
+}
+
+extern __inline int
+    __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+    __crc_w_w_w(int _1, int _2) {
+  return (int)__builtin_loongarch_crc_w_w_w((int)_1, (int)_2);
+}
+
+extern __inline int
+    __attribute__((__gnu_inline__, __always_inline__, __artificial__))
     __crc_w_d_w(long int _1, int _2) {
   return (int)__builtin_loongarch_crc_w_d_w((long int)_1, (int)_2);
 }
+
+extern __inline int
+    __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+    __crcc_w_b_w(char _1, int _2) {
+  return (int)__builtin_loongarch_crcc_w_b_w((char)_1, (int)_2);
+}
+
+extern __inline int
+    __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+    __crcc_w_h_w(short _1, int _2) {
+  return (int)__builtin_loongarch_crcc_w_h_w((short)_1, (int)_2);
+}
+
+extern __inline int
+    __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+    __crcc_w_w_w(int _1, int _2) {
+  return (int)__builtin_loongarch_crcc_w_w_w((int)_1, (int)_2);
+}
+
+extern __inline int
+    __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+    __crcc_w_d_w(long int _1, int _2) {
+  return (int)__builtin_loongarch_crcc_w_d_w((long int)_1, (int)_2);
+}
 #endif
 
 #define __break(/*ui15*/ _1) __builtin_loongarch_break((_1))
 
 #define __dbar(/*ui15*/ _1) __builtin_loongarch_dbar((_1))
 
 #define __ibar(/*ui15*/ _1) __builtin_loongarch_ibar((_1))
 
 #define __syscall(/*ui15*/ _1) __builtin_loongarch_syscall((_1))
 
 #ifdef __cplusplus
 }
 #endif
 #endif /* _LOONGARCH_BASE_INTRIN_H */

clang/lib/Sema/SemaChecking.cpp

 }
 
 bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI,
                                              unsigned BuiltinID,
                                              CallExpr *TheCall) {
   switch (BuiltinID) {
   default:
     break;
+  case LoongArch::BI__builtin_loongarch_crc_w_b_w:
+  case LoongArch::BI__builtin_loongarch_crc_w_h_w:
+  case LoongArch::BI__builtin_loongarch_crc_w_w_w:
   case LoongArch::BI__builtin_loongarch_crc_w_d_w:
+  case LoongArch::BI__builtin_loongarch_crcc_w_b_w:
+  case LoongArch::BI__builtin_loongarch_crcc_w_h_w:
+  case LoongArch::BI__builtin_loongarch_crcc_w_w_w:
+  case LoongArch::BI__builtin_loongarch_crcc_w_d_w:
     if (!TI.hasFeature("64bit"))
       return Diag(TheCall->getBeginLoc(),
                   diag::err_loongarch_builtin_requires_la64)
              << TheCall->getSourceRange();
     break;
   case LoongArch::BI__builtin_loongarch_break:
   case LoongArch::BI__builtin_loongarch_dbar:
   case LoongArch::BI__builtin_loongarch_ibar:

clang/test/CodeGen/LoongArch/intrinsic-error.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple loongarch32 -emit-llvm -S -verify %s -o /dev/null
 
 #include <larchintrin.h>
 
-int crc_w_d_w(long int a, int b) {
-  return __builtin_loongarch_crc_w_d_w(a, b); // expected-error {{this builtin requires target: loongarch64}}
-}
-
 void dbar(int a) {
   __builtin_loongarch_dbar(32768); // expected-error {{argument value 32768 is outside the valid range [0, 32767]}}
   __builtin_loongarch_dbar(-1); // expected-error {{argument value 4294967295 is outside the valid range [0, 32767]}}
   __builtin_loongarch_dbar(a); // expected-error {{argument to '__builtin_loongarch_dbar' must be a constant integer}}
 }
 
 void ibar(int a) {
   __builtin_loongarch_ibar(32769); // expected-error {{argument value 32769 is outside the valid range [0, 32767]}}
   __builtin_loongarch_ibar(-1); // expected-error {{argument value 4294967295 is outside the valid range [0, 32767]}}
   __builtin_loongarch_ibar(a); // expected-error {{argument to '__builtin_loongarch_ibar' must be a constant integer}}
 }
 
 void loongarch_break(int a) {
   __builtin_loongarch_break(32769); // expected-error {{argument value 32769 is outside the valid range [0, 32767]}}
   __builtin_loongarch_break(-1); // expected-error {{argument value 4294967295 is outside the valid range [0, 32767]}}
   __builtin_loongarch_break(a); // expected-error {{argument to '__builtin_loongarch_break' must be a constant integer}}
 }
 
 void syscall(int a) {
   __builtin_loongarch_syscall(32769); // expected-error {{argument value 32769 is outside the valid range [0, 32767]}}
   __builtin_loongarch_syscall(-1); // expected-error {{argument value 4294967295 is outside the valid range [0, 32767]}}
   __builtin_loongarch_syscall(a); // expected-error {{argument to '__builtin_loongarch_syscall' must be a constant integer}}
 }
+
+int crc_w_b_w(char a, int b) {
+  return __builtin_loongarch_crc_w_b_w(a, b); // expected-error {{this builtin requires target: loongarch64}}
+}
+
+int crc_w_h_w(short a, int b) {
+  return __builtin_loongarch_crc_w_h_w(a, b); // expected-error {{this builtin requires target: loongarch64}}
+}
+
+int crc_w_w_w(int a, int b) {
+  return __builtin_loongarch_crc_w_w_w(a, b); // expected-error {{this builtin requires target: loongarch64}}
+}
+
+int crc_w_d_w(long int a, int b) {
+  return __builtin_loongarch_crc_w_d_w(a, b); // expected-error {{this builtin requires target: loongarch64}}
+}
+int crcc_w_b_w(char a, int b) {
+  return __builtin_loongarch_crcc_w_b_w(a, b); // expected-error {{this builtin requires target: loongarch64}}
+}
+
+int crcc_w_h_w(short a, int b) {
+  return __builtin_loongarch_crcc_w_h_w(a, b); // expected-error {{this builtin requires target: loongarch64}}
+}
+
+int crcc_w_w_w(int a, int b) {
+  return __builtin_loongarch_crcc_w_w_w(a, b); // expected-error {{this builtin requires target: loongarch64}}
+}
+
+int crcc_w_d_w(long int a, int b) {
+  return __builtin_loongarch_crcc_w_d_w(a, b); // expected-error {{this builtin requires target: loongarch64}}
+}

clang/test/CodeGen/LoongArch/intrinsic-la64.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple loongarch64 -O2 -emit-llvm %s -o - | FileCheck %s
 
 #include <larchintrin.h>
 
+// CHECK-LABEL: @crc_w_b_w(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.loongarch.crc.w.b.w(i32 [[A:%.*]], i32 [[B:%.*]])
+// CHECK-NEXT:    ret i32 [[TMP0]]
+//
+int crc_w_b_w(int a, int b) {
+  return __builtin_loongarch_crc_w_b_w(a, b);
+}
+
+// CHECK-LABEL: @crc_w_h_w(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.loongarch.crc.w.h.w(i32 [[A:%.*]], i32 [[B:%.*]])
+// CHECK-NEXT:    ret i32 [[TMP0]]
+//
+int crc_w_h_w(int a, int b) {
+  return __builtin_loongarch_crc_w_h_w(a, b);
+}
+
+// CHECK-LABEL: @crc_w_w_w(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.loongarch.crc.w.w.w(i32 [[A:%.*]], i32 [[B:%.*]])
+// CHECK-NEXT:    ret i32 [[TMP0]]
+//
+int crc_w_w_w(int a, int b) {
+  return __builtin_loongarch_crc_w_w_w(a, b);
+}
+
 // CHECK-LABEL: @crc_w_d_w(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.loongarch.crc.w.d.w(i64 [[A:%.*]], i32 [[B:%.*]])
 // CHECK-NEXT:    ret i32 [[TMP0]]
 //
 int crc_w_d_w(long int a, int b) {
   return __builtin_loongarch_crc_w_d_w(a, b);
 }
+
+// CHECK-LABEL: @crcc_w_b_w(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.loongarch.crcc.w.b.w(i32 [[A:%.*]], i32 [[B:%.*]])
+// CHECK-NEXT:    ret i32 [[TMP0]]
+//
+int crcc_w_b_w(int a, int b) {
+  return __builtin_loongarch_crcc_w_b_w(a, b);
+}
+
+// CHECK-LABEL: @crcc_w_h_w(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.loongarch.crcc.w.h.w(i32 [[A:%.*]], i32 [[B:%.*]])
+// CHECK-NEXT:    ret i32 [[TMP0]]
+//
+int crcc_w_h_w(int a, int b) {
+  return __builtin_loongarch_crcc_w_h_w(a, b);
+}
+
+// CHECK-LABEL: @crcc_w_w_w(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.loongarch.crcc.w.w.w(i32 [[A:%.*]], i32 [[B:%.*]])
+// CHECK-NEXT:    ret i32 [[TMP0]]
+//
+int crcc_w_w_w(int a, int b) {
+  return __builtin_loongarch_crcc_w_w_w(a, b);
+}
+
+// CHECK-LABEL: @crcc_w_d_w(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.loongarch.crcc.w.d.w(i64 [[A:%.*]], i32 [[B:%.*]])
+// CHECK-NEXT:    ret i32 [[TMP0]]
+//
+int crcc_w_d_w(long int a, int b) {
+  return __builtin_loongarch_crcc_w_d_w(a, b);
+}

llvm/include/llvm/IR/IntrinsicsLoongArch.td

 //===----------------------------------------------------------------------===//
 // LoongArch BASE
 
 def int_loongarch_break : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
 def int_loongarch_dbar : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
 def int_loongarch_ibar : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
 def int_loongarch_syscall : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
 
+def int_loongarch_crc_w_b_w : Intrinsic<[llvm_i32_ty],
+                                        [llvm_i32_ty, llvm_i32_ty]>;
+def int_loongarch_crc_w_h_w : Intrinsic<[llvm_i32_ty],
+                                        [llvm_i32_ty, llvm_i32_ty]>;
+def int_loongarch_crc_w_w_w : Intrinsic<[llvm_i32_ty],
+                                        [llvm_i32_ty, llvm_i32_ty]>;
 def int_loongarch_crc_w_d_w : Intrinsic<[llvm_i32_ty],
                                         [llvm_i64_ty, llvm_i32_ty]>;
+
+def int_loongarch_crcc_w_b_w : Intrinsic<[llvm_i32_ty],
+                                         [llvm_i32_ty, llvm_i32_ty]>;
+def int_loongarch_crcc_w_h_w : Intrinsic<[llvm_i32_ty],
+                                         [llvm_i32_ty, llvm_i32_ty]>;
+def int_loongarch_crcc_w_w_w : Intrinsic<[llvm_i32_ty],
+                                         [llvm_i32_ty, llvm_i32_ty]>;
+def int_loongarch_crcc_w_d_w : Intrinsic<[llvm_i32_ty],
+                                         [llvm_i64_ty, llvm_i32_ty]>;
 } // TargetPrefix = "loongarch"

llvm/lib/Target/LoongArch/LoongArchISelLowering.h

enum NodeType : unsigned {
 
   // Intrinsic operations
   BREAK,
   DBAR,
   IBAR,
   SYSCALL,
 
   // CRC check operations
-  CRC_W_D_W
+  CRC_W_B_W,
+  CRC_W_H_W,
+  CRC_W_W_W,
+  CRC_W_D_W,
+  CRCC_W_B_W,
+  CRCC_W_H_W,
+  CRCC_W_W_W,
+  CRCC_W_D_W
 };
 } // end namespace LoongArchISD
 
 class LoongArchTargetLowering : public TargetLowering {
   const LoongArchSubtarget &Subtarget;
 
 public:
   explicit LoongArchTargetLowering(const TargetMachine &TM,

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
   if (Subtarget.is64Bit()) {
     setOperationAction(ISD::BITREVERSE, MVT::i32, Custom);
     setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
   } else {
     setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
     setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
     setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
     setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
+    setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
   }
 
   static const ISD::CondCode FPCCToExpand[] = {
       ISD::SETOGT, ISD::SETOGE, ISD::SETUGT, ISD::SETUGE,
       ISD::SETGE,  ISD::SETNE,  ISD::SETGT};
 
   if (Subtarget.hasBasicF()) {
     setCondCodeAction(FPCCToExpand, MVT::f32, Expand);

 
 SDValue
 LoongArchTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
                                                 SelectionDAG &DAG) const {
 
   switch (Op.getConstantOperandVal(1)) {
   default:
     return Op;
-  case Intrinsic::loongarch_crc_w_d_w: {
-    DAG.getContext()->emitError(
-        "llvm.loongarch.crc.w.d.w requires target: loongarch64");
+  case Intrinsic::loongarch_crc_w_b_w:
+  case Intrinsic::loongarch_crc_w_h_w:
+  case Intrinsic::loongarch_crc_w_w_w:
+  case Intrinsic::loongarch_crc_w_d_w:
+  case Intrinsic::loongarch_crcc_w_b_w:
+  case Intrinsic::loongarch_crcc_w_h_w:
+  case Intrinsic::loongarch_crcc_w_w_w:
+  case Intrinsic::loongarch_crcc_w_d_w: {
+    std::string Name = Op->getOperationName(0);
+    DAG.getContext()->emitError(Name + " requires target: loongarch64");
     return DAG.getMergeValues(
         {DAG.getUNDEF(Op.getValueType()), Op.getOperand(0)}, SDLoc(Op));
   }
   }
 }
 
 // Helper function that emits error message for intrinsics with void return
 // value.
case ISD::CTTZ: {
     assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
            "Unexpected custom legalisation");
     Results.push_back(customLegalizeToWOp(N, DAG, 1));
     break;
   }
   case ISD::INTRINSIC_W_CHAIN: {
     assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
            "Unexpected custom legalisation");
+    EVT VT = N->getValueType(0);
+    SDValue Op2 = N->getOperand(2);
+    SDValue Op3 = N->getOperand(3);
 
     switch (N->getConstantOperandVal(1)) {
     default:
       llvm_unreachable("Unexpected Intrinsic.");
-    case Intrinsic::loongarch_crc_w_d_w: {
-      Results.push_back(DAG.getNode(
-          ISD::TRUNCATE, DL, N->getValueType(0),
-          DAG.getNode(
-              LoongArchISD::CRC_W_D_W, DL, MVT::i64, N->getOperand(2),
-              DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(3)))));
-      Results.push_back(N->getOperand(0));
-      break;
-    }
+#define CRC_CASE_EXT_BINARYOP(NAME, NODE)                                      \
+  case Intrinsic::loongarch_##NAME: {                                          \
+    Results.push_back(DAG.getNode(                                             \
+        ISD::TRUNCATE, DL, VT,                                                 \
+        DAG.getNode(LoongArchISD::NODE, DL, MVT::i64,                          \
+                    DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2),           \
+                    DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op3))));        \
+    Results.push_back(N->getOperand(0));                                       \
+    break;                                                                     \
+  }
+      CRC_CASE_EXT_BINARYOP(crc_w_b_w, CRC_W_B_W)
+      CRC_CASE_EXT_BINARYOP(crc_w_h_w, CRC_W_H_W)
+      CRC_CASE_EXT_BINARYOP(crc_w_w_w, CRC_W_W_W)
+      CRC_CASE_EXT_BINARYOP(crcc_w_b_w, CRCC_W_B_W)
+      CRC_CASE_EXT_BINARYOP(crcc_w_h_w, CRCC_W_H_W)
+      CRC_CASE_EXT_BINARYOP(crcc_w_w_w, CRCC_W_W_W)
+
+#define CRC_CASE_EXT_UNARYOP(NAME, NODE)                                       \
+  case Intrinsic::loongarch_##NAME: {                                          \
+    Results.push_back(DAG.getNode(                                             \
+        ISD::TRUNCATE, DL, VT,                                                 \
+        DAG.getNode(LoongArchISD::NODE, DL, MVT::i64, Op2,                     \
+                    DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op3))));        \
+    Results.push_back(N->getOperand(0));                                       \
+    break;                                                                     \
+      CRC_CASE_EXT_UNARYOP(crc_w_d_w, CRC_W_D_W)
+      CRC_CASE_EXT_UNARYOP(crcc_w_d_w, CRCC_W_D_W)
     }
     break;
   }
   case ISD::READ_REGISTER: {
     if (Subtarget.is64Bit())
       DAG.getContext()->emitError(
           "On LA64, only 64-bit registers can be read.");
     else
case LoongArchISD::node:                                                     \
     NODE_NAME_CASE(ROTR_W)
     NODE_NAME_CASE(ROTL_W)
     NODE_NAME_CASE(CLZ_W)
     NODE_NAME_CASE(CTZ_W)
     NODE_NAME_CASE(DBAR)
     NODE_NAME_CASE(IBAR)
     NODE_NAME_CASE(BREAK)
     NODE_NAME_CASE(SYSCALL)
+    NODE_NAME_CASE(CRC_W_B_W)
+    NODE_NAME_CASE(CRC_W_H_W)
+    NODE_NAME_CASE(CRC_W_W_W)
     NODE_NAME_CASE(CRC_W_D_W)
+    NODE_NAME_CASE(CRCC_W_B_W)
+    NODE_NAME_CASE(CRCC_W_H_W)
+    NODE_NAME_CASE(CRCC_W_W_W)
+    NODE_NAME_CASE(CRCC_W_D_W)
   }
 #undef NODE_NAME_CASE
   return nullptr;
 }
 
 //===----------------------------------------------------------------------===//
 //                     Calling Convention Implementation
 //===----------------------------------------------------------------------===//

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

 def loongarch_tail : SDNode<"LoongArchISD::TAIL", SDT_LoongArchCall,
                             [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
                              SDNPVariadic]>;
 def loongarch_sll_w : SDNode<"LoongArchISD::SLL_W", SDT_LoongArchIntBinOpW>;
 def loongarch_sra_w : SDNode<"LoongArchISD::SRA_W", SDT_LoongArchIntBinOpW>;
 def loongarch_srl_w : SDNode<"LoongArchISD::SRL_W", SDT_LoongArchIntBinOpW>;
 def loongarch_rotr_w : SDNode<"LoongArchISD::ROTR_W", SDT_LoongArchIntBinOpW>;
 def loongarch_rotl_w : SDNode<"LoongArchISD::ROTL_W", SDT_LoongArchIntBinOpW>;
+def loongarch_crc_w_b_w
+    : SDNode<"LoongArchISD::CRC_W_B_W", SDT_LoongArchIntBinOpW>;
+def loongarch_crc_w_h_w
+    : SDNode<"LoongArchISD::CRC_W_H_W", SDT_LoongArchIntBinOpW>;
+def loongarch_crc_w_w_w
+    : SDNode<"LoongArchISD::CRC_W_W_W", SDT_LoongArchIntBinOpW>;
 def loongarch_crc_w_d_w
     : SDNode<"LoongArchISD::CRC_W_D_W", SDT_LoongArchIntBinOpW>;
+def loongarch_crcc_w_b_w
+    : SDNode<"LoongArchISD::CRCC_W_B_W", SDT_LoongArchIntBinOpW>;
+def loongarch_crcc_w_h_w
+    : SDNode<"LoongArchISD::CRCC_W_H_W", SDT_LoongArchIntBinOpW>;
+def loongarch_crcc_w_w_w
+    : SDNode<"LoongArchISD::CRCC_W_W_W", SDT_LoongArchIntBinOpW>;
+def loongarch_crcc_w_d_w
+    : SDNode<"LoongArchISD::CRCC_W_D_W", SDT_LoongArchIntBinOpW>;
 def loongarch_bstrins
     : SDNode<"LoongArchISD::BSTRINS", SDT_LoongArchBStrIns>;
 def loongarch_bstrpick
     : SDNode<"LoongArchISD::BSTRPICK", SDT_LoongArchBStrPick>;
 def loongarch_revb_2h : SDNode<"LoongArchISD::REVB_2H", SDTUnaryOp>;
 def loongarch_revb_2w : SDNode<"LoongArchISD::REVB_2W", SDTUnaryOp>;
 def loongarch_bitrev_4b : SDNode<"LoongArchISD::BITREV_4B", SDTUnaryOp>;
 def loongarch_bitrev_w : SDNode<"LoongArchISD::BITREV_W", SDTUnaryOp>;

 
 def : Pat<(loongarch_dbar uimm15:$imm15), (DBAR uimm15:$imm15)>;
 def : Pat<(loongarch_ibar uimm15:$imm15), (IBAR uimm15:$imm15)>;
 def : Pat<(loongarch_break uimm15:$imm15), (BREAK uimm15:$imm15)>;
 def : Pat<(loongarch_syscall uimm15:$imm15), (SYSCALL uimm15:$imm15)>;
 
 let Predicates = [IsLA64] in {
 // CRC Check Instructions
+def : PatGprGpr<loongarch_crc_w_b_w, CRC_W_B_W>;
+def : PatGprGpr<loongarch_crc_w_h_w, CRC_W_H_W>;
+def : PatGprGpr<loongarch_crc_w_w_w, CRC_W_W_W>;
 def : PatGprGpr<loongarch_crc_w_d_w, CRC_W_D_W>;
+def : PatGprGpr<loongarch_crcc_w_b_w, CRCC_W_B_W>;
+def : PatGprGpr<loongarch_crcc_w_h_w, CRCC_W_H_W>;
+def : PatGprGpr<loongarch_crcc_w_w_w, CRCC_W_W_W>;
+def : PatGprGpr<loongarch_crcc_w_d_w, CRCC_W_D_W>;
 } // Predicates = [IsLA64]
 
 /// Other pseudo-instructions
 
 // Pessimistically assume the stack pointer will be clobbered
 let Defs = [R3], Uses = [R3] in {
 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
                               [(callseq_start timm:$amt1, timm:$amt2)]>;

llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll

 ; RUN: not llc --mtriple=loongarch32 --disable-verify < %s 2>&1 | FileCheck %s
 
+declare i32 @llvm.loongarch.crc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.w.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.d.w(i64, i32)
+declare i32 @llvm.loongarch.crcc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.w.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.d.w(i64, i32)
+
+define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crc.w.b.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crc.w.b.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_h_w(i32 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crc.w.h.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crc.w.h.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_w_w(i32 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crc.w.w.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crc.w.w.w(i32 %a, i32 %b)
+  ret i32 %res
+}
 
 define i32 @crc_w_d_w(i64 %a, i32 %b) nounwind {
 ; CHECK: llvm.loongarch.crc.w.d.w requires target: loongarch64
 entry:
   %res = call i32 @llvm.loongarch.crc.w.d.w(i64 %a, i32 %b)
   ret i32 %res
 }
+
+define i32 @crcc_w_b_w(i32 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crcc.w.b.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crcc.w.b.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crcc_w_h_w(i32 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crcc.w.h.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crcc.w.h.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crcc_w_w_w(i32 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crcc.w.w.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crcc.w.w.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crcc_w_d_w(i64 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crcc.w.d.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crcc.w.d.w(i64 %a, i32 %b)
+  ret i32 %res
+}

llvm/test/CodeGen/LoongArch/intrinsic-la64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
+declare i32 @llvm.loongarch.crc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.w.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.d.w(i64, i32)
+declare i32 @llvm.loongarch.crcc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.w.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.d.w(i64, i32)
+
+define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc_w_b_w:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    crc.w.b.w $a0, $a0, $a1
+; CHECK-NEXT:    ret
+  %res = call i32 @llvm.loongarch.crc.w.b.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_h_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc_w_h_w:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    crc.w.h.w $a0, $a0, $a1
+; CHECK-NEXT:    ret
+  %res = call i32 @llvm.loongarch.crc.w.h.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_w_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc_w_w_w:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    crc.w.w.w $a0, $a0, $a1
+; CHECK-NEXT:    ret
+  %res = call i32 @llvm.loongarch.crc.w.w.w(i32 %a, i32 %b)
+  ret i32 %res
+}
 
 define i32 @crc_w_d_w(i64 %a, i32 %b) nounwind {
 ; CHECK-LABEL: crc_w_d_w:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    crc.w.d.w $a0, $a0, $a1
 ; CHECK-NEXT:    ret
   %res = call i32 @llvm.loongarch.crc.w.d.w(i64 %a, i32 %b)
   ret i32 %res
 }
+
+define i32 @crcc_w_b_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_b_w:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    crcc.w.b.w $a0, $a0, $a1
+; CHECK-NEXT:    ret
+  %res = call i32 @llvm.loongarch.crcc.w.b.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crcc_w_h_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_h_w:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    crcc.w.h.w $a0, $a0, $a1
+; CHECK-NEXT:    ret
+  %res = call i32 @llvm.loongarch.crcc.w.h.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crcc_w_w_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_w_w:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    crcc.w.w.w $a0, $a0, $a1
+; CHECK-NEXT:    ret
+  %res = call i32 @llvm.loongarch.crcc.w.w.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crcc_w_d_w(i64 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_d_w:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    crcc.w.d.w $a0, $a0, $a1
+; CHECK-NEXT:    ret
+  %res = call i32 @llvm.loongarch.crcc.w.d.w(i64 %a, i32 %b)
+  ret i32 %res
+}