[DAGCombiner] fold or (and x, y), x --> x

[RKSimon]

LGTM

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 /// OR combines for which the commuted variant will be tried as well.
 static SDValue visitORCommutative(SelectionDAG &DAG, SDValue N0, SDValue N1,
                                   SDNode *N) {
   EVT VT = N0.getValueType();
   if (N0.getOpcode() == ISD::AND) {
     SDValue N00 = N0.getOperand(0);
     SDValue N01 = N0.getOperand(1);
 
+    // fold or (and x, y), x --> x
+    if (N00 == N1 || N01 == N1)
+      return N1;
+
     // fold (or (and X, (xor Y, -1)), Y) -> (or X, Y)
     // TODO: Set AllowUndefs = true.
     if (getBitwiseNotOperand(N01, N00,
                              /* AllowUndefs */ false) == N1)
       return DAG.getNode(ISD::OR, SDLoc(N), VT, N00, N1);
 
     // fold (or (and (xor Y, -1), X), Y) -> (or X, Y)
     if (getBitwiseNotOperand(N00, N01,

llvm/test/CodeGen/X86/avx512-select.ll

; X64-AVX512BW-NEXT:    retq
   store <1 x i1> %c, ptr %x
   ret void
 }
 
 ; Regression test from https://github.com/JuliaLang/julia/issues/36955
 define i8 @julia_issue36955(<8 x i1> %mask, <8 x double> %a) {
 ; X86-AVX512F-LABEL: julia_issue36955:
 ; X86-AVX512F:       # %bb.0:
-; X86-AVX512F-NEXT:    vpmovsxwq %xmm0, %zmm0
-; X86-AVX512F-NEXT:    vpsllq $63, %zmm0, %zmm0
-; X86-AVX512F-NEXT:    vxorpd %xmm2, %xmm2, %xmm2
-; X86-AVX512F-NEXT:    vcmplepd %zmm2, %zmm1, %k1
-; X86-AVX512F-NEXT:    vptestmq %zmm0, %zmm0, %k0 {%k1}
-; X86-AVX512F-NEXT:    korw %k0, %k1, %k0
+; X86-AVX512F-NEXT:    vxorpd %xmm0, %xmm0, %xmm0
+; X86-AVX512F-NEXT:    vcmplepd %zmm0, %zmm1, %k0
 ; X86-AVX512F-NEXT:    kmovw %k0, %eax
 ; X86-AVX512F-NEXT:    # kill: def $al killed $al killed $eax
 ; X86-AVX512F-NEXT:    vzeroupper
 ; X86-AVX512F-NEXT:    retl
 ;
 ; X64-AVX512F-LABEL: julia_issue36955:
 ; X64-AVX512F:       # %bb.0:
-; X64-AVX512F-NEXT:    vpmovsxwq %xmm0, %zmm0
-; X64-AVX512F-NEXT:    vpsllq $63, %zmm0, %zmm0
-; X64-AVX512F-NEXT:    vxorpd %xmm2, %xmm2, %xmm2
-; X64-AVX512F-NEXT:    vcmplepd %zmm2, %zmm1, %k1
-; X64-AVX512F-NEXT:    vptestmq %zmm0, %zmm0, %k0 {%k1}
-; X64-AVX512F-NEXT:    korw %k0, %k1, %k0
+; X64-AVX512F-NEXT:    vxorpd %xmm0, %xmm0, %xmm0
+; X64-AVX512F-NEXT:    vcmplepd %zmm0, %zmm1, %k0
 ; X64-AVX512F-NEXT:    kmovw %k0, %eax
 ; X64-AVX512F-NEXT:    # kill: def $al killed $al killed $eax
 ; X64-AVX512F-NEXT:    vzeroupper
 ; X64-AVX512F-NEXT:    retq
 ;
 ; X86-AVX512BW-LABEL: julia_issue36955:
 ; X86-AVX512BW:       # %bb.0:
-; X86-AVX512BW-NEXT:    vpsllw $15, %xmm0, %xmm0
-; X86-AVX512BW-NEXT:    vpxor %xmm2, %xmm2, %xmm2
-; X86-AVX512BW-NEXT:    vxorpd %xmm3, %xmm3, %xmm3
-; X86-AVX512BW-NEXT:    vcmplepd %zmm3, %zmm1, %k1
-; X86-AVX512BW-NEXT:    vpcmpgtw %zmm0, %zmm2, %k0 {%k1}
-; X86-AVX512BW-NEXT:    korw %k0, %k1, %k0
+; X86-AVX512BW-NEXT:    vxorpd %xmm0, %xmm0, %xmm0
+; X86-AVX512BW-NEXT:    vcmplepd %zmm0, %zmm1, %k0
 ; X86-AVX512BW-NEXT:    kmovd %k0, %eax
 ; X86-AVX512BW-NEXT:    # kill: def $al killed $al killed $eax
 ; X86-AVX512BW-NEXT:    vzeroupper
 ; X86-AVX512BW-NEXT:    retl
 ;
 ; X64-AVX512BW-LABEL: julia_issue36955:
 ; X64-AVX512BW:       # %bb.0:
-; X64-AVX512BW-NEXT:    vpsllw $15, %xmm0, %xmm0
-; X64-AVX512BW-NEXT:    vpxor %xmm2, %xmm2, %xmm2
-; X64-AVX512BW-NEXT:    vxorpd %xmm3, %xmm3, %xmm3
-; X64-AVX512BW-NEXT:    vcmplepd %zmm3, %zmm1, %k1
-; X64-AVX512BW-NEXT:    vpcmpgtw %zmm0, %zmm2, %k0 {%k1}
-; X64-AVX512BW-NEXT:    korw %k0, %k1, %k0
+; X64-AVX512BW-NEXT:    vxorpd %xmm0, %xmm0, %xmm0
+; X64-AVX512BW-NEXT:    vcmplepd %zmm0, %zmm1, %k0
 ; X64-AVX512BW-NEXT:    kmovd %k0, %eax
 ; X64-AVX512BW-NEXT:    # kill: def $al killed $al killed $eax
 ; X64-AVX512BW-NEXT:    vzeroupper
 ; X64-AVX512BW-NEXT:    retq
   %fcmp = fcmp ugt <8 x double> %a, zeroinitializer
   %xor = xor <8 x i1> %fcmp, <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
   %select1 = select <8 x i1> %fcmp, <8 x i1> zeroinitializer, <8 x i1> %mask
   %select2 = select <8 x i1> %xor, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i1> %select1
   %ret = bitcast <8 x i1> %select2 to i8
   ret i8 %ret
 }

llvm/test/CodeGen/X86/bswap_tree2.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=CHECK64
 
 ; Check a few invalid patterns for halfword bswap pattern matching
 
 ; Don't match a near-miss 32-bit packed halfword bswap
 ; (with only half of the swap tree valid).
   define i32 @test1(i32 %x) nounwind {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT:    movzwl %ax, %ecx
-; CHECK-NEXT:    orl %eax, %ecx
-; CHECK-NEXT:    orl $-16777216, %ecx # imm = 0xFF000000
-; CHECK-NEXT:    shrl $8, %ecx
-; CHECK-NEXT:    andl $16711935, %eax # imm = 0xFF00FF
-; CHECK-NEXT:    shll $8, %eax
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    andl $16711935, %ecx # imm = 0xFF00FF
+; CHECK-NEXT:    shll $8, %ecx
+; CHECK-NEXT:    orl $-16777216, %eax # imm = 0xFF000000
+; CHECK-NEXT:    shrl $8, %eax
 ; CHECK-NEXT:    orl %ecx, %eax
 ; CHECK-NEXT:    retl
 ;
 ; CHECK64-LABEL: test1:
 ; CHECK64:       # %bb.0:
-; CHECK64-NEXT:    movzwl %di, %eax
-; CHECK64-NEXT:    orl %edi, %eax
-; CHECK64-NEXT:    orl $-16777216, %eax # imm = 0xFF000000
-; CHECK64-NEXT:    shrl $8, %eax
-; CHECK64-NEXT:    andl $16711935, %edi # imm = 0xFF00FF
-; CHECK64-NEXT:    shll $8, %edi
+; CHECK64-NEXT:    movl %edi, %eax
+; CHECK64-NEXT:    andl $16711935, %eax # imm = 0xFF00FF
+; CHECK64-NEXT:    shll $8, %eax
+; CHECK64-NEXT:    orl $-16777216, %edi # imm = 0xFF000000
+; CHECK64-NEXT:    shrl $8, %edi
 ; CHECK64-NEXT:    orl %edi, %eax
 ; CHECK64-NEXT:    retq
   %byte0 = and i32 %x, 255        ; 0x000000ff
   %byte1 = and i32 %x, 65280      ; 0x0000ff00
   %byte2 = and i32 %x, 16711680   ; 0x00ff0000
   %byte3 = or  i32 %x, 4278190080 ; 0xff000000
   %tmp0 = shl  i32 %byte0, 8
   %tmp1 = lshr i32 %byte1, 8

llvm/test/CodeGen/X86/known-signbits-vector.ll

; X64-NEXT:    retq
   %8 = sitofp i64 %7 to float
   ret float %8
 }
 
 define float @signbits_ashr_sextvecinreg_bitops_extract_sitofp(<2 x i64> %a0, <4 x i32> %a1) nounwind {
 ; X86-LABEL: signbits_ashr_sextvecinreg_bitops_extract_sitofp:
 ; X86:       # %bb.0:
 ; X86-NEXT:    pushl %eax
-; X86-NEXT:    vpsrlq $60, %xmm0, %xmm2
-; X86-NEXT:    vpsrlq $61, %xmm0, %xmm0
-; X86-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
-; X86-NEXT:    vmovdqa {{.*#+}} xmm2 = [4,0,8,0]
-; X86-NEXT:    vpxor %xmm2, %xmm0, %xmm0
-; X86-NEXT:    vpsubq %xmm2, %xmm0, %xmm0
-; X86-NEXT:    vpand %xmm1, %xmm0, %xmm2
-; X86-NEXT:    vpor %xmm1, %xmm2, %xmm1
+; X86-NEXT:    vpsrad $29, %xmm0, %xmm0
+; X86-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
 ; X86-NEXT:    vpxor %xmm0, %xmm1, %xmm0
 ; X86-NEXT:    vcvtdq2ps %xmm0, %xmm0
 ; X86-NEXT:    vmovss %xmm0, (%esp)
 ; X86-NEXT:    flds (%esp)
 ; X86-NEXT:    popl %eax
 ; X86-NEXT:    retl
 ;
-; X64-AVX1-LABEL: signbits_ashr_sextvecinreg_bitops_extract_sitofp:
-; X64-AVX1:       # %bb.0:
-; X64-AVX1-NEXT:    vpsrlq $60, %xmm0, %xmm2
-; X64-AVX1-NEXT:    vpsrlq $61, %xmm0, %xmm0
-; X64-AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
-; X64-AVX1-NEXT:    vmovdqa {{.*#+}} xmm2 = [4,8]
-; X64-AVX1-NEXT:    vpxor %xmm2, %xmm0, %xmm0
-; X64-AVX1-NEXT:    vpsubq %xmm2, %xmm0, %xmm0
-; X64-AVX1-NEXT:    vpand %xmm1, %xmm0, %xmm2
-; X64-AVX1-NEXT:    vpor %xmm1, %xmm2, %xmm1
-; X64-AVX1-NEXT:    vpxor %xmm0, %xmm1, %xmm0
-; X64-AVX1-NEXT:    vcvtdq2ps %xmm0, %xmm0
-; X64-AVX1-NEXT:    retq
-;
-; X64-AVX2-LABEL: signbits_ashr_sextvecinreg_bitops_extract_sitofp:
-; X64-AVX2:       # %bb.0:
-; X64-AVX2-NEXT:    vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; X64-AVX2-NEXT:    vmovdqa {{.*#+}} xmm2 = [4,8]
-; X64-AVX2-NEXT:    vpxor %xmm2, %xmm0, %xmm0
-; X64-AVX2-NEXT:    vpsubq %xmm2, %xmm0, %xmm0
-; X64-AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm2
-; X64-AVX2-NEXT:    vpor %xmm1, %xmm2, %xmm1
-; X64-AVX2-NEXT:    vpxor %xmm0, %xmm1, %xmm0
-; X64-AVX2-NEXT:    vcvtdq2ps %xmm0, %xmm0
-; X64-AVX2-NEXT:    retq
+; X64-LABEL: signbits_ashr_sextvecinreg_bitops_extract_sitofp:
+; X64:       # %bb.0:
+; X64-NEXT:    vpsrad $29, %xmm0, %xmm0
+; X64-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; X64-NEXT:    vpxor %xmm0, %xmm1, %xmm0
+; X64-NEXT:    vcvtdq2ps %xmm0, %xmm0
+; X64-NEXT:    retq
   %1 = ashr <2 x i64> %a0, <i64 61, i64 60>
   %2 = shufflevector <4 x i32> %a1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
   %3 = sext <2 x i32> %2 to <2 x i64>
   %4 = and <2 x i64> %1, %3
   %5 = or <2 x i64> %4, %3
   %6 = xor <2 x i64> %5, %1
   %7 = extractelement <2 x i64> %6, i32 0
   %8 = sitofp i64 %7 to float