[AArch64][SVE2] Add the SVE2.1 pmov instructions

[david-arm]

Summary

This patch adds the assembly/disassembly for the following instructions:

pmov : Move predicate to vector
pmov : Move vector to predicate

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

[paulwalker-arm]

llvm/lib/Target/AArch64/SVEInstrFormats.td

9289

Please can you join these into a single 4-bit opcode?

9306–9316

I think you might not need this based on https://developer.arm.com/documentation/ddi0602/2022-09/SVE-Instructions/PMOV--to-predicate---Move-predicate-from-vector-.

It says When the predicate element specifier is.B, each bit [N] from the least-significant VL/8 bits in the source vector register is copied to bit [N] of the destination predicate register. The immediate index, if specified, must be 0.

Note the last part. This suggests PMOV <Pd>.B, <Zn>[0] is allowed, but PMOV <Pd>.B, <Zn> is the preferred disassembly. I know the alias isn't shown but the text seems clear and favourable because you can just add/implement VectorIndex032b along with an InastAlias rather than needing special instruction classes.

9336

Please can you join these into a single 4-bit opcode?

9347–9348

Not sure why the docs split this but feel free to join them if you want.

[david-arm]

• Added support for both Zd[0] and Zd forms with the byte variant, plus added extra tests for the alias.

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

 defm FADDQV   : sve2p1_fp_reduction_q<0b000, "faddqv">;
 defm FMAXNMQV : sve2p1_fp_reduction_q<0b100, "fmaxnmqv">;
 defm FMINNMQV : sve2p1_fp_reduction_q<0b101, "fminnmqv">;
 defm FMAXQV   : sve2p1_fp_reduction_q<0b110, "fmaxqv">;
 defm FMINQV   : sve2p1_fp_reduction_q<0b111, "fminqv">;
 
 defm DUPQ_ZZI : sve2p1_dupq<"dupq">;
 def EXTQ_ZZI : sve2p1_extq<"extq">;
+
+defm PMOV_PZI : sve2p1_vector_to_pred<"pmov">;
+defm PMOV_ZIP : sve2p1_pred_to_vector<"pmov">;
 } // End HasSVE2p1_or_HasSME2p1

llvm/lib/Target/AArch64/SVEInstrFormats.td

multiclass sve_mem_128b_cld_ss<bits<2> dtype, string mnemonic, RegisterOperand gprsh_ty> {
   def NAME : sve_mem_128b_cld_ss<dtype, mnemonic, gprsh_ty>;
 
   def : InstAlias<mnemonic # " $Zt, $Pg/z, [$Rn, $Rm]",
                  (!cast<Instruction>(NAME) ZPR128:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprsh_ty:$Rm), 0>;
 }
 
 
 // SVE floating-point recursive reduction (quadwords)
 class sve2p1_fp_reduction_q<bits<2> sz, bits<3> opc, string mnemonic,
                             RegisterOperand zpr_ty, string vec_sfx>
     : I<(outs V128:$Vd), (ins PPR3bAny:$Pg, zpr_ty:$Zn),
         mnemonic, "\t$Vd." # vec_sfx # ", $Pg, $Zn",
         "", []>, Sched<[]> {
   bits<5> Vd;
   bits<5> Zn;
   bits<3> Pg;
   let Inst{31-24} = 0b01100100;
   let Inst{23-22} = sz;
   let Inst{21-19} = 0b010;
   let Inst{18-16} = opc;
   let Inst{15-13} = 0b101;
   let Inst{12-10} = Pg;
   let Inst{9-5}   = Zn;
   let Inst{4-0}   = Vd;
 }
 
 multiclass sve2p1_fp_reduction_q<bits<3> opc, string mnemonic> {
   def _H : sve2p1_fp_reduction_q<0b01, opc, mnemonic, ZPR16, "8h">;
   def _S : sve2p1_fp_reduction_q<0b10, opc, mnemonic, ZPR32, "4s">;
   def _D : sve2p1_fp_reduction_q<0b11, opc, mnemonic, ZPR64, "2d">;
 }
 
 
 // SVE Permute Vector - Quadwords (DUPQ)
 class sve2p1_dupq<bits<5> ind_tsz, string mnemonic, ZPRRegOp zprty, Operand itype>
     : I<(outs zprty:$Zd), (ins zprty:$Zn, itype:$index),
         mnemonic, "\t$Zd, $Zn$index",
         "", []>, Sched<[]> {
   bits<5> Zd;
   bits<5> Zn;
   let Inst{31-21} = 0b00000101001;
   let Inst{20-16} = ind_tsz;
   let Inst{15-10} = 0b001001;
   let Inst{9-5} = Zn;
   let Inst{4-0} = Zd;
 }
 
 multiclass sve2p1_dupq<string mnemonic> {
   def _B : sve2p1_dupq<{?, ?, ?, ?, 1}, mnemonic, ZPR8, VectorIndexB32b> {
     bits<4> index;
     let Inst{20-17} = index;
   }
   def _H : sve2p1_dupq<{?, ?, ?, 1, 0}, mnemonic, ZPR16, VectorIndexH32b> {
     bits<3> index;
     let Inst{20-18} = index;
   }
   def _S : sve2p1_dupq<{?, ?, 1, 0, 0}, mnemonic, ZPR32, VectorIndexS32b> {
     bits<2> index;
     let Inst{20-19} = index;
   }
   def _D : sve2p1_dupq<{?, 1, 0, 0, 0}, mnemonic, ZPR64, VectorIndexD32b> {
     bits<1> index;
     let Inst{20} = index;
   }
 }
 
 
 // SVE Permute Vector - Quadwords (EXTQ)
 class sve2p1_extq<string mnemonic>
     : I<(outs ZPR8:$Zdn), (ins ZPR8:$_Zdn, ZPR8:$Zm, imm0_15:$imm4),
         mnemonic, "\t$Zdn, $_Zdn, $Zm, $imm4",
         "", []>, Sched<[]> {
   bits<5> Zdn;
   bits<5> Zm;
   bits<4> imm4;
   let Inst{31-20} = 0b000001010110;
   let Inst{19-16} = imm4;
   let Inst{15-10} = 0b001001;
   let Inst{9-5} = Zm;
   let Inst{4-0} = Zdn;
 
   let Constraints = "$Zdn = $_Zdn";
   let DestructiveInstType = DestructiveOther;
   let ElementSize = ZPR8.ElementSize;
 }
+
+
+// SVE move predicate from vector
+class sve2p1_vector_to_pred<bits<4> opc, string mnemonic,
+                            PPRRegOp ppr_ty, Operand itype>
+    : I<(outs ppr_ty:$Pd), (ins ZPRAny:$Zn, itype:$index),
+        mnemonic, "\t$Pd, $Zn$index",
+        "", []>, Sched<[]> {
+  bits<4> Pd;
+  bits<5> Zn;
+  let Inst{31-24} = 0b00000101;
+  let Inst{23-22} = opc{3-2};
+  let Inst{21-19} = 0b101;
+  let Inst{18-17} = opc{1-0};
+  let Inst{16-10} = 0b0001110;
+  let Inst{9-5}   = Zn;
+  let Inst{4}     = 0b0;
+  let Inst{3-0}   = Pd;
+}
+
+multiclass sve2p1_vector_to_pred<string mnemonic> {
+  def _B : sve2p1_vector_to_pred<{0, 0, 0, 1}, mnemonic, PPR8,  VectorIndex0>;
+  def _H : sve2p1_vector_to_pred<{0, 0, 1, ?}, mnemonic, PPR16, VectorIndexD32b> {
+    bits<1> index;
+    let Inst{17} = index;
+  }
+  def _S : sve2p1_vector_to_pred<{0, 1, ?, ?}, mnemonic, PPR32, VectorIndexS32b> {
+    bits<2> index;
+    let Inst{18-17} = index;
+  }
+  def _D : sve2p1_vector_to_pred<{1, ?, ?, ?}, mnemonic, PPR64, VectorIndexH32b> {
+    bits<3> index;
+    let Inst{22}    = index{2};
+    let Inst{18-17} = index{1-0};
+  }
+
+  def : InstAlias<mnemonic # "\t$Pd, $Zn",
+                 (!cast<Instruction>(NAME # _B) PPR8:$Pd, ZPRAny:$Zn, 0), 1>;
+}
+
+
+// SVE move predicate into vector
+class sve2p1_pred_to_vector<bits<4> opc, string mnemonic,
+                            PPRRegOp ppr_ty, Operand itype>
+    : I<(outs ZPRAny:$Zd), (ins ZPRAny:$_Zd, itype:$index, ppr_ty:$Pn),
+        mnemonic, "\t$Zd$index, $Pn",
+        "", []>, Sched<[]> {
+  bits<5> Zd;
+  bits<4> Pn;
+  let Inst{31-24} = 0b00000101;
+  let Inst{23-22} = opc{3-2};
+  let Inst{21-19} = 0b101;
+  let Inst{18-17} = opc{1-0};
+  let Inst{16-9}  = 0b10011100;
+  let Inst{8-5}   = Pn;
+  let Inst{4-0}   = Zd;
+
+  let Constraints = "$Zd = $_Zd";
+}
+
+multiclass sve2p1_pred_to_vector<string mnemonic> {
+  def _B : sve2p1_pred_to_vector<{0, 0, 0, 1}, mnemonic, PPR8,  VectorIndex0>;
+  def _H : sve2p1_pred_to_vector<{0, 0, 1, ?}, mnemonic, PPR16, VectorIndexD32b> {
+    bits<1> index;
+    let Inst{17} = index;
+  }
+  def _S : sve2p1_pred_to_vector<{0, 1, ?, ?}, mnemonic, PPR32, VectorIndexS32b> {
+    bits<2> index;
+    let Inst{18-17} = index;
+  }
+  def _D : sve2p1_pred_to_vector<{1, ?, ?, ?}, mnemonic, PPR64, VectorIndexH32b> {
+    bits<3> index;
+    let Inst{22}    = index{2};
+    let Inst{18-17} = index{1-0};
+  }
+
+  def : InstAlias<mnemonic # "\t$Zd, $Pn",
+                 (!cast<Instruction>(NAME # _B) ZPRAny:$Zd, 0, PPR8:$Pn), 1>;
+}

llvm/test/MC/AArch64/SVE2p1/pmov-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector lane indices
+
+pmov p0.b, z0[1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected lane specifier '[0]'
+// CHECK-NEXT: pmov p0.b, z0[1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pmov p0.h, z0[2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
+// CHECK-NEXT: pmov p0.h, z0[2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pmov p0.h, z0[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
+// CHECK-NEXT: pmov p0.h, z0[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pmov p0.s, z0[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: pmov p0.s, z0[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pmov p0.s, z0[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: pmov p0.s, z0[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pmov p0.d, z0[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: pmov p0.d, z0[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pmov p0.d, z0[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: pmov p0.d, z0[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+
+pmov z0[2], p0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: pmov z0[2], p0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pmov z0[-1], p0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: pmov z0[-1], p0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pmov z0[4], p0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: pmov z0[4], p0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pmov z0[-1], p0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: pmov z0[-1], p0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pmov z0[8], p0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: pmov z0[8], p0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pmov z0[-1], p0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: pmov z0[-1], p0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+

llvm/test/MC/AArch64/SVE2p1/pmov.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN:        | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN:        | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+pmov    p0.h, z0[0]  // 00000101-00101100-00111000-00000000
+// CHECK-INST: pmov    p0.h, z0[0]
+// CHECK-ENCODING: [0x00,0x38,0x2c,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 052c3800 <unknown>
+
+pmov    p5.h, z10[0]  // 00000101-00101100-00111001-01000101
+// CHECK-INST: pmov    p5.h, z10[0]
+// CHECK-ENCODING: [0x45,0x39,0x2c,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 052c3945 <unknown>
+
+pmov    p7.h, z13[0]  // 00000101-00101100-00111001-10100111
+// CHECK-INST: pmov    p7.h, z13[0]
+// CHECK-ENCODING: [0xa7,0x39,0x2c,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 052c39a7 <unknown>
+
+pmov    p15.h, z31[1]  // 00000101-00101110-00111011-11101111
+// CHECK-INST: pmov    p15.h, z31[1]
+// CHECK-ENCODING: [0xef,0x3b,0x2e,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 052e3bef <unknown>
+
+pmov    p0.s, z0[0]  // 00000101-01101000-00111000-00000000
+// CHECK-INST: pmov    p0.s, z0[0]
+// CHECK-ENCODING: [0x00,0x38,0x68,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05683800 <unknown>
+
+pmov    p5.s, z10[2]  // 00000101-01101100-00111001-01000101
+// CHECK-INST: pmov    p5.s, z10[2]
+// CHECK-ENCODING: [0x45,0x39,0x6c,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 056c3945 <unknown>
+
+pmov    p7.s, z13[0]  // 00000101-01101000-00111001-10100111
+// CHECK-INST: pmov    p7.s, z13[0]
+// CHECK-ENCODING: [0xa7,0x39,0x68,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 056839a7 <unknown>
+
+pmov    p15.s, z31[3]  // 00000101-01101110-00111011-11101111
+// CHECK-INST: pmov    p15.s, z31[3]
+// CHECK-ENCODING: [0xef,0x3b,0x6e,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 056e3bef <unknown>
+
+pmov    p0.d, z0[0]  // 00000101-10101000-00111000-00000000
+// CHECK-INST: pmov    p0.d, z0[0]
+// CHECK-ENCODING: [0x00,0x38,0xa8,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05a83800 <unknown>
+
+pmov    p5.d, z10[6]  // 00000101-11101100-00111001-01000101
+// CHECK-INST: pmov    p5.d, z10[6]
+// CHECK-ENCODING: [0x45,0x39,0xec,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05ec3945 <unknown>
+
+pmov    p7.d, z13[4]  // 00000101-11101000-00111001-10100111
+// CHECK-INST: pmov    p7.d, z13[4]
+// CHECK-ENCODING: [0xa7,0x39,0xe8,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05e839a7 <unknown>
+
+pmov    p15.d, z31[7]  // 00000101-11101110-00111011-11101111
+// CHECK-INST: pmov    p15.d, z31[7]
+// CHECK-ENCODING: [0xef,0x3b,0xee,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05ee3bef <unknown>
+
+pmov    p0.b, z0  // 00000101-00101010-00111000-00000000
+// CHECK-INST: pmov    p0.b, z0
+// CHECK-ENCODING: [0x00,0x38,0x2a,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 052a3800 <unknown>
+
+pmov    p5.b, z10  // 00000101-00101010-00111001-01000101
+// CHECK-INST: pmov    p5.b, z10
+// CHECK-ENCODING: [0x45,0x39,0x2a,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 052a3945 <unknown>
+
+pmov    p7.b, z13  // 00000101-00101010-00111001-10100111
+// CHECK-INST: pmov    p7.b, z13
+// CHECK-ENCODING: [0xa7,0x39,0x2a,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 052a39a7 <unknown>
+
+pmov    p15.b, z31  // 00000101-00101010-00111011-11101111
+// CHECK-INST: pmov    p15.b, z31
+// CHECK-ENCODING: [0xef,0x3b,0x2a,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 052a3bef <unknown>
+
+pmov    p0.b, z0[0] // 00000101-00101010-00111000-00000000
+// CHECK-INST: pmov    p0.b, z0
+// CHECK-ENCODING: [0x00,0x38,0x2a,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 052a3800 <unknown>
+
+pmov    z0[0], p0.h  // 00000101-00101101-00111000-00000000
+// CHECK-INST: pmov    z0[0], p0.h
+// CHECK-ENCODING: [0x00,0x38,0x2d,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 052d3800 <unknown>
+
+pmov    z21[0], p10.h  // 00000101-00101101-00111001-01010101
+// CHECK-INST: pmov    z21[0], p10.h
+// CHECK-ENCODING: [0x55,0x39,0x2d,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 052d3955 <unknown>
+
+pmov    z23[0], p13.h  // 00000101-00101101-00111001-10110111
+// CHECK-INST: pmov    z23[0], p13.h
+// CHECK-ENCODING: [0xb7,0x39,0x2d,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 052d39b7 <unknown>
+
+pmov    z31[1], p15.h  // 00000101-00101111-00111001-11111111
+// CHECK-INST: pmov    z31[1], p15.h
+// CHECK-ENCODING: [0xff,0x39,0x2f,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 052f39ff <unknown>
+
+
+pmov    z0[0], p0.s  // 00000101-01101001-00111000-00000000
+// CHECK-INST: pmov    z0[0], p0.s
+// CHECK-ENCODING: [0x00,0x38,0x69,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05693800 <unknown>
+
+pmov    z21[2], p10.s  // 00000101-01101101-00111001-01010101
+// CHECK-INST: pmov    z21[2], p10.s
+// CHECK-ENCODING: [0x55,0x39,0x6d,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 056d3955 <unknown>
+
+pmov    z23[0], p13.s  // 00000101-01101001-00111001-10110111
+// CHECK-INST: pmov    z23[0], p13.s
+// CHECK-ENCODING: [0xb7,0x39,0x69,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 056939b7 <unknown>
+
+pmov    z31[3], p15.s  // 00000101-01101111-00111001-11111111
+// CHECK-INST: pmov    z31[3], p15.s
+// CHECK-ENCODING: [0xff,0x39,0x6f,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 056f39ff <unknown>
+
+pmov    z0[0], p0.d  // 00000101-10101001-00111000-00000000
+// CHECK-INST: pmov    z0[0], p0.d
+// CHECK-ENCODING: [0x00,0x38,0xa9,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05a93800 <unknown>
+
+pmov    z21[6], p10.d  // 00000101-11101101-00111001-01010101
+// CHECK-INST: pmov    z21[6], p10.d
+// CHECK-ENCODING: [0x55,0x39,0xed,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05ed3955 <unknown>
+
+pmov    z23[4], p13.d  // 00000101-11101001-00111001-10110111
+// CHECK-INST: pmov    z23[4], p13.d
+// CHECK-ENCODING: [0xb7,0x39,0xe9,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05e939b7 <unknown>
+
+pmov    z31[7], p15.d  // 00000101-11101111-00111001-11111111
+// CHECK-INST: pmov    z31[7], p15.d
+// CHECK-ENCODING: [0xff,0x39,0xef,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05ef39ff <unknown>
+
+pmov    z0, p0.b  // 00000101-00101011-00111000-00000000
+// CHECK-INST: pmov    z0, p0.b
+// CHECK-ENCODING: [0x00,0x38,0x2b,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 052b3800 <unknown>
+
+pmov    z21, p10.b  // 00000101-00101011-00111001-01010101
+// CHECK-INST: pmov    z21, p10.b
+// CHECK-ENCODING: [0x55,0x39,0x2b,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 052b3955 <unknown>
+
+pmov    z23, p13.b  // 00000101-00101011-00111001-10110111
+// CHECK-INST: pmov    z23, p13.b
+// CHECK-ENCODING: [0xb7,0x39,0x2b,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 052b39b7 <unknown>
+
+pmov    z31, p15.b  // 00000101-00101011-00111001-11111111
+// CHECK-INST: pmov    z31, p15.b
+// CHECK-ENCODING: [0xff,0x39,0x2b,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 052b39ff <unknown>
+
+pmov    z0[0], p0.b  // 00000101-00101011-00111000-00000000
+// CHECK-INST: pmov    z0, p0.b
+// CHECK-ENCODING: [0x00,0x38,0x2b,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 052b3800 <unknown>