[AsmParser] Match mandatory operands following optional operands.

[kosarev]

Summary

Currently, the asm parser stops matching instruction operands as soon as the first optional operand is encountered. This leads to the need for custom checks on missing mandatory operands that come after optional operands.

The patch changes the parser to always match all optional and mandatory instruction operands, thus making the custom checks unnecessary. This is particularly useful for the AMDGPU backend where we have numerous optional instruction modifiers.

[kosarev]

I think this could also make the hack added in https://reviews.llvm.org/D41598 unnecessary but it doesn't because of https://reviews.llvm.org/D20527 not respecting types of optional parameters, meaning mandatory parameters that follow optional ones may be off their positions and fail to match, which is a problem of its own.

[dp]

Overall it is a nice idea, but I'm not sure how useful it would be for non AMDGPU backends. I suspect that most backends do not mix optional and mandatory operands (but I may be wrong).

Anyway, I think that the change should be split to tablegen and AMDGPU parts - they probably need different reviewers.

A description of your idea with a rationale would be useful (especially for reviewers supporting non AMDGPU backends).

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

4585 ↗

(On Diff #473643)

It looks like this function is no longer necessary: it always returns true.

llvm/utils/TableGen/AsmMatcherEmitter.cpp

3657

For AMDGPU the generated code is:

...
for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 26; ++FormalIdx) {
  auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);

  if (ActualIdx >= Operands.size()) {
    OptionalOperandsMask.set(FormalIdx, 26);
    OperandsValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass);
    if (OperandsValid) {
      ++ActualIdx;
      continue;
    }
    ErrorInfo = ActualIdx;
    break;
  }
  ...
}
...

It looks like each successful match will have to iterate over 26 formal operand classes to make sure there are no mandatory operands. Isn't it wasteful?

[dp]

llvm/test/MC/AMDGPU/gfx10_err_pos.s

7

Could you also rename the section?

968–969

This and the following test should be moved to another section.

llvm/test/MC/AMDGPU/gfx9_err_pos.s

185

Could you also rename the section?

[kosarev]

Addressed review feedback.

• Removed AMDGPU-specific changes.
• Added some richer description of the idea and reasoning.
• The generated code changed to stop after the last formal.
• Tests updated as suggested.

[kosarev]

Regarding how useful it might be for other backends, feels like matching all operands may actually be that least confusing default behaviour to be expected by default?

The generated code now reads:

if (ActualIdx >= Operands.size()) {
  DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n");
  if (Formal == InvalidMatchClass) {
    OptionalOperandsMask.set(FormalIdx, 26);
    break;
  }
  if (isSubclass(Formal, OptionalMatchClass)) {
    OptionalOperandsMask.set(FormalIdx);
    continue;
  }
  OperandsValid = false;
  ErrorInfo = ActualIdx;
  break;
}

[kosarev]

AMDGPU changes went to https://reviews.llvm.org/D137638.

[kosarev]

Remove an unwanted formatting change.

[kosarev]

Ditto.

[dp]

LGTM.

[foad]

Hi @kosarev, can this help with the following issue in FLAT_Load_Pseudo, or is it a different problem?

// FIXME: Operands with default values do not work with following non-optional operands.

llvm/test/MC/AMDGPU/gfx10_err_pos.s

 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+WavefrontSize32,-WavefrontSize64 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
 
 //==============================================================================
-// dim modifier is required on this GPU
+// operands are not valid for this GPU or mode
 
 image_atomic_add v252, v2, s[8:15]
-// CHECK: error: dim modifier is required on this GPU
+// CHECK: error: operands are not valid for this GPU or mode
 // CHECK-NEXT:{{^}}image_atomic_add v252, v2, s[8:15]
 // CHECK-NEXT:{{^}}^
 
 //==============================================================================
 // duplicate data format
 
 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_DATA_FORMAT_8]
 // CHECK: error: duplicate data format

 
 //==============================================================================
 // message operation does not support streams
 
 s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP, 0)
 // CHECK: error: message operation does not support streams
 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP, 0)
 // CHECK-NEXT:{{^}}                                          ^
 
 //==============================================================================
-// missing dst operand or lds modifier
-
-buffer_load_dword off, s[8:11], s3
-// CHECK: error: missing dst operand or lds modifier
-// CHECK-NEXT:{{^}}buffer_load_dword off, s[8:11], s3
-// CHECK-NEXT:{{^}}^
-
-buffer_load_dword off, s[8:11], s3 offset:1
-// CHECK: error: missing dst operand or lds modifier
-// CHECK-NEXT:{{^}}buffer_load_dword off, s[8:11], s3 offset:1
-// CHECK-NEXT:{{^}}^
-
-//==============================================================================
 // missing message operation
 
 s_sendmsg sendmsg(MSG_SYSMSG)
 // CHECK: error: missing message operation
 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_SYSMSG)
 // CHECK-NEXT:{{^}}                  ^
 
 //==============================================================================

 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7]
 // CHECK-NEXT:{{^}}^
 
 v_add_f32_e64 v0, v1
 // CHECK: error: too few operands for instruction
 // CHECK-NEXT:{{^}}v_add_f32_e64 v0, v1
 // CHECK-NEXT:{{^}}^
 
+buffer_load_dword off, s[8:11], s3
+// CHECK: error: too few operands for instruction
+// CHECK-NEXT:{{^}}buffer_load_dword off, s[8:11], s3
+// CHECK-NEXT:{{^}}^
+
+buffer_load_dword off, s[8:11], s3 offset:1
+// CHECK: error: too few operands for instruction
+// CHECK-NEXT:{{^}}buffer_load_dword off, s[8:11], s3 offset:1
+// CHECK-NEXT:{{^}}^
+
 //==============================================================================
 // too large value for expcnt
 
 s_waitcnt expcnt(8)
 // CHECK: error: too large value for expcnt
 // CHECK-NEXT:{{^}}s_waitcnt expcnt(8)
 // CHECK-NEXT:{{^}}                 ^
 

llvm/test/MC/AMDGPU/gfx9-asm-err.s

 
 v_cvt_u32_f64 v5, v[0:1] quad_perm:[0,2,1,1] row_mask:0xf bank_mask:0xf
 // GFX9ERR: error: invalid operand for instruction
 
 global_load_lds_dword v[2:3], off
 // GFX9ERR: error: instruction not supported on this GPU
 
 global_load_dword v[2:3], off
-// GFX9ERR: error: missing dst operand or lds modifier
+// GFX9ERR: error: too few operands for instruction
 
 scratch_load_dword v2, off, offset:256
-// GFX9ERR: error: missing dst operand or lds modifier
+// GFX9ERR: error: too few operands for instruction

llvm/test/MC/AMDGPU/gfx9_err_pos.s

 // CHECK-NEXT:{{^}}                  ^
 
 v_add_i16 v5, 0.5, v2
 // CHECK: error: literal operands are not supported
 // CHECK-NEXT:{{^}}v_add_i16 v5, 0.5, v2
 // CHECK-NEXT:{{^}}              ^
 
 //==============================================================================
-// missing dst operand or lds modifier
+// too few operands for instruction
 
 buffer_load_dword off, s[8:11], s3
-// CHECK: error: missing dst operand or lds modifier
+// CHECK: error: too few operands for instruction
 // CHECK-NEXT:{{^}}buffer_load_dword off, s[8:11], s3
 // CHECK-NEXT:{{^}}^
 
 buffer_load_dword off, s[8:11], s3 offset:1
-// CHECK: error: missing dst operand or lds modifier
+// CHECK: error: too few operands for instruction
 // CHECK-NEXT:{{^}}buffer_load_dword off, s[8:11], s3 offset:1
 // CHECK-NEXT:{{^}}^
 
 //==============================================================================
 // r128 modifier is not supported on this GPU
 
 image_atomic_add v10, v6, s[8:15] dmask:0x1 r128
 // CHECK: error: r128 modifier is not supported on this GPU

llvm/test/MC/AMDGPU/mubuf.s

 // NOSICI: error: instruction not supported on this GPU
 // NOVI:   error: invalid operand for instruction
 
 buffer_store_lds_dword s[4:7], s8 offset:4 tfe lds
 // NOSICI: error: instruction not supported on this GPU
 // NOVI:   error: invalid operand for instruction
 
 buffer_load_dword off, s[8:11], s3
-// NOSICIVI: error: missing dst operand or lds modifier
+// NOSICIVI: error: too few operands for instruction
 
 buffer_load_dword off, s[8:11], s3 offset:1
-// NOSICIVI: error: missing dst operand or lds modifier
+// NOSICIVI: error: too few operands for instruction

llvm/test/MC/SystemZ/asm-match.s

 // REQUIRES: asserts
 // RUN: llvm-mc -triple s390x-linux-gnu -debug-only=asm-matcher %s 2>&1 | FileCheck %s
 //
 // Check that debug output prints the operands correctly.
 
 // CHECK: AsmMatcher: found 1 encodings with mnemonic 'sllg'
 // CHECK: Trying to match opcode SLLG
 // CHECK: Matching formal operand class MCK_GR64 against actual operand at index 1 (Reg:r3): match success using generic matcher
 // CHECK: Matching formal operand class MCK_GR64 against actual operand at index 2 (Reg:r0): match success using generic matcher
 // CHECK: Matching formal operand class MCK_BDAddr32Disp20 against actual operand at index 3 (Mem:3): match success using generic matcher
-// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 4: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 4: actual operand index out of range
+// CHECK: Opcode result: complete match, selecting this opcode
 // CHECK: AsmMatcher: found 1 encodings with mnemonic 'llill'
 // CHECK: Trying to match opcode LLILL
 // CHECK: Matching formal operand class MCK_GR64 against actual operand at index 1 (Reg:r0): match success using generic matcher
 // CHECK: Matching formal operand class MCK_U16Imm against actual operand at index 2 (Imm:0): match success using generic matcher
-// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range
+// CHECK: Opcode result: complete match, selecting this opcode
 // CHECK: AsmMatcher: found 1 encodings with mnemonic 'lgr'
 // CHECK: Trying to match opcode LGR
 // CHECK: Matching formal operand class MCK_GR64 against actual operand at index 1 (Reg:r1): match success using generic matcher
 // CHECK: Matching formal operand class MCK_GR64 against actual operand at index 2 (Reg:r0): match success using generic matcher
-// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range
+// CHECK: Opcode result: complete match, selecting this opcode
 // CHECK: AsmMatcher: found 1 encodings with mnemonic 'lg'
 // CHECK: Trying to match opcode LG
 // CHECK: Matching formal operand class MCK_GR64 against actual operand at index 1 (Reg:r1): match success using generic matcher
 // CHECK: Matching formal operand class MCK_BDXAddr64Disp20 against actual operand at index 2 (Mem:16(r2)): match success using generic matcher
-// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range
+// CHECK: Opcode result: complete match, selecting this opcode
 // CHECK: AsmMatcher: found 1 encodings with mnemonic 'lg'
 // CHECK: Trying to match opcode LG
 // CHECK: Matching formal operand class MCK_GR64 against actual operand at index 1 (Reg:r1): match success using generic matcher
 // CHECK: Matching formal operand class MCK_BDXAddr64Disp20 against actual operand at index 2 (Mem:16(r2,r3)): match success using generic matcher
-// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range
+// CHECK: Opcode result: complete match, selecting this opcode
 // CHECK: AsmMatcher: found 1 encodings with mnemonic 'stmg'
 // CHECK: Trying to match opcode STMG
 // CHECK: Matching formal operand class MCK_GR64 against actual operand at index 1 (Reg:r13): match success using generic matcher
 // CHECK: Matching formal operand class MCK_GR64 against actual operand at index 2 (Reg:r15): match success using generic matcher
 // CHECK: Matching formal operand class MCK_BDAddr64Disp20 against actual operand at index 3 (Mem:104(r15)): match success using generic matcher
-// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 4: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 4: actual operand index out of range
+// CHECK: Opcode result: complete match, selecting this opcode
 // CHECK: AsmMatcher: found 1 encodings with mnemonic 'mvc'
 // CHECK: Trying to match opcode MVC
 // CHECK: Matching formal operand class MCK_BDLAddr64Disp12Len8 against actual operand at index 1 (Mem:184(8,r15)): match success using generic matcher
 // CHECK: Matching formal operand class MCK_BDAddr64Disp12 against actual operand at index 2 (Mem:8(r2)): match success using generic matcher
-// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range
+// CHECK: Opcode result: complete match, selecting this opcode
 // CHECK: AsmMatcher: found 1 encodings with mnemonic 'mvck'
 // CHECK: Trying to match opcode MVCK
 // CHECK: Matching formal operand class MCK_BDRAddr64Disp12 against actual operand at index 1 (Mem:0(r0,r1)): match success using generic matcher
 // CHECK: Matching formal operand class MCK_BDAddr64Disp12 against actual operand at index 2 (Mem:4095(r15)): match success using generic matcher
 // CHECK: Matching formal operand class MCK_GR64 against actual operand at index 3 (Reg:r2): match success using generic matcher
-// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 4: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 4: actual operand index out of range
+// CHECK: Opcode result: complete match, selecting this opcode
 // CHECK: AsmMatcher: found 1 encodings with mnemonic 'j'
 // CHECK: Trying to match opcode J
 // CHECK: Matching formal operand class MCK_PCRel16 against actual operand at index 1 (Imm:.Ltmp0+2): match success using generic matcher
-// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 2: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 2: actual operand index out of range
+// CHECK: Opcode result: complete match, selecting this opcode
 // CHECK: AsmMatcher: found 1 encodings with mnemonic 'brasl'
 // CHECK: Trying to match opcode BRASL
 // CHECK: Matching formal operand class MCK_GR64 against actual operand at index 1 (Reg:r14): match success using generic matcher
 // CHECK: Matching formal operand class MCK_PCRelTLS32 against actual operand at index 2 (ImmTLS:fun): match success using generic matcher
-// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range
+// CHECK: Opcode result: complete match, selecting this opcode
 // CHECK: .text
 // CHECK: sllg  %r3, %r0, 3
 // CHECK: llill %r0, 0
 // CHECK: lgr %r1, %r0
 // CHECK: lg  %r1, 16(%r2)
 // CHECK: lg  %r1, 16(%r2,%r3)
 // CHECK: stmg  %r13, %r15, 104(%r15)
 // CHECK: mvc 184(8,%r15), 8(%r2)

llvm/test/MC/X86/x86_64-asm-match.s

 // REQUIRES: asserts
 // RUN: llvm-mc -triple x86_64-unknown-unknown  -debug-only=asm-matcher  %s 2>&1 | FileCheck %s
 
 // CHECK: AsmMatcher: found 4 encodings with mnemonic 'pshufb'
 // CHECK: Trying to match opcode MMX_PSHUFBrr
 // CHECK:   Matching formal operand class MCK_VR64 against actual operand at index 1 (Memory: ModeSize=64,BaseReg=rip,Scale=1,Disp=CPI1_0): Opcode result: multiple operand mismatches, ignoring this opcode
 // CHECK: Trying to match opcode PSHUFBrr
 // CHECK:   Matching formal operand class MCK_FR16 against actual operand at index 1 (Memory: ModeSize=64,BaseReg=rip,Scale=1,Disp=CPI1_0): Opcode result: multiple operand mismatches, ignoring this opcode
 // CHECK: Trying to match opcode PSHUFBrm
 // CHECK:   Matching formal operand class MCK_Mem128 against actual operand at index 1 (Memory: ModeSize=64,BaseReg=rip,Scale=1,Disp=CPI1_0): match success using generic matcher
 // CHECK:   Matching formal operand class MCK_FR16 against actual operand at index 2 (Reg:xmm1): match success using generic matcher
-// CHECK:   Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK:   Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range
+// CHECK:   Opcode result: complete match, selecting this opcode
 // CHECK: AsmMatcher: found 2 encodings with mnemonic 'sha1rnds4'
 // CHECK: Trying to match opcode SHA1RNDS4rri
 // CHECK:   Matching formal operand class MCK_ImmUnsignedi8 against actual operand at index 1 (Imm:1): match success using generic matcher
 // CHECK:   Matching formal operand class MCK_FR16 against actual operand at index 2 (Reg:xmm1): match success using generic matcher
 // CHECK:   Matching formal operand class MCK_FR16 against actual operand at index 3 (Reg:xmm2): match success using generic matcher
-// CHECK:   Matching formal operand class InvalidMatchClass against actual operand at index 4: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK:   Matching formal operand class InvalidMatchClass against actual operand at index 4: actual operand index out of range
+// CHECK:   Opcode result: complete match, selecting this opcode
 // CHECK: AsmMatcher: found 4 encodings with mnemonic 'pinsrw'
 // CHECK: Trying to match opcode MMX_PINSRWrr
 // CHECK:   Matching formal operand class MCK_ImmUnsignedi8 against actual operand at index 1 (Imm:3): match success using generic matcher
 // CHECK:   Matching formal operand class MCK_GR32orGR64 against actual operand at index 2 (Reg:ecx): match success using generic matcher
 // CHECK:   Matching formal operand class MCK_VR64 against actual operand at index 3 (Reg:xmm5): Opcode result: multiple operand mismatches, ignoring this opcode
 // CHECK: Trying to match opcode PINSRWrr
 // CHECK:   Matching formal operand class MCK_ImmUnsignedi8 against actual operand at index 1 (Imm:3): match success using generic matcher
 // CHECK:   Matching formal operand class MCK_GR32orGR64 against actual operand at index 2 (Reg:ecx): match success using generic matcher
 // CHECK:   Matching formal operand class MCK_FR16 against actual operand at index 3 (Reg:xmm5): match success using generic matcher
-// CHECK:   Matching formal operand class InvalidMatchClass against actual operand at index 4: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK:   Matching formal operand class InvalidMatchClass against actual operand at index 4: actual operand index out of range
+// CHECK:   Opcode result: complete match, selecting this opcode
 // CHECK: AsmMatcher: found 2 encodings with mnemonic 'crc32l'
 // CHECK: Trying to match opcode CRC32r32r32
 // CHECK:   Matching formal operand class MCK_GR32 against actual operand at index 1 (Memory: ModeSize=64,BaseReg=rbx,IndexReg=rcx,Scale=8,Disp=3735928559,SegReg=gs): Opcode result: multiple operand mismatches, ignoring this opcode
 // CHECK: Trying to match opcode CRC32r32m32
 // CHECK:   Matching formal operand class MCK_Mem32 against actual operand at index 1 (Memory: ModeSize=64,BaseReg=rbx,IndexReg=rcx,Scale=8,Disp=3735928559,SegReg=gs): match success using generic matcher
 // CHECK:   Matching formal operand class MCK_GR32 against actual operand at index 2 (Reg:ecx): match success using generic matcher
-// CHECK:   Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK:   Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range
+// CHECK:   Opcode result: complete match, selecting this opcode
 // CHECK: AsmMatcher: found 4 encodings with mnemonic 'punpcklbw'
 // CHECK: Trying to match opcode MMX_PUNPCKLBWrr
 // CHECK:   Matching formal operand class MCK_VR64 against actual operand at index 1 (Reg:mm0): match success using generic matcher
 // CHECK:   Matching formal operand class MCK_VR64 against actual operand at index 2 (Memory: ModeSize=64,Size=32,BaseReg=rsp,Scale=1): Opcode result: multiple operand mismatches, ignoring this opcode
 // CHECK: Trying to match opcode MMX_PUNPCKLBWrm
 // CHECK:   Matching formal operand class MCK_VR64 against actual operand at index 1 (Reg:mm0): match success using generic matcher
 // CHECK:   Matching formal operand class MCK_Mem32 against actual operand at index 2 (Memory: ModeSize=64,Size=32,BaseReg=rsp,Scale=1): match success using generic matcher
-// CHECK:   Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK:   Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range
+// CHECK:   Opcode result: complete match, selecting this opcode
 
 pshufb    CPI1_0(%rip), %xmm1
 sha1rnds4 $1, %xmm1, %xmm2
 pinsrw    $3, %ecx, %xmm5
 crc32l    %gs:0xdeadbeef(%rbx,%rcx,8),%ecx
 
 .intel_syntax
 punpcklbw mm0, dword ptr [rsp]

llvm/utils/TableGen/AsmMatcherEmitter.cpp

 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This tablegen backend emits a target specifier matcher for converting parsed
#endif
   // Emit check that the subclasses match.
   if (!ReportMultipleNearMisses)
     OS << "    bool OperandsValid = true;\n";
   if (HasOptionalOperands) {
     OS << "    OptionalOperandsMask.reset(0, " << MaxNumOperands << ");\n";
   }
   OS << "    for (unsigned FormalIdx = " << (HasMnemonicFirst ? "0" : "SIndex")
      << ", ActualIdx = " << (HasMnemonicFirst ? "1" : "SIndex")
      << "; FormalIdx != " << MaxNumOperands << "; ++FormalIdx) {\n";
   OS << "      auto Formal = "
      << "static_cast<MatchClassKind>(it->Classes[FormalIdx]);\n";
   OS << "      DEBUG_WITH_TYPE(\"asm-matcher\",\n";
   OS << "                      dbgs() << \"  Matching formal operand class \" << getMatchClassName(Formal)\n";
   OS << "                             << \" against actual operand at index \" << ActualIdx);\n";
   OS << "      if (ActualIdx < Operands.size())\n";
   OS << "        DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \" (\";\n";
   OS << "                        Operands[ActualIdx]->print(dbgs()); dbgs() << \"): \");\n";
   OS << "      else\n";
   OS << "        DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \": \");\n";
   OS << "      if (ActualIdx >= Operands.size()) {\n";
-  OS << "        DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"actual operand index out of range \");\n";
+  OS << "        DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"actual operand "
+        "index out of range\\n\");\n";
   if (ReportMultipleNearMisses) {
     OS << "        bool ThisOperandValid = (Formal == " <<"InvalidMatchClass) || "
                                    "isSubclass(Formal, OptionalMatchClass);\n";
     OS << "        if (!ThisOperandValid) {\n";
     OS << "          if (!OperandNearMiss) {\n";
     OS << "            // Record info about match failure for later use.\n";
     OS << "            DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"recording too-few-operands near miss\\n\");\n";
     OS << "            OperandNearMiss =\n";
     OS << "                NearMissInfo::getTooFewOperands(Formal, it->Opcode);\n";
     OS << "          } else if (OperandNearMiss.getKind() != NearMissInfo::NearMissTooFewOperands) {\n";
     OS << "            // If more than one operand is invalid, give up on this match entry.\n";
     OS << "            DEBUG_WITH_TYPE(\n";
     OS << "                \"asm-matcher\",\n";
     OS << "                dbgs() << \"second invalid operand, giving up on this opcode\\n\");\n";
     OS << "            MultipleInvalidOperands = true;\n";
     OS << "            break;\n";
     OS << "          }\n";
     OS << "        } else {\n";
     OS << "          DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"but formal operand not required\\n\");\n";
-    OS << "          break;\n";
     OS << "        }\n";
     OS << "        continue;\n";
   } else {
-    OS << "        OperandsValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass);\n";
-    OS << "        if (!OperandsValid) ErrorInfo = ActualIdx;\n";
+    OS << "        if (Formal == InvalidMatchClass) {\n";
     if (HasOptionalOperands) {
-      OS << "        OptionalOperandsMask.set(FormalIdx, " << MaxNumOperands
+      OS << "          OptionalOperandsMask.set(FormalIdx, " << MaxNumOperands
          << ");\n";
     }
-    OS << "        break;\n";
+    OS << "          break;\n";
+    OS << "        }\n";
+    OS << "        if (isSubclass(Formal, OptionalMatchClass)) {\n";
+    if (HasOptionalOperands) {
+      OS << "          OptionalOperandsMask.set(FormalIdx);\n";
+    }
+    OS << "          continue;\n";
+    OS << "        }\n";
+    OS << "        OperandsValid = false;\n";
+    OS << "        ErrorInfo = ActualIdx;\n";
+    OS << "        break;\n";
   }
   OS << "      }\n";
   OS << "      MCParsedAsmOperand &Actual = *Operands[ActualIdx];\n";
   OS << "      unsigned Diag = validateOperandClass(Actual, Formal);\n";
   OS << "      if (Diag == Match_Success) {\n";
   OS << "        DEBUG_WITH_TYPE(\"asm-matcher\",\n";
   OS << "                        dbgs() << \"match success using generic matcher\\n\");\n";
   OS << "        ++ActualIdx;\n";