[RISCV] Support BSET/BCLR/BINV in isAllUsesReadW.

[craig.topper]

Summary

These instructions set, clear, or invert a single bit. If their
users don't use the upper 32 bits, they don't use the upper 32 bits
of their input.

Additionally the second operand BSET/BCLR/BINV is a shift amount
which only uses 6 bits of the source.

[asb]

LGTM.

llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp

 //===-------------- RISCVSExtWRemoval.cpp - MI sext.w Removal -------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===---------------------------------------------------------------------===//
 //
for (auto &UserOp : MRI.use_operands(MI->getOperand(0).getReg())) {
         break;
       case RISCV::ORI:
         if (!isUInt<11>(UserMI->getOperand(2).getImm()))
           break;
         Worklist.push_back(UserMI);
         break;
 
       case RISCV::SLL:
+      case RISCV::BSET:
+      case RISCV::BCLR:
+      case RISCV::BINV:
         // Operand 2 is the shift amount which uses 6 bits.
         if (OpIdx == 2)
           break;
         Worklist.push_back(UserMI);
         break;
 
       case RISCV::SRA:
       case RISCV::SRL:
for (auto &UserOp : MRI.use_operands(MI->getOperand(0).getReg())) {
       case RISCV::ANDN:
       case RISCV::CLMUL:
       case RISCV::ORC_B:
       case RISCV::ORN:
       case RISCV::SH1ADD:
       case RISCV::SH2ADD:
       case RISCV::SH3ADD:
       case RISCV::XNOR:
+      case RISCV::BSETI:
+      case RISCV::BCLRI:
+      case RISCV::BINVI:
         Worklist.push_back(UserMI);
         break;
       }
     }
   }
 
   return true;
 }